diff options
Diffstat (limited to 'src/southbridge')
22 files changed, 59 insertions, 68 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index e41bca260e..80d3a46380 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -12,6 +12,7 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <cpu/x86/smm.h> #include <cbmem.h> @@ -647,9 +648,9 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -static void southbridge_inject_dsdt(const struct device *dev) +void southbridge_inject_dsdt(const struct device *dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 075eae0921..ae3304ee8e 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -4,7 +4,7 @@ #include <stdint.h> #include "vendorcode/google/chromeos/gnvs.h" -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -102,9 +102,6 @@ typedef struct global_nvs_t { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); -void acpi_create_gnvs(global_nvs_t *gnvs); +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 83799bee1d..b257fb69fb 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -17,8 +17,8 @@ #include "pch.h" #include "nvs.h" -static global_nvs_t *gnvs; -global_nvs_t *smm_get_gnvs(void) +static struct global_nvs *gnvs; +struct global_nvs *smm_get_gnvs(void) { return gnvs; } @@ -196,7 +196,7 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); + gnvs = (struct global_nvs *)((u32)state->rbx); *smm_done = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index 9bd16786a3..3cd0afb1a9 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -typedef struct { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -95,4 +95,4 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __packed global_nvs_t; +}; diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index b526a1aed0..7cd5c7056c 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -33,7 +33,7 @@ u8 mbi_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +struct global_nvs *gnvs = (struct global_nvs *)0x0; void *tcg = (void *)0x0; void *smi1 = (void *)0x0; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 3b204d44c2..9b32f6cfd9 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -12,6 +12,7 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> @@ -490,9 +491,9 @@ static void lpc_final(struct device *dev) outb(POST_OS_BOOT, 0x80); } -static void southbridge_inject_dsdt(const struct device *dev) +void southbridge_inject_dsdt(const struct device *dev) { - global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index 3f44330e5d..d2efc5c8b1 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -2,9 +2,10 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_NVS_H #define SOUTHBRIDGE_INTEL_I82801GX_NVS_H + #include <stdint.h> -typedef struct { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -96,8 +97,6 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __packed global_nvs_t; - -void acpi_create_gnvs(global_nvs_t *gnvs); +}; #endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */ diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index ad0d358abd..1757872f2b 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -22,11 +22,11 @@ u16 pmbase = DEFAULT_PMBASE; u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +struct global_nvs *gnvs = (struct global_nvs *)0x0; void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { - gnvs = *(global_nvs_t **)0x500; + gnvs = *(struct global_nvs **)0x500; *smm_done = 1; } diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 7ddd883324..883c96428f 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -12,6 +12,7 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <cbmem.h> @@ -456,9 +457,9 @@ static void i82801ix_lpc_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void southbridge_inject_dsdt(const struct device *dev) +void southbridge_inject_dsdt(const struct device *dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 3cd4c58d7c..e0e6bbd68d 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -2,9 +2,10 @@ #ifndef SOUTHBRIDGE_INTEL_I82801IX_NVS_H #define SOUTHBRIDGE_INTEL_I82801IX_NVS_H + #include <stdint.h> -typedef struct { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -96,8 +97,6 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __packed global_nvs_t; - -void acpi_create_gnvs(global_nvs_t *gnvs); +}; #endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */ diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index df3026e28f..070b7a60b8 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -12,7 +12,7 @@ /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +struct global_nvs *gnvs = (struct global_nvs *)0x0; void *tcg = (void *)0x0; void *smi1 = (void *)0x0; @@ -35,7 +35,7 @@ int southbridge_io_trap_handler(int smif) void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { - gnvs = *(global_nvs_t **)0x500; + gnvs = *(struct global_nvs **)0x500; tcg = *(void **)0x504; smi1 = *(void **)0x508; *smm_done = 1; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index c36009ed0a..2533d8cc72 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -12,6 +12,7 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> @@ -497,9 +498,9 @@ static void i82801jx_lpc_read_resources(struct device *dev) } } -static void southbridge_inject_dsdt(const struct device *dev) +void southbridge_inject_dsdt(const struct device *dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index c4879189ee..48a7d87fe1 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -4,7 +4,7 @@ #define SOUTHBRIDGE_INTEL_I82801JX_NVS_H #include <stdint.h> -typedef struct { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -96,8 +96,6 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __packed global_nvs_t; - -void acpi_create_gnvs(global_nvs_t *gnvs); +}; #endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */ diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 00b3ffaf72..af242aaf19 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -18,7 +18,7 @@ u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +struct global_nvs *gnvs = (struct global_nvs *)0x0; void *tcg = (void *)0x0; void *smi1 = (void *)0x0; @@ -41,7 +41,7 @@ int southbridge_io_trap_handler(int smif) void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { - gnvs = *(global_nvs_t **)0x500; + gnvs = *(struct global_nvs **)0x500; tcg = *(void **)0x504; smi1 = *(void **)0x508; *smm_done = 1; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 36d46f209a..2c2904627e 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -13,6 +13,7 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <elog.h> #include <acpi/acpigen.h> #include <cbmem.h> @@ -552,9 +553,9 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -static void southbridge_inject_dsdt(const struct device *dev) +void southbridge_inject_dsdt(const struct device *dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 6b82de33b2..834b3af8a8 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -3,7 +3,7 @@ #include <commonlib/helpers.h> #include "vendorcode/google/chromeos/gnvs.h" -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -99,10 +99,6 @@ typedef struct global_nvs_t { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); - -void acpi_create_gnvs(global_nvs_t *gnvs); +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index a881f33dab..2679351436 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -26,8 +26,8 @@ /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -static global_nvs_t *gnvs; -global_nvs_t *smm_get_gnvs(void) +static struct global_nvs *gnvs; +struct global_nvs *smm_get_gnvs(void) { return gnvs; } @@ -160,7 +160,7 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); + gnvs = (struct global_nvs *)((u32)state->rbx); *smm_done = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index c4ea418ade..cfdcee6896 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -41,7 +41,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet) acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); } -static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs) +static void acpi_create_serialio_ssdt_entry(int id, struct global_nvs *gnvs) { char sio_name[5] = {}; snprintf(sio_name, sizeof(sio_name), "S%1uEN", id); @@ -51,7 +51,7 @@ static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs) void acpi_create_serialio_ssdt(acpi_header_t *ssdt) { unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); - global_nvs_t *gnvs = acpi_get_gnvs(); + struct global_nvs *gnvs = acpi_get_gnvs(); int id; if (!gnvs) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 78536f6c10..f486434045 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -11,6 +11,7 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h> @@ -669,7 +670,7 @@ static void pch_lpc_add_io_resources(struct device *dev) static void pch_lpc_read_resources(struct device *dev) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -681,9 +682,9 @@ static void pch_lpc_read_resources(struct device *dev) pch_lpc_add_io_resources(dev); /* Allocate ACPI NVS in CBMEM */ - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); if (!acpi_is_wakeup_s3() && gnvs) - memset(gnvs, 0, sizeof(global_nvs_t)); + memset(gnvs, 0, sizeof(struct global_nvs)); } static void pch_lpc_enable(struct device *dev) @@ -695,9 +696,9 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -static void southbridge_inject_dsdt(const struct device *dev) +void southbridge_inject_dsdt(const struct device *dev) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index b5b6e9fc02..4abe026354 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -4,7 +4,7 @@ #include <stdint.h> #include "vendorcode/google/chromeos/gnvs.h" -typedef struct global_nvs_t { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -76,10 +76,6 @@ typedef struct global_nvs_t { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +}; -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); - -void acpi_create_gnvs(global_nvs_t * gnvs); +check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 3973a8d94a..77da5351ad 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -205,7 +205,7 @@ static void serialio_init(struct device *dev) } if (config->sio_acpi_mode) { - global_nvs_t *gnvs; + struct global_nvs *gnvs; /* Find ACPI NVS to update BARs */ gnvs = acpi_get_gnvs(); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index be842c5720..0bc1e2a86f 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -24,8 +24,8 @@ static u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -static global_nvs_t *gnvs; -global_nvs_t *smm_get_gnvs(void) +static struct global_nvs *gnvs; +struct global_nvs *smm_get_gnvs(void) { return gnvs; } @@ -325,7 +325,7 @@ static void southbridge_smi_apmc(void) state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); + gnvs = (struct global_nvs *)((u32)state->rbx); smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } |