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-rw-r--r--src/southbridge/amd/amd8111/amd8111.c8
-rw-r--r--src/southbridge/amd/amd8111/amd8111_ac97.c2
-rw-r--r--src/southbridge/amd/amd8111/amd8111_acpi.c16
-rw-r--r--src/southbridge/amd/amd8111/amd8111_ide.c2
-rw-r--r--src/southbridge/amd/amd8111/amd8111_lpc.c12
-rw-r--r--src/southbridge/amd/amd8111/amd8111_nic.c22
-rw-r--r--src/southbridge/amd/amd8111/amd8111_reset.c2
-rw-r--r--src/southbridge/amd/amd8111/amd8111_smbus.c2
-rw-r--r--src/southbridge/amd/amd8111/amd8111_smbus.h10
-rw-r--r--src/southbridge/amd/amd8111/amd8111_usb.c2
-rw-r--r--src/southbridge/amd/amd8111/amd8111_usb2.c4
-rw-r--r--src/southbridge/amd/amd8111/chip.h2
-rw-r--r--src/southbridge/amd/amd8131-disable/amd8131_bridge.c2
-rw-r--r--src/southbridge/amd/amd8131/amd8131_bridge.c26
-rw-r--r--src/southbridge/amd/amd8132/amd8132_bridge.c16
-rw-r--r--src/southbridge/amd/amd8151/amd8151_agp3.c4
-rw-r--r--src/southbridge/amd/cs5535/cs5535.c4
-rw-r--r--src/southbridge/amd/cs5535/cs5535_early_setup.c4
-rw-r--r--src/southbridge/amd/cs5535/cs5535_early_smbus.c2
-rw-r--r--src/southbridge/amd/cs5535/cs5535_smbus.h6
-rw-r--r--src/southbridge/amd/cs5536/Kconfig2
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c24
-rw-r--r--src/southbridge/amd/cs5536/cs5536.h2
-rw-r--r--src/southbridge/amd/cs5536/cs5536_smbus2.h2
-rw-r--r--src/southbridge/broadcom/bcm5780/bcm5780_pcix.c4
-rw-r--r--src/southbridge/broadcom/bcm5785/bcm5785.c4
-rw-r--r--src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c2
-rw-r--r--src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c4
-rw-r--r--src/southbridge/broadcom/bcm5785/bcm5785_lpc.c22
-rw-r--r--src/southbridge/broadcom/bcm5785/bcm5785_sata.c2
-rw-r--r--src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c14
-rw-r--r--src/southbridge/broadcom/bcm5785/bcm5785_smbus.h10
-rw-r--r--src/southbridge/broadcom/bcm5785/bcm5785_usb.c4
-rw-r--r--src/southbridge/broadcom/bcm5785/chip.h2
-rw-r--r--src/southbridge/intel/esb6300/chip.h2
-rw-r--r--src/southbridge/intel/esb6300/esb6300.c4
-rw-r--r--src/southbridge/intel/esb6300/esb6300_ac97.c2
-rw-r--r--src/southbridge/intel/esb6300/esb6300_early_smbus.c26
-rw-r--r--src/southbridge/intel/esb6300/esb6300_ehci.c4
-rw-r--r--src/southbridge/intel/esb6300/esb6300_ide.c4
-rw-r--r--src/southbridge/intel/esb6300/esb6300_lpc.c14
-rw-r--r--src/southbridge/intel/esb6300/esb6300_pic.c2
-rw-r--r--src/southbridge/intel/esb6300/esb6300_sata.c18
-rw-r--r--src/southbridge/intel/esb6300/esb6300_smbus.h2
-rw-r--r--src/southbridge/intel/esb6300/esb6300_uhci.c2
-rw-r--r--src/southbridge/intel/i3100/i3100_lpc.c12
-rw-r--r--src/southbridge/intel/i3100/i3100_sata.c14
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb_smbus.h14
-rw-r--r--src/southbridge/intel/i82801ax/i82801ax_ide.c2
-rw-r--r--src/southbridge/intel/i82801ax/i82801ax_lpc.c4
-rw-r--r--src/southbridge/intel/i82801bx/i82801bx_ide.c2
-rw-r--r--src/southbridge/intel/i82801bx/i82801bx_lpc.c4
-rw-r--r--src/southbridge/intel/i82801bx/i82801bx_smbus.h2
-rw-r--r--src/southbridge/intel/i82801cx/chip.h2
-rw-r--r--src/southbridge/intel/i82801cx/i82801cx.c2
-rw-r--r--src/southbridge/intel/i82801cx/i82801cx.h4
-rw-r--r--src/southbridge/intel/i82801cx/i82801cx_early_smbus.c10
-rw-r--r--src/southbridge/intel/i82801cx/i82801cx_lpc.c38
-rw-r--r--src/southbridge/intel/i82801cx/i82801cx_smbus.c6
-rw-r--r--src/southbridge/intel/i82801cx/i82801cx_usb.c4
-rw-r--r--src/southbridge/intel/i82801dx/i82801dx.c2
-rw-r--r--src/southbridge/intel/i82801dx/i82801dx.h12
-rw-r--r--src/southbridge/intel/i82801dx/i82801dx_early_smbus.c2
-rw-r--r--src/southbridge/intel/i82801ex/chip.h2
-rw-r--r--src/southbridge/intel/i82801ex/i82801ex.c4
-rw-r--r--src/southbridge/intel/i82801ex/i82801ex_ac97.c2
-rw-r--r--src/southbridge/intel/i82801ex/i82801ex_early_smbus.c28
-rw-r--r--src/southbridge/intel/i82801ex/i82801ex_ehci.c4
-rw-r--r--src/southbridge/intel/i82801ex/i82801ex_ide.c2
-rw-r--r--src/southbridge/intel/i82801ex/i82801ex_lpc.c14
-rw-r--r--src/southbridge/intel/i82801ex/i82801ex_pci.c4
-rw-r--r--src/southbridge/intel/i82801ex/i82801ex_sata.c6
-rw-r--r--src/southbridge/intel/i82801ex/i82801ex_smbus.h2
-rw-r--r--src/southbridge/intel/i82801ex/i82801ex_uhci.c2
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_azalia.c2
-rw-r--r--src/southbridge/intel/i82870/p64h2_ioapic.c10
-rw-r--r--src/southbridge/intel/i82870/p64h2_pcibridge.c4
-rw-r--r--src/southbridge/intel/pxhd/pxhd_bridge.c24
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_fadt.c6
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_lpc.c2
-rw-r--r--src/southbridge/ricoh/rl5c476/rl5c476.c10
-rw-r--r--src/southbridge/ricoh/rl5c476/rl5c476.h2
-rw-r--r--src/southbridge/sis/sis966/sis966_lpc.c2
-rw-r--r--src/southbridge/via/k8t890/k8t890_bridge.c6
-rw-r--r--src/southbridge/via/k8t890/k8t890_ctrl.c2
-rw-r--r--src/southbridge/via/k8t890/k8t890_early_car.c4
-rw-r--r--src/southbridge/via/k8t890/k8t890_host_ctrl.c2
-rw-r--r--src/southbridge/via/k8t890/romstrap.inc2
-rw-r--r--src/southbridge/via/vt8231/vt8231.c6
-rw-r--r--src/southbridge/via/vt8231/vt8231_acpi.c12
-rw-r--r--src/southbridge/via/vt8231/vt8231_early_serial.c16
-rw-r--r--src/southbridge/via/vt8231/vt8231_early_smbus.c4
-rw-r--r--src/southbridge/via/vt8231/vt8231_ide.c38
-rw-r--r--src/southbridge/via/vt8231/vt8231_lpc.c32
-rw-r--r--src/southbridge/via/vt8231/vt8231_nic.c2
-rw-r--r--src/southbridge/via/vt8231/vt8231_usb.c20
-rw-r--r--src/southbridge/via/vt8235/vt8235.c12
-rw-r--r--src/southbridge/via/vt8235/vt8235_early_serial.c12
-rw-r--r--src/southbridge/via/vt8235/vt8235_early_smbus.c74
-rw-r--r--src/southbridge/via/vt8235/vt8235_ide.c38
-rw-r--r--src/southbridge/via/vt8235/vt8235_lpc.c36
-rw-r--r--src/southbridge/via/vt8235/vt8235_nic.c2
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_early_smbus.c8
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_lpc.c16
104 files changed, 469 insertions, 469 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c
index 1390065c09..2707ca6b43 100644
--- a/src/southbridge/amd/amd8111/amd8111.c
+++ b/src/southbridge/amd/amd8111/amd8111.c
@@ -13,8 +13,8 @@ void amd8111_enable(device_t dev)
/* See if we are on the bus behind the amd8111 pci bridge */
bus_dev = dev->bus->dev;
- if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) &&
- (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI))
+ if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) &&
+ (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI))
{
unsigned devfn;
devfn = bus_dev->path.pci.devfn + (1 << 3);
@@ -33,7 +33,7 @@ void amd8111_enable(device_t dev)
return;
}
if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) ||
- (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA))
+ (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA))
{
uint32_t id;
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
@@ -66,7 +66,7 @@ void amd8111_enable(device_t dev)
struct chip_operations southbridge_amd_amd8111_ops = {
CHIP_NAME("AMD-8111 Southbridge")
- /* This only called when this device is listed in the
+ /* This only called when this device is listed in the
* static device tree.
*/
.enable_dev = amd8111_enable,
diff --git a/src/southbridge/amd/amd8111/amd8111_ac97.c b/src/southbridge/amd/amd8111/amd8111_ac97.c
index 697915e002..f49c9bfd5f 100644
--- a/src/southbridge/amd/amd8111/amd8111_ac97.c
+++ b/src/southbridge/amd/amd8111/amd8111_ac97.c
@@ -10,7 +10,7 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x2c,
+ pci_write_config32(dev, 0x2c,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c
index 32e3808a98..2ad54b78f6 100644
--- a/src/southbridge/amd/amd8111/amd8111_acpi.c
+++ b/src/southbridge/amd/amd8111/amd8111_acpi.c
@@ -28,7 +28,7 @@ static int lsmbus_recv_byte(device_t dev)
device = dev->path.i2c.device;
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-
+
return do_smbus_recv_byte(res->base, device);
}
@@ -51,7 +51,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address)
device = dev->path.i2c.device;
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-
+
return do_smbus_read_byte(res->base, device, address);
}
@@ -62,7 +62,7 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
device = dev->path.i2c.device;
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-
+
return do_smbus_write_byte(res->base, device, address, val);
}
@@ -109,7 +109,7 @@ static void acpi_init(struct device *dev)
*/
byte = pci_read_config8(dev, 0x41);
pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
-
+
/* power on after power fail */
on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
@@ -126,7 +126,7 @@ static void acpi_init(struct device *dev)
*/
byte = pci_read_config8(dev, 0x4a);
pci_write_config8(dev, 0x4a, byte | (1<<6));
-
+
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
@@ -177,12 +177,12 @@ static void acpi_enable_resources(device_t dev)
/* Set the class code */
pci_write_config32(dev, 0x60, 0x06800000);
-
+
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x7c,
+ pci_write_config32(dev, 0x7c,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
@@ -204,7 +204,7 @@ static struct device_operations acpi_ops = {
.init = acpi_init,
.scan_bus = scan_static_bus,
/* We don't need amd8111_enable, chip ops takes care of it.
- * It could be useful if these devices were not
+ * It could be useful if these devices were not
* enabled by default.
*/
// .enable = amd8111_enable,
diff --git a/src/southbridge/amd/amd8111/amd8111_ide.c b/src/southbridge/amd/amd8111/amd8111_ide.c
index 3b6f5a0a65..3299875187 100644
--- a/src/southbridge/amd/amd8111/amd8111_ide.c
+++ b/src/southbridge/amd/amd8111/amd8111_ide.c
@@ -42,7 +42,7 @@ static void ide_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x70,
+ pci_write_config32(dev, 0x70,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c
index 85e217bb65..8fe4982721 100644
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -19,11 +19,11 @@
static void enable_hpet(struct device *dev)
{
unsigned long hpet_address;
-
+
pci_write_config32(dev,0xa0, 0xfed00001);
hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
-
+
}
static void lpc_init(struct device *dev)
@@ -40,7 +40,7 @@ static void lpc_init(struct device *dev)
/* posted memory write enable */
byte = pci_read_config8(dev, 0x46);
- pci_write_config8(dev, 0x46, byte | (1<<0));
+ pci_write_config8(dev, 0x46, byte | (1<<0));
/* Enable 5Mib Rom window */
byte = pci_read_config8(dev, 0x43);
@@ -65,11 +65,11 @@ static void lpc_init(struct device *dev)
pci_write_config8(dev, 0x40, byte);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
- if (nmi_option) {
+ if (nmi_option) {
byte |= (1 << 7); /* set NMI */
pci_write_config8(dev, 0x40, byte);
}
-
+
/* Initialize the real time clock */
rtc_init(0);
@@ -114,7 +114,7 @@ static void amd8111_lpc_enable_resources(device_t dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x70,
+ pci_write_config32(dev, 0x70,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/amd8111_nic.c
index 8818b51b40..4ab7212eda 100644
--- a/src/southbridge/amd/amd8111/amd8111_nic.c
+++ b/src/southbridge/amd/amd8111/amd8111_nic.c
@@ -25,20 +25,20 @@ typedef enum {
ASF_INIT_DONE_ALIAS = (1 << 29),
/* VAL2 */
JUMBO = (1 << 21),
- VSIZE = (1 << 20),
+ VSIZE = (1 << 20),
VLONLY = (1 << 19),
- VL_TAG_DEL = (1 << 18),
+ VL_TAG_DEL = (1 << 18),
/* VAL1 */
- EN_PMGR = (1 << 14),
+ EN_PMGR = (1 << 14),
INTLEVEL = (1 << 13),
- FORCE_FULL_DUPLEX = (1 << 12),
- FORCE_LINK_STATUS = (1 << 11),
- APEP = (1 << 10),
- MPPLBA = (1 << 9),
+ FORCE_FULL_DUPLEX = (1 << 12),
+ FORCE_LINK_STATUS = (1 << 11),
+ APEP = (1 << 10),
+ MPPLBA = (1 << 9),
/* VAL0 */
- RESET_PHY_PULSE = (1 << 2),
- RESET_PHY = (1 << 1),
- PHY_RST_POL = (1 << 0),
+ RESET_PHY_PULSE = (1 << 2),
+ RESET_PHY = (1 << 1),
+ PHY_RST_POL = (1 << 0),
}CMD3_BITS;
static void nic_init(struct device *dev)
@@ -72,7 +72,7 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
};
-
+
static struct device_operations nic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
diff --git a/src/southbridge/amd/amd8111/amd8111_reset.c b/src/southbridge/amd/amd8111/amd8111_reset.c
index 9b26bcb90d..c96e898aea 100644
--- a/src/southbridge/amd/amd8111/amd8111_reset.c
+++ b/src/southbridge/amd/amd8111/amd8111_reset.c
@@ -67,7 +67,7 @@ void hard_reset(void)
*/
bus = node_link_to_bus(node, link);
dev = pci_locate_device_on_bus(
- PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA),
+ PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA),
bus);
/* Reset */
diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.c b/src/southbridge/amd/amd8111/amd8111_smbus.c
index 2554fd0c5e..0a0c58dce3 100644
--- a/src/southbridge/amd/amd8111/amd8111_smbus.c
+++ b/src/southbridge/amd/amd8111/amd8111_smbus.c
@@ -13,7 +13,7 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x44,
+ pci_write_config32(dev, 0x44,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h
index b5799666e9..fe9b3bff8c 100644
--- a/src/southbridge/amd/amd8111/amd8111_smbus.h
+++ b/src/southbridge/amd/amd8111/amd8111_smbus.h
@@ -27,7 +27,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
break;
}
if(loops == (SMBUS_TIMEOUT / 2)) {
- outw(inw(smbus_io_base + SMBGSTATUS),
+ outw(inw(smbus_io_base + SMBGSTATUS),
smbus_io_base + SMBGSTATUS);
}
} while(--loops);
@@ -41,7 +41,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
do {
unsigned short val;
smbus_delay();
-
+
val = inw(smbus_io_base + SMBGSTATUS);
if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) {
break;
@@ -58,7 +58,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
-
+
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
@@ -103,7 +103,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
-
+
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
@@ -146,7 +146,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
-
+
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
diff --git a/src/southbridge/amd/amd8111/amd8111_usb.c b/src/southbridge/amd/amd8111/amd8111_usb.c
index f1c331dbaf..13dccf435b 100644
--- a/src/southbridge/amd/amd8111/amd8111_usb.c
+++ b/src/southbridge/amd/amd8111/amd8111_usb.c
@@ -12,7 +12,7 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x70,
+ pci_write_config32(dev, 0x70,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
diff --git a/src/southbridge/amd/amd8111/amd8111_usb2.c b/src/southbridge/amd/amd8111/amd8111_usb2.c
index 3aa5211dd0..89115c3bbe 100644
--- a/src/southbridge/amd/amd8111/amd8111_usb2.c
+++ b/src/southbridge/amd/amd8111/amd8111_usb2.c
@@ -11,7 +11,7 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x70,
+ pci_write_config32(dev, 0x70,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
@@ -23,7 +23,7 @@ static struct pci_operations lops_pci = {
static void amd8111_usb2_enable(device_t dev)
{
- // Due to buggy USB2 we force it to disable.
+ // Due to buggy USB2 we force it to disable.
dev->enabled = 0;
amd8111_enable(dev);
printk(BIOS_DEBUG, "USB2 disabled.\n");
diff --git a/src/southbridge/amd/amd8111/chip.h b/src/southbridge/amd/amd8111/chip.h
index 6c97ef2232..601038c441 100644
--- a/src/southbridge/amd/amd8111/chip.h
+++ b/src/southbridge/amd/amd8111/chip.h
@@ -1,7 +1,7 @@
#ifndef AMD8111_CHIP_H
#define AMD8111_CHIP_H
-struct southbridge_amd_amd8111_config
+struct southbridge_amd_amd8111_config
{
unsigned int ide0_enable : 1;
unsigned int ide1_enable : 1;
diff --git a/src/southbridge/amd/amd8131-disable/amd8131_bridge.c b/src/southbridge/amd/amd8131-disable/amd8131_bridge.c
index bcb89fa22a..e90f497d95 100644
--- a/src/southbridge/amd/amd8131-disable/amd8131_bridge.c
+++ b/src/southbridge/amd/amd8131-disable/amd8131_bridge.c
@@ -112,5 +112,5 @@ static const struct pci_driver ioapic_driver __pci_driver = {
.ops = &ioapic_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x7451,
-
+
};
diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c
index 04930517e6..ae2c4cffcb 100644
--- a/src/southbridge/amd/amd8131/amd8131_bridge.c
+++ b/src/southbridge/amd/amd8131/amd8131_bridge.c
@@ -121,7 +121,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
}
}
/* Errata #56 additional limits when the bus runs at 133Mhz */
- if (info->errata_56 &&
+ if (info->errata_56 &&
(PCI_X_SSTATUS_MFREQ(info->sstatus) == PCI_X_SSTATUS_MODE1_133MHZ))
{
unsigned limit_read;
@@ -131,7 +131,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
if (sib_funcs == 0) {
/* 2k reads */
limit_read = 2;
- }
+ }
else if (sib_funcs <= 1) {
/* 1k reads */
limit_read = 1;
@@ -226,8 +226,8 @@ static unsigned int amd8131_scan_bus(struct bus *bus,
* we are running at 133Mhz and have a 4 function device.
* see errata #56
*/
- if (!bus->children ||
- (info.errata_56 &&
+ if (!bus->children ||
+ (info.errata_56 &&
(info.max_func >= 3) &&
(PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_MODE1_133MHZ)))
{
@@ -242,7 +242,7 @@ static unsigned int amd8131_scan_bus(struct bus *bus,
pcix_misc = pci_read_config32(bus->dev, 0x40);
pcix_misc &= ~(0x1f << 16);
pci_write_config32(bus->dev, 0x40, pcix_misc);
-
+
return max;
}
@@ -284,7 +284,7 @@ static void amd8131_pcix_init(device_t dev)
byte = pci_read_config8(dev, 0x04);
byte |= 0x10;
pci_write_config8(dev, 0x04, byte);
-
+
/* Set drive strength */
word = pci_read_config16(dev, 0xe0);
word = 0x0404;
@@ -292,7 +292,7 @@ static void amd8131_pcix_init(device_t dev)
word = pci_read_config16(dev, 0xe4);
word = 0x0404;
pci_write_config16(dev, 0xe4, word);
-
+
/* Set impedance */
word = pci_read_config16(dev, 0xe8);
word = 0x0404;
@@ -303,7 +303,7 @@ static void amd8131_pcix_init(device_t dev)
word = pci_read_config16(dev, 0x4c);
word |= 1;
pci_write_config16(dev, 0x4c, word);
-
+
/* Set split transaction limits */
word = pci_read_config16(dev, 0xa8);
pci_write_config16(dev, 0xaa, word);
@@ -315,12 +315,12 @@ static void amd8131_pcix_init(device_t dev)
dword = pci_read_config32(dev, 0x04);
dword |= (1<<8);
pci_write_config32(dev, 0x04, dword);
-
+
/* system and error parity enable */
dword = pci_read_config32(dev, 0x3c);
dword |= (3<<16);
pci_write_config32(dev, 0x3c, dword);
-
+
/* NMI enable */
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
@@ -329,7 +329,7 @@ static void amd8131_pcix_init(device_t dev)
dword |= (1<<0);
pci_write_config32(dev, 0x44, dword);
}
-
+
/* Set up CRC flood enable */
dword = pci_read_config32(dev, 0xc0);
if(dword) { /* do device A only */
@@ -349,7 +349,7 @@ static void bridge_read_resources(struct device *dev)
{
struct resource *res;
pci_bus_read_resources(dev);
- res = find_resource(dev, PCI_MEMORY_BASE);
+ res = find_resource(dev, PCI_MEMORY_BASE);
if (res) {
res->limit = 0xffffffffffULL;
}
@@ -428,5 +428,5 @@ static const struct pci_driver ioapic_driver __pci_driver = {
.ops = &ioapic_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x7451,
-
+
};
diff --git a/src/southbridge/amd/amd8132/amd8132_bridge.c b/src/southbridge/amd/amd8132/amd8132_bridge.c
index 2c18c5ebcb..e8283baa50 100644
--- a/src/southbridge/amd/amd8132/amd8132_bridge.c
+++ b/src/southbridge/amd/amd8132/amd8132_bridge.c
@@ -114,7 +114,7 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr)
max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
- if (info->rev == 0x01) { // only a1 need it
+ if (info->rev == 0x01) { // only a1 need it
/* Errata #53 Limit the number of split transactions to avoid starvation */
if (sibs >= 2) {
/* At most 2 outstanding split transactions when we have
@@ -186,7 +186,7 @@ static unsigned int amd8132_scan_bus(struct bus *bus,
amd8132_walk_children(bus, amd8132_count_dev, &info);
#if 0
- /* Disable the bus if there are no devices on it
+ /* Disable the bus if there are no devices on it
*/
if (!bus->children)
{
@@ -201,7 +201,7 @@ static unsigned int amd8132_scan_bus(struct bus *bus,
pcix_misc = pci_read_config32(bus->dev, 0x40);
pcix_misc &= ~(0x1f << 16);
pci_write_config32(bus->dev, 0x40, pcix_misc);
-
+
return max;
}
#endif
@@ -229,7 +229,7 @@ static void amd8132_pcix_init(device_t dev)
uint32_t dword;
uint8_t byte;
unsigned chip_rev;
-
+
/* Find the revision of the 8132 */
chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
@@ -259,7 +259,7 @@ static void amd8132_pcix_init(device_t dev)
dword = pci_read_config32(dev, 0x04);
dword |= (1<<8);
pci_write_config32(dev, 0x04, dword);
-
+
/* system and error parity enable */
dword = pci_read_config32(dev, 0x3c);
dword |= (3<<16);
@@ -267,7 +267,7 @@ static void amd8132_pcix_init(device_t dev)
dword = pci_read_config32(dev, 0x40);
// dword &= ~(1<<31); /* WriteChainEnable */
- dword |= (1<<31);
+ dword |= (1<<31);
dword |= (1<<7);// must set to 1
dword |= (3<<21); //PCIErrorSerrDisable
pci_write_config32(dev, 0x40, dword);
@@ -335,7 +335,7 @@ static void bridge_read_resources(struct device *dev)
{
struct resource *res;
pci_bus_read_resources(dev);
- res = find_resource(dev, PCI_MEMORY_BASE);
+ res = find_resource(dev, PCI_MEMORY_BASE);
if (res) {
res->limit = 0xffffffffffULL;
}
@@ -450,5 +450,5 @@ static const struct pci_driver ioapic_driver __pci_driver = {
.ops = &ioapic_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x7459,
-
+
};
diff --git a/src/southbridge/amd/amd8151/amd8151_agp3.c b/src/southbridge/amd/amd8151/amd8151_agp3.c
index 93c7992810..5d673f6ae8 100644
--- a/src/southbridge/amd/amd8151/amd8151_agp3.c
+++ b/src/southbridge/amd/amd8151/amd8151_agp3.c
@@ -38,7 +38,7 @@ static const struct pci_driver agp3bridge_driver __pci_driver = {
static void agp3dev_enable(device_t dev)
{
uint32_t value;
-
+
/* AGP enable */
value = pci_read_config32(dev, 0xa8);
value |= (3<<8)|2; //AGP 8x
@@ -71,5 +71,5 @@ static struct device_operations agp3dev_ops = {
static const struct pci_driver agp3dev_driver __pci_driver = {
.ops = &agp3dev_ops,
.vendor = PCI_VENDOR_ID_AMD,
- .device = 0x7454, //AGP Device
+ .device = 0x7454, //AGP Device
};
diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c
index 6f203558e3..50b62df0c3 100644
--- a/src/southbridge/amd/cs5535/cs5535.c
+++ b/src/southbridge/amd/cs5535/cs5535.c
@@ -21,7 +21,7 @@ static void nvram_on(struct device *dev)
/* Set positive decode on ROM */
/* Also, there is no apparent reason to turn off the devoce on the */
/* IDE devices */
-
+
reg = pci_read_config8(dev, 0x5b);
reg |= 1 << 5; /* ROM Decode */
reg |= 1 << 3; /* Primary IDE decode */
@@ -43,7 +43,7 @@ static void nvram_on(struct device *dev)
#endif
}
-
+
static void southbridge_init(struct device *dev)
{
printk(BIOS_SPEW, "cs5535: %s\n", __func__);
diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c
index fbb3647578..91dc852012 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_setup.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c
@@ -8,13 +8,13 @@
*
*/
-#define CS5535_GLINK_PORT_NUM 0x02 /* the geode link port number to the CS5535 */
+#define CS5535_GLINK_PORT_NUM 0x02 /* the geode link port number to the CS5535 */
#define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */
/**
* @brief Setup PCI IDSEL for CS5535
*
- *
+ *
*/
static void cs5535_setup_extmsr(void)
diff --git a/src/southbridge/amd/cs5535/cs5535_early_smbus.c b/src/southbridge/amd/cs5535/cs5535_early_smbus.c
index 6ff46338f6..ec801f02a8 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_smbus.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_smbus.c
@@ -18,7 +18,7 @@ static int cs5535_enable_smbus(void)
/* Setup SMBus host controller address to 0xEF */
val = inb(SMBUS_IO_BASE + SMB_ADD);
val |= (0xEF | SMB_ADD_SAEN);
- outb(val, SMBUS_IO_BASE + SMB_ADD);
+ outb(val, SMBUS_IO_BASE + SMB_ADD);
}
static int smbus_read_byte(unsigned device, unsigned address)
diff --git a/src/southbridge/amd/cs5535/cs5535_smbus.h b/src/southbridge/amd/cs5535/cs5535_smbus.h
index 9cf55ba29c..799e226f5e 100644
--- a/src/southbridge/amd/cs5535/cs5535_smbus.h
+++ b/src/southbridge/amd/cs5535/cs5535_smbus.h
@@ -105,7 +105,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device
unsigned char val;
unsigned long loops;
loops = SMBUS_TIMEOUT;
-
+
/* send the slave address */
outb(device, smbus_io_base + SMB_SDA);
@@ -123,7 +123,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device
break;
}
} while(--loops);
- return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+ return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
@@ -149,7 +149,7 @@ static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
break;
}
} while(--loops);
- return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+ return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
diff --git a/src/southbridge/amd/cs5536/Kconfig b/src/southbridge/amd/cs5536/Kconfig
index b6884b7fa9..e7caf5e27a 100644
--- a/src/southbridge/amd/cs5536/Kconfig
+++ b/src/southbridge/amd/cs5536/Kconfig
@@ -26,5 +26,5 @@ config UDELAY_TSC
default y
depends on SOUTHBRIDGE_AMD_CS5536
-
+
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 43f3b1290e..11679278f8 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -247,7 +247,7 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb)
isa_dma_init();
}
-
+
/**
* Depending on settings in the config struct, enable COM1 or COM2 or both.
@@ -263,8 +263,8 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
u16 addr = 0;
u32 gpio_addr;
device_t dev;
-
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
+
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
gpio_addr &= ~1; /* Clear I/O bit */
@@ -431,7 +431,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
msr_t msr;
device_t dev;
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
if (dev) {
@@ -452,7 +452,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
write32(bar + HCCPARAMS, 0x00005012);
}
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -480,7 +480,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
* - set PADEN (former OTGPADEN) bit in uoc register
* - set APU bit in uoc register */
if (sb->enable_USBP4_device) {
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
if (dev) {
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -499,13 +499,13 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
}
/* Disable virtual PCI UDC and OTG headers */
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
if (dev) {
pci_write_config32(dev, 0x7C, 0xDEADBEEF);
}
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
pci_write_config32(dev, 0x7C, 0xDEADBEEF);
@@ -513,14 +513,14 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
}
/****************************************************************************
- *
- * ChipsetInit
+ *
+ * ChipsetInit
*
* Called from northbridge init (Pre-VSA).
*
* NOTE! This function is NOT called if the CS5536 is combined with
* an AMD Geode GX2. It's ONLY used on Geode LX based systems.
- *
+ *
****************************************************************************/
void chipsetinit(void)
{
@@ -530,7 +530,7 @@ void chipsetinit(void)
struct southbridge_amd_cs5536_config *sb;
struct msrinit *csi;
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
if (!dev) {
diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h
index 073bb3ea59..797ac92764 100644
--- a/src/southbridge/amd/cs5536/cs5536.h
+++ b/src/southbridge/amd/cs5536/cs5536.h
@@ -465,7 +465,7 @@
#define FLASH_IO_256B 0x0000FF00
#if !defined(ASSEMBLY) && !defined(__ROMCC__)
-#if defined(__PRE_RAM__)
+#if defined(__PRE_RAM__)
void cs5536_setup_onchipuart(int uart);
void cs5536_disable_internal_uart(void);
#else
diff --git a/src/southbridge/amd/cs5536/cs5536_smbus2.h b/src/southbridge/amd/cs5536/cs5536_smbus2.h
index 3613b3d37b..dea08a437c 100644
--- a/src/southbridge/amd/cs5536/cs5536_smbus2.h
+++ b/src/southbridge/amd/cs5536/cs5536_smbus2.h
@@ -309,7 +309,7 @@ static inline int do_smbus_write_byte(unsigned smbus_io_base,
(unsigned char *)&data, 1);
}
-static inline int do_smbus_write_word(unsigned smbus_io_base,
+static inline int do_smbus_write_word(unsigned smbus_io_base,
unsigned char device, unsigned char address, unsigned short data)
{
return _dowrite(smbus_io_base, device, address, (unsigned char *)&data,
diff --git a/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c b/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c
index f83e54b682..ece7e794eb 100644
--- a/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c
+++ b/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c
@@ -10,8 +10,8 @@
#include <device/pci_ops.h>
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
- pci_write_config32(dev, 0x40,
+{
+ pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c
index 3ac28e59ca..3f92be7dec 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.c
@@ -16,7 +16,7 @@ void bcm5785_enable(device_t dev)
/* See if we are on the behind the pcix bridge */
bus_dev = dev->bus->dev;
- if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
+ if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
(bus_dev->device == 0x0036 )) // device under PCI-X Bridge
{
unsigned devfn;
@@ -34,7 +34,7 @@ void bcm5785_enable(device_t dev)
else { // same bus
unsigned devfn;
devfn = (dev->path.pci.devfn) & ~7;
- if( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
+ if( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
if(dev->device == 0x0036) //PCI-X Bridge
{ devfn += (1<<3); }
else if(dev->device == 0x0223) // USB
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
index fd2f3ed114..d448bf67c3 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
@@ -85,7 +85,7 @@ static unsigned get_sbdn(unsigned bus)
static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
{
- //ACPI Decode Enable
+ //ACPI Decode Enable
outb(0x0e, 0xcd6);
outb((1<<3), 0xcd7);
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c
index 2638e97d5c..a55ddd82e8 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c
@@ -15,11 +15,11 @@ static void enable_smbus(void)
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
}
-
+
print_debug("SMBus controller enabled\n");
/* set smbus iobase */
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
- /* Set smbus iospace enable */
+ /* Set smbus iospace enable */
pci_write_config8(dev, 0xd2, 0x03);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
index e76dd3a45a..29c08ab74e 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
@@ -52,25 +52,25 @@ static void bcm5785_lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-/**
+/**
* @brief Enable resources for children devices
- *
+ *
* @param dev the device whos children's resources are to be enabled
- *
+ *
* This function is call by the global enable_resources() indirectly via the
* device_operation::enable_resources() method of devices.
- *
+ *
* Indirect mutual recursion:
* enable_childrens_resources() -> enable_resources()
* enable_resources() -> device_operation::enable_resources()
* device_operation::enable_resources() -> enable_children_resources()
- */
+ */
static void bcm5785_lpc_enable_childrens_resources(device_t dev)
-{
- unsigned link;
+{
+ unsigned link;
uint32_t reg;
int i;
-
+
reg = pci_read_config8(dev, 0x44);
for (link = 0; link < dev->links; link++) {
@@ -93,10 +93,10 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
case 0x3f8: // COM1
reg |= (1<<6); break;
case 0x2f8: // COM2
- reg |= (1<<7); break;
+ reg |= (1<<7); break;
case 0x378: // Parallal 1
reg |= (1<<0); break;
- case 0x3f0: // FD0
+ case 0x3f0: // FD0
reg |= (1<<26); break;
case 0x220: // Aduio 0
reg |= (1<<14); break;
@@ -108,7 +108,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
}
}
pci_write_config32(dev, 0x44, reg);
-
+
}
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
index ec92ecf7e9..58d5ff5bb7 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
@@ -44,7 +44,7 @@ static void sata_init(struct device *dev)
printk(BIOS_DEBUG, "init PHY...\n");
for(i=0; i<4; i++) {
- mmio = res->base + 0x100 * i;
+ mmio = res->base + 0x100 * i;
byte = read8(mmio + 0x40);
printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
if(byte & 0x4) {// bit 2 is set
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c b/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
index a13e9f3fd0..4f518b6a54 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
@@ -30,7 +30,7 @@ static void sb_init(device_t dev)
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
- if (nmi_option) {
+ if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
} else {
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
@@ -47,16 +47,16 @@ static void bcm5785_sb_read_resources(device_t dev)
struct resource *res;
/* Get the normal pci resources of this device */
- pci_dev_read_resources(dev);
- /* Get Resource for SMBUS */
- pci_get_resource(dev, 0x90);
+ pci_dev_read_resources(dev);
+ /* Get Resource for SMBUS */
+ pci_get_resource(dev, 0x90);
- compact_resources(dev);
+ compact_resources(dev);
/* Add an extra subtractive resource for both memory and I/O */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
+
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
@@ -75,7 +75,7 @@ static int lsmbus_recv_byte(device_t dev)
return do_smbus_recv_byte(res->base, device);
}
-
+
static int lsmbus_send_byte(device_t dev, uint8_t val)
{
unsigned device;
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h b/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h
index 5f2f7717a0..e71bb5cbee 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h
@@ -19,7 +19,7 @@
#define SMBSLVDAT 0xc
-/* Between 1-10 seconds, We should never timeout normally
+/* Between 1-10 seconds, We should never timeout normally
* Longer than this is just painful when a timeout condition occurs.
*/
#define SMBUS_TIMEOUT (100*1000*10)
@@ -36,7 +36,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
do {
unsigned char val;
val = inb(smbus_io_base + SMBHSTSTAT);
- val &= 0x1f;
+ val &= 0x1f;
if (val == 0) { // ready now
return 0;
}
@@ -51,7 +51,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
loops = SMBUS_TIMEOUT;
do {
unsigned char val;
-
+
val = inb(smbus_io_base + SMBHSTSTAT);
val &= 0x1f; // mask off reserved bits
if ( val & 0x1c) {
@@ -68,7 +68,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
{
uint8_t byte;
-
+
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return -2; // not ready
}
@@ -128,7 +128,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return -2; // not ready
}
-
+
/* set the command/address... */
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_usb.c b/src/southbridge/broadcom/bcm5785/bcm5785_usb.c
index c2e7366272..15295d8329 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_usb.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_usb.c
@@ -23,8 +23,8 @@ static void usb_init(struct device *dev)
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
- pci_write_config32(dev, 0x40,
+{
+ pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
diff --git a/src/southbridge/broadcom/bcm5785/chip.h b/src/southbridge/broadcom/bcm5785/chip.h
index 4aa2ce3217..3106f60c24 100644
--- a/src/southbridge/broadcom/bcm5785/chip.h
+++ b/src/southbridge/broadcom/bcm5785/chip.h
@@ -1,7 +1,7 @@
#ifndef BCM5785_CHIP_H
#define BCM5785_CHIP_H
-struct southbridge_broadcom_bcm5785_config
+struct southbridge_broadcom_bcm5785_config
{
unsigned int ide0_enable : 1;
unsigned int ide1_enable : 1;
diff --git a/src/southbridge/intel/esb6300/chip.h b/src/southbridge/intel/esb6300/chip.h
index ff74e615fd..4082769cce 100644
--- a/src/southbridge/intel/esb6300/chip.h
+++ b/src/southbridge/intel/esb6300/chip.h
@@ -1,4 +1,4 @@
-struct southbridge_intel_esb6300_config
+struct southbridge_intel_esb6300_config
{
#define ESB6300_GPIO_USE_MASK 0x03
#define ESB6300_GPIO_USE_DEFAULT 0x00
diff --git a/src/southbridge/intel/esb6300/esb6300.c b/src/southbridge/intel/esb6300/esb6300.c
index 786daea23b..5d8f5e412d 100644
--- a/src/southbridge/intel/esb6300/esb6300.c
+++ b/src/southbridge/intel/esb6300/esb6300.c
@@ -25,7 +25,7 @@ void esb6300_enable(device_t dev)
(lpc_dev->device != PCI_DEVICE_ID_INTEL_6300ESB_LPC)) {
uint32_t id;
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
- if (id != (PCI_VENDOR_ID_INTEL |
+ if (id != (PCI_VENDOR_ID_INTEL |
(PCI_DEVICE_ID_INTEL_6300ESB_LPC << 16))) {
return;
}
@@ -39,7 +39,7 @@ void esb6300_enable(device_t dev)
if (reg != reg_old) {
pci_write_config16(lpc_dev, 0xf2, reg);
}
-
+
}
struct chip_operations southbridge_intel_esb6300_ops = {
diff --git a/src/southbridge/intel/esb6300/esb6300_ac97.c b/src/southbridge/intel/esb6300/esb6300_ac97.c
index 231f8129ad..7b7795f5df 100644
--- a/src/southbridge/intel/esb6300/esb6300_ac97.c
+++ b/src/southbridge/intel/esb6300/esb6300_ac97.c
@@ -8,7 +8,7 @@
static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* Write the subsystem vendor and device id */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
diff --git a/src/southbridge/intel/esb6300/esb6300_early_smbus.c b/src/southbridge/intel/esb6300/esb6300_early_smbus.c
index ae7cfcd227..d804fde038 100644
--- a/src/southbridge/intel/esb6300/esb6300_early_smbus.c
+++ b/src/southbridge/intel/esb6300/esb6300_early_smbus.c
@@ -12,7 +12,7 @@ static void enable_smbus(void)
pci_write_config8(dev, 0x4, 1);
/* SMBALERT_DIS */
pci_write_config8(dev, 0x11, 4);
-
+
/* Disable interrupt generation */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
}
@@ -30,7 +30,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va
return;
}
-static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
+static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
unsigned data1, unsigned data2)
{
unsigned char global_control_register;
@@ -41,11 +41,11 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
/* chear the PM timeout flags, SECOND_TO_STS */
outw(inw(0x0400 + 0x66), 0x0400 + 0x66);
-
+
if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
return -2;
}
-
+
/* setup transaction */
/* Obtain ownership */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
@@ -56,39 +56,39 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
/* disable interrupts */
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
-
+
/* set the device I'm talking too */
outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
-
+
/* set the command address */
outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
-
+
/* set the block length */
outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0);
-
+
/* try sending out the first byte of data here */
byte=(data1>>(0))&0x0ff;
outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
/* issue a block write command */
- outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
+ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
SMBUS_IO_BASE + SMBHSTCTL);
for(i=0;i<length;i++) {
-
+
/* poll for transaction completion */
if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
return -3;
}
-
+
/* load the next byte */
if(i>3)
byte=(data2>>(i%4))&0x0ff;
else
byte=(data1>>(i))&0x0ff;
outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
-
+
/* clear the done bit */
- outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
+ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
SMBUS_IO_BASE + SMBHSTSTAT);
}
diff --git a/src/southbridge/intel/esb6300/esb6300_ehci.c b/src/southbridge/intel/esb6300/esb6300_ehci.c
index 8c20c0325f..c103c4bd2f 100644
--- a/src/southbridge/intel/esb6300/esb6300_ehci.c
+++ b/src/southbridge/intel/esb6300/esb6300_ehci.c
@@ -11,7 +11,7 @@ static void ehci_init(struct device *dev)
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND,
+ pci_write_config32(dev, PCI_COMMAND,
cmd | PCI_COMMAND_MASTER);
printk(BIOS_DEBUG, "done.\n");
@@ -24,7 +24,7 @@ static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
/* Enable writes to protected registers */
pci_write_config8(dev, 0x80, access_cntl | 1);
/* Write the subsystem vendor and device id */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
/* Restore protection */
pci_write_config8(dev, 0x80, access_cntl);
diff --git a/src/southbridge/intel/esb6300/esb6300_ide.c b/src/southbridge/intel/esb6300/esb6300_ide.c
index 543468dabb..abe86a811d 100644
--- a/src/southbridge/intel/esb6300/esb6300_ide.c
+++ b/src/southbridge/intel/esb6300/esb6300_ide.c
@@ -16,7 +16,7 @@ static void ide_init(struct device *dev)
pci_write_config8(dev, 0x48, 0x05);
pci_write_config16(dev, 0x4a, 0x0101);
pci_write_config16(dev, 0x54, 0x5055);
-
+
#if 0
uint16_t word;
word = pci_read_config16(dev, 0x40);
@@ -32,7 +32,7 @@ static void ide_init(struct device *dev)
static void esb6300_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* This value is also visible in uchi[0-2] and smbus functions */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
diff --git a/src/southbridge/intel/esb6300/esb6300_lpc.c b/src/southbridge/intel/esb6300/esb6300_lpc.c
index fe035bb2c4..66ac62bb3f 100644
--- a/src/southbridge/intel/esb6300/esb6300_lpc.c
+++ b/src/southbridge/intel/esb6300/esb6300_lpc.c
@@ -96,7 +96,7 @@ static void set_esb6300_gpio_direction(
switch(config->gpio[i] & ESB6300_GPIO_SEL_MASK) {
case ESB6300_GPIO_SEL_OUTPUT: val = 0; break;
case ESB6300_GPIO_SEL_INPUT: val = 1; break;
- default:
+ default:
continue;
}
/* The caller is responsible for not playing with unimplemented bits */
@@ -133,7 +133,7 @@ static void set_esb6300_gpio_level(
case ESB6300_GPIO_LVL_LOW: val = 0; blink = 0; break;
case ESB6300_GPIO_LVL_HIGH: val = 1; blink = 0; break;
case ESB6300_GPIO_LVL_BLINK: val = 1; blink = 1; break;
- default:
+ default:
continue;
}
/* The caller is responsible for not playing with unimplemented bits */
@@ -166,7 +166,7 @@ static void set_esb6300_gpio_inv(
switch(config->gpio[i] & ESB6300_GPIO_INV_MASK) {
case ESB6300_GPIO_INV_OFF: val = 0; break;
case ESB6300_GPIO_INV_ON: val = 1; break;
- default:
+ default:
continue;
}
gpio_inv &= ~( 1 << i);
@@ -210,7 +210,7 @@ static void esb6300_gpio_init(device_t dev)
/* Find the GPIO bar */
res = find_resource(dev, GPIO_BAR);
if (!res) {
- return;
+ return;
}
/* Set the use selects */
@@ -274,7 +274,7 @@ static void lpc_init(struct device *dev)
pci_write_config8(dev, 0xa0, 0x20);
pci_write_config8(dev, 0xad, 0x03);
pci_write_config8(dev, 0xbb, 0x09);
-
+
esb6300_enable_serial_irqs(dev);
esb6300_pci_dma_cfg(dev);
@@ -292,7 +292,7 @@ static void lpc_init(struct device *dev)
/* Set up the PIRQ */
esb6300_pirq_init(dev);
-
+
/* Set the state of the gpio lines */
esb6300_gpio_init(dev);
@@ -346,7 +346,7 @@ static void esb6300_lpc_enable_resources(device_t dev)
acpi_cntl = pci_read_config8(dev, 0x44);
acpi_cntl |= (1 << 4);
pci_write_config8(dev, 0x44, acpi_cntl);
-
+
/* Enable the GPIO bar */
gpio_cntl = pci_read_config8(dev, 0x5c);
gpio_cntl |= (1 << 4);
diff --git a/src/southbridge/intel/esb6300/esb6300_pic.c b/src/southbridge/intel/esb6300/esb6300_pic.c
index 9d02536cd4..5bbf317411 100644
--- a/src/southbridge/intel/esb6300/esb6300_pic.c
+++ b/src/southbridge/intel/esb6300/esb6300_pic.c
@@ -40,7 +40,7 @@ static void pic_read_resources(device_t dev)
res->limit = res->base + res->size -1;
res->align = 8;
res->gran = 8;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
}
diff --git a/src/southbridge/intel/esb6300/esb6300_sata.c b/src/southbridge/intel/esb6300/esb6300_sata.c
index 5818df1819..6dce2d2f3a 100644
--- a/src/southbridge/intel/esb6300/esb6300_sata.c
+++ b/src/southbridge/intel/esb6300/esb6300_sata.c
@@ -15,37 +15,37 @@ static void sata_init(struct device *dev)
/* SATA configuration */
pci_write_config8(dev, 0x04, 0x07);
pci_write_config8(dev, 0x09, 0x8f);
-
+
/* Set timmings */
pci_write_config16(dev, 0x40, 0x0a307);
pci_write_config16(dev, 0x42, 0x0a307);
-
+
/* Sync DMA */
pci_write_config16(dev, 0x48, 0x000f);
pci_write_config16(dev, 0x4a, 0x1111);
-
+
/* 66 mhz */
pci_write_config16(dev, 0x54, 0xf00f);
-
+
/* Combine ide - sata configuration */
pci_write_config8(dev, 0x90, 0x0);
-
+
/* port 0 & 1 enable */
pci_write_config8(dev, 0x92, 0x33);
-
+
/* initialize SATA */
pci_write_config16(dev, 0xa0, 0x0018);
pci_write_config32(dev, 0xa4, 0x00000264);
pci_write_config16(dev, 0xa0, 0x0040);
pci_write_config32(dev, 0xa4, 0x00220043);
-
+
printk(BIOS_DEBUG, "SATA Enabled\n");
}
static void esb6300_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* This value is also visible in usb1, usb2 and smbus functions */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
@@ -66,7 +66,7 @@ static const struct pci_driver sata_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_6300ESB_SATA,
};
-
+
static const struct pci_driver sata_driver_nr __pci_driver = {
.ops = &sata_ops,
.vendor = PCI_VENDOR_ID_INTEL,
diff --git a/src/southbridge/intel/esb6300/esb6300_smbus.h b/src/southbridge/intel/esb6300/esb6300_smbus.h
index 0b793c37f9..e7a0d5c711 100644
--- a/src/southbridge/intel/esb6300/esb6300_smbus.h
+++ b/src/southbridge/intel/esb6300/esb6300_smbus.h
@@ -10,7 +10,7 @@
#define SMBTRNSADD 0x9
#define SMBSLVDATA 0xa
#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
+#define SMBUS_PIN_CTL 0xf
#define SMBUS_TIMEOUT (100*1000*10)
diff --git a/src/southbridge/intel/esb6300/esb6300_uhci.c b/src/southbridge/intel/esb6300/esb6300_uhci.c
index 10b1dfa1cc..a8bcd888f1 100644
--- a/src/southbridge/intel/esb6300/esb6300_uhci.c
+++ b/src/southbridge/intel/esb6300/esb6300_uhci.c
@@ -12,7 +12,7 @@ static void uhci_init(struct device *dev)
#if 1
printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND,
+ pci_write_config32(dev, PCI_COMMAND,
cmd | PCI_COMMAND_MASTER);
diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c
index d629e2f144..eaa81e40c7 100644
--- a/src/southbridge/intel/i3100/i3100_lpc.c
+++ b/src/southbridge/intel/i3100/i3100_lpc.c
@@ -230,9 +230,9 @@ static void i3100_power_options(device_t dev) {
/* avoid #S4 assertions */
reg8 |= (3 << 4);
/* minimum asssertion is 1 to 2 RTCCLK */
- reg8 &= ~(1 << 3);
+ reg8 &= ~(1 << 3);
pci_write_config8(dev, GEN_PMCON_3, reg8);
- printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off");
+ printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off");
/* Set up NMI on errors. */
reg8 = inb(0x61);
@@ -245,14 +245,14 @@ static void i3100_power_options(device_t dev) {
/* PCI SERR# Disable for now */
reg8 |= (1 << 2);
outb(reg8, 0x61);
-
+
reg8 = inb(0x70);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
/* Set NMI. */
printk(BIOS_INFO, "NMI sources enabled.\n");
- reg8 &= ~(1 << 7);
+ reg8 &= ~(1 << 7);
} else {
/* Can't mask NMI from PCI-E and NMI_NOW */
printk(BIOS_INFO, "NMI sources disabled.\n");
@@ -267,7 +267,7 @@ static void i3100_power_options(device_t dev) {
/* CLKRUN_EN */
// reg16 |= (1 << 2);
pci_write_config16(dev, GEN_PMCON_1, reg16);
-
+
// Set the board's GPI routing.
// i82801gx_gpi_routing(dev);
}
@@ -321,7 +321,7 @@ static void lpc_init(struct device *dev)
// TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode
// (register 0x10/0x11) while the old code used int 1 (register 0x12)
- // ... Why?
+ // ... Why?
setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID
/* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
diff --git a/src/southbridge/intel/i3100/i3100_sata.c b/src/southbridge/intel/i3100/i3100_sata.c
index cafb68fe0d..14c13da290 100644
--- a/src/southbridge/intel/i3100/i3100_sata.c
+++ b/src/southbridge/intel/i3100/i3100_sata.c
@@ -73,29 +73,29 @@ static void sata_init(struct device *dev)
/* IDE I/O configuration */
pci_write_config32(dev, SATA_IIOC, 0);
-
+
} else {
/* SATA configuration */
pci_write_config8(dev, SATA_CMD, 0x07);
pci_write_config8(dev, SATA_PI, 0x8f);
-
+
/* Set timings */
pci_write_config16(dev, SATA_PTIM, 0x0a307);
pci_write_config16(dev, SATA_STIM, 0x0a307);
-
+
/* Sync DMA */
pci_write_config8(dev, SATA_SYNCC, 0x0f);
pci_write_config16(dev, SATA_SYNCTIM, 0x1111);
-
+
/* Fast ATA */
pci_write_config16(dev, SATA_IIOC, 0x1000);
-
+
/* Select IDE mode */
pci_write_config8(dev, SATA_MAP, 0x00);
-
+
/* Enable ports 0-3 */
pci_write_config8(dev, SATA_PCS + 1, 0x0f);
-
+
}
printk(BIOS_DEBUG, "SATA Enabled\n");
}
diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.h b/src/southbridge/intel/i82371eb/i82371eb_smbus.h
index a1ede98eb6..1c6f26a47d 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_smbus.h
+++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.h
@@ -31,9 +31,9 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
if ((val & 0x1) == 0) {
break;
}
-#if 0
+#if 0
if(loops == (SMBUS_TIMEOUT / 2)) {
- outw(inw(smbus_io_base + SMBHST_STATUS),
+ outw(inw(smbus_io_base + SMBHST_STATUS),
smbus_io_base + SMBHST_STATUS);
}
#endif
@@ -48,10 +48,10 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
do {
unsigned short val;
smbus_delay();
-
+
val = inb(smbus_io_base + SMBHST_STATUS);
// Make sure the command is done
- if ((val & 0x1) != 0) {
+ if ((val & 0x1) != 0) {
continue;
}
// Don't break out until one of the interrupt
@@ -71,7 +71,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
-
+
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL);
@@ -117,7 +117,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
-
+
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL);
@@ -160,7 +160,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
-
+
/* setup transaction */
/* clear any lingering errors, so the transaction will run */
diff --git a/src/southbridge/intel/i82801ax/i82801ax_ide.c b/src/southbridge/intel/i82801ax/i82801ax_ide.c
index 2daa986bd4..da3e404d26 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_ide.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_ide.c
@@ -32,7 +32,7 @@ typedef struct southbridge_intel_i82801ax_config config_t;
static void ide_init(struct device *dev)
{
/* Get the chip configuration */
- config_t *config = dev->chip_info;
+ config_t *config = dev->chip_info;
/* TODO: Needs to be tested for compatibility with ICH5(R). */
/* Enable IDE devices so the Linux IDE driver will work. */
diff --git a/src/southbridge/intel/i82801ax/i82801ax_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_lpc.c
index 8fccdf0983..50be866be3 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_lpc.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_lpc.c
@@ -68,8 +68,8 @@ typedef struct southbridge_intel_i82801ax_config config_t;
#define PIRQG 0x0A
#define PIRQH 0x0B
-/*
- * Use 0x0ef8 for a bitmap to cover all these IRQ's.
+/*
+ * Use 0x0ef8 for a bitmap to cover all these IRQ's.
* Use the defined IRQ values above or set mainboard
* specific IRQ values in your mainboards Config.lb.
*/
diff --git a/src/southbridge/intel/i82801bx/i82801bx_ide.c b/src/southbridge/intel/i82801bx/i82801bx_ide.c
index ffbaf80dbd..9d287b2b9b 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_ide.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_ide.c
@@ -32,7 +32,7 @@ typedef struct southbridge_intel_i82801bx_config config_t;
static void ide_init(struct device *dev)
{
/* Get the chip configuration */
- config_t *config = dev->chip_info;
+ config_t *config = dev->chip_info;
/* TODO: Needs to be tested for compatibility with ICH5(R). */
/* Enable IDE devices so the Linux IDE driver will work. */
diff --git a/src/southbridge/intel/i82801bx/i82801bx_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_lpc.c
index c63de08c2a..96dbd54e37 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_lpc.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_lpc.c
@@ -68,8 +68,8 @@ typedef struct southbridge_intel_i82801bx_config config_t;
#define PIRQG 0x0A
#define PIRQH 0x0B
-/*
- * Use 0x0ef8 for a bitmap to cover all these IRQ's.
+/*
+ * Use 0x0ef8 for a bitmap to cover all these IRQ's.
* Use the defined IRQ values above or set mainboard
* specific IRQ values in your mainboards Config.lb.
*/
diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.h b/src/southbridge/intel/i82801bx/i82801bx_smbus.h
index e4ec70bc5f..6287b631af 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_smbus.h
+++ b/src/southbridge/intel/i82801bx/i82801bx_smbus.h
@@ -110,7 +110,7 @@ static int do_smbus_read_byte(unsigned device, unsigned address)
return byte;
}
-/* This function is neither used nor tested by me (Corey Osgood), the author
+/* This function is neither used nor tested by me (Corey Osgood), the author
(Yinghai) probably tested/used it on i82801er */
static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd,
unsigned data1, unsigned data2)
diff --git a/src/southbridge/intel/i82801cx/chip.h b/src/southbridge/intel/i82801cx/chip.h
index 99b069e82d..88415e0556 100644
--- a/src/southbridge/intel/i82801cx/chip.h
+++ b/src/southbridge/intel/i82801cx/chip.h
@@ -1,7 +1,7 @@
#ifndef I82801CX_CHIP_H
#define I82801CX_CHIP_H
-struct southbridge_intel_i82801cx_config
+struct southbridge_intel_i82801cx_config
{
};
extern struct chip_operations southbridge_intel_i82801cx_ops;
diff --git a/src/southbridge/intel/i82801cx/i82801cx.c b/src/southbridge/intel/i82801cx/i82801cx.c
index ddbbc7da37..685c931fc8 100644
--- a/src/southbridge/intel/i82801cx/i82801cx.c
+++ b/src/southbridge/intel/i82801cx/i82801cx.c
@@ -19,7 +19,7 @@ void i82801cx_enable(device_t dev)
// Calculate disable bit position for specified device:function
// NOTE: For ICH-3, only the following devices can be disabled:
- // D31:F1, D31:F3, D31:F5, D31:F6,
+ // D31:F1, D31:F3, D31:F5, D31:F6,
// D29:F0, D29:F1, D29:F2
if (PCI_SLOT(dev->path.pci.devfn) == 31) {
diff --git a/src/southbridge/intel/i82801cx/i82801cx.h b/src/southbridge/intel/i82801cx/i82801cx.h
index ea7d858d14..e0d377a9cd 100644
--- a/src/southbridge/intel/i82801cx/i82801cx.h
+++ b/src/southbridge/intel/i82801cx/i82801cx.h
@@ -70,9 +70,9 @@ void i82801cx_hard_reset(void);
#define SMBTRNSADD 9
#define SMBSLVDATA 10
#define SMLINK_PIN_CTL 14
-#define SMBUS_PIN_CTL 15
+#define SMBUS_PIN_CTL 15
-/* Between 1-10 seconds, We should never timeout normally
+/* Between 1-10 seconds, We should never timeout normally
* Longer than this is just painful when a timeout condition occurs.
*/
#define SMBUS_TIMEOUT (100*1000)
diff --git a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
index 02420ef75b..b62db80f9c 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
@@ -10,9 +10,9 @@ static void enable_smbus(void)
pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
/* Set smbus enable */
pci_write_config8(dev, HOSTC, HST_EN);
- /* Set smbus iospace enable */
+ /* Set smbus iospace enable */
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- /* Disable interrupt generation */
+ /* Disable interrupt generation */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
@@ -55,7 +55,7 @@ static int smbus_wait_until_ready(void)
}
if(loops == (SMBUS_TIMEOUT / 2)) {
// Clear status flags
- outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
+ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
SMBUS_IO_BASE + SMBHSTSTAT);
}
} while(--loops);
@@ -69,7 +69,7 @@ static int smbus_wait_until_done(void)
do {
unsigned char val;
smbus_delay();
-
+
val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
// !HOST_BUSY?
if ( (val & 1) == 0) {
@@ -92,7 +92,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
if (smbus_wait_until_ready() < 0) {
return -2;
}
-
+
/* setup transaction */
/* disable interrupts */
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
diff --git a/src/southbridge/intel/i82801cx/i82801cx_lpc.c b/src/southbridge/intel/i82801cx/i82801cx_lpc.c
index 7523b03f80..97b2994abf 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_lpc.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_lpc.c
@@ -23,7 +23,7 @@
#define MAINBOARD_POWER_ON 1
-static void i82801cx_enable_ioapic( struct device *dev)
+static void i82801cx_enable_ioapic( struct device *dev)
{
uint32_t dword;
volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000;
@@ -36,12 +36,12 @@ static void i82801cx_enable_ioapic( struct device *dev)
dword |= (1 << 2); /* DMA collection buf enable */
pci_write_config32(dev, GEN_CNTL, dword);
printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword);
-
+
// Must program the APIC's ID before using it
*ioapic_index = 0; // Select APIC ID register
*ioapic_data = (2<<24);
-
+
// Hang if the ID didn't take (chip not present?)
*ioapic_index = 0;
dword = *ioapic_data;
@@ -65,11 +65,11 @@ static void i82801cx_enable_serial_irqs( struct device *dev)
// Parameters: dev
// mask - identifies whether each channel should be used for PCI DMA
// (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
-// Channel 4 is not used (reserved).
+// Channel 4 is not used (reserved).
// Return Value: None
// Description: Route all DMA channels to either PCI or LPC.
//
-static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
+static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
{
uint16_t dmaConfig;
int channelIndex;
@@ -105,13 +105,13 @@ static void i82801cx_rtc_init(struct device *dev)
pmcon3 |= SLEEP_AFTER_POWER_FAIL;
}
pci_write_config8(dev, GEN_PMCON_3, pmcon3);
- printk(BIOS_INFO, "set power %s after power fail\n",
+ printk(BIOS_INFO, "set power %s after power fail\n",
pwr_on ? "on" : "off");
// See if the Safe Mode jumper is set
dword = pci_read_config32(dev, GEN_STS);
rtc_failed |= dword & (1 << 2);
-
+
rtc_init(rtc_failed);
}
@@ -120,28 +120,28 @@ static void i82801cx_1f0_misc(struct device *dev)
{
// Prevent LPC disabling, enable parity errors, and SERR# (System Error)
pci_write_config16(dev, PCI_COMMAND, 0x014f);
-
+
// Set ACPI base address to 0x1100 (I/O space)
pci_write_config32(dev, PMBASE, 0x00001101);
-
+
// Enable ACPI I/O and power management
pci_write_config8(dev, ACPI_CNTL, 0x10);
-
+
// Set GPIO base address to 0x1180 (I/O space)
pci_write_config32(dev, GPIO_BASE, 0x00001181);
-
+
// Enable GPIO
pci_write_config8(dev, GPIO_CNTL, 0x10);
-
+
// Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10
pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
-
+
// Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted.
pci_write_config8(dev, PIRQE_ROUT, 0x07);
-
+
// Enable access to the upper 128 byte bank of CMOS RAM
pci_write_config8(dev, RTC_CONF, 0x04);
-
+
// Decode 0x3F8-0x3FF (COM1) for COMA port,
// 0x2F8-0x2FF (COM2) for COMB
pci_write_config8(dev, COM_DEC, 0x10);
@@ -149,7 +149,7 @@ static void i82801cx_1f0_misc(struct device *dev)
// LPT decode defaults to 0x378-0x37F and 0x778-0x77F
// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
- // Enable COMA, COMB, LPT, floppy;
+ // Enable COMA, COMB, LPT, floppy;
// disable microcontroller, Super I/O, sound, gameport
pci_write_config16(dev, LPC_EN, 0x000F);
}
@@ -164,7 +164,7 @@ static void lpc_init(struct device *dev)
i82801cx_enable_ioapic(dev);
i82801cx_enable_serial_irqs(dev);
-
+
/* power after power fail */
/* FIXME this doesn't work! */
/* Which state do we want to goto after g3 (power restored)?
@@ -187,11 +187,11 @@ static void lpc_init(struct device *dev)
byte = inb(0x70);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
- if (nmi_option) {
+ if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
outb(byte, 0x70);
}
-
+
/* Initialize the real time clock */
i82801cx_rtc_init(dev);
diff --git a/src/southbridge/intel/i82801cx/i82801cx_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_smbus.c
index b69bbc1d9d..324f82f286 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_smbus.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_smbus.c
@@ -9,7 +9,7 @@
void smbus_enable(void)
{
/* iobase addr */
- pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE,
+ pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE,
SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
/* smbus enable */
pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN);
@@ -31,13 +31,13 @@ static void smbus_wait_until_ready(void)
static void smbus_wait_until_done(void)
{
unsigned char byte;
-
+
// Loop while HOST_BUSY
do {
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}
while((byte &1) == 1);
-
+
// Wait for SUCCESS or error or BYTE_DONE
while( (byte & ~1) == 0) {
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
diff --git a/src/southbridge/intel/i82801cx/i82801cx_usb.c b/src/southbridge/intel/i82801cx/i82801cx_usb.c
index 00b668d023..28cb3572e5 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_usb.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_usb.c
@@ -12,8 +12,8 @@ static void usb_init(struct device *dev)
uint32_t cmd;
printk(BIOS_DEBUG, "USB: Setting up controller.. ");
cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND,
- cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+ pci_write_config32(dev, PCI_COMMAND,
+ cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c
index 282ccfd247..ac904efa29 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.c
+++ b/src/southbridge/intel/i82801dx/i82801dx.c
@@ -38,7 +38,7 @@ void i82801dx_enable(device_t dev)
// Calculate disable bit position for specified device:function
// NOTE: For ICH-4, only the following devices can be disabled:
- // D31: F0, F1, F3, F5, F6,
+ // D31: F0, F1, F3, F5, F6,
// D29: F0, F1, F2, F7
if (PCI_SLOT(dev->path.pci.devfn) == 31) {
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index 885f9de0f1..1b995b1204 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -20,11 +20,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/* the problem: we have 82801dbm support in fb1, and 82801er in fb2.
- * fb1 code is what we want, fb2 structure is needed however.
- * so we need to get fb1 code for 82801dbm into fb2 structure.
+/* the problem: we have 82801dbm support in fb1, and 82801er in fb2.
+ * fb1 code is what we want, fb2 structure is needed however.
+ * so we need to get fb1 code for 82801dbm into fb2 structure.
*/
-/* What I did: took the 80801er stuff from fb2, verify it against the
+/* What I did: took the 80801er stuff from fb2, verify it against the
* db stuff in fb1, and made sure it was right.
*/
@@ -132,9 +132,9 @@ extern void i82801dx_enable(device_t dev);
#define SMBTRNSADD 0x9
#define SMBSLVDATA 0xa
#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
+#define SMBUS_PIN_CTL 0xf
-/* Between 1-10 seconds, We should never timeout normally
+/* Between 1-10 seconds, We should never timeout normally
* Longer than this is just painful when a timeout condition occurs.
*/
#define SMBUS_TIMEOUT (100*1000)
diff --git a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
index 16c6e11e72..f58cd86342 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
@@ -32,7 +32,7 @@
#define SMLINK_PIN_CTL 0xe
#define SMBUS_PIN_CTL 0xf
-/* Between 1-10 seconds, We should never timeout normally
+/* Between 1-10 seconds, We should never timeout normally
* Longer than this is just painful when a timeout condition occurs.
*/
//#define SMBUS_TIMEOUT (100*1000*10)
diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h
index 34a0a97ffd..f04fc3fd29 100644
--- a/src/southbridge/intel/i82801ex/chip.h
+++ b/src/southbridge/intel/i82801ex/chip.h
@@ -1,7 +1,7 @@
#ifndef I82801EX_CHIP_H
#define I82801EX_CHIP_H
-struct southbridge_intel_i82801ex_config
+struct southbridge_intel_i82801ex_config
{
#define ICH5R_GPIO_USE_MASK 0x03
diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c
index bc5f04bf44..fc4164523a 100644
--- a/src/southbridge/intel/i82801ex/i82801ex.c
+++ b/src/southbridge/intel/i82801ex/i82801ex.c
@@ -25,7 +25,7 @@ void i82801ex_enable(device_t dev)
(lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_LPC)) {
uint32_t id;
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
- if (id != (PCI_VENDOR_ID_INTEL |
+ if (id != (PCI_VENDOR_ID_INTEL |
(PCI_DEVICE_ID_INTEL_82801ER_LPC << 16))) {
return;
}
@@ -39,7 +39,7 @@ void i82801ex_enable(device_t dev)
if (reg != reg_old) {
pci_write_config16(lpc_dev, 0xf2, reg);
}
-
+
}
struct chip_operations southbridge_intel_i82801ex_ops = {
diff --git a/src/southbridge/intel/i82801ex/i82801ex_ac97.c b/src/southbridge/intel/i82801ex/i82801ex_ac97.c
index 65502dd8cc..08efe1534d 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_ac97.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_ac97.c
@@ -8,7 +8,7 @@
static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* Write the subsystem vendor and device id */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
diff --git a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
index 27bd3f2324..b07c77a94f 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
@@ -35,7 +35,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va
if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
return;
}
-
+
print_debug("Unimplemented smbus_write_byte() called.\n");
#if 0
@@ -60,11 +60,11 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va
/* poll for transaction completion */
smbus_wait_until_done(SMBUS_IO_BASE);
-#endif
+#endif
return;
}
-static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
+static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
unsigned data1, unsigned data2)
{
unsigned char byte;
@@ -73,11 +73,11 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
/* chear the PM timeout flags, SECOND_TO_STS */
outw(inw(0x0400 + 0x66), 0x0400 + 0x66);
-
+
if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
return -2;
}
-
+
/* setup transaction */
/* Obtain ownership */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
@@ -88,39 +88,39 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
/* disable interrupts */
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
-
+
/* set the device I'm talking too */
outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
-
+
/* set the command address */
outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
-
+
/* set the block length */
outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0);
-
+
/* try sending out the first byte of data here */
byte=(data1>>(0))&0x0ff;
outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
/* issue a block write command */
- outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
+ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
SMBUS_IO_BASE + SMBHSTCTL);
for(i=0;i<length;i++) {
-
+
/* poll for transaction completion */
if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
return -3;
}
-
+
/* load the next byte */
if(i>3)
byte=(data2>>(i%4))&0x0ff;
else
byte=(data1>>(i))&0x0ff;
outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
-
+
/* clear the done bit */
- outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
+ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
SMBUS_IO_BASE + SMBHSTSTAT);
}
diff --git a/src/southbridge/intel/i82801ex/i82801ex_ehci.c b/src/southbridge/intel/i82801ex/i82801ex_ehci.c
index 17da5d94c6..8ae921d194 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_ehci.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_ehci.c
@@ -11,7 +11,7 @@ static void ehci_init(struct device *dev)
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND,
+ pci_write_config32(dev, PCI_COMMAND,
cmd | PCI_COMMAND_MASTER);
printk(BIOS_DEBUG, "done.\n");
@@ -24,7 +24,7 @@ static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
/* Enable writes to protected registers */
pci_write_config8(dev, 0x80, access_cntl | 1);
/* Write the subsystem vendor and device id */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
/* Restore protection */
pci_write_config8(dev, 0x80, access_cntl);
diff --git a/src/southbridge/intel/i82801ex/i82801ex_ide.c b/src/southbridge/intel/i82801ex/i82801ex_ide.c
index cd622907ab..bbab6f1cc0 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_ide.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_ide.c
@@ -19,7 +19,7 @@ static void ide_init(struct device *dev)
static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* This value is also visible in uchi[0-2] and smbus functions */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
diff --git a/src/southbridge/intel/i82801ex/i82801ex_lpc.c b/src/southbridge/intel/i82801ex/i82801ex_lpc.c
index b97af3860a..8753db17e3 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_lpc.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_lpc.c
@@ -89,7 +89,7 @@ static void set_i82801ex_gpio_direction(
switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) {
case ICH5R_GPIO_SEL_OUTPUT: val = 0; break;
case ICH5R_GPIO_SEL_INPUT: val = 1; break;
- default:
+ default:
continue;
}
/* The caller is responsible for not playing with unimplemented bits */
@@ -121,7 +121,7 @@ static void set_i82801ex_gpio_level(
case ICH5R_GPIO_LVL_LOW: val = 0; blink = 0; break;
case ICH5R_GPIO_LVL_HIGH: val = 1; blink = 0; break;
case ICH5R_GPIO_LVL_BLINK: val = 1; blink = 1; break;
- default:
+ default:
continue;
}
/* The caller is responsible for not playing with unimplemented bits */
@@ -152,7 +152,7 @@ static void set_i82801ex_gpio_inv(
switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) {
case ICH5R_GPIO_INV_OFF: val = 0; break;
case ICH5R_GPIO_INV_ON: val = 1; break;
- default:
+ default:
continue;
}
gpio_inv &= ~( 1 << i);
@@ -195,7 +195,7 @@ static void i82801ex_gpio_init(device_t dev)
/* Find the GPIO bar */
res = find_resource(dev, GPIO_BAR);
if (!res) {
- return;
+ return;
}
/* Set the use selects */
@@ -271,7 +271,7 @@ static void lpc_init(struct device *dev)
/* Set up the PIRQ */
i82801ex_pirq_init(dev);
-
+
/* Set the state of the gpio lines */
i82801ex_gpio_init(dev);
@@ -283,7 +283,7 @@ static void lpc_init(struct device *dev)
/* Disable IDE (needed when sata is enabled) */
pci_write_config8(dev, 0xf2, 0x60);
-
+
enable_hpet(dev);
}
@@ -330,7 +330,7 @@ static void i82801ex_lpc_enable_resources(device_t dev)
acpi_cntl = pci_read_config8(dev, 0x44);
acpi_cntl |= (1 << 4);
pci_write_config8(dev, 0x44, acpi_cntl);
-
+
/* Enable the GPIO bar */
gpio_cntl = pci_read_config8(dev, 0x5c);
gpio_cntl |= (1 << 4);
diff --git a/src/southbridge/intel/i82801ex/i82801ex_pci.c b/src/southbridge/intel/i82801ex/i82801ex_pci.c
index 2394844ba4..80c6e49bc0 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_pci.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_pci.c
@@ -21,8 +21,8 @@ static void pci_init(struct device *dev)
dword |= (1<<8); /* SERR# Enable */
dword |= (1<<6); /* Parity Error Response */
pci_write_config32(dev, 0x04, dword);
-#endif
-
+#endif
+
word = pci_read_config16(dev, 0x1e);
word |= 0xf800; /* Clear possible errors */
pci_write_config16(dev, 0x1e, word);
diff --git a/src/southbridge/intel/i82801ex/i82801ex_sata.c b/src/southbridge/intel/i82801ex/i82801ex_sata.c
index a490f2a8c3..9b340e9afd 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_sata.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_sata.c
@@ -11,7 +11,7 @@ static void sata_init(struct device *dev)
/* SATA configuration */
pci_write_config8(dev, 0x04, 0x07);
pci_write_config8(dev, 0x09, 0x8f);
-
+
/* Set timmings */
pci_write_config16(dev, 0x40, 0x0a307);
pci_write_config16(dev, 0x42, 0x0a307);
@@ -25,10 +25,10 @@ static void sata_init(struct device *dev)
/* Combine ide - sata configuration */
pci_write_config8(dev, 0x90, 0x0);
-
+
/* port 0 & 1 enable */
pci_write_config8(dev, 0x92, 0x33);
-
+
/* initialize SATA */
pci_write_config16(dev, 0xa0, 0x0018);
pci_write_config32(dev, 0xa4, 0x00000264);
diff --git a/src/southbridge/intel/i82801ex/i82801ex_smbus.h b/src/southbridge/intel/i82801ex/i82801ex_smbus.h
index 27acca494f..f330c0a5de 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_smbus.h
+++ b/src/southbridge/intel/i82801ex/i82801ex_smbus.h
@@ -10,7 +10,7 @@
#define SMBTRNSADD 0x9
#define SMBSLVDATA 0xa
#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
+#define SMBUS_PIN_CTL 0xf
#define SMBUS_TIMEOUT (100*1000*10)
diff --git a/src/southbridge/intel/i82801ex/i82801ex_uhci.c b/src/southbridge/intel/i82801ex/i82801ex_uhci.c
index fe80079d09..56536b7273 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_uhci.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_uhci.c
@@ -12,7 +12,7 @@ static void uhci_init(struct device *dev)
#if 1
printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND,
+ pci_write_config32(dev, PCI_COMMAND,
cmd | PCI_COMMAND_MASTER);
diff --git a/src/southbridge/intel/i82801gx/i82801gx_azalia.c b/src/southbridge/intel/i82801gx/i82801gx_azalia.c
index a4cf14c4f9..5899ad6c0e 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_azalia.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_azalia.c
@@ -96,7 +96,7 @@ u32 cim_verb_data_size = 0;
static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb)
{
int idx=0;
-
+
while (idx < (cim_verb_data_size / sizeof(u32))) {
u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
if (cim_verb_data[idx] != viddid) {
diff --git a/src/southbridge/intel/i82870/p64h2_ioapic.c b/src/southbridge/intel/i82870/p64h2_ioapic.c
index b2523ff436..0f998dda9e 100644
--- a/src/southbridge/intel/i82870/p64h2_ioapic.c
+++ b/src/southbridge/intel/i82870/p64h2_ioapic.c
@@ -39,9 +39,9 @@ static void p64h2_ioapic_init(device_t dev)
num_p64h2_ioapics++;
// A note on IOAPIC addresses:
- // 0 and 1 are used for the local APICs of the dual virtual
+ // 0 and 1 are used for the local APICs of the dual virtual
// (hyper-threaded) CPUs of physical CPU 0 (mainboard/Config.lb).
- // 6 and 7 are used for the local APICs of the dual virtual
+ // 6 and 7 are used for the local APICs of the dual virtual
// (hyper-threaded) CPUs of physical CPU 1 (mainboard/Config.lb).
// 2 is used for the IOAPIC in the 82801 Southbridge (hard-coded in i82801xx_lpc.c)
@@ -63,7 +63,7 @@ static void p64h2_ioapic_init(device_t dev)
pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n",
- apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
+ apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
apic_id <<= 24; // Convert ID to bitmask
@@ -72,13 +72,13 @@ static void p64h2_ioapic_init(device_t dev)
*pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id; // Set the ID
if ((*pWindowRegister & (0xF<<24)) != apic_id)
- die("p64h2_ioapic_init failed");
+ die("p64h2_ioapic_init failed");
*pIndexRegister = 3; // Select Boot Configuration register
*pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts
if (!(*pWindowRegister & 1))
- die("p64h2_ioapic_init failed");
+ die("p64h2_ioapic_init failed");
}
static struct device_operations ioapic_ops = {
diff --git a/src/southbridge/intel/i82870/p64h2_pcibridge.c b/src/southbridge/intel/i82870/p64h2_pcibridge.c
index a489fe53f9..89b86f5966 100644
--- a/src/southbridge/intel/i82870/p64h2_pcibridge.c
+++ b/src/southbridge/intel/i82870/p64h2_pcibridge.c
@@ -35,5 +35,5 @@ static const struct pci_driver pcix_driver __pci_driver = {
.ops = &pcix_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82870_1F0,
-};
-
+};
+
diff --git a/src/southbridge/intel/pxhd/pxhd_bridge.c b/src/southbridge/intel/pxhd/pxhd_bridge.c
index 0a50e5a994..683ff20013 100644
--- a/src/southbridge/intel/pxhd/pxhd_bridge.c
+++ b/src/southbridge/intel/pxhd/pxhd_bridge.c
@@ -56,10 +56,10 @@ static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max)
word &= ~(3 << 9);
word |= (2 << 9);
pci_write_config16(dev, 0x40, word);
-
+
/* reset the bus to make the new frequencies effective */
pci_bus_reset(&dev->link[0]);
- }
+ }
return pcix_scan_bridge(dev, max);
}
static void pcix_init(device_t dev)
@@ -78,7 +78,7 @@ static void pcix_init(device_t dev)
byte = pci_read_config8(dev, 0x04);
byte |= 0x10;
pci_write_config8(dev, 0x04, byte);
-
+
/* Set drive strength */
word = pci_read_config16(dev, 0xe0);
word = 0x0404;
@@ -86,7 +86,7 @@ static void pcix_init(device_t dev)
word = pci_read_config16(dev, 0xe4);
word = 0x0404;
pci_write_config16(dev, 0xe4, word);
-
+
/* Set impedance */
word = pci_read_config16(dev, 0xe8);
word = 0x0404;
@@ -96,7 +96,7 @@ static void pcix_init(device_t dev)
word = pci_read_config16(dev, 0x4c);
word |= 1;
pci_write_config16(dev, 0x4c, word);
-
+
/* Set split transaction limits */
word = pci_read_config16(dev, 0xa8);
pci_write_config16(dev, 0xaa, word);
@@ -108,12 +108,12 @@ static void pcix_init(device_t dev)
dword = pci_read_config32(dev, 0x04);
dword |= (1<<8);
pci_write_config32(dev, 0x04, dword);
-
+
/* system and error parity enable */
dword = pci_read_config32(dev, 0x3c);
dword |= (3<<16);
pci_write_config32(dev, 0x3c, dword);
-
+
/* NMI enable */
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
@@ -122,7 +122,7 @@ static void pcix_init(device_t dev)
dword |= (1<<0);
pci_write_config32(dev, 0x44, dword);
}
-
+
/* Set up CRC flood enable */
dword = pci_read_config32(dev, 0xc0);
if(dword) { /* do device A only */
@@ -133,7 +133,7 @@ static void pcix_init(device_t dev)
dword |= (1<<1);
pci_write_config32(dev, 0xc8, dword);
}
-
+
return;
#endif
}
@@ -175,7 +175,7 @@ static void ioapic_init(device_t dev)
static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
@@ -197,14 +197,14 @@ static const struct pci_driver ioapic_driver __pci_driver = {
.ops = &ioapic_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x0326,
-
+
};
static const struct pci_driver ioapic2_driver __pci_driver = {
.ops = &ioapic_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x0327,
-
+
};
struct chip_operations southbridge_intel_pxhd_ops = {
diff --git a/src/southbridge/nvidia/mcp55/mcp55_fadt.c b/src/southbridge/nvidia/mcp55/mcp55_fadt.c
index 8d80409719..753a663239 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_fadt.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_fadt.c
@@ -34,7 +34,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
device_t dev;
- int is_mcp55 = 0;
+ int is_mcp55 = 0;
dev = dev_find_device(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_LPC, 0);
if (dev)
@@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->preferred_pm_profile = 1; //check
fadt->sci_int = 9;
/* disable system management mode by setting to 0 */
- fadt->smi_cmd = 0x0; //pm_base+0x42e; (value from proprietary acpi fadt)
+ fadt->smi_cmd = 0x0; //pm_base+0x42e; (value from proprietary acpi fadt)
fadt->acpi_enable = 0xa1;
fadt->acpi_disable = 0xa0;
fadt->s4bios_req = 0x0;
@@ -92,7 +92,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
- fadt->duty_width = 3;
+ fadt->duty_width = 3;
fadt->day_alrm = 0x7d;
fadt->mon_alrm = 0x7e;
fadt->century = 0x32;
diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
index 84612890e9..1d2a066b1b 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
@@ -65,7 +65,7 @@ static void lpc_common_init(device_t dev, int master)
if (master)
setup_ioapic(ioapic_base, 0);
- else
+ else
clear_ioapic(ioapic_base);
}
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index c276389bf7..70d74f5fab 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -51,7 +51,7 @@ static void rl5c476_init(device_t dev)
printk(BIOS_DEBUG, "CF boot not enabled.\n");
return;
}
-
+
if (PCI_FUNC(dev->path.pci.devfn) != 1) {
// Only configure if second CF slot.
return;
@@ -154,8 +154,8 @@ static void rl5c476_init(device_t dev)
cptr = (unsigned char *)(cf_base + 0x200);
printk(BIOS_DEBUG, "CF Config = %x\n",*cptr);
- /* Set CF to decode 16 IO bytes on any 16 byte boundary -
- * rely on the io windows of the bridge set up above to
+ /* Set CF to decode 16 IO bytes on any 16 byte boundary -
+ * rely on the io windows of the bridge set up above to
* map those bytes into the addresses for IDE controller 3
* (0x1e8 - 0x1ef and 0x3ed - 0x3ee)
*/
@@ -167,10 +167,10 @@ static void rl5c476_read_resources(device_t dev)
struct resource *resource;
- /* For CF socket we need an extra memory window for
+ /* For CF socket we need an extra memory window for
* the control structure of the CF itself
*/
- if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
+ if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
/* fake index as it isn't in PCI config space */
resource = new_resource(dev, 1);
resource->flags |= IORESOURCE_MEM;
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h
index 2ade87214c..576578bb65 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.h
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.h
@@ -93,5 +93,5 @@ typedef struct pc16reg {
u8 smpga0;
} __attribute__ ((packed)) pc16reg_t;
-
+
diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/sis966_lpc.c
index fc73e39431..2efc3802b2 100644
--- a/src/southbridge/sis/sis966/sis966_lpc.c
+++ b/src/southbridge/sis/sis966/sis966_lpc.c
@@ -281,7 +281,7 @@ static const struct pci_driver lpc_driver __pci_driver = {
.device = PCI_DEVICE_ID_SIS_SIS966_LPC,
};
-#ifdef SLAVE_INIT // No device?
+#ifdef SLAVE_INIT // No device?
static struct device_operations lpc_slave_ops = {
.read_resources = sis966_lpc_read_resources,
.set_resources = pci_dev_set_resources,
diff --git a/src/southbridge/via/k8t890/k8t890_bridge.c b/src/southbridge/via/k8t890/k8t890_bridge.c
index e30cf60b4d..3e1e81730d 100644
--- a/src/southbridge/via/k8t890/k8t890_bridge.c
+++ b/src/southbridge/via/k8t890/k8t890_bridge.c
@@ -32,14 +32,14 @@ static void bridge_enable(struct device *dev)
writeback(dev, 0x40, 0x91);
writeback(dev, 0x41, 0x40);
writeback(dev, 0x43, 0x44);
- writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet
- * says it is reserved
+ writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet
+ * says it is reserved
*/
writeback(dev, 0x45, 0x3a);
writeback(dev, 0x46, 0x88); /* PCI ID lo */
writeback(dev, 0x47, 0xb1); /* PCI ID hi */
- /* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP
+ /* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP
* (Forward VGA compatible memory and I/O cycles )
*/
diff --git a/src/southbridge/via/k8t890/k8t890_ctrl.c b/src/southbridge/via/k8t890/k8t890_ctrl.c
index ad17fe624d..48aa739257 100644
--- a/src/southbridge/via/k8t890/k8t890_ctrl.c
+++ b/src/southbridge/via/k8t890/k8t890_ctrl.c
@@ -23,7 +23,7 @@
#include <device/pci_ids.h>
#include <console/console.h>
-/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
+/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
* PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
*/
diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c
index 0505a6ff5a..037f5a75eb 100644
--- a/src/southbridge/via/k8t890/k8t890_early_car.c
+++ b/src/southbridge/via/k8t890/k8t890_early_car.c
@@ -38,7 +38,7 @@ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
/* This functions sets KT890 link frequency and width to same values as
* it has been setup on K8 side, by AMD NB init.
- */
+ */
u8 k8t890_early_setup_ht(void)
{
@@ -115,7 +115,7 @@ u8 k8t890_early_setup_ht(void)
static int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
{
-
+
printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
switch (size) {
case 1:
diff --git a/src/southbridge/via/k8t890/k8t890_host_ctrl.c b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
index 38f69680fe..a1c42b7d59 100644
--- a/src/southbridge/via/k8t890/k8t890_host_ctrl.c
+++ b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
@@ -52,7 +52,7 @@ static void host_ctrl_enable_k8t890(struct device *dev)
pci_write_config8(dev, 0xa6, 0x80);
/* this will be possibly removed, when I figure out
- * if the ROM SIP is good, second reason is that the
+ * if the ROM SIP is good, second reason is that the
* unknown bits are AGP related, which are dummy on K8T890
*/
diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc
index 9642aa4d5c..aaaa76694d 100644
--- a/src/southbridge/via/k8t890/romstrap.inc
+++ b/src/southbridge/via/k8t890/romstrap.inc
@@ -48,7 +48,7 @@ tblpointer:
.long 0x0
.long 0x0
.long 0x0
-.long 0x0
+.long 0x0
/*
* The pointer to above table should be at 0xffffd,
diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c
index 43238ec050..85f007a097 100644
--- a/src/southbridge/via/vt8231/vt8231.c
+++ b/src/southbridge/via/vt8231/vt8231.c
@@ -18,7 +18,7 @@ static void keyboard_on(void)
if (lpc_dev) {
regval = pci_read_config8(lpc_dev, 0x51);
- regval |= 0x0f;
+ regval |= 0x0f;
pci_write_config8(lpc_dev, 0x51, regval);
}
pc_keyboard_init(0);
@@ -27,9 +27,9 @@ static void keyboard_on(void)
static void com_port_on(void)
{
#if 0
- // enable com1 and com2.
+ // enable com1 and com2.
enables = pci_read_config8(dev, 0x6e);
-
+
/* 0x80 is enable com port b, 0x10 is to make it com2, 0x8
* is enable com port a as com1 kevinh/Ispiri - Old code
* thought 0x01 would make it com1, that was wrong enables =
diff --git a/src/southbridge/via/vt8231/vt8231_acpi.c b/src/southbridge/via/vt8231/vt8231_acpi.c
index 6cbf4c591f..647910aef6 100644
--- a/src/southbridge/via/vt8231/vt8231_acpi.c
+++ b/src/southbridge/via/vt8231/vt8231_acpi.c
@@ -10,20 +10,20 @@ static void acpi_init(struct device *dev)
// Set ACPI base address to IO 0x4000
pci_write_config32(dev, 0x48, 0x4001);
-
+
// Enable ACPI access (and setup like award)
pci_write_config8(dev, 0x41, 0x84);
-
+
// Set hardware monitor base address to IO 0x6000
pci_write_config32(dev, 0x70, 0x6001);
-
+
// Enable hardware monitor (and setup like award)
pci_write_config8(dev, 0x74, 0x01);
-
+
// set IO base address to 0x5000
pci_write_config32(dev, 0x90, 0x5001);
-
- // Enable SMBus
+
+ // Enable SMBus
pci_write_config8(dev, 0xd2, 0x01);
}
diff --git a/src/southbridge/via/vt8231/vt8231_early_serial.c b/src/southbridge/via/vt8231/vt8231_early_serial.c
index 5b38b8e521..af5a7729ee 100644
--- a/src/southbridge/via/vt8231/vt8231_early_serial.c
+++ b/src/southbridge/via/vt8231/vt8231_early_serial.c
@@ -8,18 +8,18 @@
#define SIO_BASE 0x3f0
#define SIO_DATA SIO_BASE+1
-static void vt8231_writesuper(uint8_t reg, uint8_t val)
+static void vt8231_writesuper(uint8_t reg, uint8_t val)
{
outb(reg, SIO_BASE);
outb(val, SIO_DATA);
}
-static void vt8231_writesiobyte(uint16_t reg, uint8_t val)
+static void vt8231_writesiobyte(uint16_t reg, uint8_t val)
{
outb(val, reg);
}
-static void vt8231_writesioword(uint16_t reg, uint16_t val)
+static void vt8231_writesioword(uint16_t reg, uint16_t val)
{
outw(val, reg);
}
@@ -29,26 +29,26 @@ static void vt8231_writesioword(uint16_t reg, uint16_t val)
mainboard
*/
-static void enable_vt8231_serial(void)
+static void enable_vt8231_serial(void)
{
uint8_t c;
device_t dev;
outb(6, 0x80);
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
-
+
if (dev == PCI_DEV_INVALID) {
outb(7, 0x80);
die("Serial controller not found\n");
}
-
- /* first, you have to enable the superio and superio config.
+
+ /* first, you have to enable the superio and superio config.
put a 6 reg 80
*/
c = pci_read_config8(dev, 0x50);
c |= 6;
pci_write_config8(dev, 0x50, c);
outb(2, 0x80);
- // now go ahead and set up com1.
+ // now go ahead and set up com1.
// set address
vt8231_writesuper(0xf4, 0xfe);
// enable serial out
diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c
index 40ef656c00..8ba72a387b 100644
--- a/src/southbridge/via/vt8231/vt8231_early_smbus.c
+++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c
@@ -35,7 +35,7 @@ static void enable_smbus(void)
// set IO base address to SMBUS_IO_BASE
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
- // Enable SMBus
+ // Enable SMBus
c = pci_read_config8(dev, 0xd2);
c |= 5;
pci_write_config8(dev, 0xd2, c);
@@ -244,7 +244,7 @@ static unsigned char smbus_read_byte(unsigned char devAdr, unsigned char bIndex)
}
#endif
-/* for reference, here is the fancier version which we will use at some
+/* for reference, here is the fancier version which we will use at some
* point
*/
# if 0
diff --git a/src/southbridge/via/vt8231/vt8231_ide.c b/src/southbridge/via/vt8231/vt8231_ide.c
index c1df5ef5cd..46479c4af3 100644
--- a/src/southbridge/via/vt8231/vt8231_ide.c
+++ b/src/southbridge/via/vt8231/vt8231_ide.c
@@ -18,7 +18,7 @@ static void ide_init(struct device *dev)
* or it is possibly a timing issue. Ben Hewson 29 Apr 2007.
*/
- /*
+ /*
printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", __func__);
enables = pci_read_config8(dev, 0x42);
printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables);
@@ -28,73 +28,73 @@ static void ide_init(struct device *dev)
printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables);
*/
}
-
+
enables = pci_read_config8(dev, 0x40);
printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables);
enables |= 3;
pci_write_config8(dev, 0x40, enables);
enables = pci_read_config8(dev, 0x40);
printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
-
+
// Enable prefetch buffers
enables = pci_read_config8(dev, 0x41);
enables |= 0xf0;
pci_write_config8(dev, 0x41, enables);
-
+
// Lower thresholds (cause award does it)
enables = pci_read_config8(dev, 0x43);
enables &= ~0x0f;
enables |= 0x05;
pci_write_config8(dev, 0x43, enables);
-
+
// PIO read prefetch counter (cause award does it)
pci_write_config8(dev, 0x44, 0x18);
-
+
// Use memory read multiple
pci_write_config8(dev, 0x45, 0x1c);
-
- // address decoding.
+
+ // address decoding.
// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
- // kevinh@ispiri.com - the standard linux drivers seem ass slow when
+ // kevinh@ispiri.com - the standard linux drivers seem ass slow when
// used in native mode - I've changed back to classic
enables = pci_read_config8(dev, 0x9);
printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables);
- // by the book, set the low-order nibble to 0xa.
+ // by the book, set the low-order nibble to 0xa.
if (conf->enable_native_ide) {
enables &= ~0xf;
- // cf/cg silicon needs an 'f' here.
+ // cf/cg silicon needs an 'f' here.
enables |= 0xf;
} else {
enables &= ~0x5;
}
-
+
pci_write_config8(dev, 0x9, enables);
enables = pci_read_config8(dev, 0x9);
printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables);
-
- // standard bios sets master bit.
+
+ // standard bios sets master bit.
enables = pci_read_config8(dev, 0x4);
printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables);
enables |= 7;
-
+
// No need for stepping - kevinh@ispiri.com
enables &= ~0x80;
-
+
pci_write_config8(dev, 0x4, enables);
enables = pci_read_config8(dev, 0x4);
printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
-
+
if (!conf->enable_native_ide) {
// Use compatability mode - per award bios
pci_write_config32(dev, 0x10, 0x0);
pci_write_config32(dev, 0x14, 0x0);
pci_write_config32(dev, 0x18, 0x0);
pci_write_config32(dev, 0x1c, 0x0);
-
+
// Force interrupts to use compat mode - just like Award bios
pci_write_config8(dev, 0x3d, 00);
pci_write_config8(dev, 0x3c, 0xff);
- }
+ }
}
static struct device_operations ide_ops = {
diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/vt8231_lpc.c
index 6c517ff492..c874528dec 100644
--- a/src/southbridge/via/vt8231/vt8231_lpc.c
+++ b/src/southbridge/via/vt8231/vt8231_lpc.c
@@ -25,7 +25,7 @@ static void pci_routing_fixup(struct device *dev)
printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
if (dev) {
/* initialize PCI interupts - these assignments depend
- on the PCB routing of PINTA-D
+ on the PCB routing of PINTA-D
PINTA = IRQ11
PINTB = IRQ5
@@ -61,60 +61,60 @@ static void vt8231_init(struct device *dev)
enables = pci_read_config8(dev, 0x6C);
enables |= 0x80;
pci_write_config8(dev, 0x6C, enables);
-
+
// Map 4MB of FLASH into the address space
pci_write_config8(dev, 0x41, 0x7f);
-
+
// Set bit 6 of 0x40, because Award does it (IO recovery time)
- // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
+ // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
// interrupts can be properly marked as level triggered.
enables = pci_read_config8(dev, 0x40);
pci_write_config8(dev, 0x40, enables);
-
+
// Set 0x42 to 0xf0 to match Award bios
enables = pci_read_config8(dev, 0x42);
enables |= 0xf0;
pci_write_config8(dev, 0x42, enables);
-
+
// Set bit 3 of 0x4a, to match award (dummy pci request)
enables = pci_read_config8(dev, 0x4a);
enables |= 0x08;
pci_write_config8(dev, 0x4a, enables);
-
+
// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
enables = pci_read_config8(dev, 0x4f);
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
-
+
// Set 0x58 to 0x03 to match Award
pci_write_config8(dev, 0x58, 0x03);
-
+
// enable the ethernet/RTC
if (dev) {
enables = pci_read_config8(dev, 0x51);
- enables |= 0x18;
+ enables |= 0x18;
pci_write_config8(dev, 0x51, enables);
}
// enable IDE, since Linux won't do it.
// First do some more things to devfn (17,0)
- // note: this should already be cleared, according to the book.
+ // note: this should already be cleared, according to the book.
enables = pci_read_config8(dev, 0x50);
printk(BIOS_DEBUG, "IDE enable in reg. 50 is 0x%x\n", enables);
enables &= ~8; // need manifest constant here!
printk(BIOS_DEBUG, "set IDE reg. 50 to 0x%x\n", enables);
pci_write_config8(dev, 0x50, enables);
-
+
// set default interrupt values (IDE)
enables = pci_read_config8(dev, 0x4c);
printk(BIOS_DEBUG, "IRQs in reg. 4c are 0x%x\n", enables & 0xf);
- // clear out whatever was there.
+ // clear out whatever was there.
enables &= ~0xf;
enables |= 4;
printk(BIOS_DEBUG, "setting reg. 4c to 0x%x\n", enables);
pci_write_config8(dev, 0x4c, enables);
-
- // set up the serial port interrupts.
+
+ // set up the serial port interrupts.
// com2 to 3, com1 to 4
pci_write_config8(dev, 0x46, 0x04);
pci_write_config8(dev, 0x47, 0x03);
@@ -123,7 +123,7 @@ static void vt8231_init(struct device *dev)
/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
//ethernet_fixup();
-
+
// Start the rtc
rtc_init(0);
}
diff --git a/src/southbridge/via/vt8231/vt8231_nic.c b/src/southbridge/via/vt8231/vt8231_nic.c
index d4771f6816..5cd6cd8ca1 100644
--- a/src/southbridge/via/vt8231/vt8231_nic.c
+++ b/src/southbridge/via/vt8231/vt8231_nic.c
@@ -5,7 +5,7 @@
#include <device/pci_ids.h>
/*
- * Enable the ethernet device and turn off stepping (because it is integrated
+ * Enable the ethernet device and turn off stepping (because it is integrated
* inside the southbridge)
*/
static void nic_init(struct device *dev)
diff --git a/src/southbridge/via/vt8231/vt8231_usb.c b/src/southbridge/via/vt8231/vt8231_usb.c
index 3dd0b4272b..e12a8db85a 100644
--- a/src/southbridge/via/vt8231/vt8231_usb.c
+++ b/src/southbridge/via/vt8231/vt8231_usb.c
@@ -9,7 +9,7 @@ static void usb_on(int enable)
device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
/* USB controller 2 */
device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
-
+
/* enable USB1 */
if(dev2) {
if (enable) {
@@ -20,16 +20,16 @@ static void usb_on(int enable)
pci_write_config8(dev2, 0x04, 0x00);
}
}
-
+
if(dev0) {
regval = pci_read_config8(dev0, 0x50);
- if (enable)
- regval &= ~(0x10);
+ if (enable)
+ regval &= ~(0x10);
else
- regval |= 0x10;
+ regval |= 0x10;
pci_write_config8(dev0, 0x50, regval);
}
-
+
/* enable USB2 */
if(dev3) {
if (enable) {
@@ -40,13 +40,13 @@ static void usb_on(int enable)
pci_write_config8(dev3, 0x04, 0x00);
}
}
-
+
if(dev0) {
regval = pci_read_config8(dev0, 0x50);
- if (enable)
- regval &= ~(0x20);
+ if (enable)
+ regval &= ~(0x20);
else
- regval |= 0x20;
+ regval |= 0x20;
pci_write_config8(dev0, 0x50, regval);
}
}
diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c
index 747c2157f1..4fa2784661 100644
--- a/src/southbridge/via/vt8235/vt8235.c
+++ b/src/southbridge/via/vt8235/vt8235.c
@@ -12,7 +12,7 @@ static void keyboard_on(struct device *dev)
u8 regval;
regval = pci_read_config8(dev, 0x51);
- regval |= 0x05;
+ regval |= 0x05;
regval &= 0xfd;
pci_write_config8(dev, 0x51, regval);
@@ -23,7 +23,7 @@ static void keyboard_on(struct device *dev)
void dump_south(device_t dev0)
{
int i,j;
-
+
for(i = 0; i < 256; i += 16) {
printk(BIOS_DEBUG, "0x%x: ", i);
for(j = 0; j < 16; j++) {
@@ -51,10 +51,10 @@ static void vt8235_enable(struct device *dev)
model = pci_read_config16(dev,0x2);
printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model);
-
+
/* If this is not the southbridge itself just return.
* This is necessary because USB devices are slot 10, whereas this
- * device is slot 11 therefore usb devices get called first during
+ * device is slot 11 therefore usb devices get called first during
* the bus scan. We don't want to wait until we could do dev->init
* because that's too late.
*/
@@ -69,13 +69,13 @@ static void vt8235_enable(struct device *dev)
/* enable RTC and ethernet */
regval = pci_read_config8(dev, 0x51);
- regval |= 0x18;
+ regval |= 0x18;
pci_write_config8(dev, 0x51, regval);
/* turn on keyboard */
keyboard_on(dev);
- /* enable USB 1.1 & USB 2.0 - redundant really since we've
+ /* enable USB 1.1 & USB 2.0 - redundant really since we've
* already been there - see note above
*/
regval = pci_read_config8(dev, 0x50);
diff --git a/src/southbridge/via/vt8235/vt8235_early_serial.c b/src/southbridge/via/vt8235/vt8235_early_serial.c
index 7823172485..11f98fae39 100644
--- a/src/southbridge/via/vt8235/vt8235_early_serial.c
+++ b/src/southbridge/via/vt8235/vt8235_early_serial.c
@@ -8,25 +8,25 @@
#define SIO_BASE 0x3f0
#define SIO_DATA SIO_BASE+1
-static void vt8235_writepnpaddr(uint8_t val)
+static void vt8235_writepnpaddr(uint8_t val)
{
outb(val, 0x2e);
outb(val, 0xeb);
}
-static void vt8235_writepnpdata(uint8_t val)
+static void vt8235_writepnpdata(uint8_t val)
{
outb(val, 0x2f);
outb(val, 0xeb);
}
-static void vt8235_writesiobyte(uint16_t reg, uint8_t val)
+static void vt8235_writesiobyte(uint16_t reg, uint8_t val)
{
outb(val, reg);
}
-static void vt8235_writesioword(uint16_t reg, uint16_t val)
+static void vt8235_writesioword(uint16_t reg, uint16_t val)
{
outw(val, reg);
}
@@ -36,12 +36,12 @@ static void vt8235_writesioword(uint16_t reg, uint16_t val)
mainboard
*/
-static void enable_vt8235_serial(void)
+static void enable_vt8235_serial(void)
{
// turn on pnp
vt8235_writepnpaddr(0x87);
vt8235_writepnpaddr(0x87);
- // now go ahead and set up com1.
+ // now go ahead and set up com1.
// set address
vt8235_writepnpaddr(0x7);
vt8235_writepnpdata(0x2);
diff --git a/src/southbridge/via/vt8235/vt8235_early_smbus.c b/src/southbridge/via/vt8235/vt8235_early_smbus.c
index db403eb5fb..1876461a3d 100644
--- a/src/southbridge/via/vt8235/vt8235_early_smbus.c
+++ b/src/southbridge/via/vt8235/vt8235_early_smbus.c
@@ -12,7 +12,7 @@
#define SMBTRNSADD 0x9
#define SMBSLVDATA 0xa
#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
+#define SMBUS_PIN_CTL 0xf
/* Define register settings */
#define HOST_RESET 0xff
@@ -34,17 +34,17 @@ static void enable_smbus(void)
/* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8235), 0);
-
+
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
- }
+ }
// set IO base address to SMBUS_IO_BASE
pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
-
- // Enable SMBus
+
+ // Enable SMBus
pci_write_config8(dev, 0xd2, (0x4 << 1) | 1);
-
+
/* make it work for I/O ...
*/
pci_write_config16(dev, 4, 1);
@@ -55,13 +55,13 @@ static void enable_smbus(void)
for(i = 0 ; i < 5000 ; i++)
outb(0x80,0x80);
- /*
+ /*
* The VT1211 serial port needs 48 mhz clock, on power up it is getting
* only 24 mhz, there is some mysterious device on the smbus that can
* fix this...this code below does it.
* */
- outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
- outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0);
+ outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
+ outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0);
outb(0x83, SMBUS_IO_BASE+SMBHSTCMD);
outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD);
outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL);
@@ -92,7 +92,7 @@ static int smbus_wait_until_ready(void)
print_debug_hex8(c);
print_debug("\n");
c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
- /* nop */
+ /* nop */
}
} while(--loops);
@@ -105,13 +105,13 @@ void smbus_reset(void)
outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
-
+
smbus_wait_until_ready();
print_debug("After reset status ");
print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
print_debug("\n");
}
-
+
static int smbus_wait_until_done(void)
@@ -121,11 +121,11 @@ static int smbus_wait_until_done(void)
loops = SMBUS_TIMEOUT;
do {
smbus_delay();
-
+
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
if (byte & 1)
break;
-
+
} while(--loops);
return loops?0:-1;
}
@@ -156,46 +156,46 @@ static void smbus_print_error(unsigned char host_status_register)
/* SMBus routines borrowed from VIA's Trident Driver */
/* this works, so I am not going to touch it for now -- rgm */
-static unsigned char smbus_read_byte(unsigned char devAdr,
- unsigned char bIndex)
+static unsigned char smbus_read_byte(unsigned char devAdr,
+ unsigned char bIndex)
{
unsigned short i;
unsigned char bData;
unsigned char sts = 0;
-
+
/* clear host status */
outb(0xff, SMBUS_IO_BASE);
-
+
/* check SMBUS ready */
for ( i = 0; i < 0xFFFF; i++ )
if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )
break;
-
+
/* set host command */
outb(bIndex, SMBUS_IO_BASE+3);
-
+
/* set slave address */
outb(devAdr | 0x01, SMBUS_IO_BASE+4);
-
+
/* start */
outb(0x48, SMBUS_IO_BASE+2);
-
+
/* SMBUS Wait Ready */
for ( i = 0; i < 0xFFFF; i++ )
if ( ((sts = (inb(SMBUS_IO_BASE) & 0x1f)) & 0x01) == 0 )
break;
-
+
if ((sts & ~3) != 0) {
smbus_print_error(sts);
return 0;
}
bData=inb(SMBUS_IO_BASE+5);
-
+
return bData;
-
+
}
-/* for reference, here is the fancier version which we will use at some
+/* for reference, here is the fancier version which we will use at some
* point
*/
# if 0
@@ -203,11 +203,11 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
{
unsigned char host_status_register;
unsigned char byte;
-
+
reset();
-
+
smbus_wait_until_ready();
-
+
/* setup transaction */
/* disable interrupts */
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
@@ -218,29 +218,29 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
/* set up for a byte data read */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
SMBUS_IO_BASE + SMBHSTCTL);
-
+
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-
+
/* clear the data byte...*/
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
-
+
/* start the command */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
SMBUS_IO_BASE + SMBHSTCTL);
-
+
/* poll for transaction completion */
smbus_wait_until_done();
-
+
host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-
+
/* Ignore the In Use Status... */
host_status_register &= ~(1 << 6);
-
+
/* read results of transaction */
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
smbus_print_error(byte);
-
+
*result = byte;
return host_status_register != 0x02;
}
diff --git a/src/southbridge/via/vt8235/vt8235_ide.c b/src/southbridge/via/vt8235/vt8235_ide.c
index ec22f9053b..961f860fed 100644
--- a/src/southbridge/via/vt8235/vt8235_ide.c
+++ b/src/southbridge/via/vt8235/vt8235_ide.c
@@ -28,69 +28,69 @@ static void ide_init(struct device *dev)
printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n",
enables);
/* } */
-
+
enables = pci_read_config8(dev, 0x40);
printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables);
enables |= 3;
pci_write_config8(dev, 0x40, enables);
enables = pci_read_config8(dev, 0x40);
printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
-
+
// Enable prefetch buffers
enables = pci_read_config8(dev, 0x41);
enables |= 0xf0;
pci_write_config8(dev, 0x41, enables);
-
+
// Lower thresholds (cause award does it)
enables = pci_read_config8(dev, 0x43);
enables &= ~0x0f;
enables |= 0x05;
pci_write_config8(dev, 0x43, enables);
-
+
// PIO read prefetch counter (cause award does it)
pci_write_config8(dev, 0x44, 0x18);
-
+
// Use memory read multiple
pci_write_config8(dev, 0x45, 0x1c);
-
- // address decoding.
+
+ // address decoding.
// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
- // kevinh@ispiri.com - the standard linux drivers seem ass slow when
+ // kevinh@ispiri.com - the standard linux drivers seem ass slow when
// used in native mode - I've changed back to classic
enables = pci_read_config8(dev, 0x9);
printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables);
- // by the book, set the low-order nibble to 0xa.
+ // by the book, set the low-order nibble to 0xa.
if (conf->enable_native_ide) {
enables &= ~0xf;
- // cf/cg silicon needs an 'f' here.
+ // cf/cg silicon needs an 'f' here.
enables |= 0xf;
} else {
enables &= ~0x5;
}
-
+
pci_write_config8(dev, 0x9, enables);
enables = pci_read_config8(dev, 0x9);
printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables);
-
- // standard bios sets master bit.
+
+ // standard bios sets master bit.
enables = pci_read_config8(dev, 0x4);
printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables);
enables |= 7;
-
+
// No need for stepping - kevinh@ispiri.com
enables &= ~0x80;
-
+
pci_write_config8(dev, 0x4, enables);
enables = pci_read_config8(dev, 0x4);
printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
-
+
if (!conf->enable_native_ide) {
// Use compatability mode - per award bios
pci_write_config32(dev, 0x10, 0x0);
pci_write_config32(dev, 0x14, 0x0);
pci_write_config32(dev, 0x18, 0x0);
pci_write_config32(dev, 0x1c, 0x0);
-
+
// Force interrupts to use compat mode - just like Award bios
pci_write_config8(dev, 0x3d, 0x0);
pci_write_config8(dev, 0x3c, 0xff);
@@ -103,10 +103,10 @@ static struct device_operations ide_ops = {
.enable_resources = pci_dev_enable_resources,
.init = ide_init,
.enable = 0,
- .ops_pci = 0,
+ .ops_pci = 0,
};
-static const struct pci_driver northbridge_driver __pci_driver = {
+static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &ide_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_82C586_1,
diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/vt8235_lpc.c
index 0746bc9a13..e2bfc3681e 100644
--- a/src/southbridge/via/vt8235/vt8235_lpc.c
+++ b/src/southbridge/via/vt8235/vt8235_lpc.c
@@ -88,7 +88,7 @@ static void pci_routing_fixup(struct device *dev)
printk(BIOS_INFO, "setting pci slot\n");
pci_assign_irqs(0, 0x14, pin_to_irq(slotPins));
- // Cardbus slot
+ // Cardbus slot
printk(BIOS_INFO, "setting cardbus slot\n");
pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins));
@@ -99,11 +99,11 @@ static void pci_routing_fixup(struct device *dev)
printk(BIOS_SPEW, "%s: DONE\n", __func__);
}
-/*
+/*
* Set up the power management capabilities directly into ACPI mode. This
* avoids having to handle any System Management Interrupts (SMI's) which I
* can't figure out how to do !!!!
- */
+ */
static void setup_pm(device_t dev)
{
@@ -112,7 +112,7 @@ static void setup_pm(device_t dev)
// Set ACPI base address to IO 0x4000
pci_write_config16(dev, 0x88, 0x0401);
-
+
// set ACPI irq to 5
pci_write_config8(dev, 0x82, 0x45);
@@ -138,7 +138,7 @@ static void setup_pm(device_t dev)
outw(0xffff, 0x420);
outw(0xffff, 0x428);
outl(0xffffffff, 0x430);
-
+
outw(0x0, 0x424);
outw(0x0, 0x42a);
outw(0x1, 0x42c);
@@ -152,29 +152,29 @@ static void setup_pm(device_t dev)
static void vt8235_init(struct device *dev)
{
unsigned char enables;
-
+
printk(BIOS_DEBUG, "vt8235 init\n");
// enable the internal I/O decode
enables = pci_read_config8(dev, 0x6C);
enables |= 0x80;
pci_write_config8(dev, 0x6C, enables);
-
+
// Map 4MB of FLASH into the address space
pci_write_config8(dev, 0x41, 0x7f);
-
+
// Set bit 6 of 0x40, because Award does it (IO recovery time)
- // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
+ // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
// interrupts can be properly marked as level triggered.
enables = pci_read_config8(dev, 0x40);
enables |= 0x45;
pci_write_config8(dev, 0x40, enables);
-
+
// Set 0x42 to 0xf0 to match Award bios
enables = pci_read_config8(dev, 0x42);
enables |= 0xf0;
pci_write_config8(dev, 0x42, enables);
-
+
/* Set 0x58 to 0x03 to match Award */
pci_write_config8(dev, 0x58, 0x03);
@@ -187,16 +187,16 @@ static void vt8235_init(struct device *dev)
enables = pci_read_config8(dev, 0x4a);
enables |= 0x08;
pci_write_config8(dev, 0x4a, enables);
-
+
// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
enables = pci_read_config8(dev, 0x4f);
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
-
+
// Set 0x58 to 0x03 to match Award
pci_write_config8(dev, 0x58, 0x03);
-
-
+
+
/* enable serial irq */
pci_write_config8(dev, 0x52, 0x9);
@@ -205,10 +205,10 @@ static void vt8235_init(struct device *dev)
// Power management setup
setup_pm(dev);
-
+
/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
-
+
// Start the rtc
rtc_init(0);
}
@@ -248,7 +248,7 @@ static void vt8235_enable_resources(device_t dev)
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);
}
-
+
static void southbridge_init(struct device *dev)
{
vt8235_init(dev);
diff --git a/src/southbridge/via/vt8235/vt8235_nic.c b/src/southbridge/via/vt8235/vt8235_nic.c
index 86fef895de..71f169c055 100644
--- a/src/southbridge/via/vt8235/vt8235_nic.c
+++ b/src/southbridge/via/vt8235/vt8235_nic.c
@@ -5,7 +5,7 @@
#include <device/pci_ids.h>
/*
- * Enable the ethernet device and turn off stepping (because it is integrated
+ * Enable the ethernet device and turn off stepping (because it is integrated
* inside the southbridge)
*/
static void nic_init(struct device *dev)
diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
index aa75f50651..9f824437bf 100644
--- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
+++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
@@ -171,10 +171,10 @@ void enable_smbus(void)
}
/**
- * A fixup for some systems that need time for the SMBus to "warm up". This is
- * needed on some VT823x based systems, where the SMBus spurts out bad data for
- * a short time after power on. This has been seen on the VIA Epia series and
- * Jetway J7F2-series. It reads the ID byte from SMBus, looking for
+ * A fixup for some systems that need time for the SMBus to "warm up". This is
+ * needed on some VT823x based systems, where the SMBus spurts out bad data for
+ * a short time after power on. This has been seen on the VIA Epia series and
+ * Jetway J7F2-series. It reads the ID byte from SMBus, looking for
* known-good data from a slot/address. Exits on either good data or a timeout.
*
* TODO: This should probably go into some global file, but one would need to
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index f7acb75766..5a08e3b16f 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -187,7 +187,7 @@ static void setup_pm(device_t dev)
* 6 = SUSST# Deasserted Before PWRGD for STD
* 5 = Keyboard/Mouse Swap
* 4 = PWRGOOD reset on VT8237A/S
- * 3 = GPO26/GPO27 is GPO
+ * 3 = GPO26/GPO27 is GPO
* 2 = Disable Alert on Lan
* 1 = SUSCLK/GPO4
* 0 = USB Wakeup
@@ -247,7 +247,7 @@ static void setup_pm(device_t dev)
static void vt8237r_init(struct device *dev)
{
u8 enables;
-
+
#if CONFIG_EPIA_VT8237R_INIT
printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");
/*
@@ -260,9 +260,9 @@ static void vt8237r_init(struct device *dev)
enables = pci_read_config8(dev, 0xe5);
enables |= 0x23;
pci_write_config8(dev, 0xe5, enables);
-
- /*
- * Enable Flash Write Access.
+
+ /*
+ * Enable Flash Write Access.
* Note EPIA-N Does not use REQ5 or PCISTP#(Hang)
*/
enables = pci_read_config8(dev, 0xe4);
@@ -274,14 +274,14 @@ static void vt8237r_init(struct device *dev)
enables |= 0x80;
pci_write_config8(dev, 0x4E, enables);
-#else
+#else
printk(BIOS_SPEW, "Entering vt8237r_init.\n");
/*
* Enable SATA LED, disable special CPU Frequency Change -
* GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
*/
pci_write_config8(dev, 0xe5, 0x09);
-
+
/* REQ5 as PCI request input - should be together with INTE-INTH. */
pci_write_config8(dev, 0xe4, 0x4);
#endif
@@ -329,7 +329,7 @@ static void vt8237s_init(struct device *dev)
(VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
/*
- * REQ5 as PCI request input - should be together with INTE-INTH.
+ * REQ5 as PCI request input - should be together with INTE-INTH.
*/
pci_write_config8(dev, 0xe4, 0x04);