diff options
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/lpc.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 7 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/lpc.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/lpc.c | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/sch/lpc.c | 6 |
7 files changed, 38 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0ecd3895ce..19e540738c 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -678,6 +678,7 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion(); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); @@ -686,6 +687,9 @@ static void southbridge_inject_dsdt(void) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + #if CONFIG_CHROMEOS chromeos_init_vboot(&(gnvs->chromeos)); #endif diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index e707afac20..73e11e80a6 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -640,11 +640,17 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion(); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); /* IGD OpRegion Base Address */ gnvs->aslb = (u32)opregion; + + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ccaabbaaa3..31ea130b51 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -34,6 +34,7 @@ #include <arch/acpigen.h> #include <cbmem.h> #include <string.h> +#include <drivers/intel/gma/i915.h> #include "nvs.h" #define NMI_OFF 0 @@ -617,12 +618,18 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + memset(gnvs, 0, sizeof(*gnvs)); gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ acpi_create_gnvs(gnvs); + + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index de936a3630..3cc053b19f 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -37,6 +37,7 @@ #include "i82801ix.h" #include "nvs.h" #include <southbridge/intel/common/pciehp.h> +#include <drivers/intel/gma/i915.h> #define NMI_OFF 0 @@ -544,8 +545,13 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); + + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index c33f9d948b..550ef30a30 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -671,6 +671,7 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion(); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); @@ -678,6 +679,8 @@ static void southbridge_inject_dsdt(void) gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); /* IGD OpRegion Base Address */ gnvs->aslb = (u32)opregion; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6b2a522004..c055da5733 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -38,6 +38,7 @@ #include "pch.h" #include <arch/acpigen.h> #include <cbmem.h> +#include <drivers/intel/gma/i915.h> #define NMI_OFF 0 @@ -755,6 +756,8 @@ static void southbridge_inject_dsdt(void) } if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + acpi_create_gnvs(gnvs); gnvs->apic = 1; @@ -768,6 +771,9 @@ static void southbridge_inject_dsdt(void) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + acpi_save_gnvs((unsigned long)gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index f06c149b3d..e40b051361 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -29,6 +29,7 @@ #include <cpu/cpu.h> #include <cbmem.h> #include <string.h> +#include <drivers/intel/gma/i915.h> #include "nvs.h" #include "chip.h" @@ -193,8 +194,13 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); + + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); |