summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/agesa/hudson/reset.c2
-rw-r--r--src/southbridge/amd/amd8111/early_ctrl.c4
-rw-r--r--src/southbridge/amd/amd8111/reset.c2
-rw-r--r--src/southbridge/amd/cimx/sb700/reset.c4
-rw-r--r--src/southbridge/amd/cimx/sb800/reset.c4
-rw-r--r--src/southbridge/amd/cimx/sb900/reset.c4
-rw-r--r--src/southbridge/amd/pi/hudson/reset.c2
-rw-r--r--src/southbridge/amd/sb600/early_setup.c4
-rw-r--r--src/southbridge/amd/sb600/reset.c2
-rw-r--r--src/southbridge/amd/sb700/reset.c4
-rw-r--r--src/southbridge/amd/sb800/early_setup.c4
-rw-r--r--src/southbridge/amd/sb800/reset.c2
-rw-r--r--src/southbridge/broadcom/bcm5785/early_setup.c4
-rw-r--r--src/southbridge/broadcom/bcm5785/reset.c2
-rw-r--r--src/southbridge/intel/bd82x6x/reset.c4
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/reset.c4
-rw-r--r--src/southbridge/intel/fsp_i89xx/reset.c4
-rw-r--r--src/southbridge/intel/fsp_rangeley/reset.c4
-rw-r--r--src/southbridge/intel/i3100/reset.c2
-rw-r--r--src/southbridge/intel/i82801ax/reset.c2
-rw-r--r--src/southbridge/intel/i82801bx/reset.c2
-rw-r--r--src/southbridge/intel/i82801dx/reset.c2
-rw-r--r--src/southbridge/intel/i82801gx/reset.c6
-rw-r--r--src/southbridge/intel/lynxpoint/reset.c4
-rw-r--r--src/southbridge/nvidia/ck804/early_setup.c4
-rw-r--r--src/southbridge/nvidia/ck804/early_setup_car.c4
-rw-r--r--src/southbridge/nvidia/ck804/reset.c2
-rw-r--r--src/southbridge/nvidia/mcp55/early_ctrl.c4
-rw-r--r--src/southbridge/nvidia/mcp55/reset.c2
-rw-r--r--src/southbridge/sis/sis966/early_ctrl.c4
-rw-r--r--src/southbridge/sis/sis966/reset.c2
31 files changed, 50 insertions, 50 deletions
diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c
index 200ec14c2e..e3f36f3309 100644
--- a/src/southbridge/amd/agesa/hudson/reset.c
+++ b/src/southbridge/amd/agesa/hudson/reset.c
@@ -21,7 +21,7 @@
#include <northbridge/amd/amdk8/reset_test.c>
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
index f451003aee..2161669f4f 100644
--- a/src/southbridge/amd/amd8111/early_ctrl.c
+++ b/src/southbridge/amd/amd8111/early_ctrl.c
@@ -38,7 +38,7 @@ static void enable_cf9(void)
enable_cf9_x(sbbusn, sbdn);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* reset */
@@ -71,7 +71,7 @@ static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
}
-void soft_reset(void)
+void do_soft_reset(void)
{
unsigned sblk = get_sblk();
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c
index fd2c82ab5b..fea8891a98 100644
--- a/src/southbridge/amd/amd8111/reset.c
+++ b/src/southbridge/amd/amd8111/reset.c
@@ -37,7 +37,7 @@ static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus)
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void hard_reset(void)
+void do_hard_reset(void)
{
pci_devfn_t dev;
unsigned bus;
diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c
index a5c42b72c9..40e861c215 100644
--- a/src/southbridge/amd/cimx/sb700/reset.c
+++ b/src/southbridge/amd/cimx/sb700/reset.c
@@ -40,7 +40,7 @@ static inline void set_bios_reset(void)
}
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
@@ -50,7 +50,7 @@ void hard_reset(void)
}
//SbReset();
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c
index a5c42b72c9..40e861c215 100644
--- a/src/southbridge/amd/cimx/sb800/reset.c
+++ b/src/southbridge/amd/cimx/sb800/reset.c
@@ -40,7 +40,7 @@ static inline void set_bios_reset(void)
}
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
@@ -50,7 +50,7 @@ void hard_reset(void)
}
//SbReset();
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c
index a5c42b72c9..40e861c215 100644
--- a/src/southbridge/amd/cimx/sb900/reset.c
+++ b/src/southbridge/amd/cimx/sb900/reset.c
@@ -40,7 +40,7 @@ static inline void set_bios_reset(void)
}
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
@@ -50,7 +50,7 @@ void hard_reset(void)
}
//SbReset();
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c
index 200ec14c2e..e3f36f3309 100644
--- a/src/southbridge/amd/pi/hudson/reset.c
+++ b/src/southbridge/amd/pi/hudson/reset.c
@@ -21,7 +21,7 @@
#include <northbridge/amd/amdk8/reset_test.c>
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c
index 2445310e6e..f68bfd51ee 100644
--- a/src/southbridge/amd/sb600/early_setup.c
+++ b/src/southbridge/amd/sb600/early_setup.c
@@ -173,7 +173,7 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
}
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
@@ -182,7 +182,7 @@ void hard_reset(void)
outb(0x0e, 0x0cf9);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
diff --git a/src/southbridge/amd/sb600/reset.c b/src/southbridge/amd/sb600/reset.c
index beb35d11b1..04bf3f4e83 100644
--- a/src/southbridge/amd/sb600/reset.c
+++ b/src/southbridge/amd/sb600/reset.c
@@ -21,7 +21,7 @@
#include <northbridge/amd/amdk8/reset_test.c>
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
index 3c44982e6a..08780399b1 100644
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -44,7 +44,7 @@ static void set_bios_reset(void)
}
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
@@ -56,7 +56,7 @@ void hard_reset(void)
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index c9ae08c755..9ac66fb45d 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -220,7 +220,7 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
pmio_write(0x81, byte);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
@@ -229,7 +229,7 @@ void hard_reset(void)
outb(0x0e, 0x0cf9);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c
index 200ec14c2e..e3f36f3309 100644
--- a/src/southbridge/amd/sb800/reset.c
+++ b/src/southbridge/amd/sb800/reset.c
@@ -21,7 +21,7 @@
#include <northbridge/amd/amdk8/reset_test.c>
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index 6ee4f6b856..72354440c9 100644
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
@@ -105,7 +105,7 @@ void ldtstop_sb(void)
}
-void hard_reset(void)
+void do_hard_reset(void)
{
bcm5785_enable_wdt_port_cf9();
@@ -116,7 +116,7 @@ void hard_reset(void)
outb(0x0e, 0x0cf9);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
bcm5785_enable_wdt_port_cf9();
diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c
index 7511d29ed5..1041aae301 100644
--- a/src/southbridge/broadcom/bcm5785/reset.c
+++ b/src/southbridge/broadcom/bcm5785/reset.c
@@ -21,7 +21,7 @@
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c
index 804fb8137c..7faadb62df 100644
--- a/src/southbridge/intel/bd82x6x/reset.c
+++ b/src/southbridge/intel/bd82x6x/reset.c
@@ -17,12 +17,12 @@
#include <arch/io.h>
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
outb(0x04, 0xcf9);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c
index a2e8236dc5..b1468da64b 100644
--- a/src/southbridge/intel/fsp_bd82x6x/reset.c
+++ b/src/southbridge/intel/fsp_bd82x6x/reset.c
@@ -18,12 +18,12 @@
#include <arch/io.h>
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
outb(0x04, 0xcf9);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/fsp_i89xx/reset.c b/src/southbridge/intel/fsp_i89xx/reset.c
index a2e8236dc5..b1468da64b 100644
--- a/src/southbridge/intel/fsp_i89xx/reset.c
+++ b/src/southbridge/intel/fsp_i89xx/reset.c
@@ -18,12 +18,12 @@
#include <arch/io.h>
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
outb(0x04, 0xcf9);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/fsp_rangeley/reset.c b/src/southbridge/intel/fsp_rangeley/reset.c
index 298dbce4b0..10b82ff4e5 100644
--- a/src/southbridge/intel/fsp_rangeley/reset.c
+++ b/src/southbridge/intel/fsp_rangeley/reset.c
@@ -18,12 +18,12 @@
#include <arch/io.h>
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
hard_reset();
}
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
diff --git a/src/southbridge/intel/i3100/reset.c b/src/southbridge/intel/i3100/reset.c
index 595bed3bac..af000e3e66 100644
--- a/src/southbridge/intel/i3100/reset.c
+++ b/src/southbridge/intel/i3100/reset.c
@@ -17,7 +17,7 @@
#include <arch/io.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/i82801ax/reset.c b/src/southbridge/intel/i82801ax/reset.c
index 74be595e99..25254ca929 100644
--- a/src/southbridge/intel/i82801ax/reset.c
+++ b/src/southbridge/intel/i82801ax/reset.c
@@ -17,7 +17,7 @@
#include <reset.h>
#include <arch/io.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
/* Try rebooting through port 0xcf9. */
outb((1 << 2) | (1 << 1), 0xcf9);
diff --git a/src/southbridge/intel/i82801bx/reset.c b/src/southbridge/intel/i82801bx/reset.c
index 4a82b35863..41b99c704d 100644
--- a/src/southbridge/intel/i82801bx/reset.c
+++ b/src/southbridge/intel/i82801bx/reset.c
@@ -17,7 +17,7 @@
#include <arch/io.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
/* Try rebooting through port 0xcf9. */
outb((1 << 2) | (1 << 1), 0xcf9);
diff --git a/src/southbridge/intel/i82801dx/reset.c b/src/southbridge/intel/i82801dx/reset.c
index a6db91c7ba..1839ad6f9a 100644
--- a/src/southbridge/intel/i82801dx/reset.c
+++ b/src/southbridge/intel/i82801dx/reset.c
@@ -16,7 +16,7 @@
#include <arch/io.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
/* Try rebooting through port 0xcf9 */
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
diff --git a/src/southbridge/intel/i82801gx/reset.c b/src/southbridge/intel/i82801gx/reset.c
index 97b82251f0..e18f3e8ddc 100644
--- a/src/southbridge/intel/i82801gx/reset.c
+++ b/src/southbridge/intel/i82801gx/reset.c
@@ -17,20 +17,20 @@
#include <arch/io.h>
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
outb(0x04, 0xcf9);
}
#if 0
-void hard_reset(void)
+void do_hard_reset(void)
{
/* Try rebooting through port 0xcf9. */
outb((1 << 2) | (1 << 1), 0xcf9);
}
#endif
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
diff --git a/src/southbridge/intel/lynxpoint/reset.c b/src/southbridge/intel/lynxpoint/reset.c
index 804fb8137c..7faadb62df 100644
--- a/src/southbridge/intel/lynxpoint/reset.c
+++ b/src/southbridge/intel/lynxpoint/reset.c
@@ -17,12 +17,12 @@
#include <arch/io.h>
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
outb(0x04, 0xcf9);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c
index 1d4999ccbc..79c9eff050 100644
--- a/src/southbridge/nvidia/ck804/early_setup.c
+++ b/src/southbridge/nvidia/ck804/early_setup.c
@@ -310,7 +310,7 @@ static int ck804_early_setup_x(void)
return set_ht_link_ck804(4);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
@@ -319,7 +319,7 @@ void hard_reset(void)
outb(0x0e, 0x0cf9);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c
index 689f98985f..aeea41b551 100644
--- a/src/southbridge/nvidia/ck804/early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/early_setup_car.c
@@ -357,7 +357,7 @@ static int ck804_early_setup_x(void)
return set_ht_link_ck804(4);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
@@ -366,7 +366,7 @@ void hard_reset(void)
outb(0x0e, 0x0cf9);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c
index ad994dedc4..bcb6dfc8f8 100644
--- a/src/southbridge/nvidia/ck804/reset.c
+++ b/src/southbridge/nvidia/ck804/reset.c
@@ -21,7 +21,7 @@
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9. */
diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c
index 1f80316b8f..cb3e2f0ae5 100644
--- a/src/southbridge/nvidia/mcp55/early_ctrl.c
+++ b/src/southbridge/nvidia/mcp55/early_ctrl.c
@@ -25,7 +25,7 @@
#endif
#include "mcp55.h"
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
@@ -33,7 +33,7 @@ void soft_reset(void)
outb(0x06, 0x0cf9);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c
index a381cd31a9..7be98d7a2f 100644
--- a/src/southbridge/nvidia/mcp55/reset.c
+++ b/src/southbridge/nvidia/mcp55/reset.c
@@ -24,7 +24,7 @@
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c
index 74ae1fa05a..4fb2d9d11b 100644
--- a/src/southbridge/sis/sis966/early_ctrl.c
+++ b/src/southbridge/sis/sis966/early_ctrl.c
@@ -29,7 +29,7 @@ static unsigned get_sbdn(unsigned bus)
return (dev>>15) & 0x1f;
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
@@ -44,7 +44,7 @@ static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
/* set VFSMAF ( VID/FID System Management Action Field) to 2 */
}
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c
index a381cd31a9..7be98d7a2f 100644
--- a/src/southbridge/sis/sis966/reset.c
+++ b/src/southbridge/sis/sis966/reset.c
@@ -24,7 +24,7 @@
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */