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-rw-r--r--src/southbridge/amd/pi/hudson/Kconfig16
-rw-r--r--src/southbridge/amd/pi/hudson/Makefile.inc5
-rw-r--r--src/southbridge/amd/pi/hudson/early_setup.c31
-rw-r--r--src/southbridge/amd/pi/hudson/hudson.h3
4 files changed, 55 insertions, 0 deletions
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index c720791a83..94a313d19d 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -227,3 +227,19 @@ config AZ_PIN
bit 5,4 - pin 2
bit 7,6 - pin 3
endif
+
+config HUDSON_UART
+ bool "UART controller on Kern."
+ default n
+ depends on SOUTHBRIDGE_AMD_PI_KERN
+ select DRIVERS_UART_8250MEM
+ select DRIVERS_UART_8250MEM_32
+ select NO_UART_ON_SUPERIO
+ help
+ There are two UART controllers in Kern.
+ The UART registers are memory-mapped. UART
+ controller 0 registers range from FEDC_6000h
+ to FEDC_6FFFh. UART controller 1 registers
+ range from FEDC_8000h to FEDC_8FFFh.
+
+
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index fb775c50c5..81558d3217 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -50,6 +50,11 @@ romstage-y += imc.c
ramstage-y += imc.c
endif
+ifeq ($(CONFIG_HUDSON_UART), y)
+romstage-y += uart.c
+ramstage-y += uart.c
+endif
+
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 14ffd8b82b..f4fcf8b472 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -26,6 +26,37 @@
#include "hudson.h"
#include "pci_devs.h"
+#if IS_ENABLED(CONFIG_HUDSON_UART)
+
+#include <cpu/x86/msr.h>
+#include <delay.h>
+#include <Fch/Fch.h>
+
+void configure_hudson_uart(void)
+{
+ msr_t msr;
+ u8 byte;
+
+ msr = rdmsr(0x1B);
+ msr.lo |= 1 << 11;
+ wrmsr(0x1B, msr);
+ byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2);
+ byte |= 1 << 3;
+ write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2, byte);
+ byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62);
+ byte |= 1 << 3;
+ write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62, byte);
+ write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);
+ write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0);
+ write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0);
+ write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0);
+
+ udelay(2000);
+ write8((void *)0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88, 0x01); /* reset UART */
+}
+
+#endif
+
void hudson_pci_port80(void)
{
u8 byte;
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 6f37c90ea4..23d9b3135d 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -112,6 +112,9 @@ void hudson_clk_output_48Mhz(void);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
+#if IS_ENABLED(CONFIG_HUDSON_UART)
+void configure_hudson_uart(void);
+#endif
#else
void hudson_enable(device_t dev);