2 files changed, 8 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index d8fd7ad6a5..8ffb22e140 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -286,12 +286,16 @@ static void pch_enable_lpc_decode(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
 }
 
+__weak void mainboard_pch_lpc_setup(void)
+{
+}
+
 void early_pch_init(void)
 {
 
 	pch_enable_lpc_decode();
 
-	pch_enable_lpc();
+	mainboard_pch_lpc_setup();
 
 	pch_enable_bars();
 
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index d4cd86eaa5..127fb61cce 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -75,6 +75,9 @@ void southbridge_rcba_config(void);
 /* Optional mainboard hook to do additional configuration
    on the RCBA config space. It is called after the raminit. */
 void mainboard_late_rcba_config(void);
+/* Optional mainboard hook to do additional LPC configuration
+   or to override what is set up by default. */
+void mainboard_pch_lpc_setup(void);
 void early_pch_init_native(void);
 void early_pch_init(void);
 void early_pch_init_native_dmi_pre(void);