summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i3100/i3100_early_lpc.c20
-rw-r--r--src/southbridge/intel/i3100/i3100_lpc.c2
2 files changed, 21 insertions, 1 deletions
diff --git a/src/southbridge/intel/i3100/i3100_early_lpc.c b/src/southbridge/intel/i3100/i3100_early_lpc.c
index 2fdb3dfa09..fbefcd6acb 100644
--- a/src/southbridge/intel/i3100/i3100_early_lpc.c
+++ b/src/southbridge/intel/i3100/i3100_early_lpc.c
@@ -30,3 +30,23 @@ static void i3100_enable_superio(void)
/* Enable decoding of I/O locations for SuperIO devices */
pci_write_config16(dev, 0x82, 0x340f);
}
+
+static void i3100_halt_tco_timer(void)
+{
+ device_t dev;
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_3100_LPC), 0);
+ if (dev == PCI_DEV_INVALID) {
+ die("LPC bridge not found\r\n");
+ }
+
+ /* Temporarily enable the ACPI I/O range at 0x4000 */
+ pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));
+ pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7));
+
+ /* Halt the TCO timer, preventing SMI and automatic reboot */
+ outw(inw(0x4068) | (1 << 11), 0x4068);
+
+ /* Disable the ACPI I/O range */
+ pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7));
+}
diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c
index 8914ed73de..b4fd5ca6d2 100644
--- a/src/southbridge/intel/i3100/i3100_lpc.c
+++ b/src/southbridge/intel/i3100/i3100_lpc.c
@@ -276,7 +276,7 @@ static void i3100_lpc_enable_resources(device_t dev)
/* Enable the ACPI bar */
acpi_cntl = pci_read_config8(dev, 0x44);
- acpi_cntl |= (1 << 4);
+ acpi_cntl |= (1 << 7);
pci_write_config8(dev, 0x44, acpi_cntl);
/* Enable the GPIO bar */