summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82801gx/smi.c4
-rw-r--r--src/southbridge/intel/i82801gx/smihandler.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c
index 45fcb10307..17a81c1757 100644
--- a/src/southbridge/intel/i82801gx/smi.c
+++ b/src/southbridge/intel/i82801gx/smi.c
@@ -232,9 +232,9 @@ static u32 reset_tco_status(void)
reg32 = inl(tcobase + 0x04);
/* set status bits are cleared by writing 1 to them */
- outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
+ outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
if (reg32 & (1 << 18))
- outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
+ outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS
return reg32;
}
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 6bd9517f42..6075db9e8b 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -248,9 +248,9 @@ static u32 reset_tco_status(void)
reg32 = inl(tcobase + 0x04);
/* set status bits are cleared by writing 1 to them */
- outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
+ outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
if (reg32 & (1 << 18))
- outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
+ outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS
return reg32;
}