diff options
Diffstat (limited to 'src/southbridge')
80 files changed, 47 insertions, 135 deletions
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 23be162507..65810facf3 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 00ca7c67cc..a0319abdf9 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -21,8 +21,7 @@ #define _HUDSON_EARLY_SETUP_C_ #include <stdint.h> -#include <arch/io.h> /* inl, outl */ -#include <arch/romcc_io.h> /* device_t */ +#include <arch/io.h> #include <arch/acpi.h> #include <console/console.h> #include <reset.h> diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index e1e885c4a1..c74ac9ac61 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -18,7 +18,6 @@ */ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "hudson.h" diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index c48aaeb9af..315a065380 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -17,11 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> +#include <reset.h> -#include "../../../northbridge/amd/amdk8/reset_test.c" +#include <northbridge/amd/amdk8/reset_test.c> void hard_reset(void) { diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index 2df1fb9f07..ba3dc431a0 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 8d77d22ce3..fc7f3c52cc 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -19,8 +19,6 @@ #include <arch/io.h> -#include <arch/romcc_io.h> - #if CONFIG_CONSOLE_POST diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index d9ce75aed3..13c6379def 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -17,12 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -//#include <config.h> #include <stdint.h> #include <device/pci_ids.h> -#include <arch/io.h> /* inl, outl */ -#include <arch/romcc_io.h> /* device_t */ +#include <arch/io.h> #include "Platform.h" #include "sb_cimx.h" #include "sb700_cfg.h" /*sb700_cimx_config*/ @@ -30,7 +27,6 @@ #include <console/loglevel.h> #include "smbus.h" - #if CONFIG_RAMINIT_SYSINFO /** * @brief Get SouthBridge device number diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index d21b4fdbfd..ac9351e4c2 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> static void enable_rom(void) { diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 33afdcfe7a..83087f5527 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -17,19 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -//#include <config.h> #include <stdint.h> #include <device/pci_ids.h> #include <arch/io.h> /* inl, outl */ -#include <arch/romcc_io.h> /* device_t */ #include <arch/acpi.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ #include "cbmem.h" - #if CONFIG_RAMINIT_SYSINFO /** * @brief Get SouthBridge device number diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index c88a9fa38c..106f664738 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -17,10 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <arch/io.h> -#include <arch/romcc_io.h> - #if CONFIG_CONSOLE_POST diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 5acbfa03fe..d6036ddd19 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -17,19 +17,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -//#include <config.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <stdint.h> #include <device/pci_ids.h> -#include <arch/io.h> /* inl, outl */ -#include <arch/romcc_io.h> /* device_t */ +#include <arch/io.h> #include "SbPlatform.h" #include "SbEarly.h" #include <console/console.h> #include <console/loglevel.h> #include "smbus.h" - /** * @brief Get SouthBridge device number * @param[in] bus target bus number @@ -39,13 +38,13 @@ u32 get_sbdn(u32 bus) { device_t dev; - printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - Start.\n"); - //dev = PCI_DEV(bus, 0x14, 0); - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB900_SM), - bus); + printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - Start.\n"); + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_ATI_SB900_SM), bus); + + printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - End.\n"); - printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - End.\n"); return (dev >> 15) & 0x1f; } @@ -59,7 +58,7 @@ void sb_poweron_init(void) AMDSBCFG sb_early_cfg; u8 data; - printk(BIOS_INFO, "SB900 - Early.c - sb_poweron_init - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - Start.\n"); //Enable/Disable PCI Bridge Device 14 Function 4. outb(0xEA, 0xCD6); @@ -77,7 +76,7 @@ void sb_poweron_init(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbPowerOnInit(&sb_early_cfg); - printk(BIOS_INFO, "SB900 - Early.c - sb_poweron_init - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - End.\n"); } /** @@ -88,7 +87,7 @@ void sb_before_pci_init(void) { AMDSBCFG sb_early_cfg; - printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - Start.\n"); sb900_cimx_config(&sb_early_cfg); //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; //AmdSbDispatcher(&sb_early_cfg); @@ -96,14 +95,14 @@ void sb_before_pci_init(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbBeforePciInit(&sb_early_cfg); - printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - End.\n"); } void sb_After_Pci_Init(void) { AMDSBCFG sb_early_cfg; - printk(BIOS_INFO, "SB900 - Early.c - sb_After_Pci_Init - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - Start.\n"); sb900_cimx_config(&sb_early_cfg); //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; //AmdSbDispatcher(&sb_early_cfg); @@ -111,14 +110,14 @@ void sb_After_Pci_Init(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbAfterPciInit(&sb_early_cfg); - printk(BIOS_INFO, "SB900 - Early.c - sb_After_Pci_Init - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - End.\n"); } void sb_Mid_Post_Init(void) { AMDSBCFG sb_early_cfg; - printk(BIOS_INFO, "SB900 - Early.c - sb_Mid_Post_Init - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - Start.\n"); sb900_cimx_config(&sb_early_cfg); //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; //AmdSbDispatcher(&sb_early_cfg); @@ -126,7 +125,7 @@ void sb_Mid_Post_Init(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbMidPostInit(&sb_early_cfg); - printk(BIOS_INFO, "SB900 - Early.c - sb_Mid_Post_Init - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - End.\n"); } void sb_Late_Post(void) @@ -134,7 +133,7 @@ void sb_Late_Post(void) AMDSBCFG sb_early_cfg; u8 data; - printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - Start.\n"); sb900_cimx_config(&sb_early_cfg); //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; //AmdSbDispatcher(&sb_early_cfg); @@ -160,7 +159,5 @@ void sb_Late_Post(void) outb(data, 0x4D0); } - printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - End.\n"); } - - diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index e848189df1..e31a96c8e3 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c index 4130dd5545..305362f37d 100644 --- a/src/southbridge/amd/sb600/enable_usbdebug.c +++ b/src/southbridge/amd/sb600/enable_usbdebug.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "sb600.h" diff --git a/src/southbridge/amd/sb600/reset.c b/src/southbridge/amd/sb600/reset.c index 0c94136992..0936516c4d 100644 --- a/src/southbridge/amd/sb600/reset.c +++ b/src/southbridge/amd/sb600/reset.c @@ -17,11 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> #include <reset.h> -#include "northbridge/amd/amdk8/reset_test.c" +#include <northbridge/amd/amdk8/reset_test.c> void hard_reset(void) { diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index cffa5ca1da..c290806911 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index bc6f9107d0..a16fc9f2b2 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <arch/cpu.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/msr.h> @@ -33,7 +32,6 @@ #include "sb700.h" #include "smbus.h" - static void pmio_write(u8 reg, u8 value) { outb(reg, PM_INDEX); diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index a816253439..2a7fc383e4 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "sb700.h" diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index 9203b2bede..ef4115ecbe 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> /* hard_reset, soft_rest*/ -#include <arch/io.h> /* inb, outb */ -#include <arch/romcc_io.h> /* pci_read_config32, device_t, PCI_DEV */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> +#include <reset.h> #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 9d90a34ce0..9311b978f9 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index bdb4bde23c..f085eabecb 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -18,7 +18,6 @@ */ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "sb800.h" diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c index c48aaeb9af..315a065380 100644 --- a/src/southbridge/amd/sb800/reset.c +++ b/src/southbridge/amd/sb800/reset.c @@ -17,11 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> +#include <reset.h> -#include "../../../northbridge/amd/amdk8/reset_test.c" +#include <northbridge/amd/amdk8/reset_test.c> void hard_reset(void) { diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index cc73cec54f..65bce13cf1 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/cpu.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/msr.h> #include "sr5650.h" diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index 23ac1ee90c..166464cfda 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 7f4f577cd6..85a940e2de 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/tsc.h> #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 5b266cc10c..670e1cedf5 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -21,7 +21,6 @@ #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index a626649e2b..9de97e7fe2 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c index ddfc4c2261..6f57f637a9 100644 --- a/src/southbridge/intel/bd82x6x/early_spi.c +++ b/src/southbridge/intel/bd82x6x/early_spi.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index bbe792f908..f4e526d85f 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index be6d480a62..bcc2f3dad9 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/post_codes.h> #include <northbridge/intel/sandybridge/pcie_config.c> #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c index 25eda9a74c..39241d6094 100644 --- a/src/southbridge/intel/bd82x6x/gpio.c +++ b/src/southbridge/intel/bd82x6x/gpio.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include "pch.h" #include "gpio.h" diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index b9aff37d5c..7fdf9261f8 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -38,7 +38,6 @@ #include <elog.h> #ifdef __SMM__ -# include <arch/romcc_io.h> # include <northbridge/intel/sandybridge/pcie_config.c> #else # include <device/device.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index b71f7ea12f..f79adf59c0 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -38,7 +38,6 @@ #include <elog.h> #ifdef __SMM__ -# include <arch/romcc_io.h> # include <northbridge/intel/sandybridge/pcie_config.c> #else # include <device/device.h> diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index f2c7dc1648..37a0b6422c 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -23,7 +23,6 @@ #include <delay.h> #ifdef __SMM__ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #else /* !__SMM__ */ #include <device/device.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 5d5dad1460..545e268a9c 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 4303dd0e7a..09169b1bc8 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -34,7 +34,6 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <arch/romcc_io.h> #include <northbridge/intel/sandybridge/pcie_config.c> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pcie_read_config8(dev, reg) diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c index 607a88c6c0..79a43bd308 100644 --- a/src/southbridge/intel/bd82x6x/usb_debug.c +++ b/src/southbridge/intel/bd82x6x/usb_debug.c @@ -25,7 +25,6 @@ #include "pch.h" #ifdef __PRE_RAM__ -#include <arch/romcc_io.h> void enable_usbdebug(unsigned int port) { u32 dbgctl; diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 135cbc0609..b350bde6a9 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> #include "i82371eb.h" diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index aaf86114e9..a2f055bca7 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <console/console.h> diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index d0abcf4dfb..80a4de9f80 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801ax/early_smbus.c b/src/southbridge/intel/i82801ax/early_smbus.c index dde9f33933..716652a0f4 100644 --- a/src/southbridge/intel/i82801ax/early_smbus.c +++ b/src/southbridge/intel/i82801ax/early_smbus.c @@ -21,7 +21,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801bx/early_smbus.c b/src/southbridge/intel/i82801bx/early_smbus.c index 0522e497b3..26c9e85059 100644 --- a/src/southbridge/intel/i82801bx/early_smbus.c +++ b/src/southbridge/intel/i82801bx/early_smbus.c @@ -21,7 +21,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index ca453a103c..6f4d4f8846 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 1d306da280..61ac901df5 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -21,7 +21,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index fc052068e8..b352fcad03 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> static void enable_spi_prefetch(void) { diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 7744e719dc..b11e4fa16a 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 9d71fa3362..f199b84b65 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -21,7 +21,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c index d5a743c28b..f447f7bb84 100644 --- a/src/southbridge/intel/i82801gx/usb_debug.c +++ b/src/southbridge/intel/i82801gx/usb_debug.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index fc052068e8..b352fcad03 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> static void enable_spi_prefetch(void) { diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index c25c2349ae..0514719344 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/gm45/gm45.h> diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index af2e63f67e..8849cfa2c8 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include "i82801ix.h" void i82801ix_early_init(void) diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 74b36e6ba5..226afac2d7 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 4e8edfe615..913223b0ab 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 2770d55cad..96291189cd 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/tsc.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index e41b801a8b..6b61eac3db 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -21,7 +21,6 @@ #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 3709aed63b..a390d737bc 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <elog.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index a626649e2b..9de97e7fe2 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/early_spi.c b/src/southbridge/intel/lynxpoint/early_spi.c index ddfc4c2261..6f57f637a9 100644 --- a/src/southbridge/intel/lynxpoint/early_spi.c +++ b/src/southbridge/intel/lynxpoint/early_spi.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index b2e009123e..ebd5c2c50a 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c index 2cece13e17..d9bc22531c 100644 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ b/src/southbridge/intel/lynxpoint/finalize.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/post_codes.h> #include <spi-generic.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c index 9d36887dd1..b492068ccd 100644 --- a/src/southbridge/intel/lynxpoint/gpio.c +++ b/src/southbridge/intel/lynxpoint/gpio.c @@ -20,14 +20,8 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> - -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif - #include "pch.h" #include "gpio.h" diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 2d2e0576ea..a6e4f5c998 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -20,12 +20,8 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include "pch.h" #include "lp_gpio.h" diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 2e790fc2a5..a16879b757 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -31,19 +31,14 @@ #include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_def.h> #include <string.h> #include <delay.h> #include <elog.h> -#ifdef __SMM__ -# include <arch/romcc_io.h> -#else -# include <device/device.h> -# include <device/pci.h> -#endif - #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 49f7df8d52..203a1bbfb5 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -23,7 +23,6 @@ #include <types.h> #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/spi.c b/src/southbridge/intel/lynxpoint/spi.c index 123c6a9d62..eaa17d5e21 100644 --- a/src/southbridge/intel/lynxpoint/spi.c +++ b/src/southbridge/intel/lynxpoint/spi.c @@ -34,7 +34,6 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <arch/romcc_io.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/lynxpoint/usb_debug.c b/src/southbridge/intel/lynxpoint/usb_debug.c index 1cee353e2d..d8da7b5484 100644 --- a/src/southbridge/intel/lynxpoint/usb_debug.c +++ b/src/southbridge/intel/lynxpoint/usb_debug.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/sch/early_smbus.c b/src/southbridge/intel/sch/early_smbus.c index 9a015041c0..8adc04df47 100644 --- a/src/southbridge/intel/sch/early_smbus.c +++ b/src/southbridge/intel/sch/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 99ae018770..bbaf4bb7f9 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/sch/usb_debug.c b/src/southbridge/intel/sch/usb_debug.c index 1986258d7c..4189716c08 100644 --- a/src/southbridge/intel/sch/usb_debug.c +++ b/src/southbridge/intel/sch/usb_debug.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index a8d0cc9e33..e2f6bc022d 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c index 993ff2e618..a8c12a2198 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.c +++ b/src/southbridge/nvidia/ck804/early_smbus.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ids.h> diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index c4b62e244d..659fdc68b1 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "ck804.h" diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index 59a0aaece0..431c426d04 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include "mcp55.h" static void mcp55_enable_rom(void) diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c index 4a03a2762b..f753c78538 100644 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "mcp55.h" diff --git a/src/southbridge/rdc/r8610/bootblock.c b/src/southbridge/rdc/r8610/bootblock.c index c87940a495..2e5e360d72 100644 --- a/src/southbridge/rdc/r8610/bootblock.c +++ b/src/southbridge/rdc/r8610/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c index f4cb264472..ac4919aae8 100644 --- a/src/southbridge/sis/sis966/bootblock.c +++ b/src/southbridge/sis/sis966/bootblock.c @@ -25,7 +25,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> #include "sis966.h" diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c index cf19577115..78a3838be7 100644 --- a/src/southbridge/sis/sis966/enable_usbdebug.c +++ b/src/southbridge/sis/sis966/enable_usbdebug.c @@ -25,7 +25,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "sis966.h" diff --git a/src/southbridge/via/vt8231/enable_rom.c b/src/southbridge/via/vt8231/enable_rom.c index f2d0866dc8..618adf8ddf 100644 --- a/src/southbridge/via/vt8231/enable_rom.c +++ b/src/southbridge/via/vt8231/enable_rom.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> static void vt8231_enable_rom(void) diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c index 98297911c4..0d920739e6 100644 --- a/src/southbridge/via/vt8237r/bootblock.c +++ b/src/southbridge/via/vt8237r/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> static void bootblock_southbridge_init(void) diff --git a/src/southbridge/via/vt8237r/smihandler.c b/src/southbridge/via/vt8237r/smihandler.c index 357e517994..d46c4ec7be 100644 --- a/src/southbridge/via/vt8237r/smihandler.c +++ b/src/southbridge/via/vt8237r/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/via/vt82c686/early_serial.c b/src/southbridge/via/vt82c686/early_serial.c index 8ac79d63b2..70b6b545fc 100644 --- a/src/southbridge/via/vt82c686/early_serial.c +++ b/src/southbridge/via/vt82c686/early_serial.c @@ -22,7 +22,7 @@ /* This has been ported to the VIA VT82C686(A/B) from the SMSC FDC37M60x * by Corey Osgood. See vt82c686.h for more information. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include <device/pci_ids.h> #include "vt82c686.h" |