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-rw-r--r--src/southbridge/intel/fsp_rangeley/acpi/soc.asl2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
index b55bd92dd1..dde6796ed0 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
+++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
@@ -93,7 +93,7 @@ Scope(\)
GIO2, 8,
GIO3, 8,
Offset(0x0c), // GPIO Level
- GL00, 1,
+ GP00, 1,
GP01, 1,
GP02, 1,
GP0e, 1,