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-rw-r--r--src/southbridge/amd/amd8111/amd8111_lpc.c84
-rw-r--r--src/southbridge/amd/sb600/sb600_sm.c81
-rw-r--r--src/southbridge/intel/esb6300/esb6300_lpc.c49
-rw-r--r--src/southbridge/intel/esb6300/esb6300_pic.c45
-rw-r--r--src/southbridge/intel/i3100/i3100_lpc.c69
-rw-r--r--src/southbridge/intel/i82801er/i82801er_lpc.c48
-rw-r--r--src/southbridge/intel/pxhd/pxhd_bridge.c55
-rw-r--r--src/southbridge/nvidia/ck804/ck804_lpc.c80
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_lpc.c95
-rw-r--r--src/southbridge/sis/sis966/sis966_lpc.c86
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_lpc.c97
11 files changed, 46 insertions, 743 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c
index 94ef1a44cc..edb32c240c 100644
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -10,91 +10,12 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <cpu/x86/lapic.h>
+#include <arch/ioapic.h>
#include <stdlib.h>
#include "amd8111.h"
#define NMI_OFF 0
-struct ioapicreg {
- unsigned int reg;
- unsigned int value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
- { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
- { 1, DISABLED, NONE},
- { 2, DISABLED, NONE},
- { 3, DISABLED, NONE},
- { 4, DISABLED, NONE},
- { 5, DISABLED, NONE},
- { 6, DISABLED, NONE},
- { 7, DISABLED, NONE},
- { 8, DISABLED, NONE},
- { 9, DISABLED, NONE},
- { 10, DISABLED, NONE},
- { 11, DISABLED, NONE},
- { 12, DISABLED, NONE},
- { 13, DISABLED, NONE},
- { 14, DISABLED, NONE},
- { 15, DISABLED, NONE},
- { 16, DISABLED, NONE},
- { 17, DISABLED, NONE},
- { 18, DISABLED, NONE},
- { 19, DISABLED, NONE},
- { 20, DISABLED, NONE},
- { 21, DISABLED, NONE},
- { 22, DISABLED, NONE},
- { 23, DISABLED, NONE},
- /* Be careful and don't write past the end... */
-};
-
-static void setup_ioapic(void)
-{
- int i;
- unsigned long value_low, value_high;
- unsigned long ioapic_base = 0xfec00000;
- volatile unsigned long *l;
- struct ioapicreg *a = ioapicregvalues;
- unsigned long bsp_apicid = lapicid();
-
- l = (unsigned long *) ioapic_base;
-
- ioapicregvalues[0].value_high = bsp_apicid<<(56-32);
- printk_debug("amd8111: ioapic bsp_apicid = %02lx\n", bsp_apicid);
-
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
- i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg *2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i==0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
- }
-}
-
static void enable_hpet(struct device *dev)
{
unsigned long hpet_address;
@@ -114,7 +35,8 @@ static void lpc_init(struct device *dev)
byte = pci_read_config8(dev, 0x4B);
byte |= 1;
pci_write_config8(dev, 0x4B, byte);
- setup_ioapic();
+ /* Don't rename IO APIC */
+ setup_ioapic(IO_APIC_ADDR, 0);
/* posted memory write enable */
byte = pci_read_config8(dev, 0x46);
diff --git a/src/southbridge/amd/sb600/sb600_sm.c b/src/southbridge/amd/sb600/sb600_sm.c
index b0f99533a2..318c370151 100644
--- a/src/southbridge/amd/sb600/sb600_sm.c
+++ b/src/southbridge/amd/sb600/sb600_sm.c
@@ -27,6 +27,7 @@
#include <bitops.h>
#include <arch/io.h>
#include <cpu/x86/lapic.h>
+#include <arch/ioapic.h>
#include <stdlib.h>
#include "sb600.h"
#include "sb600_smbus.c"
@@ -40,83 +41,6 @@
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-struct ioapicreg {
- u32 reg;
- u32 value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
- {0, DISABLED, NONE},
- {1, DISABLED, NONE},
- {2, DISABLED, NONE},
- {3, DISABLED, NONE},
- {4, DISABLED, NONE},
- {5, DISABLED, NONE},
- {6, DISABLED, NONE},
- {7, DISABLED, NONE},
- {8, DISABLED, NONE},
- {9, DISABLED, NONE},
- {10, DISABLED, NONE},
- {11, DISABLED, NONE},
- {12, DISABLED, NONE},
- {13, DISABLED, NONE},
- {14, DISABLED, NONE},
- {15, DISABLED, NONE},
- {16, DISABLED, NONE},
- {17, DISABLED, NONE},
- {18, DISABLED, NONE},
- {19, DISABLED, NONE},
- {20, DISABLED, NONE},
- {21, DISABLED, NONE},
- {22, DISABLED, NONE},
- {23, DISABLED, NONE},
- /* Be careful and don't write past the end... */
-};
-
-static void setup_ioapic(u32 ioapic_base)
-{
- int i;
- u32 value_low, value_high;
- volatile u32 *l;
- struct ioapicreg *a = ioapicregvalues;
-
- ioapicregvalues[0].value_high = lapicid() << (56 - 32);
-
- printk_debug("lapicid = %016x\n", ioapicregvalues[0].value_high);
-
- l = (u32 *)ioapic_base;
-
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
- i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg * 2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i == 0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- }
-}
-
/*
* SB600 enables all USB controllers by default in SMBUS Control.
* SB600 enables SATA by default in SMBUS Control.
@@ -133,7 +57,8 @@ static void sm_init(device_t dev)
printk_info("sm_init().\n");
ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
- setup_ioapic(ioapic_base);
+ /* Don't rename APIC ID */
+ setup_ioapic(ioapic_base, 0);
dword = pci_read_config8(dev, 0x62);
dword |= 1 << 2;
diff --git a/src/southbridge/intel/esb6300/esb6300_lpc.c b/src/southbridge/intel/esb6300/esb6300_lpc.c
index bae9e715d5..09caeb729f 100644
--- a/src/southbridge/intel/esb6300/esb6300_lpc.c
+++ b/src/southbridge/intel/esb6300/esb6300_lpc.c
@@ -9,6 +9,7 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "esb6300.h"
#define ACPI_BAR 0x40
@@ -22,52 +23,6 @@
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
-
-static void setup_ioapic(device_t dev)
-{
- int i;
- unsigned long value_low, value_high;
- unsigned long ioapic_base = 0xfec00000;
- volatile unsigned long *l;
- unsigned interrupts;
-
- l = (unsigned long *) ioapic_base;
-
- l[0] = 0x01;
- interrupts = (l[04] >> 16) & 0xff;
- for (i = 0; i < interrupts; i++) {
- l[0] = (i * 2) + 0x10;
- l[4] = DISABLED;
- value_low = l[4];
- l[0] = (i * 2) + 0x11;
- l[4] = NONE; /* Should this be an address? */
- value_high = l[4];
- if (value_low == 0xffffffff) {
- printk_warning("%d IO APIC not responding.\n",
- dev_path(dev));
- return;
- }
- }
-
- /* Put the ioapic in virtual wire mode */
- l[0] = 0 + 0x10;
- l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
-}
-
#define SERIRQ_CNTL 0x64
static void esb6300_enable_serial_irqs(device_t dev)
{
@@ -287,7 +242,7 @@ static void lpc_init(struct device *dev)
value |= (1 << 8)|(1<<7);
value |= (6 << 0)|(1<<13)|(1<<11);
pci_write_config32(dev, 0xd0, value);
- setup_ioapic(dev);
+ setup_ioapic(0xfec00000, 0); // don't rename IO APIC ID
/* disable reset timer */
pci_write_config8(dev, 0xd4, 0x02);
diff --git a/src/southbridge/intel/esb6300/esb6300_pic.c b/src/southbridge/intel/esb6300/esb6300_pic.c
index 97635ae524..9d02536cd4 100644
--- a/src/southbridge/intel/esb6300/esb6300_pic.c
+++ b/src/southbridge/intel/esb6300/esb6300_pic.c
@@ -6,50 +6,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
+#include <arch/ioapic.h>
#include "esb6300.h"
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
-
-static void setup_ioapic(device_t dev)
-{
- int i;
- unsigned long value_low, value_high;
- unsigned long ioapic_base = 0xfec10000;
- volatile unsigned long *l;
- unsigned interrupts;
-
- l = (unsigned long *) ioapic_base;
-
- l[0] = 0x01;
- interrupts = (l[04] >> 16) & 0xff;
- for (i = 0; i < interrupts; i++) {
- l[0] = (i * 2) + 0x10;
- l[4] = DISABLED;
- value_low = l[4];
- l[0] = (i * 2) + 0x11;
- l[4] = NONE; /* Should this be an address? */
- value_high = l[4];
- if (value_low == 0xffffffff) {
- printk_warning("%s IO APIC not responding.\n",
- dev_path(dev));
- return;
- }
- }
-}
-
static void pic_init(struct device *dev)
{
@@ -64,7 +23,7 @@ static void pic_init(struct device *dev)
pci_write_config8(dev, 0x3c, 0xff);
/* Setup the ioapic */
- setup_ioapic(dev);
+ clear_ioapic(0xfec10000);
}
static void pic_read_resources(device_t dev)
diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c
index a2d858ef17..e516939fe9 100644
--- a/src/southbridge/intel/i3100/i3100_lpc.c
+++ b/src/southbridge/intel/i3100/i3100_lpc.c
@@ -29,6 +29,7 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i3100.h"
#define ACPI_BAR 0x40
@@ -49,60 +50,6 @@
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
-
-static void setup_ioapic(device_t dev)
-{
- int i;
- u32 value_low, value_high;
- u32 ioapic_base = 0xfec00000;
- volatile u32 *l;
- u32 interrupts;
- struct resource *res;
-
- /* Enable IO APIC */
- res = find_resource(dev, RCBA);
- if (!res) {
- return;
- }
- *((u8 *)(res->base + 0x31ff)) |= (1 << 0);
-
- l = (u32 *) ioapic_base;
-
- l[0] = 0x01;
- interrupts = (l[04] >> 16) & 0xff;
- for (i = 0; i < interrupts; i++) {
- l[0] = (i * 2) + 0x10;
- l[4] = DISABLED;
- value_low = l[4];
- l[0] = (i * 2) + 0x11;
- l[4] = NONE; /* Should this be an address? */
- value_high = l[4];
- if (value_low == 0xffffffff) {
- printk_warning("%d IO APIC not responding.\n",
- dev_path(dev));
- return;
- }
- }
-
- /* Put the APIC in virtual wire mode */
- l[0] = 0x12;
- l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
-}
-
static void i3100_enable_serial_irqs(device_t dev)
{
/* set packet length and toggle silent mode bit */
@@ -363,7 +310,19 @@ static void i3100_gpio_init(device_t dev)
static void lpc_init(struct device *dev)
{
- setup_ioapic(dev);
+ struct resource *res;
+
+ /* Enable IO APIC */
+ res = find_resource(dev, RCBA);
+ if (!res) {
+ return;
+ }
+ *((u8 *)(res->base + 0x31ff)) |= (1 << 0);
+
+ // TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode
+ // (register 0x10/0x11) while the old code used int 1 (register 0x12)
+ // ... Why?
+ setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID
/* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
pci_write_config32(dev, 0xd0, 0x00000000);
diff --git a/src/southbridge/intel/i82801er/i82801er_lpc.c b/src/southbridge/intel/i82801er/i82801er_lpc.c
index 943356c2c1..357e181a9d 100644
--- a/src/southbridge/intel/i82801er/i82801er_lpc.c
+++ b/src/southbridge/intel/i82801er/i82801er_lpc.c
@@ -9,6 +9,7 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801er.h"
#define ACPI_BAR 0x40
@@ -22,51 +23,6 @@
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
-
-static void setup_ioapic(void)
-{
- int i;
- unsigned long value_low, value_high;
- unsigned long ioapic_base = 0xfec00000;
- volatile unsigned long *l;
- unsigned interrupts;
-
- l = (unsigned long *) ioapic_base;
-
- l[0] = 0x01;
- interrupts = (l[04] >> 16) & 0xff;
- for (i = 0; i < interrupts; i++) {
- l[0] = (i * 2) + 0x10;
- l[4] = DISABLED;
- value_low = l[4];
- l[0] = (i * 2) + 0x11;
- l[4] = NONE; /* Should this be an address? */
- value_high = l[4];
- if (value_low == 0xffffffff) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- }
-
- /* Put the ioapic in virtual wire mode */
- l[0] = 0 + 0x10;
- l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
-}
-
#define SERIRQ_CNTL 0x64
static void i82801er_enable_serial_irqs(device_t dev)
{
@@ -292,7 +248,7 @@ static void lpc_init(struct device *dev)
value = pci_read_config32(dev, 0xd4);
value |= (1<<1);
pci_write_config32(dev, 0xd4, value);
- setup_ioapic();
+ setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID.
i82801er_enable_serial_irqs(dev);
diff --git a/src/southbridge/intel/pxhd/pxhd_bridge.c b/src/southbridge/intel/pxhd/pxhd_bridge.c
index 5913063606..1a21a9c03e 100644
--- a/src/southbridge/intel/pxhd/pxhd_bridge.c
+++ b/src/southbridge/intel/pxhd/pxhd_bridge.c
@@ -8,6 +8,7 @@
#include <device/pci_ops.h>
#include <device/pcix.h>
#include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
#include <delay.h>
#include "pxhd.h"
@@ -159,63 +160,17 @@ static const struct pci_driver pcix_driver2 __pci_driver = {
.device = 0x032a,
};
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
-
-static void setup_ioapic(device_t dev)
-{
- int i;
- unsigned long value_low, value_high;
- unsigned long ioapic_base;
- volatile unsigned long *l;
- unsigned interrupts;
-
- ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- l = (unsigned long *) ioapic_base;
-
- /* Enable front side bus delivery */
- l[0] = 0x03;
- l[4] = 1;
-
- l[0] = 0x01;
- interrupts = (l[04] >> 16) & 0xff;
- for (i = 0; i < interrupts; i++) {
- l[0] = (i * 2) + 0x10;
- l[4] = DISABLED;
- value_low = l[4];
- l[0] = (i * 2) + 0x11;
- l[4] = NONE; /* Should this be an address? */
- value_high = l[4];
- if (value_low == 0xffffffff) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- }
-}
-
static void ioapic_init(device_t dev)
{
- uint32_t value;
+ uint32_t value, ioapic_base;
/* Enable bus mastering so IOAPICs work */
value = pci_read_config16(dev, PCI_COMMAND);
value |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, value);
- setup_ioapic(dev);
+ ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+
+ setup_ioapic(ioapic_base, 0); // Don't rename IOAPIC ID
}
static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c
index 546c27a8fd..2b840fcbdd 100644
--- a/src/southbridge/nvidia/ck804/ck804_lpc.c
+++ b/src/southbridge/nvidia/ck804/ck804_lpc.c
@@ -15,6 +15,7 @@
#include <pc80/isa-dma.h>
#include <bitops.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include "ck804.h"
@@ -23,83 +24,6 @@
#define NMI_OFF 0
-struct ioapicreg {
- unsigned int reg;
- unsigned int value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
- {0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
- {1, DISABLED, NONE},
- {2, DISABLED, NONE},
- {3, DISABLED, NONE},
- {4, DISABLED, NONE},
- {5, DISABLED, NONE},
- {6, DISABLED, NONE},
- {7, DISABLED, NONE},
- {8, DISABLED, NONE},
- {9, DISABLED, NONE},
- {10, DISABLED, NONE},
- {11, DISABLED, NONE},
- {12, DISABLED, NONE},
- {13, DISABLED, NONE},
- {14, DISABLED, NONE},
- {15, DISABLED, NONE},
- {16, DISABLED, NONE},
- {17, DISABLED, NONE},
- {18, DISABLED, NONE},
- {19, DISABLED, NONE},
- {20, DISABLED, NONE},
- {21, DISABLED, NONE},
- {22, DISABLED, NONE},
- {23, DISABLED, NONE},
- /* Be careful and don't write past the end... */
-};
-
-static void setup_ioapic(unsigned long ioapic_base)
-{
- int i;
- unsigned long value_low, value_high;
- /* unsigned long ioapic_base = 0xfec00000; */
- volatile unsigned long *l;
- struct ioapicreg *a = ioapicregvalues;
-
- ioapicregvalues[0].value_high = lapicid() << (56 - 32);
-
- l = (unsigned long *)ioapic_base;
-
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg * 2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i == 0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
- }
-}
-
// 0x7a or e3
#define PREVIOUS_POWER_STATE 0x7A
@@ -123,7 +47,7 @@ static void lpc_common_init(device_t dev)
pci_write_config8(dev, 0x74, byte);
dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
- setup_ioapic(dword);
+ setup_ioapic(dword, 0); // Don't rename IOAPIC ID
#if 1
dword = pci_read_config32(dev, 0xe4);
diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
index a9e6c36991..c247d98be1 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
@@ -33,97 +33,13 @@
#include <pc80/isa-dma.h>
#include <bitops.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include "mcp55.h"
#define NMI_OFF 0
-struct ioapicreg {
- unsigned int reg;
- unsigned int value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
- { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
- { 1, DISABLED, NONE},
- { 2, DISABLED, NONE},
- { 3, DISABLED, NONE},
- { 4, DISABLED, NONE},
- { 5, DISABLED, NONE},
- { 6, DISABLED, NONE},
- { 7, DISABLED, NONE},
- { 8, DISABLED, NONE},
- { 9, DISABLED, NONE},
- { 10, DISABLED, NONE},
- { 11, DISABLED, NONE},
- { 12, DISABLED, NONE},
- { 13, DISABLED, NONE},
- { 14, DISABLED, NONE},
- { 15, DISABLED, NONE},
- { 16, DISABLED, NONE},
- { 17, DISABLED, NONE},
- { 18, DISABLED, NONE},
- { 19, DISABLED, NONE},
- { 20, DISABLED, NONE},
- { 21, DISABLED, NONE},
- { 22, DISABLED, NONE},
- { 23, DISABLED, NONE},
- /* Be careful and don't write past the end... */
-};
-
-static void setup_ioapic(unsigned long ioapic_base, int master)
-{
- int i;
- unsigned long value_low, value_high;
-// unsigned long ioapic_base = 0xfec00000;
- volatile unsigned long *l;
- struct ioapicreg *a = ioapicregvalues;
-
- if (master) {
- ioapicregvalues[0].value_high = lapicid()<<(56-32);
- ioapicregvalues[0].value_low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
- }
- else {
- ioapicregvalues[0].value_high = NONE;
- ioapicregvalues[0].value_low = DISABLED;
- }
-
- l = (unsigned long *) ioapic_base;
-
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
- i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg *2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i==0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
- }
-}
-
// 0x7a or e3
#define PREVIOUS_POWER_STATE 0x7A
@@ -139,15 +55,18 @@ static void setup_ioapic(unsigned long ioapic_base, int master)
static void lpc_common_init(device_t dev, int master)
{
uint8_t byte;
- uint32_t dword;
+ uint32_t ioapic_base;
/* IO APIC initialization */
byte = pci_read_config8(dev, 0x74);
byte |= (1<<0); // enable APIC
pci_write_config8(dev, 0x74, byte);
- dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
+ ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
- setup_ioapic(dword, master);
+ if (master)
+ setup_ioapic(ioapic_base, 0);
+ else
+ clear_ioapic(ioapic_base);
}
static void lpc_slave_init(device_t dev)
diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/sis966_lpc.c
index dd369b694b..f549f1af8c 100644
--- a/src/southbridge/sis/sis966/sis966_lpc.c
+++ b/src/southbridge/sis/sis966/sis966_lpc.c
@@ -35,6 +35,7 @@
#include <pc80/isa-dma.h>
#include <bitops.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include "sis966.h"
@@ -42,84 +43,6 @@
#define NMI_OFF 0
-struct ioapicreg {
- unsigned int reg;
- unsigned int value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
- { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
- { 1, DISABLED, NONE},
- { 2, DISABLED, NONE},
- { 3, DISABLED, NONE},
- { 4, DISABLED, NONE},
- { 5, DISABLED, NONE},
- { 6, DISABLED, NONE},
- { 7, DISABLED, NONE},
- { 8, DISABLED, NONE},
- { 9, DISABLED, NONE},
- { 10, DISABLED, NONE},
- { 11, DISABLED, NONE},
- { 12, DISABLED, NONE},
- { 13, DISABLED, NONE},
- { 14, DISABLED, NONE},
- { 15, DISABLED, NONE},
- { 16, DISABLED, NONE},
- { 17, DISABLED, NONE},
- { 18, DISABLED, NONE},
- { 19, DISABLED, NONE},
- { 20, DISABLED, NONE},
- { 21, DISABLED, NONE},
- { 22, DISABLED, NONE},
- { 23, DISABLED, NONE},
- /* Be careful and don't write past the end... */
-};
-
-static void setup_ioapic(unsigned long ioapic_base)
-{
- int i;
- unsigned long value_low, value_high;
-// unsigned long ioapic_base = 0xfec00000;
- volatile unsigned long *l;
- struct ioapicreg *a = ioapicregvalues;
-
- ioapicregvalues[0].value_high = lapicid()<<(56-32);
-
- l = (unsigned long *) ioapic_base;
-
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
- i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg *2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i==0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
- }
-}
-
// 0x7a or e3
#define PREVIOUS_POWER_STATE 0x7A
@@ -135,16 +58,15 @@ static void setup_ioapic(unsigned long ioapic_base)
static void lpc_common_init(device_t dev)
{
uint8_t byte;
- uint32_t dword;
+ uint32_t ioapic_base;
/* IO APIC initialization */
byte = pci_read_config8(dev, 0x74);
byte |= (1<<0); // enable APIC
pci_write_config8(dev, 0x74, byte);
- dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
-
- setup_ioapic(dword);
+ ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
+ setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID
}
static void lpc_slave_init(device_t dev)
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index 21dc1210e0..25a854ce22 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -26,6 +26,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
#include <pc80/keyboard.h>
#include <pc80/i8259.h>
@@ -33,21 +34,6 @@
#include "vt8237r.h"
#include "chip.h"
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
-
extern void dump_south(device_t dev);
static void southbridge_init_common(struct device *dev);
@@ -75,85 +61,6 @@ static unsigned char *pin_to_irq(const unsigned char *pin)
}
#endif
-static struct ioapicreg {
- u32 reg;
- u32 value_low;
- u32 value_high;
-} ioapic_table[] = {
- /* IO-APIC virtual wire mode configuration. */
- /* mask, trigger, polarity, destination, delivery, vector */
- {0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST |
- ExtINT, NONE},
- {1, DISABLED, NONE},
- {2, DISABLED, NONE},
- {3, DISABLED, NONE},
- {4, DISABLED, NONE},
- {5, DISABLED, NONE},
- {6, DISABLED, NONE},
- {7, DISABLED, NONE},
- {8, DISABLED, NONE},
- {9, DISABLED, NONE},
- {10, DISABLED, NONE},
- {11, DISABLED, NONE},
- {12, DISABLED, NONE},
- {13, DISABLED, NONE},
- {14, DISABLED, NONE},
- {15, DISABLED, NONE},
- {16, DISABLED, NONE},
- {17, DISABLED, NONE},
- {18, DISABLED, NONE},
- {19, DISABLED, NONE},
- {20, DISABLED, NONE},
- {21, DISABLED, NONE},
- {22, DISABLED, NONE},
- {23, DISABLED, NONE},
-};
-
-static void setup_ioapic(u32 ioapic_base)
-{
- u32 value_low, value_high, val;
- volatile u32 *l;
- int i;
-
- /* All delivered to CPU0. */
- ioapic_table[0].value_high = (lapicid()) << (56 - 32);
- l = (u32 *)ioapic_base;
-
-#if CONFIG_EPIA_VT8237R_INIT
- /* Set APIC to APIC Serial bus. */
- l[0] = 0x3;
- l[4] = 0;
-#else
- /* Set APIC to FSB message bus. */
- l[0] = 0x3;
- val = l[4];
- l[4] = (val & 0xFFFFFE) | 1;
-#endif
-
- /* Set APIC ADDR - this will be VT8237R_APIC_ID. */
- l[0] = 0;
- val = l[4];
- l[4] = (val & 0xF0FFFF) | (VT8237R_APIC_ID << 24);
-
- for (i = 0; i < ARRAY_SIZE(ioapic_table); i++) {
- l[0] = (ioapic_table[i].reg * 2) + 0x10;
- l[4] = ioapic_table[i].value_low;
- value_low = l[4];
- l[0] = (ioapic_table[i].reg * 2) + 0x11;
- l[4] = ioapic_table[i].value_high;
- if (i == 0) {
- l[0] = (ioapic_table[i].reg * 2) + 0x10;
- value_low = l[4];
- if (value_low == 0xffffffff)
- {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- }
- }
-}
-
-
/** Set up PCI IRQ routing, route everything through APIC. */
static void pci_routing_fixup(struct device *dev)
{
@@ -622,7 +529,7 @@ static void southbridge_init_common(struct device *dev)
{
vt8237_common_init(dev);
pci_routing_fixup(dev);
- setup_ioapic(VT8237R_APIC_BASE);
+ setup_ioapic(VT8237R_APIC_BASE, VT8237R_APIC_ID);
setup_i8259();
init_keyboard(dev);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 10:05:03 +0000