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-rw-r--r--src/southbridge/intel/bd82x6x/pci.c2
-rw-r--r--src/southbridge/intel/i82801gx/pci.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index 2186287df2..6391de409c 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -77,7 +77,7 @@ static void ich_pci_bus_enable_resources(struct device *dev)
dev->command |= PCI_COMMAND_IO;
ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
ctrl |= dev->link_list->bridge_ctrl;
- ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
+ ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* error check */
printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c
index 22c516581f..1d1f902727 100644
--- a/src/southbridge/intel/i82801gx/pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
@@ -76,7 +76,7 @@ static void ich_pci_bus_enable_resources(struct device *dev)
dev->command |= PCI_COMMAND_IO;
ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
ctrl |= dev->link_list->bridge_ctrl;
- ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
+ ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* error check */
printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);