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-rw-r--r--src/southbridge/intel/fsp_rangeley/romstage.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 14611b3891..19e470e309 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <lib.h>
#include <timestamp.h>
#include <arch/io.h>
#include <device/mmio.h>
@@ -114,9 +113,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
/* Decode E0000 and F0000 segment to DRAM */
sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0));
- quick_ram_check();
- post_code(0x4d);
-
cbmem_was_initted = !cbmem_recovery(0);
/* Save the HOB pointer in CBMEM to be used in ramstage*/