diff options
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/amd8111/Config.lb | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111.c | 56 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111.h | 12 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_ac97.c | 41 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_acpi.c | 26 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_early_smbus.c | 14 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_ide.c | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_lpc.c | 18 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_nic.c | 25 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_usb.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_usb2.c | 7 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8131/amd8131_bridge.c | 19 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/chip.h | 14 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231.c | 708 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_early_serial.c | 107 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_early_smbus.c | 316 |
16 files changed, 767 insertions, 603 deletions
diff --git a/src/southbridge/amd/amd8111/Config.lb b/src/southbridge/amd/amd8111/Config.lb index f8f38a9964..904b0995b5 100644 --- a/src/southbridge/amd/amd8111/Config.lb +++ b/src/southbridge/amd/amd8111/Config.lb @@ -1,5 +1,9 @@ +config amd8111.h +driver amd8111.o driver amd8111_usb.o driver amd8111_lpc.o driver amd8111_ide.o driver amd8111_acpi.o driver amd8111_usb2.o +#driver amd8111_ac97.o +#driver amd8111_nic.o diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c new file mode 100644 index 0000000000..8dde5f13c6 --- /dev/null +++ b/src/southbridge/amd/amd8111/amd8111.c @@ -0,0 +1,56 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/chip.h> +#include "amd8111.h" + +void amd8111_enable(device_t dev) +{ + device_t lpc_dev; + device_t bus_dev; + unsigned index; + uint16_t reg_old, reg; + + /* See if we are on the behind the amd8111 pci bridge */ + bus_dev = dev->bus->dev; + if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && + (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) { + unsigned devfn; + devfn = bus_dev->path.u.pci.devfn + (1 << 3); + lpc_dev = dev_find_slot(bus_dev->bus->secondary, devfn); + index = ((dev->path.u.pci.devfn & ~7) >> 3) + 8; + } else { + unsigned devfn; + devfn = (dev->path.u.pci.devfn) & ~7; + lpc_dev = dev_find_slot(dev->bus->secondary, devfn); + index = dev->path.u.pci.devfn & 7; + } + if ((!lpc_dev) || (index >= 16) || + (lpc_dev->vendor != PCI_VENDOR_ID_AMD) || + (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) { + return; + } + + reg = reg_old = pci_read_config16(lpc_dev, 0x48); + reg &= ~(1 << index); + if (dev->enable) { + reg |= (1 << index); + } + if (reg != reg_old) { +#if 1 + printk_warning("amd8111_enable dev: %s", dev_path(dev)); + printk_warning(" lpc_dev: %s index: %d reg: %04x -> %04x ", + dev_path(lpc_dev), index, reg_old, reg); +#endif + pci_write_config16(lpc_dev, 0x48, reg); +#if 1 + printk_warning("done\n"); +#endif + } +} + +struct chip_control southbridge_amd_amd8111_control = { + .name = "AMD 8111", + .enable_dev = amd8111_enable, +}; diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h new file mode 100644 index 0000000000..10e152954f --- /dev/null +++ b/src/southbridge/amd/amd8111/amd8111.h @@ -0,0 +1,12 @@ +#ifndef AMD8111_H +#define AMD8111_H + +struct southbridge_amd_amd8111_config +{ +}; +struct chip_control; +extern struct chip_control southbridge_amd_amd8111_control; + +void amd8111_enable(device_t dev); + +#endif /* AMD8111_H */ diff --git a/src/southbridge/amd/amd8111/amd8111_ac97.c b/src/southbridge/amd/amd8111/amd8111_ac97.c new file mode 100644 index 0000000000..63a0e1264e --- /dev/null +++ b/src/southbridge/amd/amd8111/amd8111_ac97.c @@ -0,0 +1,41 @@ +/* + * (C) 2003 Linux Networx + */ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "amd8111.h" + + +static struct device_operations ac97audio_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = amd8111_enable, + .init = 0, + .scan_bus = 0, +}; + +static struct pci_driver ac97audio_driver __pci_driver = { + .ops = &ac97audio_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x746D, +}; + + +static struct device_operations ac97modem_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = amd8111_enable, + .init = 0, + .scan_bus = 0, +}; + +static struct pci_driver ac97modem_driver __pci_driver = { + .ops = &ac97modem_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x746E, +}; diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c index 5fa6fdce29..3a5a594f57 100644 --- a/src/southbridge/amd/amd8111/amd8111_acpi.c +++ b/src/southbridge/amd/amd8111/amd8111_acpi.c @@ -3,11 +3,23 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <pc80/mc146818rtc.h> +#include "amd8111.h" + +#define PREVIOUS_POWER_STATE 0x43 +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 + +#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + static void acpi_init(struct device *dev) { uint8_t byte; uint16_t word; + int on; #if 0 printk_debug("ACPI: disabling NMI watchdog.. "); @@ -35,6 +47,15 @@ static void acpi_init(struct device *dev) pci_write_config_dword(dev, 0x60, 0x06800000); printk_debug("done.\n"); #endif + on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + get_option(&on, "power_on_after_fail"); + byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); + byte &= ~0x40; + if (!on) { + byte |= 0x40; + } + pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); + printk_info("set power %s after power fail\n", on?"on":"off"); } @@ -42,8 +63,9 @@ static struct device_operations acpi_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = acpi_init, - .scan_bus = 0, + .init = acpi_init, + .scan_bus = 0, + .enable = amd8111_enable, }; static struct pci_driver acpi_driver __pci_driver = { diff --git a/src/southbridge/amd/amd8111/amd8111_early_smbus.c b/src/southbridge/amd/amd8111/amd8111_early_smbus.c index e0aaa05ff4..b9f142dc8e 100644 --- a/src/southbridge/amd/amd8111/amd8111_early_smbus.c +++ b/src/southbridge/amd/amd8111/amd8111_early_smbus.c @@ -21,6 +21,8 @@ static void enable_smbus(void) pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); enable = pci_read_config8(dev, 0x41); pci_write_config8(dev, 0x41, enable | (1 << 7)); + /* clear any lingering errors, so the transaction will run */ + outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); } @@ -40,8 +42,12 @@ static int smbus_wait_until_ready(void) if ((val & 0x800) == 0) { break; } + if(loops == (SMBUS_TIMEOUT / 2)) { + outw(inw(SMBUS_IO_BASE + SMBGSTATUS), + SMBUS_IO_BASE + SMBGSTATUS); + } } while(--loops); - return loops?0:-1; + return loops?0:-2; } static int smbus_wait_until_done(void) @@ -57,7 +63,7 @@ static int smbus_wait_until_done(void) break; } } while(--loops); - return loops?0:-1; + return loops?0:-3; } static int smbus_read_byte(unsigned device, unsigned address) @@ -67,7 +73,7 @@ static int smbus_read_byte(unsigned device, unsigned address) unsigned char byte; if (smbus_wait_until_ready() < 0) { - return -1; + return -2; } /* setup transaction */ @@ -93,7 +99,7 @@ static int smbus_read_byte(unsigned device, unsigned address) /* poll for transaction completion */ if (smbus_wait_until_done() < 0) { - return -1; + return -3; } global_status_register = inw(SMBUS_IO_BASE + SMBGSTATUS); diff --git a/src/southbridge/amd/amd8111/amd8111_ide.c b/src/southbridge/amd/amd8111/amd8111_ide.c index 11f795b0bb..4502bb3c45 100644 --- a/src/southbridge/amd/amd8111/amd8111_ide.c +++ b/src/southbridge/amd/amd8111/amd8111_ide.c @@ -3,6 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include "amd8111.h" static void ide_init(struct device *dev) { diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c index b0c1672f5d..437ed2e877 100644 --- a/src/southbridge/amd/amd8111/amd8111_lpc.c +++ b/src/southbridge/amd/amd8111/amd8111_lpc.c @@ -6,6 +6,8 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/chip.h> +#include "amd8111.h" struct ioapicreg { @@ -87,7 +89,6 @@ static void setup_ioapic(void) static void lpc_init(struct device *dev) { uint8_t byte; - uint16_t word; int pwr_on=-1; printk_debug("lpc_init\n"); @@ -100,14 +101,7 @@ static void lpc_init(struct device *dev) /* posted memory write enable */ byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1<<0)); - -//BY LYH - /* Disable AC97 and Ethernet */ - word = pci_read_config16(dev, 0x48); - pci_write_config16(dev, 0x48, word & ~((1<<5)|(1<<6)|(1<<9))); -//BY LYH END - + pci_write_config8(dev, 0x46, byte | (1<<0)); /* power after power fail */ byte = pci_read_config8(dev, 0x43); @@ -118,6 +112,10 @@ static void lpc_init(struct device *dev) } pci_write_config8(dev, 0x43, byte); + /* Enable Port 92 fast reset */ + byte = pci_read_config8(dev, 0x41); + byte |= (1 << 5); + pci_write_config8(dev, 0x41, byte); } @@ -159,6 +157,7 @@ static struct device_operations lpc_ops = { .enable_resources = pci_dev_enable_resources, .init = lpc_init, .scan_bus = walk_static_devices, + .enable = amd8111_enable, }; static struct pci_driver lpc_driver __pci_driver = { @@ -166,3 +165,4 @@ static struct pci_driver lpc_driver __pci_driver = { .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8111_ISA, }; + diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/amd8111_nic.c new file mode 100644 index 0000000000..b3792086a5 --- /dev/null +++ b/src/southbridge/amd/amd8111/amd8111_nic.c @@ -0,0 +1,25 @@ +/* + * (C) 2003 Linux Networx + */ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "amd8111.h" + + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = amd8111_enable, + .init = 0, + .scan_bus = 0, +}; + +static struct pci_driver nic_driver __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x7462, +}; diff --git a/src/southbridge/amd/amd8111/amd8111_usb.c b/src/southbridge/amd/amd8111/amd8111_usb.c index cfef06dee2..46cfabbcda 100644 --- a/src/southbridge/amd/amd8111/amd8111_usb.c +++ b/src/southbridge/amd/amd8111/amd8111_usb.c @@ -3,6 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include "amd8111.h" static void usb_init(struct device *dev) { @@ -25,6 +26,7 @@ static struct device_operations usb_ops = { .enable_resources = pci_dev_enable_resources, .init = usb_init, .scan_bus = 0, + .enable = amd8111_enable, }; static struct pci_driver usb_driver __pci_driver = { diff --git a/src/southbridge/amd/amd8111/amd8111_usb2.c b/src/southbridge/amd/amd8111/amd8111_usb2.c index 924e0e6109..15ed69b0f1 100644 --- a/src/southbridge/amd/amd8111/amd8111_usb2.c +++ b/src/southbridge/amd/amd8111/amd8111_usb2.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include "amd8111.h" static void usb2_init(struct device *dev) { @@ -23,17 +24,17 @@ static void usb2_init(struct device *dev) } -static struct device_operations usb_ops = { +static struct device_operations usb2_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb2_init, .scan_bus = 0, + .enable = amd8111_enable, }; static struct pci_driver usb2_driver __pci_driver = { - .ops = &usb_ops, + .ops = &usb2_ops, .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8111_USB2, }; - diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c index dccf962fbd..9d28de4f32 100644 --- a/src/southbridge/amd/amd8131/amd8131_bridge.c +++ b/src/southbridge/amd/amd8131/amd8131_bridge.c @@ -29,6 +29,17 @@ static void pcix_init(device_t dev) word = pci_read_config16(dev, 0xe8); word = 0x0404; pci_write_config16(dev, 0xe8, word); + + /* Set discard unrequested prefetch data */ + word = pci_read_config16(dev, 0x4c); + word |= 1; + pci_write_config16(dev, 0x4c, word); + + /* Set split transaction limits */ + word = pci_read_config16(dev, 0xa8); + pci_write_config16(dev, 0xaa, word); + word = pci_read_config16(dev, 0xac); + pci_write_config16(dev, 0xae, word); return; } @@ -58,14 +69,6 @@ static void ioapic_enable(device_t dev) value &= ~((1 << 1) | (1 << 0)); } pci_write_config32(dev, 0x44, value); - -//BY LYH - value = pci_read_config32(dev, 0x4); - value |= 6; - pci_write_config32(dev, 0x4, value); -//BY LYH END - - } static struct device_operations ioapic_ops = { diff --git a/src/southbridge/via/vt8231/chip.h b/src/southbridge/via/vt8231/chip.h index 0ae3b98c63..fe3d332675 100644 --- a/src/southbridge/via/vt8231/chip.h +++ b/src/southbridge/via/vt8231/chip.h @@ -9,13 +9,13 @@ struct southbridge_via_vt8231_config { /* I am putting in IDE as an example but obviously this needs * to be more complete! */ - int enable_ide; - /* enables of functions of devices */ - int enable_usb; - int enable_native_ide; - int enable_com_ports; - int enable_keyboard; - int enable_nvram; + int enable_ide; + /* enables of functions of devices */ + int enable_usb; + int enable_native_ide; + int enable_com_ports; + int enable_keyboard; + int enable_nvram; }; #endif /* _SOUTHBRIDGE_VIA_VT8231 */ diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c index 470ab5acf1..ea1f488f3e 100644 --- a/src/southbridge/via/vt8231/vt8231.c +++ b/src/southbridge/via/vt8231/vt8231.c @@ -11,101 +11,94 @@ void pc_keyboard_init(void); -void -hard_reset() { - printk_err("NO HARD RESET ON VT8231! FIX ME!\n"); +void hard_reset(void) +{ + printk_err("NO HARD RESET ON VT8231! FIX ME!\n"); } + static void usb_on(int enable) { - - unsigned char regval; - - /* Base 8231 controller */ - device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, \ - PCI_DEVICE_ID_VIA_8231, 0); - /* USB controller 1 */ - device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, \ - PCI_DEVICE_ID_VIA_82C586_2, 0); - /* USB controller 2 */ - device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, \ - PCI_DEVICE_ID_VIA_82C586_2, \ - dev2); - - /* enable USB1 */ - if(dev2) { - if (enable) { - pci_write_config8(dev2, 0x3c, 0x05); - pci_write_config8(dev2, 0x04, 0x07); - } else { - pci_write_config8(dev2, 0x3c, 0x00); - pci_write_config8(dev2, 0x04, 0x00); - } - } - - if(dev0) { - regval = pci_read_config8(dev0, 0x50); - if (enable) - regval &= ~(0x10); - else - regval |= 0x10; - pci_write_config8(dev0, 0x50, regval); - } - - /* enable USB2 */ - if(dev3) { - if (enable) { - pci_write_config8(dev3, 0x3c, 0x05); - pci_write_config8(dev3, 0x04, 0x07); - } else { - pci_write_config8(dev3, 0x3c, 0x00); - pci_write_config8(dev3, 0x04, 0x00); - } - } - - if(dev0) { - regval = pci_read_config8(dev0, 0x50); - if (enable) - regval &= ~(0x20); - else - regval |= 0x20; - pci_write_config8(dev0, 0x50, regval); - } - + unsigned char regval; + + /* Base 8231 controller */ + device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + /* USB controller 1 */ + device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0); + /* USB controller 2 */ + device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2); + + /* enable USB1 */ + if(dev2) { + if (enable) { + pci_write_config8(dev2, 0x3c, 0x05); + pci_write_config8(dev2, 0x04, 0x07); + } else { + pci_write_config8(dev2, 0x3c, 0x00); + pci_write_config8(dev2, 0x04, 0x00); + } + } + + if(dev0) { + regval = pci_read_config8(dev0, 0x50); + if (enable) + regval &= ~(0x10); + else + regval |= 0x10; + pci_write_config8(dev0, 0x50, regval); + } + + /* enable USB2 */ + if(dev3) { + if (enable) { + pci_write_config8(dev3, 0x3c, 0x05); + pci_write_config8(dev3, 0x04, 0x07); + } else { + pci_write_config8(dev3, 0x3c, 0x00); + pci_write_config8(dev3, 0x04, 0x00); + } + } + + if(dev0) { + regval = pci_read_config8(dev0, 0x50); + if (enable) + regval &= ~(0x20); + else + regval |= 0x20; + pci_write_config8(dev0, 0x50, regval); + } } -static void keyboard_on() +static void keyboard_on(void) { - unsigned char regval; - - /* Base 8231 controller */ - device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, \ - PCI_DEVICE_ID_VIA_8231, 0); - - /* kevinh/Ispiri - update entire function to use - new pci_write_config8 */ - - if (dev0) { - regval = pci_read_config8(dev0, 0x51); - regval |= 0x0f; - pci_write_config8(dev0, 0x51, regval); - } - pc_keyboard_init(); + unsigned char regval; + + /* Base 8231 controller */ + device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + + /* kevinh/Ispiri - update entire function to use + new pci_write_config8 */ + if (dev0) { + regval = pci_read_config8(dev0, 0x51); + regval |= 0x0f; + pci_write_config8(dev0, 0x51, regval); + } + pc_keyboard_init(); } -static void nvram_on() +static void nvram_on(void) { - /* - * the VIA 8231 South has a very different nvram setup than the - * piix4e ... - * turn on ProMedia nvram. - * TO DO: use the PciWriteByte function here. - */ - - /* - * kevinh/Ispiri - I don't think this is the correct address/value - * intel_conf_writeb(0x80008841, 0xFF); - */ + /* + * the VIA 8231 South has a very different nvram setup than the + * piix4e ... + * turn on ProMedia nvram. + * TO DO: use the PciWriteByte function here. + */ + + /* + * kevinh/Ispiri - I don't think this is the correct address/value + * intel_conf_writeb(0x80008841, 0xFF); + */ } @@ -115,22 +108,22 @@ static void nvram_on() */ static void ethernet_fixup() { - device_t edev; - uint8_t byte; - - printk_info("Ethernet fixup\n"); - - edev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0); - if (edev) { - printk_debug("Configuring VIA LAN\n"); - - /* We don't need stepping - though the device supports it */ - byte = pci_read_config8(edev, PCI_COMMAND); - byte &= ~PCI_COMMAND_WAIT; - pci_write_config8(edev, PCI_COMMAND, byte); - } else { - printk_debug("VIA LAN not found\n"); - } + device_t edev; + uint8_t byte; + + printk_info("Ethernet fixup\n"); + + edev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0); + if (edev) { + printk_debug("Configuring VIA LAN\n"); + + /* We don't need stepping - though the device supports it */ + byte = pci_read_config8(edev, PCI_COMMAND); + byte &= ~PCI_COMMAND_WAIT; + pci_write_config8(edev, PCI_COMMAND, byte); + } else { + printk_debug("VIA LAN not found\n"); + } } @@ -145,13 +138,14 @@ static void ethernet_fixup() * (e.g. device_t). This needs to get fixed. We need low-level pci scans * in the C code. */ -static void vt8231_pci_enable(struct southbridge_via_vt8231_config *conf) { - /* - unsigned long busdevfn = 0x8000; - if (conf->enable_ide) { - printk_debug("%s: enabling IDE function\n", __FUNCTION__); - } - */ +static void vt8231_pci_enable(struct southbridge_via_vt8231_config *conf) +{ + /* + unsigned long busdevfn = 0x8000; + if (conf->enable_ide) { + printk_debug("%s: enabling IDE function\n", __FUNCTION__); + } + */ } /* PIRQ init @@ -170,7 +164,7 @@ static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 }; */ static void pci_routing_fixup(void) { - device_t dev; + device_t dev; dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); printk_info("%s: dev is %p\n", __FUNCTION__, dev); @@ -204,260 +198,258 @@ static void pci_routing_fixup(void) void -dump_south(void){ - device_t dev0; - dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); - int i,j; - - for(i = 0; i < 256; i += 16) { - printk_debug("0x%x: ", i); - for(j = 0; j < 16; j++) { - printk_debug("%02x ", pci_read_config8(dev0, i+j)); - } - printk_debug("\n"); - } +dump_south(void) +{ + device_t dev0; + dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + int i,j; + + for(i = 0; i < 256; i += 16) { + printk_debug("0x%x: ", i); + for(j = 0; j < 16; j++) { + printk_debug("%02x ", pci_read_config8(dev0, i+j)); + } + printk_debug("\n"); + } } static void vt8231_init(struct southbridge_via_vt8231_config *conf) { - unsigned char enables; - device_t dev0; - device_t dev1; - device_t devpwr; - - // to do: use the pcibios_find function here, instead of - // hard coding the devfn. - // done - kevinh/Ispiri - printk_debug("vt8231 init\n"); - /* Base 8231 controller */ - dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); - /* IDE controller */ - dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, \ - 0); - /* Power management controller */ - devpwr = dev_find_device(PCI_VENDOR_ID_VIA, \ - PCI_DEVICE_ID_VIA_8231_4, 0); - - // enable the internal I/O decode - enables = pci_read_config8(dev0, 0x6C); - enables |= 0x80; - pci_write_config8(dev0, 0x6C, enables); - - // Map 4MB of FLASH into the address space - pci_write_config8(dev0, 0x41, 0x7f); - - // Set bit 6 of 0x40, because Award does it (IO recovery time) - // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI - // interrupts can be properly marked as level triggered. - enables = pci_read_config8(dev0, 0x40); - pci_write_config8(dev0, 0x40, enables); - - // Set 0x42 to 0xf0 to match Award bios - enables = pci_read_config8(dev0, 0x42); - enables |= 0xf0; - pci_write_config8(dev0, 0x42, enables); - - // Set bit 3 of 0x4a, to match award (dummy pci request) - enables = pci_read_config8(dev0, 0x4a); - enables |= 0x08; - pci_write_config8(dev0, 0x4a, enables); - - // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) - enables = pci_read_config8(dev0, 0x4f); - enables |= 0x08; - pci_write_config8(dev0, 0x4f, enables); - - // Set 0x58 to 0x03 to match Award - pci_write_config8(dev0, 0x58, 0x03); - - // enable the ethernet/RTC - if(dev0) { - enables = pci_read_config8(dev0, 0x51); - enables |= 0x18; - pci_write_config8(dev0, 0x51, enables); - } - - - // enable com1 and com2. - if (conf->enable_com_ports) { - enables = pci_read_config8(dev0, 0x6e); - - /* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 - * is enable com port a as com1 kevinh/Ispiri - Old code - * thought 0x01 would make it com1, that was wrong enables = - * 0x80 | 0x10 | 0x8 ; pci_write_config8(dev0, 0x6e, - * enables); // note: this is also a redo of some port of - * assembly, but we want everything up. - */ - - /* set com1 to 115 kbaud not clear how to do this yet. - * forget it; done in assembly. - */ - - } - // enable IDE, since Linux won't do it. - // First do some more things to devfn (17,0) - // note: this should already be cleared, according to the book. - enables = pci_read_config8(dev0, 0x50); - printk_debug("IDE enable in reg. 50 is 0x%x\n", enables); - enables &= ~8; // need manifest constant here! - printk_debug("set IDE reg. 50 to 0x%x\n", enables); - pci_write_config8(dev0, 0x50, enables); - - // set default interrupt values (IDE) - enables = pci_read_config8(dev0, 0x4c); - printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf); - // clear out whatever was there. - enables &= ~0xf; - enables |= 4; - printk_debug("setting reg. 4c to 0x%x\n", enables); - pci_write_config8(dev0, 0x4c, enables); - - // set up the serial port interrupts. - // com2 to 3, com1 to 4 - pci_write_config8(dev0, 0x46, 0x04); - pci_write_config8(dev0, 0x47, 0x03); - pci_write_config8(dev0, 0x6e, 0x98); - // - // Power management setup - // - // Set ACPI base address to IO 0x4000 - pci_write_config32(devpwr, 0x48, 0x4001); - - // Enable ACPI access (and setup like award) - pci_write_config8(devpwr, 0x41, 0x84); - - // Set hardware monitor base address to IO 0x6000 - pci_write_config32(devpwr, 0x70, 0x6001); - - // Enable hardware monitor (and setup like award) - pci_write_config8(devpwr, 0x74, 0x01); - - // set IO base address to 0x5000 - pci_write_config32(devpwr, 0x90, 0x5001); - - // Enable SMBus - pci_write_config8(devpwr, 0xd2, 0x01); - - // - // IDE setup - // - if (conf->enable_native_ide) { - // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI - // interrupts. Using PCI ints confuses linux for some reason. - - printk_info("%s: enabling native IDE addresses\n", __FUNCTION__); - enables = pci_read_config8(dev1, 0x42); - printk_debug("enables in reg 0x42 0x%x\n", enables); - enables &= ~0xc0; // compatability mode - pci_write_config8(dev1, 0x42, enables); - enables = pci_read_config8(dev1, 0x42); - printk_debug("enables in reg 0x42 read back as 0x%x\n", enables); - } - - enables = pci_read_config8(dev1, 0x40); - printk_debug("enables in reg 0x40 0x%x\n", enables); - enables |= 3; - pci_write_config8(dev1, 0x40, enables); - enables = pci_read_config8(dev1, 0x40); - printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); - - // Enable prefetch buffers - enables = pci_read_config8(dev1, 0x41); - enables |= 0xf0; - pci_write_config8(dev1, 0x41, enables); - - // Lower thresholds (cause award does it) - enables = pci_read_config8(dev1, 0x43); - enables &= ~0x0f; - enables |= 0x05; - pci_write_config8(dev1, 0x43, enables); - - // PIO read prefetch counter (cause award does it) - pci_write_config8(dev1, 0x44, 0x18); - - // Use memory read multiple - pci_write_config8(dev1, 0x45, 0x1c); - - // address decoding. - // we want "flexible", i.e. 1f0-1f7 etc. or native PCI - // kevinh@ispiri.com - the standard linux drivers seem ass slow when - // used in native mode - I've changed back to classic - enables = pci_read_config8(dev1, 0x9); - printk_debug("enables in reg 0x9 0x%x\n", enables); - // by the book, set the low-order nibble to 0xa. - if (conf->enable_native_ide) { - enables &= ~0xf; - // cf/cg silicon needs an 'f' here. - enables |= 0xf; - } else { - enables &= ~0x5; - } - - pci_write_config8(dev1, 0x9, enables); - enables = pci_read_config8(dev1, 0x9); - printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); - - // standard bios sets master bit. - enables = pci_read_config8(dev1, 0x4); - printk_debug("command in reg 0x4 0x%x\n", enables); - enables |= 7; - - // No need for stepping - kevinh@ispiri.com - enables &= ~0x80; - - pci_write_config8(dev1, 0x4, enables); - enables = pci_read_config8(dev1, 0x4); - printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); - - if (! conf->enable_native_ide) { - // Use compatability mode - per award bios - pci_write_config32(dev1, 0x10, 0x0); - pci_write_config32(dev1, 0x14, 0x0); - pci_write_config32(dev1, 0x18, 0x0); - pci_write_config32(dev1, 0x1c, 0x0); - - // Force interrupts to use compat mode - just like Award bios - pci_write_config8(dev1, 0x3d, 00); - pci_write_config8(dev1, 0x3c, 0xff); - } - - - /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ - pci_write_config8(dev0, 0x40, 0x54); - ethernet_fixup(); - - // Start the rtc - rtc_init(0); + unsigned char enables; + device_t dev0; + device_t dev1; + device_t devpwr; + + // to do: use the pcibios_find function here, instead of + // hard coding the devfn. + // done - kevinh/Ispiri + printk_debug("vt8231 init\n"); + /* Base 8231 controller */ + dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + /* IDE controller */ + dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0); + /* Power management controller */ + devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231_4, 0); + + // enable the internal I/O decode + enables = pci_read_config8(dev0, 0x6C); + enables |= 0x80; + pci_write_config8(dev0, 0x6C, enables); + + // Map 4MB of FLASH into the address space + pci_write_config8(dev0, 0x41, 0x7f); + + // Set bit 6 of 0x40, because Award does it (IO recovery time) + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // interrupts can be properly marked as level triggered. + enables = pci_read_config8(dev0, 0x40); + pci_write_config8(dev0, 0x40, enables); + + // Set 0x42 to 0xf0 to match Award bios + enables = pci_read_config8(dev0, 0x42); + enables |= 0xf0; + pci_write_config8(dev0, 0x42, enables); + + // Set bit 3 of 0x4a, to match award (dummy pci request) + enables = pci_read_config8(dev0, 0x4a); + enables |= 0x08; + pci_write_config8(dev0, 0x4a, enables); + + // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) + enables = pci_read_config8(dev0, 0x4f); + enables |= 0x08; + pci_write_config8(dev0, 0x4f, enables); + + // Set 0x58 to 0x03 to match Award + pci_write_config8(dev0, 0x58, 0x03); + + // enable the ethernet/RTC + if(dev0) { + enables = pci_read_config8(dev0, 0x51); + enables |= 0x18; + pci_write_config8(dev0, 0x51, enables); + } + + + // enable com1 and com2. + if (conf->enable_com_ports) { + enables = pci_read_config8(dev0, 0x6e); + + /* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 + * is enable com port a as com1 kevinh/Ispiri - Old code + * thought 0x01 would make it com1, that was wrong enables = + * 0x80 | 0x10 | 0x8 ; pci_write_config8(dev0, 0x6e, + * enables); // note: this is also a redo of some port of + * assembly, but we want everything up. + */ + + /* set com1 to 115 kbaud not clear how to do this yet. + * forget it; done in assembly. + */ + + } + // enable IDE, since Linux won't do it. + // First do some more things to devfn (17,0) + // note: this should already be cleared, according to the book. + enables = pci_read_config8(dev0, 0x50); + printk_debug("IDE enable in reg. 50 is 0x%x\n", enables); + enables &= ~8; // need manifest constant here! + printk_debug("set IDE reg. 50 to 0x%x\n", enables); + pci_write_config8(dev0, 0x50, enables); + + // set default interrupt values (IDE) + enables = pci_read_config8(dev0, 0x4c); + printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf); + // clear out whatever was there. + enables &= ~0xf; + enables |= 4; + printk_debug("setting reg. 4c to 0x%x\n", enables); + pci_write_config8(dev0, 0x4c, enables); + + // set up the serial port interrupts. + // com2 to 3, com1 to 4 + pci_write_config8(dev0, 0x46, 0x04); + pci_write_config8(dev0, 0x47, 0x03); + pci_write_config8(dev0, 0x6e, 0x98); + // + // Power management setup + // + // Set ACPI base address to IO 0x4000 + pci_write_config32(devpwr, 0x48, 0x4001); + + // Enable ACPI access (and setup like award) + pci_write_config8(devpwr, 0x41, 0x84); + + // Set hardware monitor base address to IO 0x6000 + pci_write_config32(devpwr, 0x70, 0x6001); + + // Enable hardware monitor (and setup like award) + pci_write_config8(devpwr, 0x74, 0x01); + + // set IO base address to 0x5000 + pci_write_config32(devpwr, 0x90, 0x5001); + + // Enable SMBus + pci_write_config8(devpwr, 0xd2, 0x01); + + // + // IDE setup + // + if (conf->enable_native_ide) { + // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI + // interrupts. Using PCI ints confuses linux for some reason. + + printk_info("%s: enabling native IDE addresses\n", __FUNCTION__); + enables = pci_read_config8(dev1, 0x42); + printk_debug("enables in reg 0x42 0x%x\n", enables); + enables &= ~0xc0; // compatability mode + pci_write_config8(dev1, 0x42, enables); + enables = pci_read_config8(dev1, 0x42); + printk_debug("enables in reg 0x42 read back as 0x%x\n", enables); + } + + enables = pci_read_config8(dev1, 0x40); + printk_debug("enables in reg 0x40 0x%x\n", enables); + enables |= 3; + pci_write_config8(dev1, 0x40, enables); + enables = pci_read_config8(dev1, 0x40); + printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); + + // Enable prefetch buffers + enables = pci_read_config8(dev1, 0x41); + enables |= 0xf0; + pci_write_config8(dev1, 0x41, enables); + + // Lower thresholds (cause award does it) + enables = pci_read_config8(dev1, 0x43); + enables &= ~0x0f; + enables |= 0x05; + pci_write_config8(dev1, 0x43, enables); + + // PIO read prefetch counter (cause award does it) + pci_write_config8(dev1, 0x44, 0x18); + + // Use memory read multiple + pci_write_config8(dev1, 0x45, 0x1c); + + // address decoding. + // we want "flexible", i.e. 1f0-1f7 etc. or native PCI + // kevinh@ispiri.com - the standard linux drivers seem ass slow when + // used in native mode - I've changed back to classic + enables = pci_read_config8(dev1, 0x9); + printk_debug("enables in reg 0x9 0x%x\n", enables); + // by the book, set the low-order nibble to 0xa. + if (conf->enable_native_ide) { + enables &= ~0xf; + // cf/cg silicon needs an 'f' here. + enables |= 0xf; + } else { + enables &= ~0x5; + } + + pci_write_config8(dev1, 0x9, enables); + enables = pci_read_config8(dev1, 0x9); + printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); + + // standard bios sets master bit. + enables = pci_read_config8(dev1, 0x4); + printk_debug("command in reg 0x4 0x%x\n", enables); + enables |= 7; + + // No need for stepping - kevinh@ispiri.com + enables &= ~0x80; + + pci_write_config8(dev1, 0x4, enables); + enables = pci_read_config8(dev1, 0x4); + printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); + + if (! conf->enable_native_ide) { + // Use compatability mode - per award bios + pci_write_config32(dev1, 0x10, 0x0); + pci_write_config32(dev1, 0x14, 0x0); + pci_write_config32(dev1, 0x18, 0x0); + pci_write_config32(dev1, 0x1c, 0x0); + + // Force interrupts to use compat mode - just like Award bios + pci_write_config8(dev1, 0x3d, 00); + pci_write_config8(dev1, 0x3c, 0xff); + } + + + /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ + pci_write_config8(dev0, 0x40, 0x54); + ethernet_fixup(); + + // Start the rtc + rtc_init(0); } -static void -southbridge_init(struct chip *chip, enum chip_pass pass) +static void southbridge_init(struct chip *chip, enum chip_pass pass) { - struct southbridge_via_vt8231_config *conf = - (struct southbridge_via_vt8231_config *)chip->chip_info; - - switch (pass) { - case CONF_PASS_PRE_PCI: - vt8231_pci_enable(conf); - break; - - case CONF_PASS_POST_PCI: - vt8231_init(conf); - printk_err("FUCK! ROUTING FIXUP!\n"); - pci_routing_fixup(); - - break; - case CONF_PASS_PRE_BOOT: - pci_routing_fixup(); - dump_south(); - break; - - default: - /* nothing yet */ - break; - } + struct southbridge_via_vt8231_config *conf = + (struct southbridge_via_vt8231_config *)chip->chip_info; + + switch (pass) { + case CONF_PASS_PRE_PCI: + vt8231_pci_enable(conf); + break; + + case CONF_PASS_POST_PCI: + vt8231_init(conf); + printk_err("FUCK! ROUTING FIXUP!\n"); + pci_routing_fixup(); + + break; + case CONF_PASS_PRE_BOOT: + pci_routing_fixup(); + dump_south(); + break; + + default: + /* nothing yet */ + break; + } } static void enumerate(struct chip *chip) @@ -468,7 +460,7 @@ static void enumerate(struct chip *chip) } struct chip_control southbridge_via_vt8231_control = { - .enumerate = enumerate, - enable: southbridge_init, - name: "VIA vt8231" + .enumerate = enumerate, + .enable = southbridge_init, + .name = "VIA vt8231" }; diff --git a/src/southbridge/via/vt8231/vt8231_early_serial.c b/src/southbridge/via/vt8231/vt8231_early_serial.c index ca7831df42..1bfffed7f5 100644 --- a/src/southbridge/via/vt8231/vt8231_early_serial.c +++ b/src/southbridge/via/vt8231/vt8231_early_serial.c @@ -8,20 +8,20 @@ #define SIO_BASE 0x3f0 #define SIO_DATA SIO_BASE+1 -static void -vt8231_writesuper(uint8_t reg, uint8_t val) { - outb(reg, SIO_BASE); - outb(val, SIO_DATA); +static void vt8231_writesuper(uint8_t reg, uint8_t val) +{ + outb(reg, SIO_BASE); + outb(val, SIO_DATA); } -static void -vt8231_writesiobyte(uint16_t reg, uint8_t val) { - outb(val, reg); +static void vt8231_writesiobyte(uint16_t reg, uint8_t val) +{ + outb(val, reg); } -static void -vt8231_writesioword(uint16_t reg, uint16_t val) { - outw(val, reg); +static void vt8231_writesioword(uint16_t reg, uint16_t val) +{ + outw(val, reg); } @@ -29,48 +29,47 @@ vt8231_writesioword(uint16_t reg, uint16_t val) { mainboard */ -static void -enable_vt8231_serial(void) { - unsigned long x; - uint8_t c; - device_t dev; - outb(6, 0x80); - dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); - - if (dev == PCI_DEV_INVALID) { - outb(7, 0x80); - die("Serial controller not found\r\n"); - } - - /* first, you have to enable the superio and superio config. - put a 6 reg 80 - */ - c = pci_read_config8(dev, 0x50); - c |= 6; - pci_write_config8(dev, 0x50, c); - outb(2, 0x80); - // now go ahead and set up com1. - // set address - vt8231_writesuper(0xf4, 0xfe); - // enable serial out - vt8231_writesuper(0xf2, 7); - // That's it for the sio stuff. - // movl $SUPERIOCONFIG, %eax - // movb $9, %dl - // PCI_WRITE_CONFIG_BYTE - // set up reg to set baud rate. - vt8231_writesiobyte(0x3fb, 0x80); - // Set 115 kb - vt8231_writesioword(0x3f8, 1); - // Set 9.6 kb - // WRITESIOWORD(0x3f8, 12) - // now set no parity, one stop, 8 bits - vt8231_writesiobyte(0x3fb, 3); - // now turn on RTS, DRT - vt8231_writesiobyte(0x3fc, 3); - // Enable interrupts - vt8231_writesiobyte(0x3f9, 0xf); - // should be done. Dump a char for fun. - vt8231_writesiobyte(0x3f8, 48); - +static void enable_vt8231_serial(void) +{ + unsigned long x; + uint8_t c; + device_t dev; + outb(6, 0x80); + dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); + + if (dev == PCI_DEV_INVALID) { + outb(7, 0x80); + die("Serial controller not found\r\n"); + } + + /* first, you have to enable the superio and superio config. + put a 6 reg 80 + */ + c = pci_read_config8(dev, 0x50); + c |= 6; + pci_write_config8(dev, 0x50, c); + outb(2, 0x80); + // now go ahead and set up com1. + // set address + vt8231_writesuper(0xf4, 0xfe); + // enable serial out + vt8231_writesuper(0xf2, 7); + // That's it for the sio stuff. + // movl $SUPERIOCONFIG, %eax + // movb $9, %dl + // PCI_WRITE_CONFIG_BYTE + // set up reg to set baud rate. + vt8231_writesiobyte(0x3fb, 0x80); + // Set 115 kb + vt8231_writesioword(0x3f8, 1); + // Set 9.6 kb + // WRITESIOWORD(0x3f8, 12) + // now set no parity, one stop, 8 bits + vt8231_writesiobyte(0x3fb, 3); + // now turn on RTS, DRT + vt8231_writesiobyte(0x3fc, 3); + // Enable interrupts + vt8231_writesiobyte(0x3f9, 0xf); + // should be done. Dump a char for fun. + vt8231_writesiobyte(0x3f8, 48); } diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c index 49b942cb23..e419d59b63 100644 --- a/src/southbridge/via/vt8231/vt8231_early_smbus.c +++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c @@ -24,115 +24,115 @@ static void enable_smbus(void) { - device_t dev; - unsigned char c; - /* Power management controller */ - dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0); - - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); - } - - // set IO base address to SMBUS_IO_BASE - pci_write_config32(dev, 0x90, SMBUS_IO_BASE|1); - - // Enable SMBus - c = pci_read_config8(dev, 0xd2); - c |= 5; - pci_write_config8(dev, 0xd2, c); - - /* make it work for I/O ... - */ - dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); - c = pci_read_config8(dev, 4); - c |= 1; - pci_write_config8(dev, 4, c); - print_err_hex8(c); - print_err(" is the comm register\n"); - - print_debug("SMBus controller enabled\r\n"); + device_t dev; + unsigned char c; + /* Power management controller */ + dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0); + + if (dev == PCI_DEV_INVALID) { + die("SMBUS controller not found\r\n"); + } + + // set IO base address to SMBUS_IO_BASE + pci_write_config32(dev, 0x90, SMBUS_IO_BASE|1); + + // Enable SMBus + c = pci_read_config8(dev, 0xd2); + c |= 5; + pci_write_config8(dev, 0xd2, c); + + /* make it work for I/O ... + */ + dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); + c = pci_read_config8(dev, 4); + c |= 1; + pci_write_config8(dev, 4, c); + print_err_hex8(c); + print_err(" is the comm register\n"); + + print_debug("SMBus controller enabled\r\n"); } static inline void smbus_delay(void) { - outb(0x80, 0x80); + outb(0x80, 0x80); } static int smbus_wait_until_ready(void) { unsigned char c; - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - c = inb(SMBUS_IO_BASE + SMBHSTSTAT); - while((c & 1) == 1) { - print_err("c is "); - print_err_hex8(c); - print_err("\n"); - c = inb(SMBUS_IO_BASE + SMBHSTSTAT); - /* nop */ - } - - } while(--loops); - return loops?0:-1; + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + c = inb(SMBUS_IO_BASE + SMBHSTSTAT); + while((c & 1) == 1) { + print_err("c is "); + print_err_hex8(c); + print_err("\n"); + c = inb(SMBUS_IO_BASE + SMBHSTSTAT); + /* nop */ + } + + } while(--loops); + return loops?0:-1; } void smbus_reset(void) { - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - - smbus_wait_until_ready(); - print_err("After reset status "); - print_err_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); - print_err("\n"); + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + + smbus_wait_until_ready(); + print_err("After reset status "); + print_err_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); + print_err("\n"); } static int smbus_wait_until_done(void) { - unsigned long loops; - unsigned char byte; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); + unsigned long loops; + unsigned char byte; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - if (byte & 1) - break; - - } while(--loops); - return loops?0:-1; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if (byte & 1) + break; + + } while(--loops); + return loops?0:-1; } static void smbus_print_error(unsigned char host_status_register) { - print_err("smbus_error: "); - print_err_hex8(host_status_register); - print_err("\n"); - if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\n"); - } - if (host_status_register & (1 << 3)) { - print_err("Bus Error\n"); - } - if (host_status_register & (1 << 2)) { - print_err("Device Error\n"); - } - if (host_status_register & (1 << 1)) { - print_err("Interrupt/SMI# was Successful Completion\n"); - } - if (host_status_register & (1 << 0)) { - print_err("Host Busy\n"); - } + print_err("smbus_error: "); + print_err_hex8(host_status_register); + print_err("\n"); + if (host_status_register & (1 << 4)) { + print_err("Interrup/SMI# was Failed Bus Transaction\n"); + } + if (host_status_register & (1 << 3)) { + print_err("Bus Error\n"); + } + if (host_status_register & (1 << 2)) { + print_err("Device Error\n"); + } + if (host_status_register & (1 << 1)) { + print_err("Interrupt/SMI# was Successful Completion\n"); + } + if (host_status_register & (1 << 0)) { + print_err("Host Busy\n"); + } } @@ -141,39 +141,39 @@ static void smbus_print_error(unsigned char host_status_register) static unsigned char smbus_read_byte(unsigned char devAdr, unsigned char bIndex) { - unsigned short i; - unsigned char bData; - unsigned char sts = 0; - - /* clear host status */ - outb(0xff, SMBUS_IO_BASE); - - /* check SMBUS ready */ - for ( i = 0; i < 0xFFFF; i++ ) - if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 ) - break; - - /* set host command */ - outb(bIndex, SMBUS_IO_BASE+3); - - /* set slave address */ - outb(devAdr | 0x01, SMBUS_IO_BASE+4); - - /* start */ - outb(0x48, SMBUS_IO_BASE+2); - - /* SMBUS Wait Ready */ - for ( i = 0; i < 0xFFFF; i++ ) - if ( ((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0 ) - break; - if ((sts & ~3) != 0) { - smbus_print_error(sts); - return 0; - } - bData=inb(SMBUS_IO_BASE+5); - - return bData; - + unsigned short i; + unsigned char bData; + unsigned char sts = 0; + + /* clear host status */ + outb(0xff, SMBUS_IO_BASE); + + /* check SMBUS ready */ + for ( i = 0; i < 0xFFFF; i++ ) + if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 ) + break; + + /* set host command */ + outb(bIndex, SMBUS_IO_BASE+3); + + /* set slave address */ + outb(devAdr | 0x01, SMBUS_IO_BASE+4); + + /* start */ + outb(0x48, SMBUS_IO_BASE+2); + + /* SMBUS Wait Ready */ + for ( i = 0; i < 0xFFFF; i++ ) + if ( ((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0 ) + break; + if ((sts & ~3) != 0) { + smbus_print_error(sts); + return 0; + } + bData=inb(SMBUS_IO_BASE+5); + + return bData; + } /* for reference, here is the fancier version which we will use at some @@ -182,48 +182,48 @@ static unsigned char smbus_read_byte(unsigned char devAdr, # if 0 int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) { - unsigned char host_status_register; - unsigned char byte; - - reset(); - - smbus_wait_until_ready(); - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), - SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), - SMBUS_IO_BASE + SMBHSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - - /* Ignore the In Use Status... */ - host_status_register &= ~(1 << 6); - - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - smbus_print_error(byte); - - *result = byte; - return host_status_register != 0x02; + unsigned char host_status_register; + unsigned char byte; + + reset(); + + smbus_wait_until_ready(); + + /* setup transaction */ + /* disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* set the command/address... */ + outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); + /* set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), + SMBUS_IO_BASE + SMBHSTCTL); + + /* clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* clear the data byte...*/ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* start the command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), + SMBUS_IO_BASE + SMBHSTCTL); + + /* poll for transaction completion */ + smbus_wait_until_done(); + + host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + + /* Ignore the In Use Status... */ + host_status_register &= ~(1 << 6); + + /* read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + smbus_print_error(byte); + + *result = byte; + return host_status_register != 0x02; } |