diff options
Diffstat (limited to 'src/superio/ite/it8705f/it8705f_early_serial.c')
| -rw-r--r-- | src/superio/ite/it8705f/it8705f_early_serial.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/src/superio/ite/it8705f/it8705f_early_serial.c b/src/superio/ite/it8705f/it8705f_early_serial.c index eca0d620be..3ae512725a 100644 --- a/src/superio/ite/it8705f/it8705f_early_serial.c +++ b/src/superio/ite/it8705f/it8705f_early_serial.c @@ -26,19 +26,19 @@ #define SIO_INDEX SIO_BASE #define SIO_DATA SIO_BASE+1 -/* Global Configuration Registers. */ +/* Global configuration registers. */ #define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8705F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8705F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ /* WTF? 0x23 and 0x24 are swapped here (when compared to other IT87xx). */ -#define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection. */ -#define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend, Flash I/F. */ +#define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection, Flash I/F. */ +#define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend. */ #define IT8705F_CONFIGURATION_PORT 0x2e /* Write-only. */ /* The content of IT8705F_CONFIG_REG_LDN (index 0x07) must be set to the - * LDN the register belongs to, before you can access the register. */ + LDN the register belongs to, before you can access the register. */ static void it8705f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) { outb(IT8705F_CONFIG_REG_LDN, SIO_BASE); @@ -47,7 +47,7 @@ static void it8705f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) outb(value, SIO_DATA); } -/* Enable the peripheral devices on the IT8705F Super IO chip. */ +/* Enable the peripheral devices on the IT8705F Super I/O chip. */ static void it8705f_enable_serial(device_t dev, unsigned iobase) { /* (1) Enter the configuration state (MB PnP mode). */ @@ -63,8 +63,8 @@ static void it8705f_enable_serial(device_t dev, unsigned iobase) /* (2) Modify the data of configuration registers. */ /* Select the chip to configure (if there's more than one). - * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - * If this register is not written, both chips are configured. */ + Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + If this register is not written, both chips are configured. */ /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */ /* Enable all devices. */ @@ -73,18 +73,17 @@ static void it8705f_enable_serial(device_t dev, unsigned iobase) it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */ it8705f_sio_write(IT8705F_PP, 0x30, 0x1); /* Parallel port */ it8705f_sio_write(IT8705F_EC, 0x30, 0x1); /* Environment controller */ - /* GPIO */ it8705f_sio_write(IT8705F_GAME, 0x30, 0x1); /* GAME port */ it8705f_sio_write(IT8705F_IR, 0x30, 0x1); /* Consumer IR */ it8705f_sio_write(IT8705F_MIDI, 0x30, 0x1); /* MIDI port */ /* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */ - /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x00); */ + /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01); */ /* Clear software suspend mode (clear bit 0). TODO: Needed? */ /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_SWSUSP, 0x00); */ /* (3) Exit the configuration state (MB PnP mode). */ - it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02); + it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02); } |