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Diffstat (limited to 'src/superio/winbond/w83627ehg/w83627ehg.h')
-rw-r--r--src/superio/winbond/w83627ehg/w83627ehg.h35
1 files changed, 18 insertions, 17 deletions
diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h
index f03cf0672d..60c2b064b2 100644
--- a/src/superio/winbond/w83627ehg/w83627ehg.h
+++ b/src/superio/winbond/w83627ehg/w83627ehg.h
@@ -23,35 +23,36 @@
#define SUPERIO_WINBOND_W83627EHG_W83627EHG_H
#define W83627EHG_FDC 0 /* Floppy */
-#define W83627EHG_PP 1 /* Parallel Port */
+#define W83627EHG_PP 1 /* Parallel port */
#define W83627EHG_SP1 2 /* Com1 */
#define W83627EHG_SP2 3 /* Com2 */
-#define W83627EHG_KBC 5 /* Keyboard & Mouse */
-#define W83627EHG_GPIO_GAME_MIDI 7 /* GPIO1, GPIO6, Game Port and MIDI Port */
+#define W83627EHG_KBC 5 /* PS/2 keyboard & mouse */
+#define W83627EHG_GPIO_GAME_MIDI 7 /* GPIO1, GPIO6, Game port, MIDI port */
#define W83627EHG_WDTO_PLED 8 /* TODO */
-#define W83627EHG_GPIO_SUSLED 9 /* GPIO2, GPIO3, GPIO4, GPIO5 and SUSLED */
+#define W83627EHG_GPIO_SUSLED 9 /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */
#define W83627EHG_ACPI 10 /* ACPI */
-#define W83627EHG_HWM 11 /* Hardware Monitor */
+#define W83627EHG_HWM 11 /* Hardware monitor */
-/* virtual devices sharing the enables are encoded as follows:
+/*
+ * Virtual devices sharing the enables are encoded as follows:
* VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN
*/
-#define W83627EHG_SFI ((1 << 8) | 6) /* Flash has bit1 as enable */
-#define W83627EHG_GPIO1 W83627EHG_GPIO_GAME_MIDI /* GPIO1 is at LDN 7, bit 0 */
-#define W83627EHG_GAME ((1 << 8) | 7)
-#define W83627EHG_MIDI ((2 << 8) | 7)
-#define W83627EHG_GPIO6 ((3 << 8) | 7)
+#define W83627EHG_SFI ((1 << 8) | 6) /* Flash has bit1 as enable */
+#define W83627EHG_GPIO1 W83627EHG_GPIO_GAME_MIDI /* GPIO1: LDN 7, bit 0 */
+#define W83627EHG_GAME ((1 << 8) | 7)
+#define W83627EHG_MIDI ((2 << 8) | 7)
+#define W83627EHG_GPIO6 ((3 << 8) | 7)
-#define W83627EHG_GPIO2 W83627EHG_GPIO_SUSLED /* GPIO2 is at LDN 9, bit 0 */
-#define W83627EHG_GPIO3 ((1 << 8) | 9)
-#define W83627EHG_GPIO4 ((2 << 8) | 9)
-#define W83627EHG_GPIO5 ((3 << 8) | 9)
+#define W83627EHG_GPIO2 W83627EHG_GPIO_SUSLED /* GPIO2: LDN 9, bit 0 */
+#define W83627EHG_GPIO3 ((1 << 8) | 9)
+#define W83627EHG_GPIO4 ((2 << 8) | 9)
+#define W83627EHG_GPIO5 ((3 << 8) | 9)
#if defined(__PRE_RAM__) && !defined(__ROMCC__)
-void w83627ehg_enable_dev(device_t dev, unsigned iobase);
+void w83627ehg_enable_dev(device_t dev, u16 iobase);
void w83627ehg_disable_dev(device_t dev);
-void w83627ehg_enable_serial(device_t dev, unsigned iobase);
+void w83627ehg_enable_serial(device_t dev, u16 iobase);
#endif
#endif