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path: root/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
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Diffstat (limited to 'src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c')
-rw-r--r--src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
index f2ba2cf0da..468e57f74c 100644
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
+++ b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
@@ -158,10 +158,10 @@ GnbLpcDmaDeadlockPrevention (
// For GPP Link core, enable special NP memory write protocol on the processor side PCIE controller
GnbLibPciIndirectRMW (
NbPciAddress.AddressValue | D0F0xE0_ADDRESS,
- CORE_SPACE (1, D0F0xE4_CORE_0010_ADDRESS),
+ CORE_SPACE (1, 0x10),
AccessWidth32,
0xFFFFFFFF,
- 1 << D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET,
+ 1 << 9,
StdHeader
);
@@ -244,4 +244,4 @@ GnbLock (
TRUE,
StdHeader
);
-} \ No newline at end of file
+}