diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1')
6 files changed, 1885 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c new file mode 100644 index 0000000000..b28e1a9189 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c @@ -0,0 +1,351 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39033 $ @e \$Date: 2010-10-04 14:23:23 -0700 (Mon, 04 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "cpuLateInit.h" +#include "cpuRegisters.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#include "GnbRegistersON.h" +#include "OptionGnb.h" +#include "PcieAlib.h" +#include "GnbFuseTable.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern UINT8 AlibSsdt[]; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +PcieAlibSetPortGenCapabilityCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +STATIC +PcieAlibSetPortInfoCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieAlibBuildAcpiTable ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **AlibSsdtPtr + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Create ACPI ALIB SSDT table + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PcieAlibFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_LATE_PARAMS *LateParamsPtr; + LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader; + return PcieAlibBuildAcpiTable (StdHeader, &LateParamsPtr->AcpiAlib); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build ALIB ACPI table + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @param[in,out] AlibSsdtPtr Pointer to pointer to ALIB SSDT table + * @retval AGESA_SUCCESS + * @retval AGESA_ERROR + */ + +AGESA_STATUS +PcieAlibBuildAcpiTable ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **AlibSsdtPtr + ) +{ + AGESA_STATUS Status; + UINT32 AmlObjName; + PCIe_PLATFORM_CONFIG *Pcie; + PP_FUSE_ARRAY *PpFuseArray; + VOID *AlibSsdtBuffer; + VOID *AmlObjPtr; + UINT8 SclkVidArray[4]; + UINT8 BootUpVid; + UINT8 BootUpVidIndex; + UINT8 Gen1VidIndex; + UINTN Index; + UINTN AlibSsdtlength; + Status = AGESA_SUCCESS; + AlibSsdtlength = ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength; + if (*AlibSsdtPtr == NULL) { + AlibSsdtBuffer = GnbAllocateHeapBuffer ( + AMD_ACPI_ALIB_BUFFER_HANDLE, + AlibSsdtlength, + StdHeader + ); + ASSERT (AlibSsdtBuffer != NULL); + if (AlibSsdtBuffer == NULL) { + return AGESA_ERROR; + } + *AlibSsdtPtr = AlibSsdtBuffer; + } else { + AlibSsdtBuffer = *AlibSsdtPtr; + } + // Copy template to buffer + LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader); + // Set PCI MMIO configuration + AmlObjName = '10DA'; + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + if (AmlObjPtr != NULL) { + UINT64 MsrRegister; + LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrRegister, StdHeader); + if ((MsrRegister & BIT0) != 0 && (MsrRegister & 0xFFFFFFFF00000000) == 0) { + *(UINT32*)((UINT8*)AmlObjPtr + 5) = (UINT32)(MsrRegister & 0xFFFFF00000); + } else { + Status = AGESA_ERROR; + } + } else { + Status = AGESA_ERROR; + } + // Set voltage configuration + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + if (PpFuseArray != NULL) { + AmlObjName = '30DA'; + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*)AmlObjPtr + 5) = PpFuseArray->PcieGen2Vid; + } else { + Status = AGESA_ERROR; + } + } else { + Status = AGESA_ERROR; + } + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), + AccessWidth32, + &SclkVidArray[0], + StdHeader + ); + Gen1VidIndex = 0; + BootUpVidIndex = 0; + BootUpVid = 0xff; + for (Index = 0; Index < 4; Index++) { + if (SclkVidArray[Index] > SclkVidArray[Gen1VidIndex]) { + Gen1VidIndex = (UINT8) Index; + } + if (SclkVidArray[Index] != 0 && SclkVidArray[Index] < BootUpVid) { + BootUpVid = SclkVidArray[Index]; + BootUpVidIndex = (UINT8) Index; + } + } + AmlObjName = '40DA'; + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*)AmlObjPtr + 5) = Gen1VidIndex; + } else { + Status = AGESA_ERROR; + } + AmlObjName = '50DA'; + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*)AmlObjPtr + 5) = BootUpVidIndex; + } else { + Status = AGESA_ERROR; + } + // Set PCIe configuration + if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { + AmlObjName = '20DA'; + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*)AmlObjPtr + 5) = Pcie->PsppPolicy; + } else { + Status = AGESA_ERROR; + } + AmlObjName = '60DA'; + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieAlibSetPortGenCapabilityCallback, + (UINT8*)((UINT8*)AmlObjPtr + 7), + Pcie + ); + } else { + Status = AGESA_ERROR; + } + AmlObjName = '70DA'; + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieAlibSetPortInfoCallback, + (UINT8*)((UINT8*)AmlObjPtr + 4), + Pcie + ); + } else { + Status = AGESA_ERROR; + } + } else { + ASSERT (FALSE); + Status = AGESA_ERROR; + } + if (Status == AGESA_ERROR) { + //Shrink table length to size of the header + ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER); + } + ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init max port Gen capability + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAlibSetPortGenCapabilityCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 *PsppMaxPortCapbilityArray; + PsppMaxPortCapbilityArray = (UINT8*) Buffer; + if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PsppMaxPortCapbilityArray[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie) + 1; + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init port info + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAlibSetPortInfoCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + ALIB_PORT_INFO_PACKAGE *PortInfoPackage; + UINT8 PortIndex; + PortInfoPackage = (ALIB_PORT_INFO_PACKAGE*) Buffer; + PortIndex = (UINT8) Engine->Type.Port.Address.Address.Device - 2; + PortInfoPackage->PortInfo[PortIndex].StartPhyLane = (UINT8) Engine->EngineData.StartLane; + PortInfoPackage->PortInfo[PortIndex].EndPhyLane = (UINT8) Engine->EngineData.EndLane; + PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane; + PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane; + PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId; + PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieEngineGetParentWrapper (Engine)->WrapId); + PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug; + PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie); +} + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h new file mode 100644 index 0000000000..ae7e774c66 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h @@ -0,0 +1,83 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _PCIEALIB_H_ +#define _PCIEALIB_H_ + +#pragma pack (push, 1) +///Port info asl buffer +typedef struct { + UINT8 BufferOp; ///< Opcode + UINT8 PkgLength; ///< Package length + UINT8 BufferSize; ///< Buffer size + UINT8 ByteList; ///< Byte lisy + UINT8 StartPhyLane; ///< Port Start PHY lane + UINT8 EndPhyLane; ///< Port End PHY lane + UINT8 StartCoreLane; ///< Port Start Core lane + UINT8 EndCoreLane; ///< Port End Core lane + UINT8 PortId; ///< Port ID + UINT16 WrapperId; ///< Wrapper ID + UINT8 LinkHotplug; ///< Link hotplug type + UINT8 MaxSpeedCap; ///< Max port speed capability + UINT8 Reserved[1]; ///< Reserved +} ALIB_PORT_INFO_BUFFER; +///Ports info asl package +typedef struct { + UINT8 PackageOp; ///< Opcode + UINT8 PkgLength; ///< Package length + UINT8 NumElements; ///< number of elements + UINT8 PackageElementList; ///< package element list + ALIB_PORT_INFO_BUFFER PortInfo[7]; ///< Array of port info buffers +} ALIB_PORT_INFO_PACKAGE; + +#pragma pack (pop) + +AGESA_STATUS +PcieAlibFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl new file mode 100644 index 0000000000..e595c28036 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl @@ -0,0 +1,68 @@ +/** + * @file + * + * ALIB PSPP config + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 25430 $ @e \$Date: 2010-01-18 22:25:55 -0800 (Mon, 18 Jan 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _PCIEALIBCONFIG_H_ +#define _PCIEALIBCONFIG_H_ + +#define DEF_OFFSET_START_CORE_LANE 2 +#define DEF_OFFSET_END_CORE_LANE 3 +#define DEF_OFFSET_START_PHY_LANE 0 +#define DEF_OFFSET_END_PHY_LANE 1 +#define DEF_OFFSET_PORT_ID 4 +#define DEF_OFFSET_WRAPPER_ID 5 +#define DEF_OFFSET_LINK_HOTPLUG 7 +#define DEF_OFFSET_GEN2_CAP 8 +#define DEF_BASIC_HOTPLUG 1 + +#define DEF_PSPP_POLICY_START 1 +#define DEF_PSPP_POLICY_STOP 0 +#define DEF_PSPP_POLICY_PERFORMANCE 1 +#define DEF_PSPP_POLICY_BALANCEHIGH 2 +#define DEF_PSPP_POLICY_BALANCELOW 3 +#define DEF_PSPP_POLICY_POWERSAVING 4 +#define DEF_PSPP_STATE_AC 0 +#define DEF_PSPP_STATE_DC 1 + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl new file mode 100644 index 0000000000..7b785a80e8 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl @@ -0,0 +1,373 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 31805 $ @e \$Date: 2010-05-21 17:58:16 -0700 (Fri, 21 May 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe MMIO Base address + * + */ + + Name ( + AD01, + 0xE0000000 + ) + + Alias ( + AD01, + varPcieBase + ) + + + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe port info + * + */ + + Name ( + AD07, + Package () { + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev2 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev3 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev4 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev5 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev6 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev7 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev8 + } + ) + + Alias ( + AD07, + varPortInfo + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * Master control method + * + * Arg0 - Function ID + * Arg1 - Function specific data buffer + */ + Method (ALIB, 2, NotSerialized) { + If (Lequal (Arg0, 0x1)) { + return (procPsppReportAcDsState (Arg1)) + } + If (LEqual (Arg0, 0x2)) { + return (procPsppPerformanceRequest (Arg1)) + } + If (LEqual (Arg0, 0x3)) { + return (procPsppControl (Arg1)) + } + If (LEqual (Arg0, 0x4)) { + return (procPcieSetBusWidth (Arg1)) + } + If (LEqual (Arg0, 0x5)) { + return (procAlibInit ()) + } + If (LEqual (Arg0, 0x6)) { + return (procPciePortHotplug (Arg1)) + } + return (0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Alib Init + * + * + */ + Method (procAlibInit, 0, Serialized) { + + return (0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCI config register + * + * Arg0 - Port Index + * + */ + + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCI config register through MMIO + * + * Arg0 - PCI address Bus/device/func + * Arg1 - Register offset + */ + Method (procPciDwordRead, 2, NotSerialized) { + Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) + Add (Arg1, Local0, Local0) + OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) + Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { + Offset (0x0), + varPciReg32, 32, + } + return (varPciReg32) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Write PCI config register through MMIO + * + * Arg0 - PCI address Bus/device/func + * Arg1 - Register offset + * Arg2 - Value + */ + Method (procPciDwordWrite, 3, NotSerialized) { + Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) + Add (Arg1, Local0, Local0) + OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) + Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { + Offset (0x0), + varPciReg32, 32, + } + Store (Arg2, varPciReg32) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Write PCI config register through MMIO + * + * Arg0 - PCI address Bus/device/func + * Arg1 - Register offset + * Arg2 - AND mask + * Arg3 - OR mask + */ + Method (procPciDwordRMW, 4, NotSerialized) { + Store (procPciDwordRead (Arg0, Arg1), Local0) + Or (And (Local0, Arg2), Arg3, Local0) + procPciDwordWrite (Arg0, Arg1, Local0) + } + + Mutex(varPciePortAccessMutex, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - Port Index + * Arg1 - Register offset + * + */ + Method (procPciePortIndirectRegisterRead, 2, NotSerialized) { + Acquire(varPciePortAccessMutex, 0xFFFF) + Store (ShiftLeft (Add( Arg0, 2), 3), Local0) + procPciDwordWrite (Local0, 0xe0, Arg1) + Store (procPciDwordRead (Local0, 0xe4), Local0) + Release (varPciePortAccessMutex) + return (Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Write PCIe port indirect register + * + * Arg0 - Port Index + * Arg1 - Register offset + * Arg2 - Value + */ + Method (procPciePortIndirectRegisterWrite, 3, NotSerialized) { + Acquire(varPciePortAccessMutex, 0xFFFF) + Store (ShiftLeft (Add( Arg0, 2), 3), Local0) + procPciDwordWrite (Local0, 0xe0, Arg1) + procPciDwordWrite (Local0, 0xe4, Arg2) + Release (varPciePortAccessMutex) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - Port Index + * Arg1 - Register offset + * Arg2 - AND Mask + * Arg3 - OR Mask + * + */ + Method (procPciePortIndirectRegisterRMW, 4, NotSerialized) { + Store (procPciePortIndirectRegisterRead (Arg0, Arg1), Local0) + Or (And (Local0, Arg2), Arg3, Local0) + procPciePortIndirectRegisterWrite (Arg0, Arg1, Local0) + } + Mutex(varHostAccessMutex, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - BDF + * Arg1 - Register offset + * Arg2 - Register address + * + */ + Method (procIndirectRegisterRead, 3, NotSerialized) { + Acquire(varHostAccessMutex, 0xFFFF) + procPciDwordWrite (Arg0, Arg1, Arg2) + Store (procPciDwordRead (Arg0, Add (Arg1, 4)), Local0) + Release(varHostAccessMutex) + return (Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Write PCIe port indirect register + * + * Arg0 - BDF + * Arg1 - Register offset + * Arg2 - Register address + * Arg3 - Value + */ + Method (procIndirectRegisterWrite, 4, NotSerialized) { + Acquire(varHostAccessMutex, 0xFFFF) + procPciDwordWrite (Arg0, Arg1, Arg2) + procPciDwordWrite (Arg0, Add (Arg1, 4), Arg3) + Release(varHostAccessMutex) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Read Modify Write indirect registers + * + * Arg0 - BDF + * Arg1 - Register Offset + * Arg2 - Register Address + * Arg3 - AND Mask + * Arg4 - OR Mask + * + */ + Method (procIndirectRegisterRMW, 5, NotSerialized) { + Store (procIndirectRegisterRead (Arg0, Arg1, Arg2), Local0) + Or (And (Local0, Arg3), Arg4, Local0) + procIndirectRegisterWrite (Arg0, Arg1, Arg2, Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * + * + * Arg0 - Port ID + * Retval - buffer that represent port data set + */ + Method (procPcieGetPortInfo, 1, NotSerialized) { + return (DeRefOf (Index (varPortInfo, Arg0))) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Find Pci Capability + * + * Arg0 - PCI address Bus/device/func + * Arg1 - Capability id + */ + Method (procFindPciCapability, 2, NotSerialized) { + Store (0x34, Local1) + if (LEqual (procPciDwordRead (Arg0, 0x0), 0xFFFFFFFF)) { + // Device not present + return (0) + } + Store (1, Local0) + while (LEqual (Local0, 1)) { + Store (And (procPciDwordRead (Arg0, Local1), 0xFF), Local1) + if (LNotEqual (Local1, 0)) { + if (LEqual (And (procPciDwordRead (Arg0, Local1), 0xFF), Arg1)) { + Store (0, Local0) + } else { + Increment (Local1) + } + } + } + return (Local1) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * + * + * Arg0 - Aspm + * Arg1 - 0: Read, 1: Write + */ + Method (procPcieSbAspmControl, 2, NotSerialized) { + // Create an opregion for PM IO Registers + OperationRegion (PMIO, SystemIO, 0xCD6, 0x2) + Field (PMIO, ByteAcc, NoLock, Preserve) + { + PMRI, 8, + PMRD, 8 + } + IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) + { + Offset(0xE0), // IO Base address of A-Link Express/ A-Link Bridge register + ABAR, 32, + } + OperationRegion (ACFG, SystemIO, ABAR, 0x8) + Field (ACFG, DWordAcc, Nolock, Preserve) //AB_INDX/AB_DATA + { + ABIX, 32, + ABDA, 32 + } + + Store (0, Local0) + if (LEqual (Arg1, 0)) { + Store (0x80000068, ABIX) + Store (ABDA, Local0) + return (Local0) + } else { + Store (0x80000068, ABIX) + Store (ABDA, Local0) + Or (And (Local0, 0xfffffffc), Arg0, Local0) + Store (Local0, ABDA) + } + + } + +#ifdef ALIB_DEBUG + Name (ABUF, Buffer (256) {}) + Name (AFUN, 0xff) + Method (ADBG, 0, Serialized) { + ALIB (AFUN, ABUF); + } + Alias (procPciDwordRead, AXPR) +#endif + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl new file mode 100644 index 0000000000..fead211aed --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl @@ -0,0 +1,328 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 31805 $ @e \$Date: 2010-05-21 17:58:16 -0700 (Fri, 21 May 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + /*----------------------------------------------------------------------------------------*/ + /** + * Set PCIe Bus Width + * + * Arg0 - Data Buffer + */ + Method (procPcieSetBusWidth, 1, Serialized) { + Store (Buffer (256) {}, Local7) + CreateWordField (Local7, 0x0, varReturnBufferLength) + CreateWordField (Local7, 0x2, varReturnBusWidth) + CreateByteField (Arg0, 0x2, varArgBusWidth) + //@todo deternime correct lane bitmap (check for reversal) gate/ungate unused lanes + Store (3, varReturnBufferLength) + Store (varArgBusWidth, varReturnBusWidth) + return (Local7) + } + + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe port hotplug + * + * Arg0 - Data Buffer + * Local7 - Return buffer + */ + Method (procPciePortHotplug, 1, Serialized) { + Store ("PciePortHotplug Enter", Debug) + Store (Buffer (256) {}, Local7) + CreateWordField (Local7, 0x0, varReturnBufferLength) + CreateByteField (Local7, 0x2, varReturnStatus) + CreateByteField (Local7, 0x3, varReturnDeviceStatus) + CreateWordField (Arg0, 0x2, varPortBdf) + CreateByteField (Arg0, 0x4, varHotplugState) + Subtract (ShiftRight (varPortBdf, 3), 2, Local1); + if (LEqual(varHotplugState, 1)) { + // Enable port + Store (procPciePortEnable (Local1), varHotplugState); + } else { + // Disable port + Store (procPciePortDisable (Local1), varHotplugState); + } + Store (0x4, varReturnBufferLength) + Store (0x0, varReturnStatus) + Store (varHotplugState, varReturnDeviceStatus) + Store ("PciePortHotplug Exit", Debug) + return (Local7) + } + + + /*----------------------------------------------------------------------------------------*/ + /** + * Enable PCIe port + * + * 1) Ungate lanes + * 2) Enable Lanes + * 3) Train port + * 4) Disable unused lanes + * 5) Gate unused lanes + * + * Arg0 - Port Index + * + */ + Method (procPciePortEnable, 1, NotSerialized) { + Store ("PciePortEnable Enter", Debug) + Name (varLinkIsLinkReversed, 0) + Store (procPcieGetPortInfo (Arg0), Local7) + CreateByteField (Local7, DEF_OFFSET_LINK_HOTPLUG, varHotplugType) + if (LNotEqual (varHotplugType, DEF_BASIC_HOTPLUG)) { + Store (" No action.[Hotplug type]", Debug) + Store ("PciePortEnable Exit", Debug) + return (1) + } + // Poweron phy lanes + CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane) + CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane) + procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0) + // Enable lanes + CreateByteField (Local7, DEF_OFFSET_START_CORE_LANE, varStartCoreLane) + CreateByteField (Local7, DEF_OFFSET_END_CORE_LANE, varEndCoreLane) + procPcieLaneEnableControl (Arg0, varStartPhyLane, varEndPhyLane, 0) + //Release training + procPcieTrainingControl (Arg0, 0) + //Train link + Store (procPcieCheckDevicePrecence (Arg0), Local1) + if (LEqual (Local1, 1)) { + Store (" Device detected", Debug) + Store (procPcieIsPortReversed (Arg0), varLinkIsLinkReversed) + Subtract (procPcieGetLinkWidth (Arg0, 1), procPcieGetLinkWidth (Arg0, 0), Local2) + if (LNotEqual (Local2, 0)) { + //There is unused lanes after device plugged + if (LNotEqual(varLinkIsLinkReversed, 0)) { + Add (varStartCoreLane, Local2, Local3) + Store (varEndCoreLane, Local4) + } else { + Subtract (varEndCoreLane, Local2, Local4) + Store (varStartCoreLane, Local3) + } + procPcieLaneEnableControl (Arg0, Local3, Local4, 1) + if (LGreater (varStartPhyLane, varEndPhyLane)) { + Store (varEndPhyLane, Local3) + Store (varStartPhyLane, Local4) + } else { + Store (varEndPhyLane, Local4) + Store (varStartPhyLane, Local3) + } + if (LNotEqual(varLinkIsLinkReversed, 0)) { + Add (Local3, Local2, Local3) + } else { + Subtract (Local4, Local2, Local4) + } + procPcieLanePowerControl (Local3, Local4, 1) + } + Store ("PciePortEnable Exit", Debug) + return (1) + } + Store (" Device detection fail", Debug) + procPciePortDisable (Arg0) + Store ("PciePortEnable Exit", Debug) + return (0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Disable PCIe port + * + * 1) Hold training + * 2) Disable lanes + * 3) Gate lanes + * + * Arg0 - Port Index + * + */ + Method (procPciePortDisable, 1, NotSerialized) { + Store ("PciePortDisable Enter", Debug) + Store (procPcieGetPortInfo (Arg0), Local7) + CreateByteField (Local7, DEF_OFFSET_LINK_HOTPLUG, varHotplugType) + if (LNotEqual (varHotplugType, DEF_BASIC_HOTPLUG)) { + Store (" No action. [Hotplug type]", Debug) + Store ("PciePortDisable Exit", Debug) + return (0) + } + //Hold training + procPcieTrainingControl (Arg0, 1) + CreateByteField (Local7, DEF_OFFSET_START_CORE_LANE, varStartCoreLane) + CreateByteField (Local7, DEF_OFFSET_END_CORE_LANE, varEndCoreLane) + // Disable lane + procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 1) + CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane) + CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane) + // Poweroff phy lanes + procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1) + + Store ("PciePortDisable Exit", Debug) + return (0) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Is port reversed + * + * Arg0 - Port Index + * Retval - 0 - Not reversed / 1 - Reversed + */ + Method (procPcieIsPortReversed , 1, NotSerialized) { + Store (procPcieGetPortInfo (Arg0), Local7) + CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane) + CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane) + Store (0, Local0) + if (LGreater (varStartPhyLane, varEndPhyLane)) { + Store (1, Local0) + } + And (procPciePortIndirectRegisterRead (Arg0, 0x50), 0x1, Local1) + return (Xor (Local0, Local1)) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Training Control + * + * Arg0 - Port Index + * Arg1 - Hold Training (1) / Release Training (0) + */ + Method (procPcieTrainingControl , 2, NotSerialized) { + Store ("PcieTrainingControl Enter", Debug) + Store (procPcieGetPortInfo (Arg0), Local7) + CreateByteField (Local7, DEF_OFFSET_PORT_ID, varPortId) + CreateWordField (Local7, DEF_OFFSET_WRAPPER_ID, varWrapperId) + procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), Add (0x800, Multiply (0x100, varPortId))), Not (0x1), Arg1); + Store ("PcieTrainingControl Exit", Debug) + } + + + /*----------------------------------------------------------------------------------------*/ + /** + * Check device presence + * + * Arg0 - Port Index + * Retval - 1 - Device present, 0 - Device not present + */ + Method (procPcieCheckDevicePrecence, 1, NotSerialized) { + Store ("PcieCheckDevicePrecence Enter", Debug) + Store (0, Local0) + Store (0, Local7) + while (LLess (Local0, 320)) { // @todo for debug only should be 80 + And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, Local1) + if (LEqual (Local1, 0x10)) { + Store (1, Local7) + Store (320, Local0) + Break + } + Stall (250) + Increment (Local0) + } + //Store (Concatenate ("Device Presence Status :", ToHexString (Local7)), Debug) + Store ("PcieCheckDevicePrecence Exit", Debug) + return (Local7) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Get actual negotiated/PHY or core link width + * + * Arg0 - Port Index + * Arg1 - 0/1 Negotiated/Phy + * Retval - Link Width + */ + Method (procPcieGetLinkWidth, 2, NotSerialized) { + if (LEqual (Arg0, 0)){ + //Get negotiated length + And (ShiftRight (procPciePortIndirectRegisterRead (Arg0, 0xA2), 4), 0x7, Local0) + Store (DeRefOf (Index (Buffer (){0, 1, 2, 4, 8, 12, 16}, Local0)), Local1) + } else { + //Get phy length + Store (procPcieGetPortInfo (Arg0), Local7) + CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane) + CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane) + if (LGreater (varStartPhyLane, varEndPhyLane)) { + Subtract (varStartPhyLane, varEndPhyLane, Local1) + } else { + Subtract (varEndPhyLane, varStartPhyLane, Local1) + } + Increment (Local1) + } + //Store (Concatenate ("Link Width :", ToHexString (Local7)), Debug) + return (Local1) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe lane mux lane enable control (hotplug support) + * + * Arg0 - Port Index + * Arg1 - Start Lane + * Arg2 - End Lane + * Arg3 - Enable(0) / Disable(1) + */ + Method (procPcieLaneEnableControl, 4, NotSerialized) { + Store ("PcieLaneEnableControl Enter", Debug) + Name (varStartCoreLane, 0) + Name (varEndCoreLane, 0) + Store (procPcieGetPortInfo (Arg0), Local7) + Store (Arg1, varStartCoreLane) + Store (Arg2, varEndCoreLane) + CreateWordField (Local7, DEF_OFFSET_WRAPPER_ID, varWrapperId) + if (LGreater (varStartCoreLane, varEndCoreLane)) { + Subtract (varStartCoreLane, varEndCoreLane, Local1) + Store (varEndCoreLane, Local2) + } else { + Subtract (varEndCoreLane, varStartCoreLane, Local1) + Store (varStartCoreLane, Local2) + } + ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, Local1) + //Store (Concatenate ("Lane Bitmap :", ToHexString (Local1)), Debug) + if (Lequal (Arg3, 0)) { + procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), 0xffffffff, Local1); + } else { + procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), Not (Local1), 0x0); + } + Stall (10) + Store ("PcieLaneEnableControl Exit", Debug) + } + + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl new file mode 100644 index 0000000000..70d6a93b84 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl @@ -0,0 +1,682 @@ +/** +* @file +* +* ALIB PSPP ASL library +* +* +* +* @xrefitem bom "File Content Label" "Release Content" +* @e project: AGESA +* @e sub-project: GNB +* @e \$Revision: 31805 $ @e \$Date: 2010-05-21 17:58:16 -0700 (Fri, 21 May 2010) $ +* +*/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe Performance Policy + * + * varPsppPolicy - 0 Disabled + * 1 Performance + * 2 Balance Hight + * 3 Balance Low + * 4 Power Saving + */ + Name ( + AD02, + 0x0 + ) + + Alias ( + AD02, + varPsppPolicy + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * GEN2 VID + * + */ + + Name ( + AD03, + 0x0 + ) + + Alias ( + AD03, + varGen2Vid + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * GEN1 VID + * + */ + Name ( + AD04, + 0x0 + ) + + Alias ( + AD04, + varGen1Vid + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * Boot VID + * + */ + + Name ( + AD05, + 0x0 + ) + + Alias ( + AD05, + varBootVid + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * Max Port GEN capability + * + */ + Name ( + AD06, + Package () { + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 + } + ) + + Alias ( + AD06, + varPsppMaxPortCapabilityArray + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * Policy service status + * + * varPsppPolicyService - 0 (Stopped) + * 1 (Started) + */ + + Name ( + varPsppPolicyService, + 0x0 + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * AC DC state + * + * varPsppAcDcState - 0 (AC) + * 1 (DC) + */ + + Name ( + varPsppAcDcState, + 0x0 + ) + + + Name ( + varPsppClientIdArray, + Package () { + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000 + } + ) + + Name ( + varPsppClientCapabilityArray, + Package () { + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 + } + ) + + Name ( + varPsppCurrentCapabilityArray, + Package () { + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 + } + ) + Name ( + varDefaultGen1CapabilityArray, + Package () { + 0x2, + 0x2, + 0x2, + 0x2, + 0x2, + 0x2, + 0x2 + } + ) + + + /*----------------------------------------------------------------------------------------*/ + /** + * Report AC/DC state + * + * Arg0 - Data Buffer + */ + Method (procPsppReportAcDsState, 1, Serialized) { + Store ("PsppReportAcDsState Enter", Debug) + CreateByteField (Arg0, 0x2, varArgAcDcState) + + Store ("AC/DC state = ", Debug) + Store (varArgAcDcState, Debug) + if (LEqual (varArgAcDcState, varPsppAcDcState)) { + Store (" No action. [AC/DC state not changed]", Debug) + Store ("PsppReportAcDsState Exit", Debug) + return (0) + } + Store (varArgAcDcState, varPsppAcDcState) + // Set DPM state for Power Saving, due to this policy will not attend ApplyPsppState service. + if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { + procNbLclkDpmActivate(1, varPsppAcDcState) + } + if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { + Store (" No action. [Policy type]", Debug) + Store ("PsppReportAcDsState Exit", Debug) + return (0) + } + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { + Store (" No action. [Policy not started]", Debug) + Store ("PsppReportAcDsState Exit", Debug) + return (0) + } + procApplyPsppState () + Store ("PsppReportAcDsState Exit", Debug) + return (0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe Performance Request + * + * Arg0 - Data Buffer + */ + Method (procPsppPerformanceRequest, 1) { + Store ("PsppPerformanceRequest Enter", Debug) + Name (varClientBus, 0) + Name (varPortIndex, 0) + Store (Buffer (256) {}, Local7) + CreateWordField (Local7, 0x0, varReturnBufferLength) + Store (3, varReturnBufferLength) + CreateByteField (Local7, 0x2, varReturnStatus) + Store (1, varReturnStatus) + if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { + Store (" No action. [Policy type]", Debug) + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { + Store (" No action. [Policy not started]", Debug) + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + CreateWordField (Arg0, 0x2, varClientId) + CreateWordField (Arg0, 0x4, varValidFlag) + CreateWordField (Arg0, 0x6, varFlag) + CreateByteField (Arg0, 0x8, varRequestType) + CreateByteField (Arg0, 0x9, varRequestData) + + Store (" Client ID:", Debug) + Store (varClientId, Debug) + Store (" Valid Flags:", Debug) + Store (varValidFlag, Debug) + Store (" Flags:", Debug) + Store (varFlag, Debug) + Store (" Request Type:", Debug) + Store (varRequestType, Debug) + Store (" Request Data:", Debug) + Store (varRequestData, Debug) + + And (ShiftRight (varClientId, 8), 0xff, varClientBus) + While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) { + Increment (varPortIndex) + Continue + } + Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) + And (ShiftRight (Local1, 16), 0xff, Local2) //Local2 Port Subordinate Bus number + And (ShiftRight (Local1, 8), 0xff, Local1) //Local1 Port Secondary Bus number + if (LAnd (LLess (varClientBus, Local1), LGreater (varClientBus, Local2))) { + Increment (varPortIndex) + Continue + } + Store ("Performance request for port index", Debug) + Store (varPortIndex, Debug) + + if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) { + Store (varClientId, Index (varPsppClientIdArray, varPortIndex)) + } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) { + // We already have registered client + Store (" No action. [Unsupported request]", Debug) + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + if (LEqual (varRequestData, 0)) { + Store (0x0000, Index (varPsppClientIdArray, varPortIndex)) + } else { + if (LEqual (And (varValidFlag, varFlag), 0x1)) { + Store (DerefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), Index (varPsppClientCapabilityArray, varPortIndex)) + } else { + Store (varRequestData, Index (varPsppClientCapabilityArray, varPortIndex)) + } + } + procApplyPsppState () + Store (2, varReturnStatus) + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * PSPP Start/Stop Management Request + * + * Arg0 - Data Buffer + */ + Method (procPsppControl, 1, Serialized) { + Store ("PsppControl Enter", Debug) + Store (Buffer (256) {}, Local7) + CreateWordField (Local7, 0x0, varReturnBufferLength) + Store (3, varReturnBufferLength) + CreateByteField (Local7, 0x2, varReturnStatus) + CreateByteField (Arg0, 0x2, varArgPsppRequest) + Store (varArgPsppRequest, varPsppPolicyService) + // Set DPM state for PSPP Power Saving, due to this policy will not attend ApplyPsppState service. + if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { + procNbLclkDpmActivate(1, varPsppAcDcState) + } + //Reevaluate PCIe speed for all devices base on PSPP state switch to boot up voltage + if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { + // Load default speed capability state + if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCEHIGH)) { + procCopyPackage (RefOf (varPsppMaxPortCapabilityArray), RefOf (varPsppCurrentCapabilityArray)) + } else { + procCopyPackage (RefOf (varDefaultGen1CapabilityArray), RefOf (varPsppCurrentCapabilityArray)) + } + // Unregister all clients + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { + Name (varDefaultPsppClientIdArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}) + procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray)) + } + procApplyPsppState () + } + Store (3, varReturnBufferLength) + Store (0, varReturnStatus) + Store ("PsppControl Exit", Debug) + return (Local7) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Evaluate PCIe speed on all links according to PSPP state and client requests + * + * + * + */ + Method (procApplyPsppState, 0, Serialized) { + Store ("ApplyPsppState Enter", Debug) + Name (varPortIndex, 0) + Name (varLowPowerMode, 0) + Name (varPcieCapabilityArray, Package () {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}) + + Store (0, varPortIndex) + While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LNotEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) { + Store (procGetPortRequestedCapability (varPortIndex), Index (varPcieCapabilityArray, varPortIndex)) + } + Increment (varPortIndex) + } + if (LNotEqual(Match (varPcieCapabilityArray, MEQ, 0x01, MTR, 0, 0), ONES)) { + procCopyPackage (RefOf (varDefaultGen1CapabilityArray), RefOf (varPcieCapabilityArray)) + } + if (LNotEqual(Match (varPcieCapabilityArray, MEQ, 0x03, MTR, 0, 0), ONES)) { + // Set GEN2 voltage + Store ("Set GEN2 VID", Debug) + procPcieSetVoltage (varGen2Vid, 1) + procPcieAdjustPll (2) + procNbLclkDpmActivate(2, varPsppAcDcState) + } + Store (0, varPortIndex) + While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) { + Increment (varPortIndex) + Continue + } + Store (procGetPortCurrentCapability (varPortIndex), Local0) + Store (DerefOf (Index (varPcieCapabilityArray, varPortIndex)), Local2) + if (LEqual (Local0, Local2)) { + Increment (varPortIndex) + Continue + } + procSetPortCapabilityAndSpeed (varPortIndex, Local2, 0) + Increment (varPortIndex) + } + if (LEqual(Match (varPcieCapabilityArray, MEQ, 0x03, MTR, 0, 0), ONES)) { + // Set GEN1 voltage + Store ("Set GEN1 VID", Debug) + procNbLclkDpmActivate(1, varPsppAcDcState) + procPcieAdjustPll (1) + procPcieSetVoltage (varGen1Vid, 0) + } + Store ("ApplyPsppState Exit", Debug) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCI config register + * + * Arg0 - Port Index + * + */ + Method (procGetPortRequestedCapability, 1) { + Store (0x3, Local0) + if (LEqual (DerefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { + if (LOr (LEqual (varPsppAcDcState, DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) { + // Default policy cap to GEN1 + Store (0x2, Local0) + } + } else { + Store (DerefOf (Index (varPsppClientCapabilityArray, Arg0)), Local0) + } + return (Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCI config register + * + * Arg0 - Port Index + * + */ + Method (procGetPortCurrentCapability, 1) { + return (DerefOf (Index (varPsppCurrentCapabilityArray, Arg0))) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Set capability and speed + * + * Arg0 - Port Index + * Arg1 - Capability + * Arg2 - Speed + */ + Method (procSetPortCapabilityAndSpeed, 3) { + Store ("SetPortCapabilityAndSpeed Enter", Debug) + if (LOr (LEqual (Arg1, 0x2), LEqual (Arg1, 0x3))) { + Store ("Port Index = ", Debug) + Store (Arg0, Debug) + Store ("Cap = ", Debug) + Store (Arg1, Debug) + Store ("Speed = ", Debug) + Store (Arg2, Debug) + + Name (varDxF0xE4_xA4, 0x20000001) + Name (varPortPresent, 0x00000000) + Name (varDxF0x88, 0x00000002) + Name (varAXCFGx68_PmCtrl, 0x00000000) + Name (varLcCurrentDataRate,0x00000000) + Name (varSecondaryBus, 0x00000000) + Name (varHeaderType, 0x00000000) + Name (varMultiFunction, 0x00000000) + Name (varPcieLinkControlOffset, 0x00000000) + Name (varPcieLinkControlData, 0x00000000) + Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}) + + + //If request for UMI unhihe port congig space + if (LEqual (Arg0, 6)) { + procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40); + + } + Store (Arg1, Index (varPsppCurrentCapabilityArray, Arg0)) + if (LEqual (Arg1, 0x2)) { + //Gen1 + Store (0x00000000, varDxF0xE4_xA4) + Store (0x21, varDxF0x88) + } + + // Programming for LcInitSpdChgWithCsrEn + if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { + // Registered port, LcInitSpdChgWithCsrEn = 0. + procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0) + } else { + procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000) + } + + // Initialize port + procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), varDxF0xE4_xA4) + //set target link speed + Store (ShiftLeft (Add( Arg0, 2), 3), Local0) + procPciDwordRMW (Local0, 0x88, Not (0x0000002f), varDxF0x88) + + // Determine port PCI address and check port present + Store (ShiftLeft (Add( Arg0, 2), 3), Local0) + And (procPciDwordRead (Local0, 0x70), 0x400000, varPortPresent) + if (LNotEqual (varPortPresent, 0)) { + //Disable ASPM on EP + if (LNotEqual (Arg0, 6)) { + Store (procPciDwordRead (Local0, 0x18), Local3) + Store (And (ShiftRight (Local3, 8), 0xFF), varSecondaryBus) + Store ("Disable EP ASPM on SecondaryBus = ", Debug) + Store (varSecondaryBus, Debug) + Store (ShiftLeft (varSecondaryBus, 8), Local3) + Store (procPciDwordRead (Local3, 0xC), Local3) + Store (And (ShiftRight (Local3, 16), 0xFF), varHeaderType) + Store ("Header Type = ", Debug) + Store (varHeaderType, Debug) + + if (LNotEqual (And (varHeaderType, 0x80), 0)) { + Store (0x7, varMultiFunction) + } + + Store (ShiftLeft (varSecondaryBus, 8), Local3) + Store (0, Local2) + while (LLessEqual (Local2, varMultiFunction)) { + + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Local3, 0x10), varPcieLinkControlOffset) + if (LNotEqual (varPcieLinkControlOffset, 0)) { + Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) + + Store ("Function number of SecondaryBus = ", Debug) + Store (Local2, Debug) + Store ("Find PcieLinkControl register offset = ", Debug) + Store (varPcieLinkControlOffset, Debug) + // Save ASPM on EP + Store (procPciDwordRead (Local3, varPcieLinkControlOffset), varPcieLinkControlData) + Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, Local2)) + Store ("PcieLinkControlData = ", Debug) + Store (varPcieLinkControlData, Debug) + Store ("Save ASPM = ", Debug) + Store (DerefOf (Index (varPcieLinkControlArray, Local2)), Debug) + // Disable ASPM + if (LNotEqual (And (varPcieLinkControlData, 0x3), 0x0)) { + procPciDwordRMW (Local3, varPcieLinkControlOffset, Not (0x00000003), 0x00) + Store ("Disable ASPM on EP Complete!!", Debug) + } + } + Increment (Local2) + Increment (Local3) + } + + } else { + + Store (procPcieSbAspmControl (0, 0), varAXCFGx68_PmCtrl) + And (varAXCFGx68_PmCtrl, 0x3, Local1) + if (LNotEqual (Local1, 0x0)) { + procPcieSbAspmControl (0, 1) + } + } + Store (1, Local2) + while (Local2) { + //retrain port + procPciDwordRMW (Local0, 0x68, Not (0x00000000), 0x20) + Sleep (30) + while (And (procPciDwordRead (Local0, 0x68), 0x08000000)) {Sleep (10)} + Store (0, Local2) + if (LEqual (Arg1, 0x2)) { // if Gen1 + Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentDataRate) + if (LNotEqual (And (varLcCurrentDataRate, 0x800), 0)) { + Store (1, Local2) + } + } + } + //restore ASPM setting + if (LNotEqual (Arg0, 6)) { + // Restore EP + //if (LNotEqual (varPcieLinkControlOffset, 0)) { + // procPciDwordWrite (Local3, varPcieLinkControlOffset, varPcieLinkControlData) + //} + Store (ShiftLeft (varSecondaryBus, 8), Local3) + Store (0, Local2) + while (LLessEqual (Local2, varMultiFunction)) { + + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Local3, 0x10), varPcieLinkControlOffset) + if (LNotEqual (varPcieLinkControlOffset, 0)) { + Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) + + Store ("Restore Function number of SecondaryBus = ", Debug) + Store (Local2, Debug) + Store ("Restore Find PcieLinkControl register offset = ", Debug) + Store (varPcieLinkControlOffset, Debug) + Store ("Restore ASPM = ", Debug) + Store (DerefOf (Index (varPcieLinkControlArray, Local2)), Debug) + procPciDwordWrite (Local3, varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, Local2))) + } + Increment (Local2) + Increment (Local3) + } + + } else { + // Restore SB + procPcieSbAspmControl (varAXCFGx68_PmCtrl, 1) + } + } else { + Store (" Device not present. Set capability and speed only", Debug) + } + //If request for UMI hide port congig space + if (LEqual (Arg0, 6)) { + procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00); + } + } + Store ("SetPortCapabilityAndSpeed Exit", Debug) + } + Mutex (varVoltageChangeMutex, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * Request VID + * + * Arg0 - VID index + * Arg1 - 0 = do not wait intil voltage is set + * 1 = wait until voltage is set + */ + Method (procPcieSetVoltage, 2) { + Store ("PcieSetVoltage(procPcieSetVoltage) Enter", Debug) + Acquire(varVoltageChangeMutex, 0xFFFF) + Store (procIndirectRegisterRead (0x0, 0x60, 0xEA), Local1) + //Enable voltage change + Or (Local1, 0x2, Local1) + procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1) + //Clear voltage index + And (Local1, Not (ShiftLeft (0x3, 3)), Local1) + //Set new voltage index + Store (" Voltage Index:", Debug) + Store (Arg0, Debug) + Or (Local1, ShiftLeft (Arg0, 3), Local1) + //Togle request + And (Not (Local1), 0x4, Local2) + Or (And (Local1, Not (0x4)), Local2, Local1) + procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1) + if (LNotEqual (Arg1, 0)) { + while (LNotEqual (ShiftLeft(Local1, 0x2), Local2)) { + And (procIndirectRegisterRead (0x0, 0x60, 0xEB), 0x1, Local1) + } + } + Release (varVoltageChangeMutex) + Store ("PcieSetVoltage(procPcieSetVoltage) Exit", Debug) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - Ref Source Pckage + * Arg1 - Ref to Destination Package + * + */ + Method (procCopyPackage, 2, NotSerialized) { + + Store (SizeOf (Arg0), Local1) + Store (0, Local0) + While (LLess (Local0, Local1)) { + Store (DerefOf(Index(DerefOf (Arg0), Local0)), Index(DerefOf (Arg1), Local0)) + Increment (Local0) + } + } + |