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path: root/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
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Diffstat (limited to 'src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c')
-rw-r--r--src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
index 5a288a429c..ef868203dd 100644
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
+++ b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
@@ -424,9 +424,9 @@ PcieLockRegisters (
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
- CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS),
- D0F0xE4_CORE_0010_HwInitWrLock_OFFSET,
- D0F0xE4_CORE_0010_HwInitWrLock_WIDTH,
+ CORE_SPACE (CoreId, 0x10),
+ 0,
+ 1,
0x1,
TRUE,
Pcie