diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/Proc/GNB/Modules')
4 files changed, 17 insertions, 24 deletions
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c index f2ba2cf0da..468e57f74c 100644 --- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c +++ b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c @@ -158,10 +158,10 @@ GnbLpcDmaDeadlockPrevention ( // For GPP Link core, enable special NP memory write protocol on the processor side PCIE controller GnbLibPciIndirectRMW ( NbPciAddress.AddressValue | D0F0xE0_ADDRESS, - CORE_SPACE (1, D0F0xE4_CORE_0010_ADDRESS), + CORE_SPACE (1, 0x10), AccessWidth32, 0xFFFFFFFF, - 1 << D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET, + 1 << 9, StdHeader ); @@ -244,4 +244,4 @@ GnbLock ( TRUE, StdHeader ); -}
\ No newline at end of file +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c index 31d5f5a0db..b2c490f122 100644 --- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c +++ b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c @@ -144,9 +144,9 @@ PcieLinkInitHotplug ( ); PcieRegisterWriteField ( PcieEngineGetParentWrapper (Engine), - CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS), - D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET, - D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH, + CORE_SPACE (Engine->Type.Port.CoreId, 0x10), + 1, + 3, 0x5, TRUE, Pcie diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index e45ecc67a1..2bddde40f1 100644 --- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -525,29 +525,22 @@ PcieTopologyInitSrbmReset ( IN PCIe_PLATFORM_CONFIG *Pcie ) { - D0F0xE4_WRAP_8063_STRUCT D0F0xE4_WRAP_8063; - D0F0xE4_WRAP_8063.Value = PcieRegisterRead ( + UINT32 pcireg; + UINT32 regmask = 0x7030;; + pcireg = PcieRegisterRead ( Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8063_ADDRESS), + WRAP_SPACE (Wrapper->WrapId, 0x8063), Pcie ); if (SrbmResetEnable) { - D0F0xE4_WRAP_8063.Field.ResetSrbm0En = 0x1; - D0F0xE4_WRAP_8063.Field.ResetSrbm1En = 0x1; - D0F0xE4_WRAP_8063.Field.ResetSrbmNbEn = 0x1; - D0F0xE4_WRAP_8063.Field.ResetSrbmGfxEn = 0x1; - D0F0xE4_WRAP_8063.Field.ResetSrbmDcEn = 0x1; + pcireg |= regmask; } else { - D0F0xE4_WRAP_8063.Field.ResetSrbm0En = 0x0; - D0F0xE4_WRAP_8063.Field.ResetSrbm1En = 0x0; - D0F0xE4_WRAP_8063.Field.ResetSrbmNbEn = 0x0; - D0F0xE4_WRAP_8063.Field.ResetSrbmGfxEn = 0x0; - D0F0xE4_WRAP_8063.Field.ResetSrbmDcEn = 0x0; + pcireg &= ~(regmask); } PcieRegisterWrite ( Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8063_ADDRESS), - D0F0xE4_WRAP_8063.Value, + WRAP_SPACE (Wrapper->WrapId, 0x8063), + pcireg, FALSE, Pcie ); diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c index 5a288a429c..ef868203dd 100644 --- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +++ b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c @@ -424,9 +424,9 @@ PcieLockRegisters ( for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { PcieRegisterWriteField ( Wrapper, - CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS), - D0F0xE4_CORE_0010_HwInitWrLock_OFFSET, - D0F0xE4_CORE_0010_HwInitWrLock_WIDTH, + CORE_SPACE (CoreId, 0x10), + 0, + 1, 0x1, TRUE, Pcie |