diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/Proc/GNB/Nb')
31 files changed, 6604 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c new file mode 100644 index 0000000000..3c918aa2cb --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c @@ -0,0 +1,348 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * LCLK DPM initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39007 $ @e \$Date: 2010-10-05 00:32:54 +0800 (Tue, 05 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbFuseTable.h" +#include "GnbPcie.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "GnbRegistersON.h" +#include "OptionGnb.h" +#include "GfxLib.h" +#include "NbConfigData.h" +#include "NbSmuLib.h" +#include "NbLclkDpm.h" +#include "NbFamilyServices.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_NB_FAMILY_0X14_F14NBLCLKDPM_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +UINT32 LclkDpmCacTable [] = { + 0x0, + 0x0, + 0x0, + 0x0 +}; + +UINT32 LclkDpmActivityThresholdTable [] = { + 0x100, + 0x40FFFF, + 0x40FFFF, + 0x0 +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Init NB LCLK DPM in Root Complex Activity mode + * + * + * + * @param[in] StdHeader Pointer to Standard configuration + * @retval Initialization status + */ + +AGESA_STATUS +NbFmInitLclkDpmRcActivity ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PP_FUSE_ARRAY *PpFuseArray; + INT8 Index; + UINTN LclkState; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "NbFmInitLclkDpmRcActivity F14 Enter\n"); + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + if (PpFuseArray != NULL) { + UINT32 ActivityThreshold [8]; + UINT16 SamplingPeriod [10]; + UINT8 LclkScalingDid [4]; + UINT8 LclkScalingVid [4]; + UINT32 LclkDpmValid; + UINT32 MainPllVcoKHz; + LibAmdMemFill (&ActivityThreshold[0], 0, sizeof (ActivityThreshold), StdHeader); + LibAmdMemFill (&SamplingPeriod[0], 0, sizeof (SamplingPeriod), StdHeader); + MainPllVcoKHz = GfxLibGetMainPllFreq (StdHeader) * 100; + LclkDpmValid = 0; + LclkState = 7; + for (Index = 3; Index >= 0; Index--) { + if (PpFuseArray->LclkDpmValid [Index] != 0) { + // Set valid DPM state + LclkDpmValid |= (1 << (LclkState)); + // Set LCLK scaling DID + LclkScalingDid [7 - LclkState] = PpFuseArray->LclkDpmDid [Index]; + // Set LCLK scaling VID + LclkScalingVid [7 - LclkState] = PpFuseArray->LclkDpmVid [Index]; + // Set sampling period + SamplingPeriod [LclkState] = 0xC350; + // Changed from 0xC350 to 0x1388 for DPM 0 + if (Index == 0) { + SamplingPeriod [LclkState] = 0x1388; + } + // Set activity threshold from BKDG: + // Raising -- ActivityThreshold [LclkState] = ((102 * (GfxLibCalculateClk (LclkScalingDid [7 - LclkState], MainPllVcoKHz) / 100)) - 10) / 10; + // Lowering -- ActivityThreshold [LclkState] |= (((407 * (GfxLibCalculateClk (LclkScalingDid [7 - LclkState], MainPllVcoKHz) / 100)) + 99) / 10) << 16; + // For ON specific enable LCLK DPM : + ActivityThreshold [LclkState] = LclkDpmActivityThresholdTable [Index]; + + IDS_HDT_CONSOLE (GNB_TRACE, "Fused State Index:%d LCLK DPM State [%d]: LclkScalingDid - 0x%x, ActivityThreshold - 0x%x, SamplingPeriod - 0x%x\n", + Index, LclkState, LclkScalingDid [7 - LclkState], ActivityThreshold [LclkState], SamplingPeriod [LclkState] + ); + LclkState--; + } + } + if (LclkState != 7) { + SMUx33_STRUCT SMUx33; + SMUx0B_x8434_STRUCT SMUx0B_x8434; + FCRxFF30_01E4_STRUCT FCRxFF30_01E4; + UINT8 CurrentUnit; + UINT16 FinalUnit; + UINT16 FinalPeriod; + UINT32 Freq; + UINT32 FreqDelta; + UINT32 Value; + ASSERT (LclkScalingDid [0] != 0); + FreqDelta = 0xffffffff; + FinalPeriod = 0; + FinalUnit = 0; + Freq = (65535 * 100 * 100) / GfxLibCalculateClk (LclkScalingDid [0], MainPllVcoKHz); + for (CurrentUnit = 0; CurrentUnit < 16; CurrentUnit++) { + UINT32 CurrentFreqDelta; + UINT32 CurrentPeriod; + UINT32 Temp; + Temp = GnbLibPowerOf (4, CurrentUnit); + CurrentPeriod = Freq / Temp; + if (CurrentPeriod <= 0xFFFF) { + CurrentFreqDelta = Freq - Temp * CurrentPeriod; + if (FreqDelta > CurrentFreqDelta) { + FinalUnit = CurrentUnit; + FinalPeriod = (UINT16) CurrentPeriod; + FreqDelta = CurrentFreqDelta; + } + } + } + //Process to enablement LCLK DPM States + NbSmuIndirectRead (SMUx33_ADDRESS, AccessWidth32, &SMUx33.Value, StdHeader); + SMUx33.Field.BusyCntSel = 0x3; + SMUx33.Field.LclkActMonUnt = FinalUnit; + SMUx33.Field.LclkActMonPrd = FinalPeriod; + NbSmuIndirectWrite (SMUx33_ADDRESS, AccessS3SaveWidth32, &SMUx33.Value, StdHeader); + SMUx0B_x8434.Value = 0; + SMUx0B_x8434.Field.LclkDpmType = 0x1; + SMUx0B_x8434.Field.LclkDpmEn = 0x1; + SMUx0B_x8434.Field.LclkTimerPeriod = 0x0C350; + SMUx0B_x8434.Field.LclkTimerPrescalar = 0x1; + NbSmuRcuRegisterWrite ( + SMUx0B_x8434_ADDRESS, + &SMUx0B_x8434.Value, + 1, + TRUE, + StdHeader + ); + NbSmuRcuRegisterWrite ( + 0x84AC, + &LclkDpmCacTable[0], + sizeof (LclkDpmCacTable) / sizeof (UINT32), + TRUE, + StdHeader + ); + // Program activity threshold + IDS_HDT_CONSOLE (GNB_TRACE, "ActivityThreshold[4] - 0x%x ActivityThreshold[5] - 0x%x ActivityThreshold[6] - 0x%x ActivityThreshold[7] - 0x%x\n", + ActivityThreshold[4], ActivityThreshold[5], ActivityThreshold[6], ActivityThreshold [7] + ); + NbSmuRcuRegisterWrite ( + SMUx0B_x8470_ADDRESS, + &ActivityThreshold[4], + 4, + TRUE, + StdHeader + ); + // Program sampling period + for (Index = 0; Index < (sizeof (SamplingPeriod) / sizeof (SamplingPeriod[0])); Index = Index + 2) { + UINT16 Temp; + Temp = SamplingPeriod[Index]; + SamplingPeriod[Index] = SamplingPeriod[Index + 1]; + SamplingPeriod[Index + 1] = Temp; + } + IDS_HDT_CONSOLE (GNB_TRACE, "SamplingPeriod[4] - 0x%x SamplingPeriod[5] - 0x%x SamplingPeriod[6] - 0x%x SamplingPeriod[7] - 0x%x \n", + SamplingPeriod[4], SamplingPeriod[5], SamplingPeriod[6], SamplingPeriod[7] + ); + NbSmuRcuRegisterWrite ( + SMUx0B_x8440_ADDRESS, + (UINT32*) &SamplingPeriod[4], + 2, + TRUE, + StdHeader + ); + // Program LCK scaling DID + NbSmuRcuRegisterWrite ( + SMUx0B_x848C_ADDRESS, + (UINT32*) &LclkScalingDid[0], + 1, + TRUE, + StdHeader + ); + // Program LCK scaling VID + NbSmuRcuRegisterWrite ( + SMUx0B_x8498_ADDRESS, + (UINT32*) &LclkScalingVid[0], + 1, + TRUE, + StdHeader + ); + // Program valid LCLK DPM states + LclkDpmValid = NbFmDpmStateBootupInit (LclkDpmValid, StdHeader); + NbSmuRcuRegisterWrite ( + SMUx0B_x8490_ADDRESS, + &LclkDpmValid, + 1, + TRUE, + StdHeader + ); + //Setup Activity Monitor Coefficients + Value = (0x24 << SMUx35_DownTrendCoef_OFFSET) | (0x24 << SMUx35_UpTrendCoef_OFFSET); + NbSmuIndirectWrite (SMUx35_ADDRESS, AccessS3SaveWidth32, &Value, StdHeader); + Value = (0x22 << SMUx35_DownTrendCoef_OFFSET) | (0x22 << SMUx35_UpTrendCoef_OFFSET); + for (Index = SMUx37_ADDRESS; Index <= SMUx51_ADDRESS; Index = Index + 2) { + NbSmuIndirectWrite (Index, AccessS3SaveWidth32, &Value, StdHeader); + } + // Enable LCLK DPM as voltage client + NbSmuSrbmRegisterRead (FCRxFF30_01E4_ADDRESS, &FCRxFF30_01E4.Value, StdHeader); + FCRxFF30_01E4.Field.VoltageChangeEn = 0x1; + NbSmuSrbmRegisterWrite (FCRxFF30_01E4_ADDRESS, &FCRxFF30_01E4.Value, TRUE, StdHeader); + // Start LCLK service + NbSmuServiceRequest (0x8, TRUE, StdHeader); + } + } else { + IDS_HDT_CONSOLE (GNB_TRACE, " ERROR! Cannot locate fuse table\n"); + Status = AGESA_ERROR; + } + IDS_HDT_CONSOLE (GNB_TRACE, "NbFmInitLclkDpmRcActivity F14 Exit [0x%x]\n", Status); + return Status; +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Family specific check PsppPolicy to initially enable appropriate DPM states + * + * + * @param[in] LclkDpmValid UINT32 Lclk Dpm Valid + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + */ +UINT32 +NbFmDpmStateBootupInit ( + IN UINT32 LclkDpmValid, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIe_PLATFORM_CONFIG *Pcie; + UINT32 LclkDpmValidState; + UINT8 Dpm0ValidOffset; + + if ((LclkDpmValid & 0xFF) == 0) { + IDS_HDT_CONSOLE (NB_MISC, " No valid DPM State Bootup Init\n"); + return 0; + } + + // For ON, from DPM0(the most right non-zero bit) to highest DPM(bit 7) + Dpm0ValidOffset = LibAmdBitScanForward (LclkDpmValid & 0xFF); + // Enable DPM0 + LclkDpmValidState = 1 << Dpm0ValidOffset; + + if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { + switch (Pcie->PsppPolicy) { + case PsppDisabled: + case PsppPerformance: + case PsppBalanceHigh: + if ((Dpm0ValidOffset + 2) <= 7) { + // Enable DPM0 + DPM2 + LclkDpmValidState = LclkDpmValidState + (1 << (Dpm0ValidOffset + 2)); + } + break; + case PsppBalanceLow: + if ((Dpm0ValidOffset + 1) <= 7) { + // Enable DPM0 + DPM1 + LclkDpmValidState = LclkDpmValidState + (1 << (Dpm0ValidOffset + 1)); + } + break; + case PsppPowerSaving: + // Enable DPM0 + break; + default: + ASSERT (FALSE); + } + } else { + IDS_HDT_CONSOLE (NB_MISC, " DPM State Bootup Init Pcie Locate ConfigurationData Fail!! -- Enable DPM0 only\n"); + } + return LclkDpmValidState; +} + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c new file mode 100644 index 0000000000..889fec3249 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c @@ -0,0 +1,222 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB Lclk/Nclk Ratios + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 41658 $ @e \$Date: 2010-11-09 06:39:38 +0800 (Tue, 09 Nov 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "GnbFuseTable.h" +#include "Gnb.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include "GfxLib.h" +#include "GnbRegistersON.h" +#include "F14NbLclkNclkRatio.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_NB_FAMILY_0X14_F14NBLCLKNCLKRATIO_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT8 NclkDiv; + UINT8 LclkDid; +} NLCK_SCLK; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Power gate unused blocks + * + * + * + * @param[in] Nclk10kHz NCLK + * @param[in] Lclk10kHz LCLK + * @param[in] LclkNclk NCLK/LCLK array + * @retval AGESA_STATUS + */ + +VOID +STATIC +F14NbLclkNclkAllocatePair ( + IN UINT8 NclkDiv, + IN UINT8 LclkDid, + IN OUT NLCK_SCLK *LclkNclk + ) +{ + UINTN Index; + for (Index = 0; Index < 8 ; Index++) { + if (LclkNclk[Index].LclkDid == 0 && LclkNclk[Index].NclkDiv == 0) { + LclkNclk[Index].LclkDid = LclkDid; + LclkNclk[Index].NclkDiv = NclkDiv; + break; + } else if (LclkNclk[Index].LclkDid == LclkDid && LclkNclk[Index].NclkDiv == NclkDiv) { + break; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Power gate unused blocks + * + * + * + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +F14NbLclkNclkRatioFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PP_FUSE_ARRAY *PpFuseArray; + D18F3xD4_STRUCT D18F3xD4; + D18F3xDC_STRUCT D18F3xDC; + D18F6x90_STRUCT D18F6x90; + D18F6x110_STRUCT D18F6x110; + UINT32 MainPllFreq10kHz; + UINT8 NclkDiv[2]; + INT32 Nclk_offset; + INT32 Lclk_offset; + UINT8 Index; + UINT8 LclkIndex; + UINT32 Lclk_period; + UINT32 Nclk_period; + NLCK_SCLK LclkNclk [8]; + IDS_HDT_CONSOLE (GNB_TRACE, "F14NbLclkNclkRatioFeature Enter\n"); + PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray == NULL) { + IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); + return AGESA_ERROR; + } + + //main PLL COF in 10kHz + MainPllFreq10kHz = GfxLibGetMainPllFreq (StdHeader) * 100; + + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xD4_ADDRESS), + AccessWidth32, + &D18F3xD4.Value, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xDC_ADDRESS), + AccessWidth32, + &D18F3xDC.Value, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS), + AccessWidth32, + &D18F6x90.Value, + StdHeader + ); + + NclkDiv[0] = (UINT8) D18F3xDC.Field.NbPs0NclkDiv; + NclkDiv[1] = (UINT8) D18F6x90.Field.NbPs1NclkDiv; + + LibAmdMemFill(&LclkNclk, 0x0, sizeof (LclkNclk), StdHeader); + + for (Index = 0; Index < 2; Index++) { + if (NclkDiv[Index] != 0) { + for (LclkIndex = 0; LclkIndex < 4; LclkIndex++) { + if ((PpFuseArray->LclkDpmValid[LclkIndex] != 0) && (PpFuseArray->LclkDpmDid[LclkIndex] != 0)) { + F14NbLclkNclkAllocatePair (NclkDiv[Index], PpFuseArray->LclkDpmDid[LclkIndex], &LclkNclk[0]); + } + } + } + }; + for (Index = 0; Index < 8; Index++) { + if (LclkNclk[Index].NclkDiv != 0 && LclkNclk[Index].LclkDid != 0) { + UINT32 Nclk10kHz; + UINT32 Lclk10kHz; + Nclk10kHz = GfxLibCalculateNclk (LclkNclk[Index].NclkDiv, MainPllFreq10kHz); + Lclk10kHz = GfxLibCalculateClk (LclkNclk[Index].LclkDid, MainPllFreq10kHz); + IDS_HDT_CONSOLE (GNB_TRACE, " Offset for Nclk = %d Lclk = %d\n", Nclk10kHz / 100, Lclk10kHz / 100); + Lclk_period = 100000000 / Lclk10kHz; + Nclk_period = 100000000 / Nclk10kHz; + + if ((Nclk10kHz * 2) >= Lclk10kHz) { + Nclk_offset = (Nclk_period * 35 - 30110) / (Lclk_period * 10); + Lclk_offset = - 1 - (INT32) ((491 * 10 + Nclk_period * 65 + 3052 * 10 - 1) / (Lclk_period * 10) + 1); + } else { + Nclk_offset = - (INT32) (MIN (2 * (961 * 10 + 175 * Lclk_period + 3011 * 10 - 1) / (Nclk_period * 10) + 1, + 2 * (961 * 10 + 165 * Lclk_period + 3011 * 10 - 1) / (Nclk_period * 10) + 1 + 1)); + Lclk_offset = MAX (2 * (35 * Lclk_period - 3052 * 10) / (Nclk_period * 10), + 2 * (45 * Lclk_period - 3052 * 10) / (Nclk_period * 10) - 1); + } + Nclk_offset = Nclk_offset % 8; + Lclk_offset = Lclk_offset % 8; + + D18F6x110.Field.NclkFreqType = 1; + D18F6x110.Field.NclkFreq = LclkNclk[Index].NclkDiv; + D18F6x110.Field.LclkFreqType = 1; + D18F6x110.Field.LclkFreq = LclkNclk[Index].LclkDid; + D18F6x110.Field.Enable = 1; + D18F6x110.Field.PllMult = D18F3xD4.Field.MainPllOpFreqId + 16; + D18F6x110.Field.LclkFifoOff = Lclk_offset & 0x7; + D18F6x110.Field.NclkFifoOff = Nclk_offset & 0x7; + + GnbLibPciWrite ( + MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x110_ADDRESS + Index * 4), + AccessS3SaveWidth32, + &D18F6x110.Value, + StdHeader + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "F14NbLclkNclkRatioFeature Exit\n"); + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.h new file mode 100644 index 0000000000..3a07f21cef --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB Lclk/Nclk Ratio + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _F14NBLCLKNCLKRATIO_H_ +#define _F14NBLCLKNCLKRATIO_H_ + +AGESA_STATUS +F14NbLclkNclkRatioFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c new file mode 100644 index 0000000000..8b717fb8bb --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c @@ -0,0 +1,636 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB Power gate Gfx/Uvd/Gmc + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 41777 $ @e \$Date: 2010-11-10 22:29:39 +0800 (Wed, 10 Nov 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbFuseTable.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include "GnbRegistersON.h" +#include "GfxLib.h" +#include "NbSmuLib.h" +#include "NbConfigData.h" +#include "NbFamilyServices.h" +#include "GfxLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_NB_FAMILY_0x14_F14NBPOWERGATE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define POWER_GATE_GMC_PSO_CONTROL_VALID_NUM 1 +#define POWER_GATE_GMC_MOTH_PSO_PWRUP 153 +#define POWER_GATE_GMC_MOTH_PSO_PWRDN 50 +#define POWER_GATE_GMC_DAUG_PSO_PWRUP 50 +#define POWER_GATE_GMC_DAUG_PSO_PWRDN 0 +#define POWER_GATE_GMC_RESET_TIMER 10 +#define POWER_GATE_GMC_ISO_TIMER 10 +#define POWER_GATE_GMC_SAVE_RESTORE_WIDTH 2 +#define POWER_GATE_GMC_RSO_RESTORE_TIMER 10 +#define POWER_GATE_GMCPSO_CONTROL_PERIOD_7to4 7 +#define POWER_GATE_GMCPSO_CONTROL_PERIOD_3to0 7 + + +#define POWER_GATE_UVD_MOTH_PSO_PWRUP 113 +#define POWER_GATE_UVD_MOTH_PSO_PWRDN 50 +#define POWER_GATE_UVD_DAUG_PSO_PWRUP 50 +#define POWER_GATE_UVD_DAUG_PSO_PWRDN 50 +#define POWER_GATE_UVD_RESET_TIMER 50 +#define POWER_GATE_UVD_ISO_TIMER 50 +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +POWER_GATE_DATA F14NbGmcPowerGatingData = { + POWER_GATE_GMC_MOTH_PSO_PWRUP, + POWER_GATE_GMC_MOTH_PSO_PWRDN, + POWER_GATE_GMC_DAUG_PSO_PWRUP, + POWER_GATE_GMC_DAUG_PSO_PWRDN, + POWER_GATE_GMC_RESET_TIMER, + POWER_GATE_GMC_ISO_TIMER +}; + +/// GMC power gating +UINT32 F14GmcPowerGatingTable_1[] = { +// SMUx0B_x8408_ADDRESS + 0, +// SMUx0B_x840C_ADDRESS + 0, +// SMUx0B_x8410_ADDRESS + (0x1 << SMUx0B_x8410_PwrGatingEn_OFFSET) | + (0x0 << SMUx0B_x8410_Reserved_2_1_OFFSET) | + (POWER_GATE_GMC_PSO_CONTROL_VALID_NUM << SMUx0B_x8410_PsoControlValidNum_OFFSET) | + (((POWER_GATE_GMCPSO_CONTROL_PERIOD_7to4 << 4) | POWER_GATE_GMCPSO_CONTROL_PERIOD_3to0) << SMUx0B_x8410_SavePsoDelay_OFFSET) | + (0x0 << SMUx0B_x8410_PwrGaterSel_OFFSET) +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * GMC Power Gating + * + * + * @param[in] StdHeader Standard Configuration Header + * @param[in] PowerGateData Pointer power gate data + * @retval AGESA_STATUS + */ + +AGESA_STATUS +STATIC +F14NbSmuGmcPowerGatingInit ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN POWER_GATE_DATA *PowerGateData + ) +{ + SMUx0B_x8504_STRUCT SMUx0B_x8504; + + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcPowerGatingInit Enter\n"); + NbSmuRcuRegisterWrite ( + SMUx0B_x8408_ADDRESS, + &F14GmcPowerGatingTable_1[0], + sizeof (POWER_GATE_DATA) / sizeof (UINT32), + TRUE, + StdHeader + ); + + NbSmuRcuRegisterWrite ( + SMUx0B_x84A0_ADDRESS, + (UINT32 *) PowerGateData, + sizeof (POWER_GATE_DATA) / sizeof (UINT32), + TRUE, + StdHeader + ); + + SMUx0B_x8504.Value = 0; + SMUx0B_x8504.Field.SaveRestoreWidth = POWER_GATE_GMC_SAVE_RESTORE_WIDTH; + SMUx0B_x8504.Field.PsoRestoreTimer = POWER_GATE_GMC_RSO_RESTORE_TIMER; + NbSmuRcuRegisterWrite ( + SMUx0B_x8504_ADDRESS, + &SMUx0B_x8504.Value, + 1, + TRUE, + StdHeader + ); + + NbSmuServiceRequest (0x01, TRUE, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcPowerGatingInit Exit\n"); + return AGESA_SUCCESS; +} + + +POWER_GATE_DATA F14NbUvdPowerGatingData = { + POWER_GATE_UVD_MOTH_PSO_PWRUP, + POWER_GATE_UVD_MOTH_PSO_PWRDN, + POWER_GATE_UVD_DAUG_PSO_PWRUP, + POWER_GATE_UVD_DAUG_PSO_PWRDN, + POWER_GATE_UVD_RESET_TIMER, + POWER_GATE_UVD_ISO_TIMER +}; + +/// UVD power gating +UINT32 F14UvdPowerGatingTable_1[] = { +// SMUx0B_x8408_ADDRESS + 0, +// SMUx0B_x840C_ADDRESS + 0, +// SMUx0B_x8410_ADDRESS + (0x0 << SMUx0B_x8410_PwrGatingEn_OFFSET) | + (0x0 << SMUx0B_x8410_Reserved_2_1_OFFSET) | + (0x1 << SMUx0B_x8410_PsoControlValidNum_OFFSET) | + (0x77 << SMUx0B_x8410_SavePsoDelay_OFFSET) | + (0x2 << SMUx0B_x8410_PwrGaterSel_OFFSET) +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * UVD Power Gating + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @param[in] PowerGateData Pointer power gate data + * + */ + + +VOID +STATIC +F14NbSmuUvdPowerGatingInit ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN POWER_GATE_DATA *PowerGateData + ) +{ + SMUx0B_x8504_STRUCT SMUx0B_x8504; + + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdPowerGatingInit Enter\n"); + NbSmuRcuRegisterWrite ( + SMUx0B_x8408_ADDRESS, + &F14UvdPowerGatingTable_1[0], + sizeof (F14UvdPowerGatingTable_1) / sizeof (UINT32), + TRUE, + StdHeader + ); + + NbSmuRcuRegisterWrite ( + SMUx0B_x84A0_ADDRESS, + (UINT32 *) PowerGateData, + sizeof (POWER_GATE_DATA) / sizeof (UINT32), + TRUE, + StdHeader + ); + + SMUx0B_x8504.Value = 0; + SMUx0B_x8504.Field.SaveRestoreWidth = 0x02; + SMUx0B_x8504.Field.PsoRestoreTimer = 0x0A; + NbSmuRcuRegisterWrite ( + SMUx0B_x8504_ADDRESS, + &SMUx0B_x8504.Value, + 1, + TRUE, + StdHeader + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdPowerGatingInit Exit\n"); + NbSmuServiceRequest (0x01, TRUE, StdHeader); +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * UVD Power Shutdown + * + * + * + * @param[in] StdHeader Standard Configuration Header + */ + + +VOID +STATIC +F14NbSmuUvdShutdown ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdShutdown Enter\n"); + NbSmuServiceRequest (0x03, TRUE, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdShutdown Exit\n"); +} + + +/// GMC shutdown table +UINT32 F14SmuGmcShutdownTable_1[] = { +// SMUx0B_x8600_ADDRESS, + (0x3 << SMUx0B_x8600_TransactionCount_OFFSET) | + (0x8650 << SMUx0B_x8600_MemAddr_7_0__OFFSET), +// SMUx0B_x8604_ADDRESS, + (0xFE << SMUx0B_x8604_Txn1MBusAddr_31_24__OFFSET) | + (0x60 << SMUx0B_x8604_Txn1MBusAddr_23_16__OFFSET) | + (0x14 << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET), +// SMUx0B_x8608_ADDRESS, + (0x03ull << SMUx0B_x8608_Txn1Tsize_OFFSET) | + (0x01ull << SMUx0B_x8608_Txn1Overlap_OFFSET) | + (0x01ull << SMUx0B_x8608_Txn1Mode_OFFSET) | + (0x07ull << SMUx0B_x8608_Txn2Mbusaddr70_OFFSET), +// SMUx0B_x860C_ADDRESS, + (0xFE << SMUx0B_x860C_Txn2MBusAddr3124_OFFSET) | + (0x60 << SMUx0B_x860C_Txn2MBusAddr2316_OFFSET) | + (0x4 << SMUx0B_x860C_Txn2TransferLength70_OFFSET) | + (0x3 << SMUx0B_x860C_Txn2Tsize_OFFSET), +// SMUx0B_x8610_ADDRESS, + (0x1 << SMUx0B_x8610_Txn2Overlap_OFFSET) | + (0x1 << SMUx0B_x8610_Txn2Mode_OFFSET) | + (0x60 << SMUx0B_x8610_Txn3MBusAddr2316_OFFSET) | + (0x6 << SMUx0B_x8610_Txn3MBusAddr70_OFFSET), +// SMUx0B_x8614_ADDRESS, + (0xFEull << SMUx0B_x8614_Txn3MBusAddr3124_OFFSET) | + (0x04ull << SMUx0B_x8614_Txn3TransferLength70_OFFSET) | + (0x03ull << SMUx0B_x8614_Txn3Tsize_OFFSET) | + (0x01ull << SMUx0B_x8614_Txn3Mode_OFFSET), +}; + +UINT32 F14SmuGmcShutdownTable_2[] = { +// SMUx0B_x8650_ADDRESS, + 0x76543210, +// SMUx0B_x8654_ADDRESS, + 0xFEDCBA98, +// SMUx0B_x8658_ADDRESS, + 0x8, +// SMUx0B_x865C_ADDRESS, + 0x00320032, +// SMUx0B_x8660_ADDRESS, + 0x00100010, +// SMUx0B_x8664_ADDRESS, + 0x00320032, +// SMUx0B_x866C_ADDRESS, + 0x00 +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Shutdown GMC + * + * + * + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +STATIC +F14NbSmuGmcShutdown ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcShutdown Enter\n"); + NbSmuRcuRegisterWrite ( + SMUx0B_x8600_ADDRESS, + &F14SmuGmcShutdownTable_1[0], + sizeof (F14SmuGmcShutdownTable_1) / sizeof (UINT32), + TRUE, + StdHeader + ); + + NbSmuRcuRegisterWrite ( + SMUx0B_x8650_ADDRESS, + &F14SmuGmcShutdownTable_2[0], + sizeof (F14SmuGmcShutdownTable_2) / sizeof (UINT32), + TRUE, + StdHeader + ); + + NbSmuServiceRequest (0x0B, TRUE, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcShutdown Exit\n"); +} + +/// GFX shutdown table +UINT32 F14SmuGfxShutdownTable_1[] = { +// SMUx0B_x8600_ADDRESS, + (0x09ull << SMUx0B_x8600_TransactionCount_OFFSET) | + (0x8650ull << SMUx0B_x8600_MemAddr_7_0__OFFSET) | + (0x00ull << SMUx0B_x8600_Txn1MBusAddr_7_0__OFFSET), +// SMUx0B_x8604_ADDRESS, + (0xFEull << SMUx0B_x8604_Txn1MBusAddr_31_24__OFFSET) | + (0x70ull << SMUx0B_x8604_Txn1MBusAddr_23_16__OFFSET) | + (0x00ull << SMUx0B_x8604_Txn1MBusAddr_15_8__OFFSET) | + (0x14ull << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET), +// SMUx0B_x8608_ADDRESS, + (0x03ull << SMUx0B_x8608_Txn1Tsize_OFFSET) | + (0x00ull << SMUx0B_x8608_Txn1TransferLength_13_8__OFFSET) | + (0x00ull << SMUx0B_x8608_Txn1Spare_OFFSET) | + (0x01ull << SMUx0B_x8608_Txn1Overlap_OFFSET) | + (0x00ull << SMUx0B_x8608_Txn1Static_OFFSET) | + (0x01ull << SMUx0B_x8608_Txn1Mode_OFFSET) | + (0x00ull << SMUx0B_x8608_Txn2Mbusaddr158_OFFSET) | + (0x07ull << SMUx0B_x8608_Txn2Mbusaddr70_OFFSET), +// SMUx0B_x860C_ADDRESS, + (0xFEull << SMUx0B_x860C_Txn2MBusAddr3124_OFFSET) | + (0x70ull << SMUx0B_x860C_Txn2MBusAddr2316_OFFSET) | + (0x04ull << SMUx0B_x860C_Txn2TransferLength70_OFFSET) | + (0x03ull << SMUx0B_x860C_Txn2Tsize_OFFSET) | + (0x00ull << SMUx0B_x860C_Txn2TransferLength138_OFFSET), +// SMUx0B_x8610_ADDRESS, + (0x00ull << SMUx0B_x8610_Txn2Spare_OFFSET) | + (0x01ull << SMUx0B_x8610_Txn2Overlap_OFFSET) | + (0x00ull << SMUx0B_x8610_Txn2Static_OFFSET) | + (0x01ull << SMUx0B_x8610_Txn2Mode_OFFSET) | + (0x70ull << SMUx0B_x8610_Txn3MBusAddr2316_OFFSET) | + (0x00ull << SMUx0B_x8610_Txn3MBusAddr158_OFFSET) | + (0x06ull << SMUx0B_x8610_Txn3MBusAddr70_OFFSET), +// SMUx0B_x8614_ADDRESS, + (0xFEull << SMUx0B_x8614_Txn3MBusAddr3124_OFFSET) | + (0x04ull << SMUx0B_x8614_Txn3TransferLength70_OFFSET) | + (0x03ull << SMUx0B_x8614_Txn3Tsize_OFFSET) | + (0x00ull << SMUx0B_x8614_Txn3TransferLength138_OFFSET) | + (0x00ull << SMUx0B_x8614_Txn3Spare_OFFSET) | + (0x00ull << SMUx0B_x8614_Txn3Overlap_OFFSET) | + (0x00ull << SMUx0B_x8614_Txn3Static_OFFSET) | + (0x01ull << SMUx0B_x8614_Txn3Mode_OFFSET), +// SMUx0B_x8618_ADDRESS, + (0xFEull << SMUx0B_x8618_Txn4MBusAddr3124_OFFSET) | + (0xA0ull << SMUx0B_x8618_Txn4MBusAddr2316_OFFSET) | + (0x00ull << SMUx0B_x8618_Txn4MBusAddr158_OFFSET) | + (0x00ull << SMUx0B_x8618_Txn4MBusAddr70_OFFSET), +// SMUx0B_x861C_ADDRESS, + (0x07ull << SMUx0B_x861C_Txn5Mbusaddr70_OFFSET) | + (0x14ull << SMUx0B_x861C_Txn4TransferLength70_OFFSET) | + (0x03ull << SMUx0B_x861C_Txn4Tsize_OFFSET) | + (0x00ull << SMUx0B_x861C_Txn4TransferLength138_OFFSET) | + (0x00ull << SMUx0B_x861C_Txn4Spare_OFFSET) | + (0x01ull << SMUx0B_x861C_Txn4Overlap_OFFSET) | + (0x00ull << SMUx0B_x861C_Txn4Static_OFFSET) | + (0x01ull << SMUx0B_x861C_Txn4Mode_OFFSET), +// SMUx0B_x8620_ADDRESS, + (0x00ull << SMUx0B_x8620_Txn5MBusAddr158_OFFSET) | + (0xA0ull << SMUx0B_x8620_Txn5MBusAddr2316_OFFSET) | + (0xFEull << SMUx0B_x8620_Txn5MBusAddr3124_OFFSET) | + (0x04ull << SMUx0B_x8620_Txn5TransferLength70_OFFSET), +// SMUx0B_x8624_ADDRESS, + (0x03ull << SMUx0B_x8624_Txn5Tsize_OFFSET) | + (0x00ull << SMUx0B_x8624_Txn5TransferLength138_OFFSET) | + (0x00ull << SMUx0B_x8624_Txn5Spare_OFFSET) | + (0x01ull << SMUx0B_x8624_Txn5Overlap_OFFSET) | + (0x00ull << SMUx0B_x8624_Txn5Static_OFFSET) | + (0x01ull << SMUx0B_x8624_Txn5Mode_OFFSET) | + (0x00ull << SMUx0B_x8624_Txn6MBusAddr158_OFFSET) | + (0x06ull << SMUx0B_x8624_Txn6MBusAddr70_OFFSET), +// SMUx0B_x8628_ADDRESS, + (0xFEull << SMUx0B_x8628_Txn6MBusAddr3124_OFFSET) | + (0xA0ull << SMUx0B_x8628_Txn6MBusAddr2316_OFFSET) | + (0x04ull << SMUx0B_x8628_Txn6TransferLength70_OFFSET) | + (0x03ull << SMUx0B_x8628_Txn6Tsize_OFFSET) | + (0x00ull << SMUx0B_x8628_Txn6TransferLength138_OFFSET), +// SMUx0B_x862C_ADDRESS, + (0xB0ull << SMUx0B_x862C_Txn7MBusAddr2316_OFFSET) | + (0x00ull << SMUx0B_x862C_Txn7MBusAddr158_OFFSET) | + (0x00ull << SMUx0B_x862C_Txn7MBusAddr70_OFFSET) | + (0x00ull << SMUx0B_x862C_Txn6Spare_OFFSET) | + (0x00ull << SMUx0B_x862C_Txn6Overlap_OFFSET) | + (0x00ull << SMUx0B_x862C_Txn6Static_OFFSET) | + (0x01ull << SMUx0B_x862C_Txn6Mode_OFFSET), +// SMUx0B_x8630_ADDRESS, + (0xFEull << SMUx0B_x8630_Txn7MBusAddr3124_OFFSET) | + (0x14ull << SMUx0B_x8630_Txn7TransferLength70_OFFSET) | + (0x03ull << SMUx0B_x8630_Txn7Tsize_OFFSET) | + (0x00ull << SMUx0B_x8630_Txn7TransferLength138_OFFSET) | + (0x00ull << SMUx0B_x8630_Txn7Spare_OFFSET) | + (0x01ull << SMUx0B_x8630_Txn7Overlap_OFFSET) | + (0x00ull << SMUx0B_x8630_Txn7Static_OFFSET) | + (0x01ull << SMUx0B_x8630_Txn7Mode_OFFSET), +// SMUx0B_x8634_ADDRESS, + (0xFEull << SMUx0B_x8634_Txn8MBusAddr3124_OFFSET) | + (0xB0ull << SMUx0B_x8634_Txn8MBusAddr2316_OFFSET) | + (0x00ull << SMUx0B_x8634_Txn8MBusAddr158_OFFSET) | + (0x07ull << SMUx0B_x8634_Txn8MBusAddr70_OFFSET), +// SMUx0B_x8638_ADDRESS, + (0x06ull << SMUx0B_x8638_Txn9MBusAddr70_OFFSET) | + (0x04ull << SMUx0B_x8638_Txn8TransferLength70_OFFSET) | + (0x03ull << SMUx0B_x8638_Txn8Tsize_OFFSET) | + (0x00ull << SMUx0B_x8638_Txn8TransferLength138_OFFSET) | + (0x00ull << SMUx0B_x8638_Txn8Spare_OFFSET) | + (0x01ull << SMUx0B_x8638_Txn8Overlap_OFFSET) | + (0x00ull << SMUx0B_x8638_Txn8Static_OFFSET) | + (0x01ull << SMUx0B_x8638_Txn8Mode_OFFSET), +// SMUx0B_x863C_ADDRESS, + (0x00ull << SMUx0B_x863C_Txn9MBusAddr158_OFFSET) | + (0xB0ull << SMUx0B_x863C_Txn9MBuAaddr2316_OFFSET) | + (0xFEull << SMUx0B_x863C_Txn9MBusAddr3124_OFFSET) | + (0x04ull << SMUx0B_x863C_Txn9TransferLength70_OFFSET), +// SMUx0B_x8640_ADDRESS, + (0x03ull << SMUx0B_x8640_Txn9Tsize_OFFSET) | + (0x00ull << SMUx0B_x8640_Txn9TransferLength138_OFFSET) | + (0x00ull << SMUx0B_x8640_Txn9Spare_OFFSET) | + (0x00ull << SMUx0B_x8640_Txn9Overlap_OFFSET) | + (0x00ull << SMUx0B_x8640_Txn9Static_OFFSET) | + (0x01ull << SMUx0B_x8640_Txn9Mode_OFFSET) | + (0x00ull << SMUx0B_x8640_Txn10MBusAddr158_OFFSET) | + (0x00ull << SMUx0B_x8640_Txn10MBusAddr70_OFFSET) +}; +UINT32 F14SmuGfxShutdownTable_2[] = { +// SMUx0B_x8650_ADDRESS, + 0x10103210, +// SMUx0B_x8654_ADDRESS, + 0x10101010, +// SMUx0B_x8658_ADDRESS, + 0x20, +// SMUx0B_x865C_ADDRESS, + 0x00320032, +// SMUx0B_x8660_ADDRESS, + 0x00100010, +// SMUx0B_x8664_ADDRESS, + 0x0032000A, +// SMUx0B_x866C_ADDRESS, + 0x00, +// SMUx0B_x8670_ADDRESS, + 0x10103210, +// SMUx0B_x8674_ADDRESS, + 0x10101010, +// SMUx0B_x8678_ADDRESS, + 0x20, +// SMUx0B_x867C_ADDRESS, + 0x00320032, +// SMUx0B_x8680_ADDRESS, + 0x00100010, +// SMUx0B_x8684_ADDRESS, + 0x00320010, +// SMUx0B_x868C_ADDRESS, + 0x00, +// SMUx0B_x8690_ADDRESS, + 0x10103210, +// SMUx0B_x8694_ADDRESS, + 0x10101010, +// SMUx0B_x8698_ADDRESS, + 0x20, +// SMUx0B_x869C_ADDRESS, + 0x00320032, +// SMUx0B_x86A0_ADDRESS, + 0x00100010, +// SMUx0B_x86A4_ADDRESS, + 0x00320016, +// SMUx0B_x86AC_ADDRESS, + 0x00 +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Shutdown GFX + * + * + * + * @param[in] StdHeader Standard Configuration Header + */ + + + +VOID +STATIC +F14NbSmuGfxShutdown ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGfxShutdown Enter\n"); + NbSmuRcuRegisterWrite ( + SMUx0B_x8600_ADDRESS, + &F14SmuGfxShutdownTable_1[0], + sizeof (F14SmuGfxShutdownTable_1) / sizeof (UINT32), + TRUE, + StdHeader + ); + + NbSmuRcuRegisterWrite ( + SMUx0B_x8650_ADDRESS, + &F14SmuGfxShutdownTable_2[0], + sizeof (F14SmuGfxShutdownTable_2) / sizeof (UINT32), + TRUE, + StdHeader + ); + + NbSmuServiceRequest (0x0B, TRUE, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGfxShutdown Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Power gate unused blocks + * + * + * + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +F14NbPowerGateFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + NB_POWERGATE_CONFIG NbPowerGate; + FCRxFF30_0398_STRUCT FCRxFF30_0398; + IDS_HDT_CONSOLE (GNB_TRACE, "NbPowerGateFeature Enter\n"); + + NbPowerGate.Services.GmcPowerGate = 0x1; + NbPowerGate.Services.UvdPowerGate = 0x1; + NbPowerGate.Services.GfxPowerGate = 0x1; + LibAmdMemCopy (&NbPowerGate.Gmc, &F14NbGmcPowerGatingData, sizeof (POWER_GATE_DATA), StdHeader); + LibAmdMemCopy (&NbPowerGate.Uvd, &F14NbUvdPowerGatingData, sizeof (POWER_GATE_DATA), StdHeader); + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG, &NbPowerGate, StdHeader); + F14NbSmuGmcPowerGatingInit (StdHeader, &NbPowerGate.Gmc); + F14NbSmuUvdPowerGatingInit (StdHeader, &NbPowerGate.Uvd); + if (!GfxLibIsControllerPresent (StdHeader)) { + FCRxFF30_0398.Value = (1 << FCRxFF30_0398_SoftResetGrbm_OFFSET) | (1 << FCRxFF30_0398_SoftResetMc_OFFSET) | + (1 << FCRxFF30_0398_SoftResetDc_OFFSET) | (1 << FCRxFF30_0398_SoftResetRlc_OFFSET) | + (1 << FCRxFF30_0398_SoftResetUvd_OFFSET); + NbSmuSrbmRegisterWrite (FCRxFF30_0398_ADDRESS, &FCRxFF30_0398.Value, TRUE, StdHeader); + if (NbPowerGate.Services.GmcPowerGate == 1) { + IDS_HDT_CONSOLE (GNB_TRACE, " Shutdown GMC\n"); + F14NbSmuGmcShutdown (StdHeader); + } + if (NbPowerGate.Services.UvdPowerGate == 1) { + IDS_HDT_CONSOLE (GNB_TRACE, " Shutdown UVD\n"); + F14NbSmuUvdShutdown (StdHeader); + } + if (NbPowerGate.Services.GfxPowerGate == 1) { + IDS_HDT_CONSOLE (GNB_TRACE, " Shutdown GFX\n"); + F14NbSmuGfxShutdown (StdHeader); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "NbPowerGateFeature Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get GMC restore latency + * + * Restore Latency = ((( DAUG_PSO_PWRUP + MOTH_PSO_PWRUP + PSO_RESTORE_TIMER + SAVE_RESTORE_WIDTH + PSO_CONTROL_PERIOD_7to4 + + * ISO_TIMER + 10) * PSO_CONTROL_VALID_NUM) + RESET_TIMER ) * 10ns + * + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +UINT32 +F14NbPowerGateGmcRestoreLatency ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RestoreLatency; + //may need dynamic calculation + RestoreLatency = ((POWER_GATE_GMC_DAUG_PSO_PWRUP + POWER_GATE_GMC_MOTH_PSO_PWRUP + + POWER_GATE_GMC_SAVE_RESTORE_WIDTH + POWER_GATE_GMC_RSO_RESTORE_TIMER + + POWER_GATE_GMCPSO_CONTROL_PERIOD_7to4 + POWER_GATE_GMC_ISO_TIMER + 10) * + POWER_GATE_GMC_PSO_CONTROL_VALID_NUM + POWER_GATE_GMC_RESET_TIMER) * 10; + return RestoreLatency; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.h new file mode 100644 index 0000000000..90c54db9df --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.h @@ -0,0 +1,61 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB Power gate Gfx/Uvd/Gmc + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _F14NBPOWERGATE_H_ +#define _F14NBPOWERGATE_H_ + +AGESA_STATUS +F14NbPowerGateFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +UINT32 +F14NbPowerGateGmcRestoreLatency ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c new file mode 100644 index 0000000000..efd1660e60 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c @@ -0,0 +1,677 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Graphics Controller family specific service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 41363 $ @e \$Date: 2010-11-04 03:24:17 +0800 (Thu, 04 Nov 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbFuseTable.h" +#include "GnbPcie.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1) +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "OptionGnb.h" +#include "NbLclkDpm.h" +#include "NbFamilyServices.h" +#include "GfxLib.h" +#include "GnbRegistersON.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_NB_FAMILY_0X14_F14NBSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +FUSE_TABLE FuseTable; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * UnitID Clumping + * + * + * @param[in] NbPciAddress + * @param[in] StdHeader + * @retval AGESA_STATUS + */ + +VOID +NbFmClumpUnitID ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Fuse translation table + * + * + * @retval pointer to fuse translation table + */ + +FUSE_TABLE* +NbFmGetFuseTranslationTable ( + ) +{ + return &FuseTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Family specific fuse table patch + * Is's correct behavior if we would have 4 states, it would be + * PP_FUSE_ARRAY->LclkDpmDid[0] - Goes to State 5 + * PP_FUSE_ARRAY->LclkDpmDid[1] - Goes to State 6 + * PP_FUSE_ARRAY->LclkDpmDid[2] - Goes to State 7 + * If we would have 4 states it would be + * PP_FUSE_ARRAY->LclkDpmDid[0] - Goes to State 4 + * PP_FUSE_ARRAY->LclkDpmDid[1] - Goes to State 5 + * PP_FUSE_ARRAY->LclkDpmDid[2] - Goes to State 6 + * PP_FUSE_ARRAY->LclkDpmDid[3] - Goes to State 7 + * + * @param[in] PpFuseArray Pointer to PP_FUSE_ARRAY + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + */ +VOID +NbFmFuseAdjustFuseTablePatch ( + IN OUT PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 LclkDpmMode; + UINT8 SwSatateIndex; + UINT8 MaxSclkIndex; + UINT8 DpmStateIndex; + UINT8 CurrentSclkDpmDid; + CPU_LOGICAL_ID LogicalId; + + LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled; + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + if ((LogicalId.Revision & (AMD_F14_ON_A0 | AMD_F14_ON_A1)) != 0) { + LclkDpmMode = LclkDpmDisabled; + } + IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader); + + //For all CPU rev LclkDpmValid[3] = 0 + PpFuseArray->LclkDpmValid[3] = 0; + PpFuseArray->LclkDpmVid[3] = 0; + PpFuseArray->LclkDpmDid[3] = 0; + + // For LCLKDPM set LclkDpmVid[0] = 0, no matter if LCLK DMP enable or disable. + PpFuseArray->LclkDpmVid[0] = 0; + + if (LclkDpmMode != LclkDpmRcActivity) { + //If LCLK DPM disable (LclkDpmMode != LclkDpmRcActivity) + // - LclkDpmDid[1,2] = LclkDpmDid [0], LclkDpmVid[1,2] = LclkDpmVid[0] + // - Execute LCLK DPM init + + PpFuseArray->LclkDpmVid[1] = PpFuseArray->LclkDpmVid[0]; + PpFuseArray->LclkDpmVid[2] = PpFuseArray->LclkDpmVid[0]; + PpFuseArray->LclkDpmDid[1] = PpFuseArray->LclkDpmDid[0]; + PpFuseArray->LclkDpmDid[2] = PpFuseArray->LclkDpmDid[0]; + IDS_HDT_CONSOLE (NB_MISC, " F14 LCLK DPM Mode Disable -- use DPM0 fusing\n"); + + } else { + // If LCLK DPM enabled + // - use fused values for LclkDpmDid[0,1,2] and appropriate voltage + // - Execute LCLK DPM init + PpFuseArray->LclkDpmVid[2] = PpFuseArray->PcieGen2Vid; + if (GfxLibIsControllerPresent (StdHeader)) { + //VID index = VID index associated with highest SCLK DPM state in the Powerplay state where Label_Performance=1 // This would ignore the UVD case (where Label_Performance would be 0). + for (SwSatateIndex = 0 ; SwSatateIndex < PP_FUSE_MAX_NUM_SW_STATE; SwSatateIndex++) { + if (PpFuseArray->PolicyLabel[SwSatateIndex] == 1) { + break; + } + } + MaxSclkIndex = 0; + CurrentSclkDpmDid = 0xff; + ASSERT (PpFuseArray->SclkDpmValid[SwSatateIndex] != 0); + for (DpmStateIndex = 0; DpmStateIndex < PP_FUSE_MAX_NUM_DPM_STATE; DpmStateIndex++) { + if ((PpFuseArray->SclkDpmValid[SwSatateIndex] & (1 << DpmStateIndex)) != 0) { + if (PpFuseArray->SclkDpmDid[DpmStateIndex] < CurrentSclkDpmDid) { + CurrentSclkDpmDid = PpFuseArray->SclkDpmDid[DpmStateIndex]; + MaxSclkIndex = DpmStateIndex; + } + } + } + PpFuseArray->LclkDpmVid[1] = PpFuseArray->SclkDpmVid[MaxSclkIndex]; + } else { + PpFuseArray->LclkDpmVid[1] = PpFuseArray->LclkDpmVid[0]; + PpFuseArray->LclkDpmDid[1] = PpFuseArray->LclkDpmDid[0]; + } + // - use fused values for LclkDpmDid[0,1,2] and appropriate voltage + //Keep using actual fusing + IDS_HDT_CONSOLE (NB_MISC, " LCLK DPM use actaul fusing.\n"); + } + +} + + +/*---------------------------------------------------------------------------------------- + * FUSE translation table + *---------------------------------------------------------------------------------------- + */ + +FUSE_REGISTER_ENTRY FCRxFE00_600E_TABLE [] = { + { + FCRxFE00_600E_MainPllOpFreqIdStartup_OFFSET, + FCRxFE00_600E_MainPllOpFreqIdStartup_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, MainPllId) + }, + { + FCRxFE00_600E_WrCkDid_OFFSET, + FCRxFE00_600E_WrCkDid_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, WrCkDid) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70A2_TABLE [] = { + { + FCRxFE00_70A2_PPlayTableRev_OFFSET, + FCRxFE00_70A2_PPlayTableRev_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PPlayTableRev) + }, + { + FCRxFE00_70A2_SclkThermDid_OFFSET, + FCRxFE00_70A2_SclkThermDid_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkThermDid) + }, + { + FCRxFE00_70A2_PcieGen2Vid_OFFSET, + FCRxFE00_70A2_PcieGen2Vid_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PcieGen2Vid) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70A4_TABLE [] = { + { + FCRxFE00_70A4_SclkDpmVid0_OFFSET, + FCRxFE00_70A4_SclkDpmVid0_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[0]) + }, + { + FCRxFE00_70A4_SclkDpmVid1_OFFSET, + FCRxFE00_70A4_SclkDpmVid1_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[1]) + }, + { + FCRxFE00_70A4_SclkDpmVid2_OFFSET, + FCRxFE00_70A4_SclkDpmVid2_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[2]) + }, + { + FCRxFE00_70A4_SclkDpmVid3_OFFSET, + FCRxFE00_70A4_SclkDpmVid3_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[3]) + }, + { + FCRxFE00_70A4_SclkDpmVid4_OFFSET, + FCRxFE00_70A4_SclkDpmVid4_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[4]) + }, +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70A5_TABLE [] = { + { + FCRxFE00_70A5_SclkDpmDid0_OFFSET, + FCRxFE00_70A5_SclkDpmDid0_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[0]) + }, + { + FCRxFE00_70A5_SclkDpmDid1_OFFSET, + FCRxFE00_70A5_SclkDpmDid1_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[1]) + }, + { + FCRxFE00_70A5_SclkDpmDid2_OFFSET, + FCRxFE00_70A5_SclkDpmDid2_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[2]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70A8_TABLE [] = { + { + FCRxFE00_70A8_SclkDpmDid3_OFFSET, + FCRxFE00_70A8_SclkDpmDid3_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[3]) + }, + { + FCRxFE00_70A8_SclkDpmDid4_OFFSET, + FCRxFE00_70A8_SclkDpmDid4_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[4]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70AA_TABLE [] = { + { + FCRxFE00_70AA_SclkDpmCacBase_OFFSET, + FCRxFE00_70AA_SclkDpmCacBase_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmCac[4]) + } +}; + + +FUSE_REGISTER_ENTRY FCRxFE00_70AE_TABLE [] = { + { + FCRxFE00_70AE_DispClkDid0_OFFSET, + FCRxFE00_70AE_DispClkDid0_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[0]) + }, + { + FCRxFE00_70AE_DispClkDid1_OFFSET, + FCRxFE00_70AE_DispClkDid1_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[1]) + }, + { + FCRxFE00_70AE_DispClkDid2_OFFSET, + FCRxFE00_70AE_DispClkDid2_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[2]) + }, + { + FCRxFE00_70AE_DispClkDid3_OFFSET, + FCRxFE00_70AE_DispClkDid3_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[3]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70B1_TABLE [] = { + { + FCRxFE00_70B1_LclkDpmDid0_OFFSET, + FCRxFE00_70B1_LclkDpmDid0_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[0]) + }, + { + FCRxFE00_70B1_LclkDpmDid1_OFFSET, + FCRxFE00_70B1_LclkDpmDid1_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[1]) + }, + { + FCRxFE00_70B1_LclkDpmDid2_OFFSET, + FCRxFE00_70B1_LclkDpmDid2_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[2]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70B4_TABLE [] = { + { + FCRxFE00_70B4_LclkDpmDid3_OFFSET, + FCRxFE00_70B4_LclkDpmDid3_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[3]) + }, + { + FCRxFE00_70B4_LclkDpmValid0_OFFSET, + FCRxFE00_70B4_LclkDpmValid0_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[0]) + }, + { + FCRxFE00_70B4_LclkDpmValid1_OFFSET, + FCRxFE00_70B4_LclkDpmValid1_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[1]) + }, + { + FCRxFE00_70B4_LclkDpmValid2_OFFSET, + FCRxFE00_70B4_LclkDpmValid2_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[2]) + }, + { + FCRxFE00_70B4_LclkDpmValid3_OFFSET, + FCRxFE00_70B4_LclkDpmValid3_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[3]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70B5_TABLE [] = { + { + FCRxFE00_70B5_DclkDid0_OFFSET, + FCRxFE00_70B5_DclkDid0_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[0]) + }, + { + FCRxFE00_70B5_DclkDid1_OFFSET, + FCRxFE00_70B5_DclkDid1_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[1]) + }, + { + FCRxFE00_70B5_DclkDid2_OFFSET, + FCRxFE00_70B5_DclkDid2_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[2]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70B8_TABLE [] = { + { + FCRxFE00_70B8_DclkDid3_OFFSET, + FCRxFE00_70B8_DclkDid3_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[3]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70B9_TABLE [] = { + { + FCRxFE00_70B9_VclkDid0_OFFSET, + FCRxFE00_70B9_VclkDid0_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[0]) + }, + { + FCRxFE00_70B9_VclkDid1_OFFSET, + FCRxFE00_70B9_VclkDid1_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[1]) + }, + { + FCRxFE00_70B9_VclkDid2_OFFSET, + FCRxFE00_70B9_VclkDid2_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[2]) + }, + { + FCRxFE00_70B9_VclkDid3_OFFSET, + FCRxFE00_70B9_VclkDid3_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[3]) + } +}; + + +FUSE_REGISTER_ENTRY FCRxFE00_70BC_TABLE [] = { + { + FCRxFE00_70BC_SclkDpmValid0_OFFSET, + FCRxFE00_70BC_SclkDpmValid0_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[0]) + }, + { + FCRxFE00_70BC_SclkDpmValid1_OFFSET, + FCRxFE00_70BC_SclkDpmValid1_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[1]) + }, + { + FCRxFE00_70BC_SclkDpmValid2_OFFSET, + FCRxFE00_70BC_SclkDpmValid2_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[2]) + }, + { + FCRxFE00_70BC_SclkDpmValid3_OFFSET, + FCRxFE00_70BC_SclkDpmValid3_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[3]) + }, + { + FCRxFE00_70BC_SclkDpmValid4_OFFSET, + FCRxFE00_70BC_SclkDpmValid4_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[4]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70BF_TABLE [] = { + { + FCRxFE00_70BF_SclkDpmValid5_OFFSET, + FCRxFE00_70BF_SclkDpmValid5_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[5]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70C0_TABLE [] = { + { + FCRxFE00_70C0_PolicyLabel0_OFFSET, + FCRxFE00_70C0_PolicyLabel0_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[0]) + }, + { + FCRxFE00_70C0_PolicyLabel1_OFFSET, + FCRxFE00_70C0_PolicyLabel1_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[1]) + }, + { + FCRxFE00_70C0_PolicyLabel2_OFFSET, + FCRxFE00_70C0_PolicyLabel2_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[2]) + }, + { + FCRxFE00_70C0_PolicyLabel3_OFFSET, + FCRxFE00_70C0_PolicyLabel3_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[3]) + }, + { + FCRxFE00_70C0_PolicyLabel4_OFFSET, + FCRxFE00_70C0_PolicyLabel4_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[4]) + }, + { + FCRxFE00_70C0_PolicyLabel5_OFFSET, + FCRxFE00_70C0_PolicyLabel5_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[5]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70C1_TABLE [] = { + { + FCRxFE00_70C1_PolicyFlags0_OFFSET, + FCRxFE00_70C1_PolicyFlags0_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[0]) + }, + { + FCRxFE00_70C1_PolicyFlags1_OFFSET, + FCRxFE00_70C1_PolicyFlags1_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[1]) + }, + { + FCRxFE00_70C1_PolicyFlags2_OFFSET, + FCRxFE00_70C1_PolicyFlags2_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[2]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70C4_TABLE [] = { + { + FCRxFE00_70C4_PolicyFlags3_OFFSET, + FCRxFE00_70C4_PolicyFlags3_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[3]) + }, + { + FCRxFE00_70C4_PolicyFlags4_OFFSET, + FCRxFE00_70C4_PolicyFlags4_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[4]) + }, + { + FCRxFE00_70C4_PolicyFlags5_OFFSET, + FCRxFE00_70C4_PolicyFlags5_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[5]) + } +}; + + +FUSE_REGISTER_ENTRY FCRxFE00_70C7_TABLE [] = { + { + FCRxFE00_70C7_DclkVclkSel0_OFFSET, + FCRxFE00_70C7_DclkVclkSel0_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[0]) + }, + { + FCRxFE00_70C7_DclkVclkSel1_OFFSET, + FCRxFE00_70C7_DclkVclkSel1_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[1]) + }, + { + FCRxFE00_70C7_DclkVclkSel2_OFFSET, + FCRxFE00_70C7_DclkVclkSel2_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[2]) + }, + { + FCRxFE00_70C7_DclkVclkSel3_OFFSET, + FCRxFE00_70C7_DclkVclkSel3_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[3]) + }, + + { + FCRxFE00_70C7_DclkVclkSel4_OFFSET, + FCRxFE00_70C7_DclkVclkSel4_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[4]) + }, + { + FCRxFE00_70C7_DclkVclkSel5_OFFSET, + FCRxFE00_70C7_DclkVclkSel5_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[5]) + }, +}; + + + + +FUSE_TABLE_ENTRY FuseRegisterTable [] = { + { + FCRxFE00_70A2_ADDRESS, + sizeof (FCRxFE00_70A2_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70A2_TABLE + }, + { + FCRxFE00_70A4_ADDRESS, + sizeof (FCRxFE00_70A4_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70A4_TABLE + }, + { + FCRxFE00_70A5_ADDRESS, + sizeof (FCRxFE00_70A5_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70A5_TABLE + }, + { + FCRxFE00_70A8_ADDRESS, + sizeof (FCRxFE00_70A8_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70A8_TABLE + }, + { + FCRxFE00_600E_ADDRESS, + sizeof (FCRxFE00_600E_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_600E_TABLE + }, + { + FCRxFE00_70AA_ADDRESS, + sizeof (FCRxFE00_70AA_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70AA_TABLE + }, + { + FCRxFE00_70AE_ADDRESS, + sizeof (FCRxFE00_70AE_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70AE_TABLE + }, + { + FCRxFE00_70B1_ADDRESS, + sizeof (FCRxFE00_70B1_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70B1_TABLE + }, + { + FCRxFE00_70B4_ADDRESS, + sizeof (FCRxFE00_70B4_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70B4_TABLE + }, + { + FCRxFE00_70B5_ADDRESS, + sizeof (FCRxFE00_70B5_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70B5_TABLE + }, + { + FCRxFE00_70B8_ADDRESS, + sizeof (FCRxFE00_70B8_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70B8_TABLE + }, + { + FCRxFE00_70B9_ADDRESS, + sizeof (FCRxFE00_70B9_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70B9_TABLE + }, + { + FCRxFE00_70BC_ADDRESS, + sizeof (FCRxFE00_70BC_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70BC_TABLE + }, + { + FCRxFE00_70BF_ADDRESS, + sizeof (FCRxFE00_70BF_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70BF_TABLE + }, + { + FCRxFE00_70C0_ADDRESS, + sizeof (FCRxFE00_70C0_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70C0_TABLE + }, + { + FCRxFE00_70C1_ADDRESS, + sizeof (FCRxFE00_70C1_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70C1_TABLE + }, + { + FCRxFE00_70C4_ADDRESS, + sizeof (FCRxFE00_70C4_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70C4_TABLE + }, + { + FCRxFE00_70C7_ADDRESS, + sizeof (FCRxFE00_70C7_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70C7_TABLE + }, + +}; + +FUSE_TABLE FuseTable = { + sizeof (FuseRegisterTable) / sizeof (FUSE_TABLE_ENTRY), + FuseRegisterTable +}; diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbSmu.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbSmu.c new file mode 100644 index 0000000000..014e1a3ba0 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbSmu.c @@ -0,0 +1,98 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * SMU initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "NbSmuLib.h" +#include "F14NbSmuFirmware.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_NB_FAMILY_0X14_F14NBSMU_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU Initialize + * + * + * + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +F14NbSmuInitFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + SMU_FIRMWARE_REV Revision; + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuInitFeature Enter\n"); + Revision = NbSmuFirmwareRevision (StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Current SMU firmware rev %d.%x\n", Revision.MajorRev, Revision.MinorRev); + IDS_HDT_CONSOLE (NB_MISC, " New SMU firmware rev %d.%x\n", Fm.Revision.MajorRev, Fm.Revision.MinorRev); + if ((Revision.MajorRev < Fm.Revision.MajorRev) || (Revision.MajorRev == Fm.Revision.MajorRev && Revision.MinorRev < Fm.Revision.MinorRev)) { + IDS_HDT_CONSOLE (NB_MISC, " Updating SMU firmware\n"); + NbSmuFirmwareDownload (&Fm, StdHeader); + } + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuInitFeature Exit\n"); + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h new file mode 100644 index 0000000000..80e6830799 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h @@ -0,0 +1,981 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * SMU firmware. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 37675 $ @e \$Date: 2010-09-09 22:33:48 +0800 (Thu, 09 Sep 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +#ifndef _F14NBSMUFIRMWARE_H_ +#define _F14NBSMUFIRMWARE_H_ + +UINT32 DataBlock0[] = { + 0x00020100, + 0xbdff018e, + 0x00ce3d9d, + 0x00ce1810, + 0xa6082000, + 0x00a71800, + 0x8c081808, + 0xf3251000, + 0x270000cc, + 0xda9dce0b, + 0x8308006f, + 0xf8260100, + 0x9dbd248d, + 0x90fb2040, + 0xde20900a, + 0x02de3c00, + 0x3c04de3c, + 0x9f3c06de, + 0x06df3806, + 0x3804df38, + 0xdf3802df, + 0x06de3b00, + 0xce069f3c, + 0x90fc0c83, + 0xfc02ed02, + 0x00ed0090, + 0x1caa7fce, + 0x82ce0300, + 0x3191ccda, + 0x82ce00ed, + 0x5d91cce2, + 0x82ce00ed, + 0x5b94cce4, + 0x82ce00ed, + 0x699bcce6, + 0x82ce00ed, + 0x2891cce8, + 0x82ce00ed, + 0xce00edea, + 0x00edec82, + 0xedee82ce, + 0xf082ce00, + 0x82ce00ed, + 0xce00edf2, + 0x93ccf482, + 0xce00ed9d, + 0x9accf682, + 0xce00ed3c, + 0x91ccf882, + 0xce00edb5, + 0x91ccfa82, + 0xbd00edf8, + 0x82ce349b, + 0x6698cc9a, + 0xce0e00ed, + 0x01c6ed84, + 0x02c600e7, + 0x9dcc00e7, + 0x659dfd44, + 0xcfa09dfd, + 0x00defd20, + 0x3c02de3c, + 0xde3c04de, + 0x069f3c06, + 0x3806df38, + 0xdf3804df, + 0x00df3802, + 0x3c00de3b, + 0xde3c02de, + 0x06de3c04, + 0x38069f3c, + 0xdf3806df, + 0x02df3804, + 0x3b00df38, + 0x9f3c06de, + 0x06df3806, + 0x3c06de39, + 0x7ece069f, + 0xe7dfc601, + 0x647ece00, + 0xed02ffcc, + 0x627ece00, + 0xed0086cc, + 0x017ece00, + 0x20c400e6, + 0x95bdf727, + 0x06df3801, + 0x3c06de39, + 0x85ce069f, + 0xce00e607, + 0x8c4f0000, + 0x06260000, + 0x0100831a, + 0x008c2d27, + 0x2b362e00, + 0x00831a34, + 0x8c0b2201, + 0x29260000, + 0x0f2700dd, + 0x008c2320, + 0x1a1e2600, + 0x27020083, + 0xcc162012, + 0x95bd0885, + 0xcc0e2029, + 0x95bd3085, + 0xcc062029, + 0x95bd5885, + 0x06df3829, + 0x3c06de39, + 0x08de069f, + 0x3c0ade3c, + 0x1daa7fce, + 0x7fce0100, + 0x10001c8f, + 0x6b8d1bc6, + 0x36377f84, + 0x92bd1bc6, + 0x8d04c6f7, + 0x8f7fce5e, + 0xce10001d, + 0x001daa7f, + 0x01001c01, + 0xdf383131, + 0x08df380a, + 0x3906df38, + 0x9f3c06de, + 0x3c08de06, + 0xce3c0ade, + 0x001daa7f, + 0x8f7fce01, + 0xc610001c, + 0x8a288d1b, + 0xc6363780, + 0xf792bd1b, + 0x1b8d04c6, + 0x1d8f7fce, + 0x7fce1000, + 0x01001daa, + 0x3101001c, + 0x0adf3831, + 0x3808df38, + 0xde3906df, + 0x069f3c06, + 0xde3c08de, + 0x0cde3c0a, + 0x3c0ede3c, + 0x00cc0dd7, + 0x4f36374d, + 0xcc36375f, + 0x02ce6000, + 0x3697bd00, + 0xce6400cc, + 0x97bd0002, + 0xcc08df14, + 0x3637cd00, + 0x36375f4f, + 0xce6000cc, + 0x97bd0002, + 0xd68f1836, + 0x188f180d, + 0x007f0edf, + 0xdd0edc0e, + 0x0f007f0c, + 0x180e007f, + 0x18381838, + 0xdc381838, + 0x26018508, + 0x8f0cde08, + 0xdf8f018a, + 0x370edc0c, + 0x370cdc36, + 0x6400cc36, + 0xbd0002ce, + 0x00cc3697, + 0x4f36374e, + 0xcc36375f, + 0x02ce6000, + 0x3697bd00, + 0xce6400cc, + 0x97bd0002, + 0x18381814, + 0x18381838, + 0x18381838, + 0x38180edf, + 0x180cdf18, + 0x0adf1838, + 0xdf183818, + 0x18381808, + 0xde3906df, + 0x069f3c06, + 0xde3c08de, + 0x0cde3c0a, + 0x3c0ede3c, + 0x00cc0dd7, + 0x4f36374d, + 0xcc36375f, + 0x02ce6000, + 0x3697bd00, + 0xce6400cc, + 0x97bd0002, + 0xcc08df14, + 0x3637cd00, + 0x36375f4f, + 0xce6000cc, + 0x97bd0002, + 0xd68f1836, + 0x188f180d, + 0x007f0edf, + 0x0d007f0e, + 0x4f0c007f, + 0x0002ce5f, + 0xda0e9a8f, + 0x0edd8f0f, + 0x06de0cdf, + 0x0e9a05ec, + 0x0cde0fda, + 0x38180edd, + 0x38183818, + 0x08dc3818, + 0x06260185, + 0x8f018a8f, + 0x0edc0cdf, + 0x0cdc3637, + 0x00cc3637, + 0x0002ce64, + 0x383697bd, + 0x0edf3838, + 0x380cdf38, + 0xdf380adf, + 0x06df3808, + 0x3c06de39, + 0x08de069f, + 0x3c0ade3c, + 0xde3c0cde, + 0x85ce3c0e, + 0xdd02ec90, + 0xdd00ec0e, + 0x5f0edc0c, + 0x04caf084, + 0x0edd0e8a, + 0x1daa7fce, + 0x0cde0100, + 0xdd7196bd, + 0xce08df0a, + 0x00e69785, + 0x0adc0626, + 0x0420118a, + 0xef840adc, + 0x36370add, + 0x363708dc, + 0x0cde0edc, + 0xcebc96bd, + 0x001caa7f, + 0x38383801, + 0xdf380edf, + 0x0adf380c, + 0x3808df38, + 0xde3906df, + 0x069f3c06, + 0x80ce8f18, + 0x2600e6ff, + 0xe704c60c, + 0x207ece00, + 0x2001001c, + 0x04001c03, + 0xc6007ece, + 0xce00e7ef, + 0x00ec217e, + 0xd300df18, + 0x277ece00, + 0x7ece00ed, + 0xc400e600, + 0xcef72710, + 0x001dff80, + 0x2600e604, + 0x207ece06, + 0x3801001d, + 0xde3906df, + 0x069f3c06, + 0xe68385ce, + 0x2701c400, + 0xb885ce74, + 0x02ed5f4f, + 0x85ce00ed, + 0xed02edbc, + 0xc085ce00, + 0x00ed02ed, + 0xedc485ce, + 0xce00ed02, + 0x02edc885, + 0x85ce00ed, + 0xed02edcc, + 0x8285ce00, + 0x08c400e6, + 0x97bd0326, + 0xff80ceaa, + 0xce08001c, + 0x00e68285, + 0x7ecef0c4, + 0xe701ca20, + 0x217ece00, + 0xce00ee1a, + 0x00ec8085, + 0x8f1800dd, + 0x8f1800d3, + 0x1a297ece, + 0x7ece00ef, + 0xe7dfc600, + 0x027ece00, + 0x2020001c, + 0xff80ce20, + 0xe608001d, + 0xce062600, + 0x001d207e, + 0x007ece01, + 0x00e7dfc6, + 0x1d027ece, + 0x99bd2000, + 0x06df38c1, + 0x3c08de39, + 0xb65086ce, + 0x19270086, + 0x00a60897, + 0xa703a616, + 0xec03e700, + 0xe702a701, + 0x3a04c601, + 0x2e08007a, + 0x08df38e9, + 0x3c08de39, + 0xde3c0ade, + 0x08dd3c0c, + 0x86607ece, + 0xcc0ba701, + 0x0cedc015, + 0xedc115cc, + 0x0080cc0e, + 0xc6cc0add, + 0xdc0cdd54, + 0x868f1808, + 0xdc089709, + 0xdc00ed0a, + 0xa602ed0c, + 0x27018407, + 0x00ec18fa, + 0xec1800ed, + 0xa602ed02, + 0x27018407, + 0x8a0adcfa, + 0xdc00ed01, + 0xcb02ed0c, + 0xa60cdd04, + 0x27018407, + 0x00ec18fa, + 0xec1800ed, + 0xc602ed02, + 0xa63a1804, + 0x27018407, + 0x08007afa, + 0x0adcb52e, + 0x0cdc00ed, + 0x07a602ed, + 0xfa270184, + 0xed00ec18, + 0x02ec1800, + 0x07a602ed, + 0xfa270184, + 0x380ba74f, + 0xdf380cdf, + 0x08df380a, + 0x06de1839, + 0x069f3c18, + 0x807fce18, + 0x3701a718, + 0x02caf8c4, + 0x8f00e718, + 0xfc8a0384, + 0x1803a718, + 0xfd8602e7, + 0x8604a718, + 0x07c43301, + 0x5a480427, + 0xa718fc2e, + 0x0002cc05, + 0x1806a718, + 0x06de07e7, + 0x181606a6, + 0xed1808ed, + 0xb703860a, + 0x7fb68c7f, + 0x2680848c, + 0x06df38f9, + 0x7fce1839, + 0x01a71880, + 0xf8c43737, + 0xe71804ca, + 0x03848f00, + 0xa718fc8a, + 0x02e71803, + 0xa718fd86, + 0x33018604, + 0x042707c4, + 0xfc2e5a48, + 0xcc05a718, + 0xa7180002, + 0x07e71806, + 0x7fb70186, + 0x8c7fb68c, + 0xf9268084, + 0x1803c433, + 0x00e6183a, + 0x7fce1839, + 0x01a71880, + 0xcaf8c437, + 0x00e71804, + 0x03a7188f, + 0x4f02e718, + 0x3304a718, + 0x042704c4, + 0x0220f086, + 0xa7180f86, + 0x0002cc05, + 0x1806a718, + 0x018607e7, + 0xb68c7fb7, + 0x80848c7f, + 0xa618f926, + 0x02e61803, + 0x01a6188f, + 0x3900e618, + 0x1806de18, + 0x18069f3c, + 0x18807fce, + 0xc43701a7, + 0x00e718f8, + 0x03a7188f, + 0x4f02e718, + 0x3304a718, + 0x042704c4, + 0x0220f086, + 0xa7180f86, + 0x0002cc05, + 0x1806a718, + 0x06de07e7, + 0xe71807ec, + 0x09a71808, + 0xe71805ec, + 0x0ba7180a, + 0x7fb70386, + 0x8c7fb68c, + 0xf9268084, + 0x3906df38, + 0x807fce18, + 0x3701a718, + 0x04caf8c4, + 0x8f00e718, + 0xfc8a0384, + 0x1803a718, + 0xfd8602e7, + 0x7e04a718, + 0xde188b96, + 0x9f3c1806, + 0x7fce1806, + 0x01a71880, + 0xcaf8c437, + 0x00e71802, + 0x8a03848f, + 0x03a718fc, + 0x8602e718, + 0x04a718fd, + 0xeddb967e, + 0x8407a602, + 0x39fa2701, + 0x018407a6, + 0xce39fa27, + 0x046fc010, + 0xed8f184f, + 0xa7078605, + 0x6400cc09, + 0x09a607ed, + 0xfa270184, + 0x0fc48f18, + 0x17274d17, + 0x04e740c6, + 0x07c6056f, + 0x04c609e7, + 0x09e606e7, + 0xfa2701c4, + 0xecef2e4a, + 0xfecc3902, + 0xfc84fd00, + 0xfdf370cc, + 0x00ccfe84, + 0xfa84fd03, + 0x8de0d6bd, + 0xa085f775, + 0x8fa185b7, + 0x86a285b7, + 0xff84b7f6, + 0x8de0d6bd, + 0xa385f761, + 0x8fa685b7, + 0x86a785b7, + 0xff84b7f9, + 0x8de0d6bd, + 0xae85fd4d, + 0xad85b78f, + 0x84b7fc86, + 0xe0d6bdff, + 0x85fd3c8d, + 0x85b78faa, + 0xb7ff86a9, + 0xd6bdff84, + 0xf72b8de0, + 0x85b7a485, + 0x85b78fa5, + 0x0a71cca8, + 0xbdfe84fd, + 0x85cee0d6, + 0x02ee1a00, + 0x185401e6, + 0x1856468f, + 0x8f18548f, + 0x84fd5646, + 0x08de39be, + 0x0085ce3c, + 0x03a600e6, + 0x01e608dd, + 0x007902a6, + 0x79495909, + 0x00790800, + 0x79495909, + 0x00790800, + 0x79495909, + 0x08de0800, + 0xdf183818, + 0x08de3908, + 0x0090cc3c, + 0xcc5884fd, + 0x84fde4c6, + 0xc3e4bd5a, + 0xb60000ce, + 0xc4165f84, + 0x04163a01, + 0x3a01c404, + 0xc4040416, + 0x04163a01, + 0x3a01c404, + 0x04cb508f, + 0xce4f08d7, + 0x9abdb885, + 0x4f08d60a, + 0xbdc085ce, + 0x85f60a9a, + 0x1809d7a6, + 0xbdb885ce, + 0x85f6ee99, + 0x1809d7a7, + 0xbdc085ce, + 0x8086ee99, + 0x85b60897, + 0x27048482, + 0x607ece5b, + 0x08a70386, + 0xed70fecc, + 0x0200cc04, + 0x04a606ed, + 0x018407a6, + 0x03a6fa27, + 0x44440484, + 0xce5f0188, + 0x9abdc885, + 0xa585f60a, + 0xce1809d7, + 0x99bdc885, + 0xcc85ceee, + 0x0000ce18, + 0x142600ec, + 0x102602a6, + 0x85b103a6, + 0x18092ca4, + 0xb6be84fe, + 0x0897a885, + 0xab7fff18, + 0xad7fb74f, + 0xf6ac85ce, + 0xfe18a085, + 0x2026bc85, + 0x26be85b6, + 0xbf85b61b, + 0xa1a385f6, + 0xf6112d03, + 0x02a1a285, + 0x85f60a2d, + 0x2d01a1a1, + 0xa085f603, + 0x85ce09d7, + 0xa085f6a8, + 0xc485fe18, + 0x85b61d26, + 0xb61826c6, + 0x01a1c785, + 0x85f6112e, + 0x2e02a1a1, + 0xa285f60a, + 0x032e03a1, + 0xd1a385f6, + 0xd7022e09, + 0x4f08d609, + 0xd68f1805, + 0xeabd4f09, + 0xcc09d740, + 0x84fd0091, + 0x0cc4cc58, + 0xbd5a84fd, + 0x09d6c3e4, + 0xc65d84f7, + 0x5884f781, + 0xfc92e4bd, + 0x7ef38085, + 0x297efd21, + 0x7eb7df86, + 0x08df3800, + 0x0091cc39, + 0xcc5884fd, + 0x84fd0cc4, + 0xc3e4bd5a, + 0xf7a085f6, + 0x81c65d84, + 0xbd5884f7, + 0x85b692e4, + 0x27048482, + 0xfd4f5f08, + 0x7fb7ab7f, + 0xec1839ad, + 0x02eecd00, + 0x2709007d, + 0x468f040a, + 0x007a8f56, + 0x18f62609, + 0xefcd04ed, + 0x58583906, + 0x02e35858, + 0x00ec02ed, + 0x008900c9, + 0x04ec00ed, + 0x8f184353, + 0x435306ec, + 0x180100c3, + 0x8900c98f, + 0xe38f1800, + 0x1802ed02, + 0xa901e98f, + 0x3900ed00, + 0xde3c06de, + 0x069f3c08, + 0x1daa7fce, + 0x7fce0100, + 0x10001c8f, + 0xced60ccc, + 0x96bd0000, + 0xc608d725, + 0xcc3437c8, + 0x00ced60c, + 0xcd95bd00, + 0xced70ccc, + 0x96bd0000, + 0x3720ca25, + 0xd70ccc34, + 0xbd0000ce, + 0xd8c6cd95, + 0x0ccc3437, + 0x0000ced6, + 0xc6cd95bd, + 0xcc34371f, + 0x00ced70c, + 0xcd95bd00, + 0x3437d9c6, + 0xced60ccc, + 0x95bd0000, + 0xd70ccccd, + 0xbd0000ce, + 0x8f302596, + 0x8f0a00c3, + 0x2620c435, + 0xd6448d02, + 0xcc343708, + 0x00ced60c, + 0xcd95bd00, + 0x00a0cc38, + 0xbd0002ce, + 0x20ca2596, + 0x022722c1, + 0xa0cc258d, + 0x0002ce01, + 0xc12596bd, + 0x8d022710, + 0x8f7fce16, + 0xce10001d, + 0x001daa7f, + 0x01001c01, + 0x3808df38, + 0xce3906df, + 0x0386607e, + 0xffcc08a7, + 0xcc04ed30, + 0x06ede701, + 0x00ed5f4f, + 0x02ed7fc6, + 0x018407a6, + 0x01ccfa27, + 0x5f06ede9, + 0xed00ed4f, + 0x8407a602, + 0x01fa2701, + 0x39fd20cf, + 0xcc607ece, + 0x04ed30ff, + 0xed3d26cc, + 0xfe00cc06, + 0xbd5f00ed, + 0x0fcc5f97, + 0xcc06ede2, + 0x00edfe00, + 0x5f97bd5f, + 0xed5422cc, + 0xfcffcc06, + 0xfccc00ed, + 0x5f97bd00, + 0x3c08de39, + 0xde3c0ade, + 0x0ede3c0c, + 0xb7df863c, + 0x7ece017e, + 0x02ffcc60, + 0x9dcc04ed, + 0xb602ed64, + 0x2084017e, + 0x01ccf927, + 0xcc08dd01, + 0x0add1100, + 0xdd0000cc, + 0x0f00cc0c, + 0x9cbd0edd, + 0x3001cca9, + 0x80cc08dd, + 0xcc0add62, + 0x0cddffff, + 0xddfff7cc, + 0xdb9cbd0e, + 0xdd0200cc, + 0xffffcc0a, + 0xffcc0cdd, + 0xbd0eddfb, + 0x80ccdb9c, + 0xcc0add63, + 0x0cdd0101, + 0xdd0080cc, + 0xa99cbd0e, + 0xdd6280cc, + 0x0000cc0a, + 0x00cc0cdd, + 0xbd0edd01, + 0x80cca99c, + 0xcc0add60, + 0x0cdd0000, + 0xdd0100cc, + 0xa99cbd0e, + 0x0200ce18, + 0x54207ef6, + 0xbd545454, + 0x94bd6f97, + 0x1001cc0b, + 0x00cc08dd, + 0xcc0add10, + 0x0cdd0000, + 0xdd0100cc, + 0xcc7e8d0e, + 0x08dd3001, + 0xdd6080cc, + 0x0301cc0a, + 0x9dbd0cdd, + 0x3001cc0d, + 0x80cc08dd, + 0xcc0add62, + 0x0cddffff, + 0xddfeffcc, + 0xdb9cbd0e, + 0xdd0000cc, + 0x0008cc0c, + 0x498d0edd, + 0xdd6380cc, + 0xfefecc0a, + 0x7fcc0cdd, + 0x8d0eddff, + 0x2001cc6a, + 0x44cc08dd, + 0xcc0add50, + 0x0cdd0203, + 0x860d9dbd, + 0x017eb7df, + 0xcc607ece, + 0x04ed02ff, + 0xed9f9dcc, + 0x017eb602, + 0xf9272084, + 0x380edf38, + 0xdf380cdf, + 0x08df380a, + 0x607ece39, + 0xed30ffcc, + 0x2800cc04, + 0x08dc06ed, + 0x0adc00ed, + 0xcc5f97bd, + 0x06ed2900, + 0x97bd04a6, + 0x9a00ec68, + 0xed0dda0c, + 0x9a02ec00, + 0xbd0fda0e, + 0xce395f97, + 0xffcc607e, + 0xcc04ed30, + 0x06ed2800, + 0x00ed08dc, + 0x97bd0adc, + 0x2900cc5f, + 0x04a606ed, + 0xec6897bd, + 0xd40c9400, + 0xec00ed0d, + 0xd40e9402, + 0x5f97bd0f, + 0x607ece39, + 0x607ece18, + 0x3a180dd6, + 0xed30ffcc, + 0x2800cc04, + 0x08dc06ed, + 0x0adc00ed, + 0xcc5f97bd, + 0x06ed2900, + 0x97bd04a6, + 0x00e61868, + 0xf4260cd4, + 0x39064f39, + 0xfc203e0e, + 0x28202001, + 0x00000000, + 0x20202001, + 0x00000000, + 0x24202001, + 0x00000000, + 0x2c202001, + 0x00000000, + 0x28000008, + 0x04ff3000, + 0x002901c0, + 0xc004ff30, + 0x30002800, + 0x01c004ff, + 0xff300029, + 0x2800c004, + 0x04ff3000, + 0x002901c0, + 0xc004ff30, + 0x30002800, + 0x01c004ff, + 0xff300029, + 0x0800c004, + 0x00280000, + 0xc004ff30, + 0x30002909, + 0x09c004ff, + 0xff300028, + 0x2909c004, + 0x04ff3000, + 0x002809c0, + 0xc004ff30, + 0x30002909, + 0x09c004ff, + 0xff300028, + 0x2909c004, + 0x04ff3000, + 0x000001c0 +}; + +UINT32 DataBlock1[] = { + 0x3b903b90, + 0x3b903b90, + 0x3b903b90, + 0x3b903b90, + 0x3b903b90, + 0x3b903b90, + 0x3b903b90, + 0x3b903b90, + 0x3b903b90, + 0x3b903b90, + 0x3b903b90, + 0x3b903b90, + 0x96d53b90, + 0x3b90aed5, + 0x04900490, + 0x04900490 +}; + +SMU_FIRMWARE_BLOCK FmBlockArray[] = { + { + 0x9000, + 0x377, + &DataBlock0[0] + }, + { + 0xbfc0, + 0x10, + &DataBlock1[0] + } +}; + +SMU_FIRMWARE_HEADER Fm = { + { + 0x1, 0x200 + }, + 2, + &FmBlockArray[0] +}; +#endif + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h new file mode 100644 index 0000000000..9442277453 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h @@ -0,0 +1,108 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific service routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 40044 $ @e \$Date: 2010-10-19 06:43:22 +0800 (Tue, 19 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _NBFAMILYSERVICES_H_ +#define _NBFAMILYSERVICES_H_ + +/// Fuse field entry +typedef struct { + UINT8 FieldOffset; ///< Field offset in fuse register + UINT8 FieldWidth; ///< Width of field + UINT16 FuseOffset; ///< destination offset in translation table +} FUSE_REGISTER_ENTRY; + +/// Fuse register entry +typedef struct { + UINT32 Register; ///< FCR register address + UINT8 FuseRegisterTableLength; ///< Length of field table for this register + FUSE_REGISTER_ENTRY *FuseRegisterTable; ///< Pointer to field table +} FUSE_TABLE_ENTRY; + +/// Fuse translation table +typedef struct { + UINT8 FuseTableLength; ///< Length of translation table + FUSE_TABLE_ENTRY *FuseTable; ///< Pointer to register table +} FUSE_TABLE; + +/// NB power gate configuration +typedef struct { + struct { + UINT32 GmcPowerGate:1; ///< Power Gate GMC + UINT32 GfxPowerGate:1; ///< Power gate GFX + UINT32 UvdPowerGate:1; ///< Power gate UVD + } Services; ///< Power gate services + POWER_GATE_DATA Gmc; ///< Gmc Power gating Data + POWER_GATE_DATA Uvd; ///< Uvd Power gating Data +} NB_POWERGATE_CONFIG; + +VOID +NbFmClumpUnitID ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +FUSE_TABLE* +NbFmGetFuseTranslationTable ( + ); + +VOID +NbFmFuseAdjustFuseTablePatch ( + IN OUT PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +NbFmDpmStateBootupInit ( + IN UINT32 LclkDpmValid, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +NbFmInitLclkDpmRcActivity ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +#endif + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbFuseTable.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbFuseTable.c new file mode 100644 index 0000000000..d3f3e6c496 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbFuseTable.c @@ -0,0 +1,401 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Fuse table initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbFuseTable.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include "GnbRegistersON.h" +#include "NbSmuLib.h" +#include "NbConfigData.h" +#include "NbFuseTable.h" +#include "NbFamilyServices.h" +#include "GfxLib.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +NbFuseLoadDefaultFuseTable ( + OUT PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NbFuseLoadFuseTableFromFcr ( + OUT PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NbFuseDebugDump ( + IN PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NbFuseAdjustFuseTableToCurrentMainPllVco ( + IN OUT PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +PP_FUSE_ARRAY DefaultPpFuseArray = { + 0, ///< PP table revision + {1, 0, 0, 0, 0, 0}, ///< Valid DPM states + {0x40, 0, 0, 0, 0}, ///< Sclk DPM DID + {0, 0, 0, 0, 0}, ///< Sclk DPM VID + {0, 0, 0, 0, 0}, ///< Sclk DPM Cac + {1, 0, 0, 0, 0, 0}, ///< State policy flags + {2, 0, 0, 0, 0, 0}, ///< State policy label + {0x40, 0, 0, 0}, ///< VCLK DID + {0x40, 0, 0, 0}, ///< DCLK DID + 0, ///< Thermal SCLK + {0, 0, 0, 0, 0, 0}, ///< Vclk/Dclk selector + {0, 0, 0, 0}, ///< Valid Lclk DPM states + {0, 0, 0, 0}, ///< Lclk DPM DID + {0, 0, 0, 0}, ///< Lclk DPM VID + {0, 0, 0, 0}, ///< Displclk DID + 3, ///< Pcie Gen 2 VID + 0x10 ///< Main PLL id for 3200 VCO +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Fuse Table Init + * + * + * + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +NbFuseTableFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PP_FUSE_ARRAY *PpFuseArray; + D18F3xA0_STRUCT D18F3xA0; + BOOLEAN LoadDefaultFuses; + IDS_HDT_CONSOLE (GNB_TRACE, "NbFuseTableFeature Enter\n"); + + PpFuseArray = (PP_FUSE_ARRAY *) GnbAllocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, sizeof (PP_FUSE_ARRAY), StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray == NULL) { + IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Allocation\n"); + return AGESA_ERROR; + } + LibAmdMemFill (PpFuseArray, 0x00, sizeof (PP_FUSE_ARRAY), StdHeader); + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xA0_ADDRESS), + AccessWidth32, + &D18F3xA0.Value, + StdHeader + ); + +#ifndef GNB_FORCE_DEFAULT_FUSE + LoadDefaultFuses = FALSE; + if (D18F3xA0.Field.CofVidProg == 1) { + IDS_HDT_CONSOLE (NB_MISC, " Processor Fused\n"); + NbFuseLoadFuseTableFromFcr (PpFuseArray, StdHeader); + if (PpFuseArray->PPlayTableRev == 0) { + IDS_HDT_CONSOLE (NB_MISC, " PowerPlay Table Unfused\n"); + LoadDefaultFuses = TRUE; + } + } else { + IDS_HDT_CONSOLE (NB_MISC, " Processor Unfuse\n"); + LoadDefaultFuses = TRUE; + } +#else + LoadDefaultFuses = TRUE; +#endif + if (LoadDefaultFuses) { + IDS_HDT_CONSOLE (NB_MISC, " Load default fuses\n"); + NbFuseLoadDefaultFuseTable (PpFuseArray, StdHeader); + } + NbFmFuseAdjustFuseTablePatch (PpFuseArray, StdHeader); + NbFuseAdjustFuseTableToCurrentMainPllVco (PpFuseArray, StdHeader); + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PPFUSE_OVERRIDE, PpFuseArray, StdHeader); + GNB_DEBUG_CODE ( + NbFuseDebugDump (PpFuseArray, StdHeader) + ); + IDS_HDT_CONSOLE (GNB_TRACE, "NbFuseTableFeature Exit\n"); + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Load Fuse Table From FCRs + * + * + * @param[out] PpFuseArray Pointer to save fuse table + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +VOID +NbFuseLoadFuseTableFromFcr ( + OUT PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + FUSE_TABLE *FuseTable; + UINTN RegisterIndex; + FuseTable = NbFmGetFuseTranslationTable (); + for (RegisterIndex = 0; RegisterIndex < FuseTable->FuseTableLength; RegisterIndex++ ) { + UINTN FieldIndex; + UINTN FuseRegisterTableLength; + UINT32 FuseValue; + FuseRegisterTableLength = FuseTable->FuseTable[RegisterIndex].FuseRegisterTableLength; + FuseValue = NbSmuReadEfuse ( + FuseTable->FuseTable[RegisterIndex].Register, + StdHeader + ); + for (FieldIndex = 0; FieldIndex < FuseRegisterTableLength; FieldIndex++) { + FUSE_REGISTER_ENTRY RegisterEntry; + RegisterEntry = FuseTable->FuseTable[RegisterIndex].FuseRegisterTable[FieldIndex]; + *((UINT8 *) PpFuseArray + RegisterEntry.FuseOffset) = (UINT8) ((FuseValue >> RegisterEntry.FieldOffset) & + ((1 << RegisterEntry.FieldWidth) - 1)); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Load Default Fuse Table + * + * + * @param[out] PpFuseArray Pointer to save fuse table + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +VOID +NbFuseLoadDefaultFuseTable ( + OUT PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D18F3x15C_STRUCT D18F3x15C; + UINT8 MaxVidIndex; + LibAmdMemCopy (PpFuseArray, &DefaultPpFuseArray, sizeof (PP_FUSE_ARRAY), StdHeader); + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), + AccessWidth32, + &D18F3x15C.Value, + StdHeader + ); + if (D18F3x15C.Value == 0) { + D18F3x15C.Value = 0x24242424; + GnbLibPciWrite ( + MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), + AccessWidth32, + &D18F3x15C.Value, + StdHeader + ); + } + MaxVidIndex = GfxLibMaxVidIndex (StdHeader); + PpFuseArray->SclkDpmVid[0] = MaxVidIndex; + PpFuseArray->PcieGen2Vid = MaxVidIndex; + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Adjust DIDs to current main PLL VCO + * + * Main PLL VCO can be changed for debug perpouses + * + * @param[in,out] PpFuseArray Pointer to save fuse table + * @param[in] StdHeader Pointer to Standard configuration + */ + +VOID +NbFuseAdjustFuseTableToCurrentMainPllVco ( + IN OUT PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 EffectiveMainPllFreq10KHz; + UINT32 FusedMainPllFreq10KHz; + UINT32 TempVco; + UINTN Index; + EffectiveMainPllFreq10KHz = GfxLibGetMainPllFreq (StdHeader) * 100; + FusedMainPllFreq10KHz = (PpFuseArray->MainPllId + 0x10) * 100 * 100; + if (FusedMainPllFreq10KHz != EffectiveMainPllFreq10KHz) { + IDS_HDT_CONSOLE (NB_MISC, " WARNING! Adjusting fuse table for reprogrammed VCO\n"); + for (Index = 0; Index < 5; Index++) { + if (PpFuseArray->SclkDpmDid[Index] != 0) { + TempVco = GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], FusedMainPllFreq10KHz); + PpFuseArray->SclkDpmDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); + } + } + for (Index = 0; Index < 4; Index++) { + if (PpFuseArray->VclkDid[Index] != 0) { + TempVco = GfxLibCalculateClk (PpFuseArray->VclkDid[Index], FusedMainPllFreq10KHz); + PpFuseArray->VclkDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); + } + if (PpFuseArray->DclkDid[Index] != 0) { + TempVco = GfxLibCalculateClk (PpFuseArray->DclkDid[Index], FusedMainPllFreq10KHz); + PpFuseArray->DclkDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); + } + if (PpFuseArray->LclkDpmDid[Index] != 0) { + TempVco = GfxLibCalculateClk (PpFuseArray->LclkDpmDid[Index], FusedMainPllFreq10KHz); + PpFuseArray->LclkDpmDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); + } + if (PpFuseArray->DisplclkDid[Index] != 0) { + TempVco = GfxLibCalculateClk (PpFuseArray->DisplclkDid[Index], FusedMainPllFreq10KHz); + PpFuseArray->DisplclkDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); + } + } + if (PpFuseArray->SclkThermDid != 0) { + TempVco = GfxLibCalculateClk (PpFuseArray->SclkThermDid , FusedMainPllFreq10KHz); + PpFuseArray->SclkThermDid = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Debug dump fuse table + * + * + * @param[out] PpFuseArray Pointer to save fuse table + * @param[in] StdHeader Pointer to Standard configuration + */ + +VOID +NbFuseDebugDump ( + IN PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN Index; + UINT32 EffectiveMainPllFreq10KHz; + + EffectiveMainPllFreq10KHz = GfxLibGetMainPllFreq (StdHeader) * 100; + IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n"); + for (Index = 0; Index < 4; Index++) { + if (PpFuseArray->LclkDpmValid[Index] != 0) { + IDS_HDT_CONSOLE ( + NB_MISC, + " LCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->LclkDpmDid[Index], + GfxLibCalculateClk (PpFuseArray->LclkDpmDid[Index], EffectiveMainPllFreq10KHz) / 100); + IDS_HDT_CONSOLE (NB_MISC, " LCLK VID[%d] - 0x02%x\n", Index, PpFuseArray->LclkDpmVid[Index]); + } + } + for (Index = 0; Index < 4; Index++) { + IDS_HDT_CONSOLE ( + NB_MISC, + " VCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->VclkDid[Index], + (PpFuseArray->VclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->VclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 + ); + IDS_HDT_CONSOLE ( + NB_MISC, + " DCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->DclkDid[Index], + (PpFuseArray->DclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->DclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 + ); + } + for (Index = 0; Index < 4; Index++) { + IDS_HDT_CONSOLE ( + NB_MISC, + " DISPCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->DisplclkDid[Index], + (PpFuseArray->DisplclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->DisplclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 + ); + } + for (Index = 0; Index < 5; Index++) { + IDS_HDT_CONSOLE ( + NB_MISC, + " SCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->SclkDpmDid[Index], + (PpFuseArray->SclkDpmDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 + ); + IDS_HDT_CONSOLE (NB_MISC, " SCLK VID[%d] - 0x%02x\n", Index, PpFuseArray->SclkDpmVid[Index]); + } + for (Index = 0; Index < 6; Index++) { + IDS_HDT_CONSOLE (NB_MISC, " State #%d\n", Index); + IDS_HDT_CONSOLE (NB_MISC, " Policy Label - 0x%x\n", PpFuseArray->PolicyLabel[Index]); + IDS_HDT_CONSOLE (NB_MISC, " Policy Flag - 0x%x\n", PpFuseArray->PolicyFlags[Index]); + IDS_HDT_CONSOLE (NB_MISC, " Valid SCLK - 0x%x\n", PpFuseArray->SclkDpmValid[Index]); + IDS_HDT_CONSOLE (NB_MISC, " Vclk/Dclk Index - 0x%x\n", PpFuseArray->VclkDclkSel[Index]); + } + IDS_HDT_CONSOLE (NB_MISC, " GEN2 VID - 0x%x\n", PpFuseArray->PcieGen2Vid); + IDS_HDT_CONSOLE (NB_MISC, " Main PLL Id - 0x%x\n", PpFuseArray->MainPllId); + IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE END-------------->\n"); +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbFuseTable.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbFuseTable.h new file mode 100644 index 0000000000..876cb6a2e6 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbFuseTable.h @@ -0,0 +1,54 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Fuse table initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +#ifndef _NBFUSETABLE_H_ +#define _NBFUSETABLE_H_ + +AGESA_STATUS +NbFuseTableFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbLclkDpm.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbLclkDpm.c new file mode 100644 index 0000000000..b8f683ecc2 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbLclkDpm.c @@ -0,0 +1,109 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * LCLK DPM initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 40044 $ @e \$Date: 2010-10-19 06:43:22 +0800 (Tue, 19 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbFuseTable.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include "GnbRegistersON.h" +#include "OptionGnb.h" +#include "GfxLib.h" +#include "NbConfigData.h" +#include "NbSmuLib.h" +#include "NbLclkDpm.h" +#include "NbFamilyServices.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * LCLK DPM init + * + * + * + * @param[in] StdHeader Pointer to Standard configuration + * @retval Initialization status + */ + +AGESA_STATUS +NbLclkDpmFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "NbLclkDpmFeature Enter\n"); + + Status = NbFmInitLclkDpmRcActivity (StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "NbLclkDpmFeature Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbLclkDpm.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbLclkDpm.h new file mode 100644 index 0000000000..272fc775d8 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbLclkDpm.h @@ -0,0 +1,61 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB Lclk DPM + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 38842 $ @e \$Date: 2010-10-01 05:04:55 +0800 (Fri, 01 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _NBLCLKDPM_H_ +#define _NBLCLKDPM_H_ + +/// LCLK DPM enable control +typedef enum { + LclkDpmDisabled, ///<LCLK DPM disabled + LclkDpmRcActivity, ///<LCLK DPM enabled and use Root Complex Activity monitor method +} LCLK_DPM_MODE; + +AGESA_STATUS +NbLclkDpmFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbConfigData.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbConfigData.c new file mode 100644 index 0000000000..0dd2f9ad8b --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbConfigData.c @@ -0,0 +1,95 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize NB configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "NbConfigData.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_NB_NBCONFIGDATA_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Create configuration data + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] Gnb Pointer to global Gnb configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +NbAllocateConfigData ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN GNB_PLATFORM_CONFIG *Gnb + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + Gnb->StdHeader = StdHeader; + return Status; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbConfigData.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbConfigData.h new file mode 100644 index 0000000000..fc93a7a259 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbConfigData.h @@ -0,0 +1,69 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize NB configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _NBCONFIGDATA_H_ +#define _NBCONFIGDATA_H_ + +/// NB register entry +typedef struct { + UINT16 Reg; ///< Register address + UINT32 Mask; ///< Mask + UINT32 Data; ///< Data +} NB_REGISTER_ENTRY; + +/// GNB Platform Configuration +typedef struct { + AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header + PCI_ADDR GnbPciAddress; ///< PCI Address +} GNB_PLATFORM_CONFIG; + +AGESA_STATUS +NbAllocateConfigData ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN GNB_PLATFORM_CONFIG *Gnb + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInit.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInit.c new file mode 100644 index 0000000000..88ef6bf813 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInit.c @@ -0,0 +1,204 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various NB initialization services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 41506 $ @e \$Date: 2010-11-05 22:31:30 +0800 (Fri, 05 Nov 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include "GfxLib.h" +#include "NbSmuLib.h" +#include "NbConfigData.h" +#include "GnbRegistersON.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_NB_NBINIT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +CONST NB_REGISTER_ENTRY NbPciInitTable [] = { + { + D0F0x04_ADDRESS, + 0xffffffff, + (0x1 << D0F0x04_MemAccessEn_WIDTH) | (0x1 << D0F0x04_BusMasterEn_OFFSET) + }, + { + D0F0x4C_ADDRESS, + ~(0x3ull << D0F0x4C_CfgRdTime_OFFSET), + 0x2 << D0F0x4C_CfgRdTime_OFFSET + }, + { + D0F0x84_ADDRESS, + ~(0x1ull << D0F0x84_Ev6Mode_OFFSET), + 0x1 << D0F0x84_Ev6Mode_OFFSET + } +}; + +CONST NB_REGISTER_ENTRY NbMiscInitTable [] = { + { + D0F0x64_x46_ADDRESS, + ~(0x3ull << D0F0x64_x46_P2PMode_OFFSET), + 1 << D0F0x64_x46_Msi64bitEn_OFFSET + } +}; + + +CONST NB_REGISTER_ENTRY NbOrbInitTable [] = { + { + D0F0x98_x07_ADDRESS, + 0xffffffff, + (1 << D0F0x98_x07_IocBwOptEn_OFFSET) | + (1 << D0F0x98_x07_MSIHTIntConversionEn_OFFSET) | + (1 << D0F0x98_x07_DropZeroMaskWrEn_OFFSET) + }, + { + D0F0x98_x08_ADDRESS, + ~(0xffull << D0F0x98_x08_NpWrrLenC_OFFSET), + 1 << D0F0x98_x08_NpWrrLenC_OFFSET + }, + { + D0F0x98_x09_ADDRESS, + ~(0xffull << D0F0x98_x09_PWrrLenD_OFFSET), + 1 << D0F0x98_x09_PWrrLenD_OFFSET + }, + { + D0F0x98_x0C_ADDRESS, + 0xffffffff, + 1 << D0F0x98_x0C_StrictSelWinnerEn_OFFSET + }, + { + D0F0x98_x0E_ADDRESS, + 0xffffffff, + 1 << D0F0x98_x0E_MsiHtRsvIntRemapEn_OFFSET + }, + { + D0F0x98_x28_ADDRESS, + 0xffffffff, + (1 << D0F0x98_x28_SmuPmInterfaceEn_OFFSET) | + (1 << D0F0x98_x28_ForceCoherentIntr_OFFSET) + } +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init NB at Power On + * + * + * + * @param[in] Gnb Pointer to global Gnb configuration + * @retval AGESA_STATUS + */ + + +AGESA_STATUS +NbInitOnPowerOn ( + IN GNB_PLATFORM_CONFIG *Gnb + ) +{ + UINTN Index; + FCRxFF30_0398_STRUCT FCRxFF30_0398; + // Init NBCONFIG + for (Index = 0; Index < (sizeof (NbPciInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { + GnbLibPciRMW ( + Gnb->GnbPciAddress.AddressValue | NbPciInitTable[Index].Reg, + AccessWidth32, + NbPciInitTable[Index].Mask, + NbPciInitTable[Index].Data, + Gnb->StdHeader + ); + } + + // Init MISCIND + for (Index = 0; Index < (sizeof (NbMiscInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { + GnbLibPciIndirectRMW ( + Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, + NbMiscInitTable[Index].Reg | IOC_WRITE_ENABLE, + AccessWidth32, + NbMiscInitTable[Index].Mask, + NbMiscInitTable[Index].Data, + Gnb->StdHeader + ); + } + + // Init ORB + for (Index = 0; Index < (sizeof (NbOrbInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { + GnbLibPciIndirectRMW ( + Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, + NbOrbInitTable[Index].Reg | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessWidth32, + NbOrbInitTable[Index].Mask, + NbOrbInitTable[Index].Data, + Gnb->StdHeader + ); + } + if (!GfxLibIsControllerPresent (Gnb->StdHeader)) { + FCRxFF30_0398.Value = (1 << FCRxFF30_0398_SoftResetGrbm_OFFSET) | (1 << FCRxFF30_0398_SoftResetMc_OFFSET) | + (1 << FCRxFF30_0398_SoftResetDc_OFFSET) | (1 << FCRxFF30_0398_SoftResetRlc_OFFSET) | + (1 << FCRxFF30_0398_SoftResetUvd_OFFSET); + NbSmuSrbmRegisterWrite (FCRxFF30_0398_ADDRESS, &FCRxFF30_0398.Value, FALSE, Gnb->StdHeader); + } + + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInit.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInit.h new file mode 100644 index 0000000000..3fb65f4390 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInit.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various NB initialization services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _NBINIT_H_ +#define _NBINIT_H_ + +AGESA_STATUS +NbInitOnPowerOn ( + IN GNB_PLATFORM_CONFIG *Gnb + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEarly.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEarly.c new file mode 100644 index 0000000000..b09d19295e --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEarly.c @@ -0,0 +1,123 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB early initialization interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbNbInitLibV1) +#include "NbConfigData.h" +#include "NbInit.h" +#include "NbInitAtEarly.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_NB_NBINITATEARLY_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Reset + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +NbInitAtEarly ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GNB_PLATFORM_CONFIG Gnb; + UINT32 NumberOfSockets; + UINT32 SocketId; + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEarly Enter\n"); + NbAllocateConfigData (StdHeader, &Gnb); + NumberOfSockets = GnbGetNumberOfSockets (StdHeader); + for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { + UINT32 NumberOfSilicons; + UINT32 SiliconId; + if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) { + continue; + } + NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader); + for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) { + Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader); + Status = NbInitOnPowerOn (&Gnb); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEarly Exit[0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEarly.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEarly.h new file mode 100644 index 0000000000..acc6735e98 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEarly.h @@ -0,0 +1,54 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB early initialization interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: + * @e sub-project: + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +#ifndef _NBINITATRESET_H_ +#define _NBINITATRESET_H_ + +AGESA_STATUS +NbInitAtEarly ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEnv.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEnv.c new file mode 100644 index 0000000000..0317e4c296 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEnv.c @@ -0,0 +1,124 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB init at ENV interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbFuseTable.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbNbInitLibV1) +#include "NbConfigData.h" +#include "NbFamilyServices.h" +#include "NbInitAtEnv.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_NB_NBINITATENV_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at ENV + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +NbInitAtEnv ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GNB_PLATFORM_CONFIG Gnb; + UINT32 NumberOfSockets; + UINT32 SocketId; + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEnv Enter\n"); + NbAllocateConfigData (StdHeader, &Gnb); + NumberOfSockets = GnbGetNumberOfSockets (StdHeader); + for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { + UINT32 NumberOfSilicons; + UINT32 SiliconId; + if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) { + continue; + } + NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader); + for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) { + Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader); + GnbLpcDmaDeadlockPrevention (Gnb.GnbPciAddress, StdHeader); + Status = GnbSetTom (Gnb.GnbPciAddress, StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + NbFmClumpUnitID (Gnb.GnbPciAddress, StdHeader); + GnbOrbDynamicWake (Gnb.GnbPciAddress, StdHeader); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEnv Exit[0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEnv.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEnv.h new file mode 100644 index 0000000000..533cdd2a39 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEnv.h @@ -0,0 +1,58 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB post init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _NBINITATENV_H_ +#define _NBINITATENV_H_ + +AGESA_STATUS +NbInitAtEnv ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif + + + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtLatePost.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtLatePost.c new file mode 100644 index 0000000000..854f900cbd --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtLatePost.c @@ -0,0 +1,122 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB late POST init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: + * @e sub-project: + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbNbInitLibV1) +#include "NbConfigData.h" +#include "NbPowerMgmt.h" +#include "NbInitAtLatePost.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_NB_NBINITATLATEPOST_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Late Post + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +NbInitAtLatePost ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GNB_PLATFORM_CONFIG Gnb; + UINT32 NumberOfSockets; + UINT32 SocketId; + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtLatePost Enter\n"); + Status = NbAllocateConfigData (StdHeader, &Gnb); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + NumberOfSockets = GnbGetNumberOfSockets (StdHeader); + for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { + UINT32 NumberOfSilicons; + UINT32 SiliconId; + if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) { + continue; + } + NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader); + for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) { + Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader); + Status = NbInitPowerManagement (&Gnb); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + GnbLock (Gnb.GnbPciAddress, StdHeader); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtLatePost Exit[0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtLatePost.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtLatePost.h new file mode 100644 index 0000000000..c01b8fb372 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtLatePost.h @@ -0,0 +1,56 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB late POST init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: + * @e sub-project: + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _NBINITATLATEPOST_H_ +#define _NBINITATLATEPOST_H_ + +AGESA_STATUS +NbInitAtLatePost ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtPost.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtPost.c new file mode 100644 index 0000000000..c092f7f4a2 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtPost.c @@ -0,0 +1,122 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB Post initialization interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbNbInitLibV1) +#include "NbConfigData.h" +#include "NbInitAtPost.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_NB_NBINITATPOST_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init NB at POST + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +NbInitAtPost ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GNB_PLATFORM_CONFIG Gnb; + UINT32 NumberOfSockets; + UINT32 SocketId; + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtPost Enter\n"); + NbAllocateConfigData (StdHeader, &Gnb); + NumberOfSockets = GnbGetNumberOfSockets (StdHeader); + for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { + UINT32 NumberOfSilicons; + UINT32 SiliconId; + if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) { + continue; + } + NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader); + for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) { + Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader); + Status = GnbSetTom (Gnb.GnbPciAddress, StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtPost Exit[0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtPost.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtPost.h new file mode 100644 index 0000000000..01065736f2 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtPost.h @@ -0,0 +1,54 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB Post initialization interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: + * @e sub-project: + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +#ifndef _NBINITATPOST_H_ +#define _NBINITATPOST_H_ + +AGESA_STATUS +NbInitAtPost ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtReset.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtReset.c new file mode 100644 index 0000000000..1620c48be7 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtReset.c @@ -0,0 +1,96 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB reset init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "NbInitAtReset.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_NB_NBINITATRESET_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Reset + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +NbInitAtReset ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + return Status; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtReset.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtReset.h new file mode 100644 index 0000000000..203ca22016 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtReset.h @@ -0,0 +1,54 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB reset init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: + * @e sub-project: + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +#ifndef _NBINITATRESET_H_ +#define _NBINITATRESET_H_ + +AGESA_STATUS +NbInitAtReset ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.c new file mode 100644 index 0000000000..11a872408a --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.c @@ -0,0 +1,600 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB power management features + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include "NbConfigData.h" +#include "NbSmuLib.h" +#include "NbPowerMgmt.h" +#include "OptionGnb.h" +#include "GfxLib.h" +#include "GnbRegistersON.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_NB_NBPOWERMGMT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- +*/ + +VOID +NbInitLclkDeepSleep ( + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitClockGating ( + IN GNB_PLATFORM_CONFIG *Gnb + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Init various power management features + * + * + * + * @param[in] Gnb Pointer to global Gnb configuration + * @retval AGESA_SUCCESS LCLK DPM initialization success + * @retval AGESA_ERROR LCLK DPM initialization error + */ + +AGESA_STATUS +NbInitPowerManagement ( + IN GNB_PLATFORM_CONFIG *Gnb + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + NbInitLclkDeepSleep (Gnb); + NbInitClockGating (Gnb); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init NB LCLK Deep Sleep + * + * + * + * @param[in] Gnb Pointer to global Gnb configuration + */ + +VOID +NbInitLclkDeepSleep ( + IN GNB_PLATFORM_CONFIG *Gnb + ) +{ + SMUx1B_STRUCT SMUx1B; + SMUx1D_STRUCT SMUx1D; + UINT32 LclkDpSlpEn; + IDS_HDT_CONSOLE (GNB_TRACE, "NbInitLclkDeepSleep Enter\n"); + LclkDpSlpEn = GnbBuildOptions.LclkDeepSleepEn ? 1 : 0; + NbSmuIndirectRead (SMUx1B_ADDRESS, AccessWidth16, &SMUx1B.Value, Gnb->StdHeader); + NbSmuIndirectRead (SMUx1D_ADDRESS, AccessWidth16, &SMUx1D.Value, Gnb->StdHeader); + SMUx1B.Field.LclkDpSlpDiv = 5; + SMUx1B.Field.LclkDpSlpMask = (GfxLibIsControllerPresent (Gnb->StdHeader) ? (0xFF) : 0xEF); + SMUx1B.Field.RampDis = 0; + SMUx1D.Field.LclkDpSlpHyst = 0xf; + IDS_OPTION_HOOK (IDS_GNB_LCLK_DEEP_SLEEP, &LclkDpSlpEn, Gnb->StdHeader); + SMUx1D.Field.LclkDpSlpEn = LclkDpSlpEn; + IDS_HDT_CONSOLE (GNB_TRACE, " LCLK Deep Sleep [%s]\n", (LclkDpSlpEn != 0) ? "Enabled" : "Disabled"); + NbSmuIndirectWrite (SMUx1B_ADDRESS, AccessS3SaveWidth16, &SMUx1B.Value, Gnb->StdHeader); + NbSmuIndirectWrite (SMUx1D_ADDRESS, AccessS3SaveWidth16, &SMUx1D.Value, Gnb->StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "NbInitLclkDeepSleep Exit\n"); +} + +/** + * Init NB SMU clock gating + * + * + * + * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure + * @param[in] Gnb Pointer to global Gnb configuration + */ + +VOID +NbInitSmuClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ) +{ + BOOLEAN Smu_Lclk_Gating; + BOOLEAN Smu_Sclk_Gating; + SMUx73_STRUCT SMUx73; + UINT32 Value; + + Smu_Lclk_Gating = NbClkGatingCtrl->Smu_Lclk_Gating; + Smu_Sclk_Gating = NbClkGatingCtrl->Smu_Sclk_Gating; +//SMUx6F + Value = 0x006001F0; + NbSmuIndirectWrite (SMUx6F_ADDRESS, AccessS3SaveWidth32, &Value, Gnb->StdHeader); +//SMUx71 + Value = 0x007001F0; + NbSmuIndirectWrite (SMUx71_ADDRESS, AccessS3SaveWidth32, &Value, Gnb->StdHeader); +//SMUx73 + NbSmuIndirectRead (SMUx73_ADDRESS, AccessWidth16, &SMUx73.Value, Gnb->StdHeader); + SMUx73.Field.DisLclkGating = Smu_Lclk_Gating ? 0 : 1; + SMUx73.Field.DisSclkGating = Smu_Sclk_Gating ? 0 : 1; + NbSmuIndirectWrite (SMUx73_ADDRESS, AccessS3SaveWidth16, &SMUx73.Value, Gnb->StdHeader); + +} + +/** + * Init NB ORB clock gating + * + * + * + * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure + * @param[in] Gnb Pointer to global Gnb configuration + */ + +VOID +NbInitOrbClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ) +{ + BOOLEAN Orb_Sclk_Gating; + BOOLEAN Orb_Lclk_Gating; + D0F0x98_x49_STRUCT D0F0x98_x49; + D0F0x98_x4A_STRUCT D0F0x98_x4A; + D0F0x98_x4B_STRUCT D0F0x98_x4B; + FCRxFF30_01F5_STRUCT FCRxFF30_01F5; + + Orb_Sclk_Gating = NbClkGatingCtrl->Orb_Sclk_Gating; + Orb_Lclk_Gating = NbClkGatingCtrl->Orb_Lclk_Gating; + + // ORB clock gating (Lclk) +//D0F0x98_x4[A:9] + GnbLibPciIndirectRead ( + Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x49_ADDRESS, + AccessWidth32, + &D0F0x98_x49.Value, + Gnb->StdHeader + ); + + D0F0x98_x49.Field.SoftOverrideClk6 = Orb_Lclk_Gating ? 0 : 1; + D0F0x98_x49.Field.SoftOverrideClk5 = Orb_Lclk_Gating ? 0 : 1; + D0F0x98_x49.Field.SoftOverrideClk4 = Orb_Lclk_Gating ? 0 : 1; + D0F0x98_x49.Field.SoftOverrideClk3 = Orb_Lclk_Gating ? 0 : 1; + D0F0x98_x49.Field.SoftOverrideClk2 = Orb_Lclk_Gating ? 0 : 1; + D0F0x98_x49.Field.SoftOverrideClk1 = Orb_Lclk_Gating ? 0 : 1; + D0F0x98_x49.Field.SoftOverrideClk0 = Orb_Lclk_Gating ? 0 : 1; + + GnbLibPciIndirectWrite ( + Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x49_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + &D0F0x98_x49.Value, + Gnb->StdHeader + ); + + GnbLibPciIndirectRead ( + Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x4A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessWidth32, + &D0F0x98_x4A.Value, + Gnb->StdHeader + ); + + D0F0x98_x4A.Field.SoftOverrideClk6 = Orb_Lclk_Gating ? 0 : 1; + D0F0x98_x4A.Field.SoftOverrideClk5 = Orb_Lclk_Gating ? 0 : 1; + D0F0x98_x4A.Field.SoftOverrideClk4 = Orb_Lclk_Gating ? 0 : 1; + D0F0x98_x4A.Field.SoftOverrideClk3 = Orb_Lclk_Gating ? 0 : 1; + D0F0x98_x4A.Field.SoftOverrideClk2 = Orb_Lclk_Gating ? 0 : 1; + D0F0x98_x4A.Field.SoftOverrideClk1 = Orb_Lclk_Gating ? 0 : 1; + D0F0x98_x4A.Field.SoftOverrideClk0 = Orb_Lclk_Gating ? 0 : 1; + + + GnbLibPciIndirectWrite ( + Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x4A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + &D0F0x98_x4A.Value, + Gnb->StdHeader + ); + +//D0F0x98_x4B + GnbLibPciIndirectRead ( + Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x4B_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessWidth32, + &D0F0x98_x4B.Value, + Gnb->StdHeader + ); + + D0F0x98_x4B.Field.SoftOverrideClk = Orb_Sclk_Gating ? 0 : 1; + + GnbLibPciIndirectWrite ( + Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x4B_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + &D0F0x98_x4B.Value, + Gnb->StdHeader + ); + +//FCRxFF30_01F5[CgOrbCgttLclkOverride, CgOrbCgttSclkOverride] + NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); + FCRxFF30_01F5.Field.CgOrbCgttLclkOverride = 0; + FCRxFF30_01F5.Field.CgOrbCgttSclkOverride = 0; + NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); + +} + +/** + * Init NB IOC clock gating + * + * + * + * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure + * @param[in] Gnb Pointer to global Gnb configuration + */ + +VOID +NbInitIocClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ) +{ + BOOLEAN Ioc_Lclk_Gating; + BOOLEAN Ioc_Sclk_Gating; + D0F0x64_x22_STRUCT D0F0x64_x22; + D0F0x64_x23_STRUCT D0F0x64_x23; + D0F0x64_x24_STRUCT D0F0x64_x24; + FCRxFF30_01F5_STRUCT FCRxFF30_01F5; + + Ioc_Lclk_Gating = NbClkGatingCtrl->Ioc_Lclk_Gating; + Ioc_Sclk_Gating = NbClkGatingCtrl->Ioc_Sclk_Gating; + +//D0F0x64_x22 + GnbLibPciIndirectRead ( + Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x22_ADDRESS | IOC_WRITE_ENABLE, + AccessWidth32, + &D0F0x64_x22.Value, + Gnb->StdHeader + ); + + D0F0x64_x22.Field.SoftOverrideClk4 = Ioc_Lclk_Gating ? 0 : 1; + D0F0x64_x22.Field.SoftOverrideClk3 = Ioc_Lclk_Gating ? 0 : 1; + D0F0x64_x22.Field.SoftOverrideClk2 = Ioc_Lclk_Gating ? 0 : 1; + D0F0x64_x22.Field.SoftOverrideClk1 = Ioc_Lclk_Gating ? 0 : 1; + D0F0x64_x22.Field.SoftOverrideClk0 = Ioc_Lclk_Gating ? 0 : 1; + + GnbLibPciIndirectWrite ( + Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x22_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &D0F0x64_x22.Value, + Gnb->StdHeader + ); +//D0F0x64_x23 + GnbLibPciIndirectRead ( + Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x23_ADDRESS | IOC_WRITE_ENABLE, + AccessWidth32, + &D0F0x64_x23.Value, + Gnb->StdHeader + ); + + //D0F0x64_x23.Field.SoftOverrideClk4 = Ioc_Lclk_Gating ? 0 : 1; + D0F0x64_x23.Field.SoftOverrideClk3 = Ioc_Lclk_Gating ? 0 : 1; + D0F0x64_x23.Field.SoftOverrideClk2 = Ioc_Lclk_Gating ? 0 : 1; + D0F0x64_x23.Field.SoftOverrideClk1 = Ioc_Lclk_Gating ? 0 : 1; + D0F0x64_x23.Field.SoftOverrideClk0 = Ioc_Lclk_Gating ? 0 : 1; + + GnbLibPciIndirectWrite ( + Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x23_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &D0F0x64_x23.Value, + Gnb->StdHeader + ); + //D0F0x64_x24 + GnbLibPciIndirectRead ( + Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x24_ADDRESS | IOC_WRITE_ENABLE, + AccessWidth32, + &D0F0x64_x24.Value, + Gnb->StdHeader + ); + + D0F0x64_x24.Field.SoftOverrideClk1 = Ioc_Sclk_Gating ? 0 : 1; + D0F0x64_x24.Field.SoftOverrideClk0 = Ioc_Sclk_Gating ? 0 : 1; + + GnbLibPciIndirectWrite ( + Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x24_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &D0F0x64_x24.Value, + Gnb->StdHeader + ); +//FCRxFF30_01F5[CgIocCgttLclkOverride, CgIocCgttSclkOverride] + NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); + FCRxFF30_01F5.Field.CgIocCgttLclkOverride = 0; + FCRxFF30_01F5.Field.CgIocCgttSclkOverride = 0; + NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); +} +/** + * Init NB BIF clock gating + * + * + * + * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure + * @param[in] Gnb Pointer to global Gnb configuration + */ + +VOID +NbInitBifClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ) +{ + BOOLEAN Bif_Sclk_Gating; + FCRxFF30_01F4_STRUCT FCRxFF30_01F4; + FCRxFF30_1512_STRUCT FCRxFF30_1512; + + + Bif_Sclk_Gating = NbClkGatingCtrl->Bif_Sclk_Gating; + +//FCRxFF30_01F4[CgBifCgttSclkOverride]. + NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); + FCRxFF30_01F4.Field.CgBifCgttSclkOverride = 0; + NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader); +//FCRxFF30_1512 + NbSmuSrbmRegisterRead (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, Gnb->StdHeader); + FCRxFF30_1512.Field.SoftOverride0 = Bif_Sclk_Gating ? 0 : 1; + NbSmuSrbmRegisterWrite (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, TRUE, Gnb->StdHeader); + +} + +/** + * Init NB Gmc clock gating + * + * + * + * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure + * @param[in] Gnb Pointer to global Gnb configuration + */ + +VOID +NbInitGmcClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ) +{ + BOOLEAN Gmc_Sclk_Gating; + FCRxFF30_01F4_STRUCT FCRxFF30_01F4; + FCRxFF30_01F5_STRUCT FCRxFF30_01F5; + + Gmc_Sclk_Gating = NbClkGatingCtrl->Gmc_Sclk_Gating; + +//FCRxFF30_01F4[CgMcdwCgttSclkOverride, CgMcbCgttSclkOverride] + NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); + FCRxFF30_01F4.Field.CgMcbCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1; + FCRxFF30_01F4.Field.CgMcdwCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1; + NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader); + +//FCRxFF30_01F5[CgVmcCgttSclkOverride] + NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); + FCRxFF30_01F5.Field.CgVmcCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1; + NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); + +} + +/** + * Init NB Dce Sclk clock gating + * + * + * + * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure + * @param[in] Gnb Pointer to global Gnb configuration + */ + +VOID +NbInitDceSclkClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ) +{ + BOOLEAN Dce_Sclk_Gating; + FCRxFF30_0134_STRUCT FCRxFF30_0134; + FCRxFF30_01F4_STRUCT FCRxFF30_01F4; + + Dce_Sclk_Gating = NbClkGatingCtrl->Dce_Sclk_Gating; + +//GMMx4D0[SymclkbGateDisable, SymclkaGateDisable, SclkGateDisable] + NbSmuSrbmRegisterRead (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, Gnb->StdHeader); + FCRxFF30_0134.Field.SclkGateDisable = Dce_Sclk_Gating ? 0 : 1; + FCRxFF30_0134.Field.SymclkaGateDisable = Dce_Sclk_Gating ? 0 : 1; + FCRxFF30_0134.Field.SymclkbGateDisable = Dce_Sclk_Gating ? 0 : 1; + NbSmuSrbmRegisterWrite (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, TRUE, Gnb->StdHeader); + +//FCRxFF30_01F4[CgDcCgttSclkOverride] + NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); + FCRxFF30_01F4.Field.CgDcCgttSclkOverride = 0; + NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader); + +} + +/** + * Init NB Dce Display clock gating + * + * + * + * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure + * @param[in] Gnb Pointer to global Gnb configuration + */ + +VOID +NbInitDceDisplayClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ) +{ + BOOLEAN Dce_Dispclk_Gating; + FCRxFF30_0134_STRUCT FCRxFF30_0134; + FCRxFF30_1B7C_STRUCT FCRxFF30_1B7C; + FCRxFF30_1E7C_STRUCT FCRxFF30_1E7C; + FCRxFF30_01F5_STRUCT FCRxFF30_01F5; + + Dce_Dispclk_Gating = NbClkGatingCtrl->Dce_Dispclk_Gating; + +//GMMx4D0[DispclkRDccgGateDisable,DispclkDccgGateDisable] + NbSmuSrbmRegisterRead (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, Gnb->StdHeader); + FCRxFF30_0134.Field.DispclkDccgGateDisable = Dce_Dispclk_Gating ? 0 : 1; + FCRxFF30_0134.Field.DispclkRDccgGateDisable = Dce_Dispclk_Gating ? 0 : 1; + NbSmuSrbmRegisterWrite (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, TRUE, Gnb->StdHeader); + +//GMMx[79,6D]F0[CrtcDispclkGSclGateDisable, CrtcDispclkGDcpGateDisable, CrtcDispclkRDcfeGateDisable] + NbSmuSrbmRegisterRead (FCRxFF30_1B7C_ADDRESS, &FCRxFF30_1B7C.Value, Gnb->StdHeader); + FCRxFF30_1B7C.Field.CrtcDispclkRDcfeGateDisable = Dce_Dispclk_Gating ? 0 : 1; + FCRxFF30_1B7C.Field.CrtcDispclkGDcpGateDisable = Dce_Dispclk_Gating ? 0 : 1; + FCRxFF30_1B7C.Field.CrtcDispclkGSclGateDisable = Dce_Dispclk_Gating ? 0 : 1; + NbSmuSrbmRegisterWrite (FCRxFF30_1B7C_ADDRESS, &FCRxFF30_1B7C.Value, TRUE, Gnb->StdHeader); + + NbSmuSrbmRegisterRead (FCRxFF30_1E7C_ADDRESS, &FCRxFF30_1E7C.Value, Gnb->StdHeader); + FCRxFF30_1E7C.Field.CrtcDispclkRDcfeGateDisable = Dce_Dispclk_Gating ? 0 : 1; + FCRxFF30_1E7C.Field.CrtcDispclkGDcpGateDisable = Dce_Dispclk_Gating ? 0 : 1; + FCRxFF30_1E7C.Field.CrtcDispclkGSclGateDisable = Dce_Dispclk_Gating ? 0 : 1; + NbSmuSrbmRegisterWrite (FCRxFF30_1E7C_ADDRESS, &FCRxFF30_1E7C.Value, TRUE, Gnb->StdHeader); + +//FCRxFF30_01F5[CgDcCgttDispclkOverride] + NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); + FCRxFF30_01F5.Field.CgDcCgttDispClkOverride = 0; + NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init NB clock gating + * + * + * + * @param[in] Gnb Pointer to global Gnb configuration + */ + +VOID +NbInitClockGating ( + IN GNB_PLATFORM_CONFIG *Gnb + ) +{ + NB_CLK_GATING_CTRL NbClkGatingCtrl; + + //Init the default value of control structure. + NbClkGatingCtrl.Smu_Sclk_Gating = GnbBuildOptions.SmuSclkClockGatingEnable; + NbClkGatingCtrl.Smu_Lclk_Gating = TRUE; + NbClkGatingCtrl.Orb_Sclk_Gating = TRUE; + NbClkGatingCtrl.Orb_Lclk_Gating = TRUE; + NbClkGatingCtrl.Ioc_Sclk_Gating = TRUE; + NbClkGatingCtrl.Ioc_Lclk_Gating = TRUE; + NbClkGatingCtrl.Bif_Sclk_Gating = TRUE; + NbClkGatingCtrl.Gmc_Sclk_Gating = TRUE; + NbClkGatingCtrl.Dce_Sclk_Gating = TRUE; + NbClkGatingCtrl.Dce_Dispclk_Gating = TRUE; + + IDS_OPTION_HOOK (IDS_GNB_CLOCK_GATING, &NbClkGatingCtrl, Gnb->StdHeader); + + + IDS_HDT_CONSOLE (GNB_TRACE, "NbInitClockGating Enter\n"); + +//SMU SCLK/LCLK clock gating + NbInitSmuClockGating (&NbClkGatingCtrl, Gnb); + +// ORB clock gating + NbInitOrbClockGating (&NbClkGatingCtrl, Gnb); + +//IOC clock gating + NbInitIocClockGating (&NbClkGatingCtrl, Gnb); + +//BIF Clock Gating + NbInitBifClockGating (&NbClkGatingCtrl, Gnb); + +//GMC Clock Gating + NbInitGmcClockGating (&NbClkGatingCtrl, Gnb); + +//DCE Sclk clock gating + NbInitDceSclkClockGating (&NbClkGatingCtrl, Gnb); + +//DCE Display clock gating + NbInitDceDisplayClockGating (&NbClkGatingCtrl, Gnb); + + GNB_DEBUG_CODE ( + { + FCRxFF30_01F4_STRUCT FCRxFF30_01F4; + FCRxFF30_01F5_STRUCT FCRxFF30_01F5; + FCRxFF30_1512_STRUCT FCRxFF30_1512; + NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); + NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); + NbSmuSrbmRegisterRead (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, Gnb->StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_01F4 - 0x%x\n", FCRxFF30_01F4.Value); + IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_01F5 - 0x%x\n", FCRxFF30_01F5.Value); + IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_1512 - 0x%x\n", FCRxFF30_1512.Value); + } + ); + IDS_HDT_CONSOLE (GNB_TRACE, "NbInitClockGating End\n"); +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.h new file mode 100644 index 0000000000..bb5a54904c --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.h @@ -0,0 +1,70 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB power management features + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _NBPOWERMGMT_H_ +#define _NBPOWERMGMT_H_ + + +AGESA_STATUS +NbInitPowerManagement ( + IN GNB_PLATFORM_CONFIG *Gnb + ); + +///Control structure for clock gating feature +typedef struct { + BOOLEAN Smu_Sclk_Gating; ///<Control Smu SClk gating 1 Enable 0 Disable + BOOLEAN Smu_Lclk_Gating; ///<Control Smu LClk gating 1 Enable 0 Disable + BOOLEAN Orb_Sclk_Gating; ///<Control ORB SClk gating 1 Enable 0 Disable + BOOLEAN Orb_Lclk_Gating; ///<Control ORB LClk gating 1 Enable 0 Disable + BOOLEAN Ioc_Sclk_Gating; ///<Control IOC SClk gating 1 Enable 0 Disable + BOOLEAN Ioc_Lclk_Gating; ///<Control IOC LClk gating 1 Enable 0 Disable + BOOLEAN Bif_Sclk_Gating; ///<Control BIF SClk gating 1 Enable 0 Disable + BOOLEAN Gmc_Sclk_Gating; ///<Control GMC SClk gating 1 Enable 0 Disable + BOOLEAN Dce_Sclk_Gating; ///<Control DCE SClk gating 1 Enable 0 Disable + BOOLEAN Dce_Dispclk_Gating; ///<Control DCE dispaly gating 1 Enable 0 Disable +} NB_CLK_GATING_CTRL; + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.c new file mode 100644 index 0000000000..fa3ac0686c --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.c @@ -0,0 +1,652 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * SMU access routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include "OptionGnb.h" +#include "NbSmuLib.h" +#include "GnbRegistersON.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_NB_NBSMULIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/// Efuse write packet +typedef struct { + SMUx0B_x8600_STRUCT SMUx0B_x8600; ///< Reg SMUx0B_x8600 + SMUx0B_x8604_STRUCT SMUx0B_x8604; ///< Reg SMUx0B_x8604 + SMUx0B_x8608_STRUCT SMUx0B_x8608; ///< Reg SMUx0B_x8605 +} MBUS; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU indirect register read + * + * + * + * @param[in] Address Register Address + * @param[in] Width Data width for read + * @param[out] Value Pointer read value + * @param[in] StdHeader Pointer to standard configuration + */ + + +VOID +NbSmuIndirectRead ( + IN UINT8 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + D0F0x64_x4D_STRUCT D0F0x64_x4D; + UINT32 Data; + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE, + AccessWidth32, + &D0F0x64_x4D.Value, + StdHeader + ); + + D0F0x64_x4D.Field.ReqType = 0; + D0F0x64_x4D.Field.SmuAddr = Address; + if (Width == AccessS3SaveWidth32 || Width == AccessWidth32) { + D0F0x64_x4D.Field.SmuAddr += 1; + } + + D0F0x64_x4D.Field.ReqToggle = !D0F0x64_x4D.Field.ReqToggle; + + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE, + (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32, + &D0F0x64_x4D.Value, + StdHeader + ); + + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + D0F0x64_x4E_ADDRESS | IOC_WRITE_ENABLE, + (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32, + &Data, + StdHeader + ); + + switch (Width) { + case AccessWidth16: + //no break; intended to fall through + case AccessS3SaveWidth16: + *(UINT16 *) Value = (UINT16) Data; + break; + case AccessWidth32: + //no break; intended to fall through + case AccessS3SaveWidth32: + *(UINT32 *) Value = Data; + break; + default: + ASSERT (FALSE); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU indirect register read + * + * + * + * @param[in] Address Register Address + * @param[in] Width Access width + * @param[in] Mask Data mask for compare + * @param[in] CompateData Compare data + * @param[in] StdHeader Pointer to standard configuration + */ + + +VOID +NbSmuIndirectPoll ( + IN UINT8 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 CompateData, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Value; + + do { + NbSmuIndirectRead ( + Address, + Width, + &Value, + StdHeader + ); + } while ((Value & Mask) != CompateData); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU indirect register write + * + * + * + * @param[in] Address Register Address + * @param[in] Width Data width for write + * @param[in] Value Pointer to write value + * @param[in] StdHeader Pointer to standard configuration + */ + + +VOID +NbSmuIndirectWriteEx ( + IN UINT8 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0x64_x4D_STRUCT D0F0x64_x4D; + ASSERT (Width != AccessWidth8); + ASSERT (Width != AccessS3SaveWidth8); + + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE, + AccessWidth32, + &D0F0x64_x4D.Value, + StdHeader + ); + + D0F0x64_x4D.Field.ReqType = 0x1; + D0F0x64_x4D.Field.SmuAddr = Address; + D0F0x64_x4D.Field.ReqToggle = (!D0F0x64_x4D.Field.ReqToggle); + + D0F0x64_x4D.Field.WriteData = ((UINT16 *) Value) [0]; + + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE, + (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32, + &D0F0x64_x4D.Value, + StdHeader + ); + if (LibAmdAccessWidth (Width) <= 2) { + return; + } + D0F0x64_x4D.Field.ReqType = 0x1; + D0F0x64_x4D.Field.SmuAddr = Address + 1; + D0F0x64_x4D.Field.ReqToggle = (!D0F0x64_x4D.Field.ReqToggle); + D0F0x64_x4D.Field.WriteData = ((UINT16 *) Value)[1]; + + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE, + (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32, + &D0F0x64_x4D.Value, + StdHeader + ); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU indirect register write + * + * + * + * @param[in] Address Register Address + * @param[in] Width Data width for write + * @param[in] Value Pointer to write value + * @param[in] StdHeader Pointer to standard configuration + */ + + +VOID +NbSmuIndirectWrite ( + IN UINT8 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (Width >= AccessS3SaveWidth8) { + SMU_INDIRECT_WRITE_DATA Data; + Data.Address = Address; + Data.Width = Width; + Data.Value = *((UINT32*) Value); + S3_SAVE_DISPATCH (StdHeader, S3DispatchGnbSmuIndirectWrite, sizeof (SMU_INDIRECT_WRITE_DATA), &Data); + Width = Width - (AccessS3SaveWidth8 - AccessWidth8); + } + NbSmuIndirectWriteEx (Address, Width, Value, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU Service request for S3 script + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Not used + * @param[in] Context Pointer to service request ID + */ + +VOID +NbSmuIndirectWriteS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ) +{ + SMU_INDIRECT_WRITE_DATA *Data; + Data = (SMU_INDIRECT_WRITE_DATA*) Context; + NbSmuIndirectWriteEx (Data->Address, Data->Width, &Data->Value, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU RAM mapped register write + * + * + * + * @param[in] Address Register Address + * @param[in] Value Data pointer for write + * @param[in] Count Number of registers to write + * @param[in] S3Save Save for S3 (True/False) + * @param[in] StdHeader Standard configuration header + */ + +VOID +NbSmuRcuRegisterWrite ( + IN UINT16 Address, + IN UINT32 *Value, + IN UINT32 Count, + IN BOOLEAN S3Save, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CurrentAddress; + CurrentAddress = Address; + NbSmuIndirectWrite ( + SMUx0B_ADDRESS, + S3Save ? AccessS3SaveWidth16 : AccessWidth16, + &Address, + StdHeader + ); + while (Count-- > 0) { + IDS_HDT_CONSOLE (NB_SMUREG_TRACE, " *WR SMUx0B:0x%x = 0x%x\n", CurrentAddress, *Value); + NbSmuIndirectWrite ( + SMUx05_ADDRESS, + S3Save ? AccessS3SaveWidth32 : AccessWidth32, + Value++, + StdHeader + ); + CurrentAddress += 4; + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU RAM mapped register read + * + * + * + * @param[in] Address Register Address + * @param[out] Value Pointer read value + * @param[in] Count Number of registers to read + * @param[in] StdHeader Pointer to standard configuration + */ + +VOID +NbSmuRcuRegisterRead ( + IN UINT16 Address, + OUT UINT32 *Value, + IN UINT32 Count, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + NbSmuIndirectWrite (SMUx0B_ADDRESS, AccessWidth16, &Address, StdHeader); + while (Count-- > 0) { + NbSmuIndirectRead (SMUx05_ADDRESS, AccessWidth32, Value++, StdHeader); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU Service request Ext + * + * + * @param[in] RequestId request ID + * @param[in] Flags Flags + * @param[in] StdHeader Standard configuration header + */ + +VOID +NbSmuServiceRequestEx ( + IN UINT8 RequestId, + IN UINT8 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + SMUx03_STRUCT SMUx03; + SMUx03.Value = 0; + SMUx03.Field.IntReq = 1; + SMUx03.Field.ServiceIndex = RequestId; + NbSmuIndirectWrite (SMUx03_ADDRESS, AccessWidth32, &SMUx03.Value, StdHeader); + if ((Flags & SMU_EXT_SERVICE_FLAGS_POLL_ACK) != 0) { + NbSmuIndirectPoll (SMUx03_ADDRESS, AccessWidth32, BIT1, BIT1, StdHeader); // Wait till IntAck + } + if ((Flags & SMU_EXT_SERVICE_FLAGS_POLL_DONE) != 0) { + NbSmuIndirectPoll (SMUx03_ADDRESS, AccessWidth32, BIT2, BIT2, StdHeader); // Wait till IntDone + } + SMUx03.Value = 0; // Clear IRQ register + NbSmuIndirectWrite (SMUx03_ADDRESS, AccessWidth32, &SMUx03.Value, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU Service request + * + * + * @param[in] RequestId request ID + * @param[in] S3Save Save for S3 (True/False) + * @param[in] StdHeader Standard configuration header + */ + +VOID +NbSmuServiceRequest ( + IN UINT8 RequestId, + IN BOOLEAN S3Save, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuServiceRequest Enter [0x%02x]\n", RequestId); + if (S3Save) { + S3_SAVE_DISPATCH (StdHeader, S3DispatchGnbSmuServiceRequest, sizeof (RequestId), &RequestId); + } + NbSmuServiceRequestEx ( + RequestId, + SMU_EXT_SERVICE_FLAGS_POLL_ACK | SMU_EXT_SERVICE_FLAGS_POLL_DONE, + StdHeader + ); + IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuServiceRequest Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU Service request for S3 script + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Not used + * @param[in] Context Pointer to service request ID + */ + +VOID +NbSmuServiceRequestS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ) +{ + NbSmuServiceRequest (*((UINT8*) Context), FALSE, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU Read FCR register + * + * + * @param[in] Address FCR Address + * @param[in] StdHeader Standard configuration header + */ + +UINT32 +NbSmuReadEfuse ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Value; + + NbSmuSrbmRegisterRead (Address, &Value, StdHeader); + Value = (Value >> 24) | (Value << 24) | ((Value >> 8) & 0xFF00) | ((Value << 8) & 0xFF0000); + return Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU Read arbitrary fuse field + * + * + * @param[in] Chain Address + * @param[in] Offset Offcet + * @param[in] Length Length + * @param[in] StdHeader Standard configuration header + */ + +UINT32 +NbSmuReadEfuseField ( + IN UINT8 Chain, + IN UINT16 Offset, + IN UINT8 Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Value; + UINT32 Result; + UINT32 Address; + UINT16 Shift; + ASSERT (Length <= 32); + ASSERT (Chain <= 0xff); + Shift = (Offset - (Offset & ~0x7)); + Address = 0xFE000000 | (Chain << 12) | (Offset >> 3); + Value = NbSmuReadEfuse (Address, StdHeader); + Result = Value >> Shift; + if ((Shift + Length) > 32) { + Value = NbSmuReadEfuse (Address + 1, StdHeader); + Result |= (Value << (32 - Shift)); + } + Result &= ((1 << Length) - 1); + return Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU SRBM (GMM) register read + * + * + * + * @param[in] Address Register Address + * @param[out] Value Pointer read value + * @param[in] StdHeader Pointer to standard configuration + */ + +VOID +NbSmuSrbmRegisterRead ( + IN UINT32 Address, + OUT UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + MBUS Mbus; + Mbus.SMUx0B_x8600.Value = (0x8650 << SMUx0B_x8600_MemAddr_7_0__OFFSET) | + (1 << SMUx0B_x8600_TransactionCount_OFFSET); + Mbus.SMUx0B_x8604.Value = (4 << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET); + Mbus.SMUx0B_x8608.Value = (UINT32) (3 << SMUx0B_x8608_Txn1Tsize_OFFSET); + Mbus.SMUx0B_x8600.Field.Txn1MBusAddr_7_0_ = Address & 0xff; + Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_15_8_ = (Address >> 8) & 0xff; + Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_23_16_ = (Address >> 16) & 0xff; + Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_31_24_ = (Address >> 24) & 0xff; + NbSmuRcuRegisterWrite (SMUx0B_x8600_ADDRESS, (UINT32*) &Mbus, 3, FALSE, StdHeader); + NbSmuServiceRequest (0x0B, FALSE, StdHeader); + NbSmuRcuRegisterRead (SMUx0B_x8650_ADDRESS, Value, 1, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU SRBM (GMM) register write + * + * + * + * @param[in] Address Register Address + * @param[in] Value Data pointer for write + * @param[in] S3Save Save for S3 (True/False) + * @param[in] StdHeader Standard configuration header + */ + +VOID +NbSmuSrbmRegisterWrite ( + IN UINT32 Address, + IN UINT32 *Value, + IN BOOLEAN S3Save, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + MBUS Mbus; + IDS_HDT_CONSOLE (NB_SMUREG_TRACE, " *WR SRBM (GMM):0x%x = 0x%x\n", Address, *Value); + Mbus.SMUx0B_x8600.Value = (0x8650 << SMUx0B_x8600_MemAddr_7_0__OFFSET) | + (1 << SMUx0B_x8600_TransactionCount_OFFSET); + Mbus.SMUx0B_x8604.Value = (4 << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET); + Mbus.SMUx0B_x8608.Value = (UINT32) (3 << SMUx0B_x8608_Txn1Tsize_OFFSET); + Mbus.SMUx0B_x8608.Field.Txn1Mode = 0x1; + Mbus.SMUx0B_x8600.Field.Txn1MBusAddr_7_0_ = Address & 0xff; + Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_15_8_ = (Address >> 8) & 0xff; + Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_23_16_ = (Address >> 16) & 0xff; + Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_31_24_ = (Address >> 24) & 0xff; + NbSmuRcuRegisterWrite (SMUx0B_x8600_ADDRESS, (UINT32*) &Mbus, 3, S3Save, StdHeader); + NbSmuRcuRegisterWrite (SMUx0B_x8650_ADDRESS, Value, 1, S3Save, StdHeader); + NbSmuServiceRequest (0x0B, S3Save, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU firmware download + * + * + * + * @param[in] StdHeader Pointer to Standard configuration + * @param[in] Firmware Pointer to SMU firmware header + * @retval AGESA_STATUS + */ + +VOID +NbSmuFirmwareDownload ( + IN SMU_FIRMWARE_HEADER *Firmware, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN Index; + SMUx01_STRUCT SMUx01; + NbSmuServiceRequestEx (0x10, SMU_EXT_SERVICE_FLAGS_POLL_ACK , StdHeader); + SMUx01.Value = (1 << SMUx01_RamSwitch_OFFSET) | (1 << SMUx01_VectorOverride_OFFSET); + NbSmuIndirectWrite (SMUx01_ADDRESS, AccessWidth32, &SMUx01.Value, StdHeader); + for (Index = 0; Index < Firmware->NumberOfBlock; Index++) { + NbSmuRcuRegisterWrite ( + (Firmware->BlockArray)[Index].Address, + (Firmware->BlockArray)[Index].Data, + (Firmware->BlockArray)[Index].Length, + FALSE, + StdHeader + ); + } + SMUx01.Value = (1 << SMUx01_Reset_OFFSET) | (1 << SMUx01_VectorOverride_OFFSET); + NbSmuIndirectWrite (SMUx01_ADDRESS, AccessWidth32, &SMUx01.Value, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU firmware revision + * + * + * + * @param[in] StdHeader Pointer to Standard configuration + * @retval Firmware revision info + */ + +SMU_FIRMWARE_REV +NbSmuFirmwareRevision ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + SMU_FIRMWARE_REV Revision; + UINT32 FmRev; + NbSmuRcuRegisterRead ( + 0x830C, + &FmRev, + 1, + StdHeader + ); + Revision.MajorRev = ((UINT16*)&FmRev) [1]; + Revision.MinorRev = ((UINT16*)&FmRev) [0]; + return Revision; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.h new file mode 100644 index 0000000000..a54b7e8939 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.h @@ -0,0 +1,185 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various NB initialization services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +#ifndef _NBSMULIB_H_ +#define _NBSMULIB_H_ + + +#define SMU_EXT_SERVICE_FLAGS_POLL_ACK 0x1 +#define SMU_EXT_SERVICE_FLAGS_POLL_DONE 0x2 +#define SMU_GMM_TO_FCR(GmmReg) ((GmmReg >> 2) | 0xFF300000) + +#pragma pack (push, 1) +/// SMU Register Entry +typedef struct { + UINT16 Reg; ///< Register address + UINT32 Value; ///< Register data +} SMU_REGISTER_ENTRY; + +/// SMU Firmware revision +typedef struct { + UINT16 MajorRev; ///< Major revision + UINT16 MinorRev; ///< Minor revision +} SMU_FIRMWARE_REV; + +/// Firmware block +typedef struct { + UINT16 Address; ///< Block Address + UINT16 Length; ///< Block length in DWORD + UINT32 *Data; ///< Pointer to data array +} SMU_FIRMWARE_BLOCK; + +/// Firmware header +typedef struct { + SMU_FIRMWARE_REV Revision; ///< Revision info + UINT16 NumberOfBlock; ///< Number of blocks + SMU_FIRMWARE_BLOCK *BlockArray; ///< Pointer to block definition array +} SMU_FIRMWARE_HEADER; + +/// SMU indirect register write data context +typedef struct { + UINT8 Address; ///< SMU indirect register address + ACCESS_WIDTH Width; ///< SMU indirect register width + UINT32 Value; ///< Value +} SMU_INDIRECT_WRITE_DATA; +#pragma pack (pop) + +VOID +NbSmuIndirectRead ( + IN UINT8 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NbSmuIndirectPoll ( + IN UINT8 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 CompateData, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NbSmuIndirectWrite ( + IN UINT8 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NbSmuRcuRegisterWrite ( + IN UINT16 Address, + IN UINT32 *Value, + IN UINT32 Count, + IN BOOLEAN S3Save, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NbSmuRcuRegisterRead ( + IN UINT16 Address, + OUT UINT32 *Value, + IN UINT32 Count, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NbSmuSrbmRegisterRead ( + IN UINT32 Address, + OUT UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NbSmuSrbmRegisterWrite ( + IN UINT32 Address, + IN UINT32 *Value, + IN BOOLEAN S3Save, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NbSmuServiceRequestEx ( + IN UINT8 RequestId, + IN UINT8 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NbSmuServiceRequest ( + IN UINT8 RequestId, + IN BOOLEAN S3Save, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NbSmuServiceRequestS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); + +UINT32 +NbSmuReadEfuse ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NbSmuFirmwareDownload ( + IN SMU_FIRMWARE_HEADER *Firmware, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +SMU_FIRMWARE_REV +NbSmuFirmwareRevision ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#define SMI_FIRMWARE_REVISION(x) ((x.MajorRev << 16) | x.MinorRev) +#endif |