summaryrefslogtreecommitdiff
path: root/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk
diff options
context:
space:
mode:
Diffstat (limited to 'src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk')
-rwxr-xr-xsrc/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/marc32_3.c577
-rwxr-xr-xsrc/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/mauc32_3.c352
-rwxr-xr-xsrc/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda2.c202
-rwxr-xr-xsrc/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda3.c256
-rwxr-xr-xsrc/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/mauda3.c255
-rwxr-xr-xsrc/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr2.c269
-rwxr-xr-xsrc/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr3.c424
-rwxr-xr-xsrc/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/maudr3.c255
-rwxr-xr-xsrc/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/marhy3.c561
-rwxr-xr-xsrc/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/mauhy3.c352
-rwxr-xr-xsrc/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/masNi3.c256
-rwxr-xr-xsrc/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/mauNi3.c255
-rwxr-xr-xsrc/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/ma.c136
13 files changed, 4150 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/marc32_3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/marc32_3.c
new file mode 100755
index 0000000000..73e3c06121
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/marc32_3.c
@@ -0,0 +1,577 @@
+/**
+ * @file
+ *
+ * marc32_3.c
+ *
+ * Memory Controller, registered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "ma.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_C32_MARC32_3_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA C32RDdr3CLKDis[] = {0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00};
+
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA C32RDdr3CKETri[] = {0x55, 0xAA};
+
+// 2 dimms per channel
+// Dimm 0: BP_MEMODTx[2,0]
+// Dimm 1: BP_MEMODTx[3,1]
+STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
+// 3 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[3,1]
+// Dimm 2: BP_MEMODTx[2]
+STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
+// 4 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[1]
+// Dimm 2: BP_MEMODTx[2]
+// Dimm 3: BP_MEMODTx[3]
+STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
+
+// BIOS must not tri-state chip select pin corresponding to the second chip
+// select of a single rank registered dimm
+STATIC CONST UINT8 ROMDATA C32RDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This is function sets the platform specific settings for C32 DDR3 L1 system
+ *
+ * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
+ * @param[in] SocketID Socket number
+ * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return AGESA_SUCCESS
+ * @return CurrentChannel->MemClkDisMap Points this pointer to C32 MemClkDis table
+ * @return CurrentChannel->ChipSelTriMap Points this pointer to C32 CS table
+ * @return CurrentChannel->CKETriMap Points this pointer to C32 ODT table
+ * @return CurrentChannel->ODTTriMap Points this pointer to C32 CKE table
+ * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
+ * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
+ * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
+ * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
+ * @return CurrentChannel->SlowMode Slow Mode
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgRC32_3 (
+ IN OUT MEM_DATA_STRUCT *MemData,
+ IN UINT8 SocketID,
+ IN OUT CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ //
+ // Address Timings and Drive Strengths for 1 DIMM per channel or 2 Dimms per Channel
+ //
+ // Code searches table for matching speed, then matches the current dimm
+ // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
+ //
+ // RC2/RC8 Value - This field id dependent upon the number of Registers on the Dimm, as indicated
+ // in SPD Byte 63.
+ // Bits 15-12 RC2 if One register
+ // Bits 11-8 RC8 if One register
+ // Bits 7-4 RC2 for more than one register
+ // Bits 3-0 RC8 for more than one register
+ //
+ // Frequency, Dimm Config ,
+ // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
+ //
+ STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = {
+ {DDR667_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+ 0x00000000, 0x4004, 2},
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x00000000, 0x0000, 1},
+ {DDR800_FREQUENCY, QR_DIMM1, \
+ 0x00000000, 0x0040, 1},
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x00000000, 0x4004, 2},
+ {DDR800_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \
+ 0x00000000, 0x4004, 2},
+ {DDR800_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \
+ 0x00000000, 0x4004, 2},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x003C3C3C, 0x0000,1},
+ {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+ 0x003C3C3C, 0x0040, 1},
+ {DDR1066_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+ 0x003A3C3A, 0x4004, 2},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x003A3A3A, 0x0000, 1},
+ {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+ 0x003A3A3A, 0x0040, 1},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x00383A38, 0x4040, 2},
+ };
+ //
+ // Address Timings and Drive Strengths for 3 DIMMs per channel
+ //
+ // Code searches table for matching speed, then matches the current dimm
+ // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
+ //
+ // RC2/RC8 Value - This field id dependent upon the number of Registers on the Dimm, as indicated
+ // in SPD Byte 63.
+ // Bits 15-12 RC2 if One register
+ // Bits 11-8 RC8 if One register
+ // Bits 7-4 RC2 for more than one register
+ // Bits 3-0 RC8 for more than one register
+ //
+ // Frequency, Dimm Config ,
+ // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
+ //
+ STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = {
+ {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x0000, 1},
+ {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x4040, 2},
+ {DDR667_FREQUENCY, QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x4004, 2},
+ {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00380038, 0x4004, 3},
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x0000, 1},
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x4040, 2},
+ {DDR800_FREQUENCY, QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x4004, 2},
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00380038, 0x4004, 3},
+ {DDR800_FREQUENCY, QR_DIMM1, \
+ 0x00000000, 0x0040, 1},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x003C3C3C, 0x0000, 1},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
+ 0x003A3C3A, 0x4040, 2},
+ {DDR1066_FREQUENCY, SR_DIMM0 + SR_DIMM1 + SR_DIMM2, \
+ 0x00373C37, 0x4040, 3},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x003A3A3A, 0x0000, 1},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
+ 0x00383A38, 0x4040, 2},
+ };
+
+ //
+ // DIMM ODT Pattern (1 or 2 DIMMs per channel)
+ //
+ // Dimm Config ,
+ // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
+ //
+ STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
+ {SR_DIMM0, \
+ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
+ {DR_DIMM0, \
+ 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
+ {QR_DIMM0, \
+ 0x00000000, 0x00000000, 0x00000505, 0x00000505, 1},
+ {SR_DIMM1, \
+ 0x00000000, 0x00000000, 0x00020000, 0x00000000, 1},
+ {DR_DIMM1, \
+ 0x00000000, 0x00000000, 0x02080000, 0x00000000, 1},
+ {QR_DIMM1, \
+ 0x00000000, 0x00000000, 0x0A0A0000, 0x0A0A0000, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x01010202, 0x00000000, 0x09030603, 0x00000000, 2},
+ {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
+ 0x01010A0A, 0x01010000, 0x01030E0B, 0x01090000, 2},
+ {QR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x05050202, 0x00000202, 0x0D070203, 0x00000206, 2},
+ {QR_DIMM0 + QR_DIMM1, \
+ 0x05050A0A, 0x05050A0A, 0x05070A0B, 0x050D0A0E, 2}
+ };
+ // DIMM ODT Pattern (3 DIMMs per channel)
+ //
+ // Dimm Config ,
+ // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
+ //
+ STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
+ {SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
+ {SR_DIMM0 + DR_DIMM0, \
+ 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
+ {QR_DIMM1, \
+ 0x00000000, 0x00000000, 0x080A0000, 0x020A0000, 1},
+ {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x04040000, 0x04040A0A, 0x04060000, 0x040C0A0E, 2},
+ {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
+ 0x01010A0A, 0x01010000, 0x01030A0B, 0x01090000, 2},
+ {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x05050E0E, 0x05050B0B, 0x05070E0F, 0x050D0B0F, 3}
+ };
+ //
+ // DIMM ODT Pattern (4 DIMMs per channel)
+ //
+ // Dimm Config ,
+ // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
+ //
+ STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg4DIMMsODT[] = {
+ {ANY_DIMM3, \
+ 0x00000000, 0x00000000, 0x00000000, 0x08080000, 1},
+ {ANY_DIMM2 + ANY_DIMM3, \
+ 0x00000000, 0x04040808, 0x00000000, 0x0C0C0C0C, 2},
+ {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
+ 0x0C0C0000, 0x06060A0A, 0x0E0E0000, 0x0E0E0E0E, 3},
+ {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
+ 0x0D0D0E0E, 0x07070B0B, 0x0F0F0F0F, 0x0F0F0F0F, 4}
+ };
+ //
+ // DIMM Write Leveling ODT Pattern 1 or 2 Dimms Per Channel
+ //
+ // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
+ //
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
+ {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
+ {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
+ {QR_DIMM0, {0x05, 0x00, 0x00, 0x00}, 1},
+ {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
+ {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
+ {QR_DIMM1, {0x00, 0x0A, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2},
+ {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+ {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+ {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
+ {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
+ {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2}
+ };
+ //
+ // DIMM Write Leveling ODT Pattern 3 Dimms Per Channel
+ //
+ // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
+ //
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
+ {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
+ {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1},
+ {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2},
+ {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+ {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3}
+ };
+ //
+ // DIMM Write Leveling ODT Pattern 4 Dimms Per Channel
+ //
+ // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
+ //
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = {
+ {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1},
+ {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2},
+ {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3},
+ {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4}
+ };
+
+
+ UINT16 i;
+ UINT16 j;
+ UINT8 MaxDimmPerCH;
+ UINT8 Dimms;
+ UINT16 Speed;
+ UINT16 DIMMRankType;
+ UINT16 _DIMMRankType;
+ UINT8 DimmTpMatch;
+ UINT32 AddrTmgCTL;
+ UINT32 DctOdcCtl;
+ UINT16 RC2RC8;
+ UINT32 PhyRODTCSLow;
+ UINT32 PhyRODTCSHigh;
+ UINT32 PhyWODTCSLow;
+ UINT32 PhyWODTCSHigh;
+ BOOLEAN SlowMode;
+ UINT8 PSCfgSize;
+ UINT8 PSCfgODTSize;
+ UINT8 PSCfgWlODTSize;
+ UINT8 PhyWLODT[4];
+
+ CONST ADV_R_PSCFG_ENTRY *PSCfgPtr;
+ CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
+ CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
+ UINT8 *DimmsPerChPtr;
+
+ ASSERT (MemData != NULL);
+ ASSERT (CurrentChannel != NULL);
+
+ AddrTmgCTL = 0;
+ DctOdcCtl = 0;
+ RC2RC8 = 0;
+ PhyRODTCSLow = 0;
+ PhyRODTCSHigh = 0;
+ PhyWODTCSLow = 0;
+ PhyWODTCSHigh = 0;
+ SlowMode = FALSE;
+ PhyWLODT[0] = 0x0F;
+ PhyWLODT[1] = 0x0F;
+ PhyWLODT[2] = 0x0F;
+ PhyWLODT[3] = 0x0F;
+ // Prepare inputs
+ Dimms = CurrentChannel->Dimms;
+ Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+ DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+ if (DimmsPerChPtr != NULL) {
+ MaxDimmPerCH = *DimmsPerChPtr;
+ } else {
+ MaxDimmPerCH = 2;
+ }
+
+ DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+ if (MaxDimmPerCH == 4) {
+ PSCfgPtr = NULL;
+ PSCfgSize = NULL;
+ PSCfgODTPtr = PSCfg4DIMMsODT;
+ PSCfgWlODTPtr = PSCfg4DIMMsWlODT;
+ PSCfgODTSize = sizeof (PSCfg4DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+ PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+ } else if (MaxDimmPerCH == 3) {
+ PSCfgPtr = PSCfg3DIMMs;
+ PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
+ PSCfgODTPtr = PSCfg3DIMMsODT;
+ PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
+ PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+ PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+ } else {
+ PSCfgPtr = PSCfg2DIMMs;
+ PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
+ PSCfgODTPtr = PSCfg2DIMMsODT;
+ PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
+ PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+ PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+ }
+
+ // AddrTmgCTL and DctOdcCtl
+ if (MaxDimmPerCH != 4) {
+ for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) {
+ if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgPtr->Dimms) {
+ AddrTmgCTL = PSCfgPtr->AddrTmg;
+ DctOdcCtl = 0x00223222;
+ RC2RC8 = PSCfgPtr->RC2RC8;
+ break;
+ }
+ }
+ }
+
+ //
+ // Overrides and/or exceptions
+ //
+ //
+ // Count slots with SR/DR poulated.
+ //
+ DimmTpMatch = 0;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ //
+ // DimmTpMatch is equal to the count of slot that have either an SR or DR
+ // installed.
+ //
+ if (MaxDimmPerCH == 4) {
+ //
+ // Any SR/DR in 4 DPCH
+ //
+ if (DimmTpMatch > 0) {
+ DctOdcCtl = 0x00223222;
+ if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) {
+ DctOdcCtl = 0x00113222;
+ }
+ }
+ //
+ // At Least 3 SR/DR in 4 DPCH
+ //
+ if (DimmTpMatch >= 3) {
+ AddrTmgCTL |= 0x002F0000;
+ }
+ // At Least 2 SR/DR in 4 DPCH
+ if (DimmTpMatch >= 2) {
+ RC2RC8 = 0x4040;
+ }
+ } else {
+ //
+ // Less than 4 DPCH
+ //
+ //
+ // Only 1 Dimm Populated and its a SR or DR OR
+ // 3 Dimms Populated and Frequency is 800 MHz
+ //
+ if (((Dimms == 1) && (DimmTpMatch == 1)) ||
+ ((Dimms == 3) && ((Speed == DDR800_FREQUENCY) ||
+ (Speed == DDR1066_FREQUENCY)))) {
+ DctOdcCtl = 0x00113222;
+ }
+ }
+
+ //RC2 and RC8
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution.
+ if (CurrentChannel->CtrlWrd02[j] > 0) {
+ if (CurrentChannel->CtrlWrd02[j] == 1) {
+ // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s).
+ CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F;
+ CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F;
+ } else {
+ // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s).
+ CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F;
+ CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F;
+ }
+ }
+ }
+
+ //Programmable ODT
+ for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) {
+ if (Dimms != PSCfgODTPtr->Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgODTPtr->Dimms) {
+ PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
+ PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
+ PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
+ PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
+ break;
+ }
+ }
+
+ //WLODT
+ for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
+ if (Dimms != PSCfgWlODTPtr->Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
+ PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
+ PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
+ PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
+ PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
+ break;
+ }
+ }
+
+ // Set ProcODT
+ DctOdcCtl |= 0x20000000;
+
+ CurrentChannel->MemClkDisMap = (UINT8 *) C32RDdr3CLKDis;
+ CurrentChannel->CKETriMap = (UINT8 *) C32RDdr3CKETri;
+ CurrentChannel->ChipSelTriMap = (UINT8 *) C32RDdr3CSTri;
+
+ switch (MaxDimmPerCH) {
+ case 3:
+ CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri3D;
+ break;
+ case 4:
+ CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri4D;
+ break;
+ default:
+ CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri2D; // Most conservative
+ }
+
+ CurrentChannel->DctAddrTmg = AddrTmgCTL;
+ CurrentChannel->DctOdcCtl = DctOdcCtl;
+ CurrentChannel->PhyRODTCSLow = PhyRODTCSLow;
+ CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
+ CurrentChannel->PhyWODTCSLow = PhyWODTCSLow;
+ CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
+ for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+ CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+ }
+ CurrentChannel->SlowMode = SlowMode;
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/mauc32_3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/mauc32_3.c
new file mode 100755
index 0000000000..720b3df559
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/mauc32_3.c
@@ -0,0 +1,352 @@
+/**
+ * @file
+ *
+ * mauc32_3.c
+ *
+ * Platform specific settings for C32 DDR3 unbuffered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_C32_MAUC32_3_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA C32UDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA C32UDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri2D[] = {0x01, 0x04, 0x02, 0x08};
+// 3 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[3,1]
+// Dimm 2: BP_MEMODTx[2]
+STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA C32UDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This is function sets the platform specific settings for C32 DDR3 unbuffered dimms
+ *
+ *
+ * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
+ * @param[in] SocketID Socket number
+ * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return AGESA_SUCCESS
+ * @return CurrentChannel->MemClkDisMap Points this pointer to C32 MemClkDis table
+ * @return CurrentChannel->ChipSelTriMap Points this pointer to C32 CS table
+ * @return CurrentChannel->CKETriMap Points this pointer to C32 ODT table
+ * @return CurrentChannel->ODTTriMap Points this pointer to C32 CKE table
+ * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
+ * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
+ * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
+ * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
+ * @return CurrentChannel->SlowMode Slow Mode
+ *
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgUC32_3 (
+ IN OUT MEM_DATA_STRUCT *MemData,
+ IN UINT8 SocketID,
+ IN OUT CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ STATIC CONST PSCFG_ENTRY PSCfg[] = {
+ {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
+ {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
+ {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
+ {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
+ };
+
+ STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
+ {SR_DIMM0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
+ {DR_DIMM0, 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
+ {SR_DIMM1, 0x00000000,0x00000000,0x00020000, 0x00000000, 1},
+ {DR_DIMM1, 0x00000000,0x00000000,0x02080000, 0x00000000, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x01010202,0x00000000,0x09030603, 0x00000000, 2},
+ };
+
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
+ {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
+ {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
+ {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
+ {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+ };
+
+ STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
+ {SR_DIMM2 + DR_DIMM2, 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
+ //{SR_DIMM0 + DR_DIMM0, 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
+ //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
+ };
+
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
+ {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
+ //{SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
+ //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
+ };
+
+ UINT16 i;
+ UINT16 j;
+ UINT8 MaxDimmPerCH;
+ UINT8 Loads;
+ UINT8 Dimms;
+ UINT16 Speed;
+ UINT16 DIMMRankType;
+ UINT16 _DIMMRankType;
+ UINT32 AddrTmgCTL;
+ UINT32 DctOdcCtl;
+ UINT32 PhyRODTCSLow;
+ UINT32 PhyRODTCSHigh;
+ UINT32 PhyWODTCSLow;
+ UINT32 PhyWODTCSHigh;
+ UINT8 PhyWLODT[4];
+ UINT8 PSCfgODTSize;
+ UINT8 PSCfgWlODTSize;
+ BOOLEAN SlowMode;
+ UINT8 DimmTpMatch;
+ CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
+ CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
+ UINT8 *DimmsPerChPtr;
+
+ ASSERT (MemData != NULL);
+ ASSERT (CurrentChannel != NULL);
+
+ AddrTmgCTL = 0;
+ DctOdcCtl = 0;
+ PhyRODTCSLow = 0;
+ PhyRODTCSHigh = 0;
+ PhyWODTCSLow = 0;
+ PhyWODTCSHigh = 0;
+ PhyWLODT[0] = 0x0F;
+ PhyWLODT[1] = 0x0F;
+ PhyWLODT[2] = 0x0F;
+ PhyWLODT[3] = 0x0F;
+
+ if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->RegDimmPresent) {
+ return AGESA_UNSUPPORTED;
+ }
+ // Prepare inputs
+
+ DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+ if (DimmsPerChPtr != NULL) {
+ MaxDimmPerCH = *DimmsPerChPtr;
+ } else {
+ MaxDimmPerCH = 2;
+ }
+
+ Loads = CurrentChannel->Loads;
+ Dimms = CurrentChannel->Dimms;
+ Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+ DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+ if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
+ SlowMode = TRUE; // 2T
+ } else {
+ SlowMode = FALSE; // 1T
+ }
+
+ for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
+ if (Speed == PSCfg[i].Speed) {
+ if (Loads <= PSCfg[i].Loads) {
+ AddrTmgCTL = PSCfg[i].AddrTmg;
+ DctOdcCtl = PSCfg[i].Odc;
+ break;
+ }
+ }
+ }
+
+ ASSERT (i < GET_SIZE_OF (PSCfg));
+
+ if (MaxDimmPerCH == 3) {
+ PSCfgODTPtr = PSCfg3DIMMsODT;
+ PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
+ PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+ PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+ } else {
+ PSCfgODTPtr = PSCfg2DIMMsODT;
+ PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
+ PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+ PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+ }
+
+ // Programmable ODT
+ for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) {
+ if (Dimms != PSCfgODTPtr->Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgODTPtr->Dimms) {
+ PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
+ PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
+ PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
+ PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
+ break;
+ }
+ }
+
+ // WL ODT
+ for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
+ if (Dimms != PSCfgWlODTPtr->Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
+ PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
+ PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
+ PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
+ PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
+ break;
+ }
+ }
+
+ //
+ // Overrides and/or exceptions
+ //
+ if (Dimms == 1) {
+ if (Loads >= 16) {
+ if (Speed == DDR800_FREQUENCY) {
+ AddrTmgCTL = 0x003B0000;
+ } else if (Speed == DDR1066_FREQUENCY) {
+ AddrTmgCTL = 0x00380000;
+ } else if (Speed == DDR1333_FREQUENCY) {
+ AddrTmgCTL = 0x00360000;
+ } else {
+ AddrTmgCTL = 0x00340000;
+ SlowMode = TRUE;
+ }
+ } else {
+ AddrTmgCTL = 0;
+ }
+ DctOdcCtl = 0x20113222;
+ }
+
+ CurrentChannel->MemClkDisMap = (UINT8 *) C32UDdr3CLKDis;
+ CurrentChannel->CKETriMap = (UINT8 *) C32UDdr3CKETri;
+ CurrentChannel->ChipSelTriMap = (UINT8 *) C32UDdr3CSTri;
+
+ switch (MaxDimmPerCH) {
+ case 3:
+ CurrentChannel->ODTTriMap = (UINT8 *) C32UDdr3ODTTri3D;
+ break;
+ default:
+ CurrentChannel->ODTTriMap = (UINT8 *) C32UDdr3ODTTri2D; // Most conservative
+ }
+
+ CurrentChannel->DctEccDqsLike = 0x0403;
+ CurrentChannel->DctEccDqsScale = 0x70;
+ CurrentChannel->DctAddrTmg = AddrTmgCTL;
+ CurrentChannel->DctOdcCtl = DctOdcCtl;
+ CurrentChannel->PhyRODTCSLow = PhyRODTCSLow;
+ CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
+ CurrentChannel->PhyWODTCSLow = PhyWODTCSLow;
+ CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
+ for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+ CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+ }
+ CurrentChannel->SlowMode = SlowMode;
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda2.c
new file mode 100755
index 0000000000..1d19acb7d2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda2.c
@@ -0,0 +1,202 @@
+/*
+ * @file
+ *
+ * masda2.c
+ *
+ * Platform specific settings for DA DDR2 SO-dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/* This file contains routine that add platform specific support S1g3 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_DA_MASDA2_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA DASDdr2CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA DASDdr2CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA DASDdr2ODTTri[] = {0x01, 0x04, 0x02, 0x08};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA DASDdr2CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This is function sets the platform specific settings for DA DDR2 SO-dimms
+ *
+ *
+ * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
+ * @param[in] SocketID Socket number
+ * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return AGESA_SUCCESS
+ * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
+ * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
+ * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
+ * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
+ * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
+ * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
+ * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
+ * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
+ * @return CurrentChannel->SlowMode Slow Mode
+ *
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgSDA2 (
+ IN OUT MEM_DATA_STRUCT *MemData,
+ IN UINT8 SocketID,
+ IN OUT CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ STATIC CONST PSCFG_ENTRY PSCfg[] = {
+ {DDR400_FREQUENCY, 0xFF, 0x002F2F2F, 0x10111222},
+ {DDR533_FREQUENCY, 0xFF, 0x002F2F2F, 0x10111222},
+ {DDR667_FREQUENCY, 0xFF, 0x002A2A2A, 0x10111222},
+ {DDR800_FREQUENCY, 0xFF, 0x002A2A2A, 0x10111222},
+ };
+
+ UINT16 i;
+ UINT8 Loads;
+ UINT8 Ranks;
+ UINT16 Speed;
+ UINT32 AddrTmgCTL;
+ UINT32 DctOdcCtl;
+ BOOLEAN SlowMode;
+
+ ASSERT (MemData != 0);
+ ASSERT (CurrentChannel != 0);
+
+ AddrTmgCTL = 0;
+ DctOdcCtl = 0;
+
+ if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->TechType != DDR2_TECHNOLOGY) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
+ return AGESA_UNSUPPORTED;
+ }
+
+ // Prepare inputs
+ Loads = CurrentChannel->Loads;
+ Ranks = CurrentChannel->Ranks;
+ Speed = CurrentChannel->DCTPtr->Timings.Speed;
+ SlowMode = FALSE; // 1T
+
+ for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
+ if (Speed == PSCfg[i].Speed) {
+ if (Loads <= PSCfg[i].Loads) {
+ AddrTmgCTL = PSCfg[i].AddrTmg;
+ DctOdcCtl = PSCfg[i].Odc;
+ break;
+ }
+ }
+ }
+ ASSERT (i < GET_SIZE_OF (PSCfg));
+
+ //
+ // Overrides and/or exceptions
+ //
+ if (Loads == 16) {
+ if ((Speed == DDR533_FREQUENCY) && (Ranks == 2)) {
+ AddrTmgCTL = 0x002C2C2C;
+ } else if ((Speed == DDR667_FREQUENCY) && (Ranks == 1)) {
+ AddrTmgCTL = 0x00272727;
+ } else if ((Speed == DDR667_FREQUENCY) && (Ranks == 2)) {
+ AddrTmgCTL = 0x00002828;
+ SlowMode = TRUE; // 2T
+ } else if ((Speed == DDR800_FREQUENCY) && (Ranks == 1)) {
+ AddrTmgCTL = 0x00292929;
+ } else if ((Speed == DDR800_FREQUENCY) && (Ranks == 2)) {
+ AddrTmgCTL = 0x00002F2F;
+ SlowMode = TRUE; // 2T
+ }
+ }
+ CurrentChannel->MemClkDisMap = (UINT8 *) DASDdr2CLKDis;
+ CurrentChannel->CKETriMap = (UINT8 *) DASDdr2CKETri;
+ CurrentChannel->ODTTriMap = (UINT8 *) DASDdr2ODTTri;
+ CurrentChannel->ChipSelTriMap = (UINT8 *) DASDdr2CSTri;
+ CurrentChannel->DctAddrTmg = AddrTmgCTL;
+ CurrentChannel->DctOdcCtl = DctOdcCtl;
+ CurrentChannel->SlowMode = SlowMode;
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda3.c
new file mode 100755
index 0000000000..18faf2653a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda3.c
@@ -0,0 +1,256 @@
+/*
+ * @file
+ *
+ * masda3.c
+ *
+ * Platform specific settings for DA DDR3 SO-dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/* This file contains routine that add platform specific support S1g4 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "ma.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_DA_MASDA3_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA DASDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA DASDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA DASDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA DASDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This is function sets the platform specific settings for DA DDR3 SO-dimms
+ *
+ *
+ * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
+ * @param[in] SocketID Socket number
+ * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return AGESA_SUCCESS
+ * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
+ * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
+ * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
+ * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
+ * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
+ * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
+ * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
+ * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
+ * @return CurrentChannel->SlowMode Slow Mode
+ *
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgSDA3 (
+ IN OUT MEM_DATA_STRUCT *MemData,
+ IN UINT8 SocketID,
+ IN OUT CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ STATIC CONST PSCFG_ENTRY PSCfg[] = {
+ {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222},
+ {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222},
+ {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222},
+ };
+
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
+ {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
+ {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+ };
+
+ UINT16 i;
+ UINT16 j;
+ UINT8 Loads;
+ UINT8 Dimms;
+ UINT16 Speed;
+ UINT32 AddrTmgCTL;
+ UINT32 DctOdcCtl;
+ UINT8 PhyWLODT[4];
+ BOOLEAN SlowMode;
+ UINT8 MaxDimmPerCH;
+ UINT8 *DimmsPerChPtr;
+ UINT16 DIMMRankType;
+ UINT16 _DIMMRankType;
+ UINT8 DimmTpMatch;
+
+ ASSERT (MemData != 0);
+ ASSERT (CurrentChannel != 0);
+
+ AddrTmgCTL = 0;
+ DctOdcCtl = 0;
+ PhyWLODT[0] = 0x0F;
+ PhyWLODT[1] = 0x0F;
+ PhyWLODT[2] = 0x0F;
+ PhyWLODT[3] = 0x0F;
+ SlowMode = FALSE; // 1T
+ if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
+ return AGESA_UNSUPPORTED;
+ }
+ // Prepare inputs
+ Loads = CurrentChannel->Loads;
+ Dimms = CurrentChannel->Dimms;
+ Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+ DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+ DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+ if (DimmsPerChPtr != NULL) {
+ MaxDimmPerCH = *DimmsPerChPtr;
+ } else {
+ MaxDimmPerCH = 2;
+ }
+
+ for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
+ if (Speed == PSCfg[i].Speed) {
+ if (Loads <= PSCfg[i].Loads) {
+ AddrTmgCTL = PSCfg[i].AddrTmg;
+ DctOdcCtl = PSCfg[i].Odc;
+ break;
+ }
+ }
+ }
+
+ // WL ODT
+ for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
+ if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
+ PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
+ PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
+ PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
+ PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
+ break;
+ }
+ }
+
+ //
+ // Overrides and/or exceptions
+ //
+ if (MaxDimmPerCH == 2) {
+ if (Dimms == 2) {
+ DctOdcCtl = 0x20223323;
+ SlowMode = TRUE;
+ if (Speed == DDR800_FREQUENCY) {
+ AddrTmgCTL = 0x00000039;
+ } else if (Speed == DDR1066_FREQUENCY) {
+ AddrTmgCTL = 0x00000037;
+ }
+ } else {
+ DctOdcCtl = 0x20113222;
+ }
+ } else {
+ if (CurrentChannel->DimmSRPresent != 0) {
+ PhyWLODT[0] = 1;
+ } else if (CurrentChannel->DimmDrPresent != 0) {
+ PhyWLODT[0] = 4;
+ }
+ }
+
+ CurrentChannel->MemClkDisMap = (UINT8 *) DASDdr3CLKDis;
+ CurrentChannel->CKETriMap = (UINT8 *) DASDdr3CKETri;
+ CurrentChannel->ODTTriMap = (UINT8 *) DASDdr3ODTTri;
+ CurrentChannel->ChipSelTriMap = (UINT8 *) DASDdr3CSTri;
+
+ CurrentChannel->DctAddrTmg = AddrTmgCTL;
+ CurrentChannel->DctOdcCtl = DctOdcCtl;
+ for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+ CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+ }
+ CurrentChannel->SlowMode = SlowMode;
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/mauda3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/mauda3.c
new file mode 100755
index 0000000000..046e9b2a19
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/mauda3.c
@@ -0,0 +1,255 @@
+/*
+ * @file
+ *
+ * mauda3.c
+ *
+ * Platform specific settings for DA DDR3 unbuffered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_DA_MAUDA3_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA DAUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA DAUDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA DAUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA DAUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This is function sets the platform specific settings for DA DDR3 Unbuffered dimms
+ *
+ *
+ * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
+ * @param[in] SocketID Socket number
+ * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return AGESA_SUCCESS
+ * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
+ * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
+ * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
+ * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
+ * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
+ * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
+ * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
+ * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
+ * @return CurrentChannel->SlowMode Slow Mode
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgUDA3 (
+ IN OUT MEM_DATA_STRUCT *MemData,
+ IN UINT8 SocketID,
+ IN OUT CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
+ {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
+ {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
+ {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
+ {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
+ };
+ STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
+ {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
+ {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
+ {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
+ {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
+ };
+
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
+ {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
+ {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
+ {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
+ {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+ };
+
+ UINT16 i;
+ UINT16 j;
+ UINT8 Loads;
+ UINT8 Dimms;
+ UINT16 Speed;
+ UINT16 DIMMRankType;
+ UINT16 _DIMMRankType;
+ UINT32 AddrTmgCTL;
+ UINT32 DctOdcCtl;
+ UINT8 PhyWLODT[4];
+ BOOLEAN SlowMode;
+ UINT8 DimmTpMatch;
+
+ ASSERT (MemData != 0);
+ ASSERT (CurrentChannel != 0);
+
+ AddrTmgCTL = 0;
+ DctOdcCtl = 0;
+ PhyWLODT[0] = 0x0F;
+ PhyWLODT[1] = 0x0F;
+ PhyWLODT[2] = 0x0F;
+ PhyWLODT[3] = 0x0F;
+
+ if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+ return AGESA_UNSUPPORTED;
+ }
+ if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
+ return AGESA_UNSUPPORTED;
+ }
+ // Prepare inputs
+ Loads = CurrentChannel->Loads;
+ Dimms = CurrentChannel->Dimms;
+ Speed = CurrentChannel->DCTPtr->Timings.Speed;
+ DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+ if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
+ SlowMode = TRUE; // 2T
+ } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
+ SlowMode = TRUE; // 2T
+ } else {
+ SlowMode = FALSE; // 1T
+ }
+
+ if (Dimms == 1) {
+ for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
+ if (Speed == PSCfg1Dimm[i].Speed) {
+ if (Loads >= PSCfg1Dimm[i].Loads) {
+ AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
+ DctOdcCtl = PSCfg1Dimm[i].Odc;
+ } else {
+ DctOdcCtl = 0x20113222;
+ }
+ break;
+ }
+ }
+ ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
+ } else {
+ for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
+ if (Speed == PSCfg2Dimm[i].Speed) {
+ if (Loads <= PSCfg2Dimm[i].Loads) {
+ AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
+ DctOdcCtl = PSCfg2Dimm[i].Odc;
+ break;
+ }
+ }
+ }
+ ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
+ }
+
+ // WL ODT
+ for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
+ if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
+ PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
+ PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
+ PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
+ PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
+ break;
+ }
+ }
+
+ CurrentChannel->MemClkDisMap = (UINT8 *) DAUDdr3CLKDis;
+ CurrentChannel->CKETriMap = (UINT8 *) DAUDdr3CKETri;
+ CurrentChannel->ODTTriMap = (UINT8 *) DAUDdr3ODTTri;
+ CurrentChannel->ChipSelTriMap = (UINT8 *) DAUDdr3CSTri;
+
+ CurrentChannel->DctEccDqsLike = 0x0403;
+ CurrentChannel->DctEccDqsScale = 0x70;
+ CurrentChannel->DctAddrTmg = AddrTmgCTL;
+ CurrentChannel->DctOdcCtl = DctOdcCtl;
+ for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+ CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+ }
+ CurrentChannel->SlowMode = SlowMode;
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr2.c
new file mode 100755
index 0000000000..67b1263e02
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr2.c
@@ -0,0 +1,269 @@
+/**
+ * @file
+ *
+ * mardr2.c
+ *
+ * Platform specific settings for DR DDR2 L1 system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "ma.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_DR_MARDR2_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA DrRDdr2CLKDis[] = {0x00, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0x00};
+
+// Chip select 0, 1, 4, 5 maps to M[B,A]_CKE[0]
+// Chip select 2, 3, 6, 7 maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA DrRDdr2CKETri[] = {0x33, 0xCC};
+
+// 2 dimms per channel
+// Dimm 0: BP_MEMODTx[2,0]
+// Dimm 1: BP_MEMODTx[3,1]
+STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
+// 3 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[3,1]
+// Dimm 2: BP_MEMODTx[2]
+STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
+// 4 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[1]
+// Dimm 2: BP_MEMODTx[2]
+// Dimm 3: BP_MEMODTx[3]
+STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
+
+// BIOS must not tri-state chip select pin corresponding to the second chip
+// select of a single rank registered dimm
+STATIC CONST UINT8 ROMDATA DrRDdr2CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This is function sets the platform specific settings for DR DDR2 L1 system
+ *
+ * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
+ * @param[in] SocketID Socket number
+ * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return AGESA_SUCCESS
+ * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
+ * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
+ * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
+ * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
+ * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
+ * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
+ * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
+ * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
+ * @return CurrentChannel->SlowMode Slow Mode
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgRDr2 (
+ IN OUT MEM_DATA_STRUCT *MemData,
+ IN UINT8 SocketID,
+ IN OUT CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ STATIC CONST ADV_PSCFG_ENTRY PSCfg4D[] = {
+ {ANY_, ANY_, 0x00000000, 0x00111222, 1},
+ {ANY_, ANY_, 0x00370000, 0x00111222, 2}
+ };
+
+ STATIC CONST ADV_PSCFG_ENTRY PSCfg8D[] = {
+ {ANY_, ANY_, 0x00000000, 0x00111222, 1},
+ {ANY_, ANY_, 0x00370000, 0x00111222, 2},
+ {ANY_, ANY_, 0x002F0000, 0x00111222, ANY_}
+ };
+
+ CONST ADV_PSCFG_ENTRY *PSCfgPtr;
+ UINT16 i;
+ UINT8 MaxDimmPerCH;
+ UINT16 TabSize;
+ UINT8 Loads;
+ UINT8 Dimms;
+ UINT16 Speed;
+ UINT32 AddrTmgCTL;
+ UINT32 DctOdcCtl;
+ UINT16 QRPresent;
+ UINT16 DRx4Present;
+ BOOLEAN SlowMode;
+ UINT8 *DimmsPerChPtr;
+
+ ASSERT (MemData != 0);
+ ASSERT (CurrentChannel != 0);
+
+ if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->TechType != DDR2_TECHNOLOGY) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->RegDimmPresent != CurrentChannel->ChDimmValid) {
+ return AGESA_UNSUPPORTED;
+ }
+
+ // Prepare inputs
+ Loads = CurrentChannel->Loads;
+ Dimms = CurrentChannel->Dimms;
+ Speed = CurrentChannel->DCTPtr->Timings.Speed;
+ DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+ if (DimmsPerChPtr != NULL) {
+ MaxDimmPerCH = *DimmsPerChPtr;
+ } else {
+ MaxDimmPerCH = 2;
+ }
+ QRPresent = CurrentChannel->DimmQrPresent;
+ DRx4Present = CurrentChannel->DimmDrPresent & CurrentChannel->Dimmx4Present;
+ if (QRPresent) {
+ Dimms = (Dimms + 1) / 2;
+ }
+
+ // Table look up
+ if (MaxDimmPerCH <= 2) {
+ PSCfgPtr = PSCfg4D;
+ TabSize = GET_SIZE_OF (PSCfg4D);
+ } else {
+ PSCfgPtr = PSCfg8D;
+ TabSize = GET_SIZE_OF (PSCfg8D);
+ }
+ DctOdcCtl = 0;
+ AddrTmgCTL = 0;
+ for (i = 0; i < TabSize; i++) {
+ if ((PSCfgPtr[i].Dimms == ANY_) || (PSCfgPtr[i].Dimms == Dimms)) {
+ if ((PSCfgPtr[i].Speed == ANY_) || (PSCfgPtr[i].Speed == Speed)) {
+ if ((PSCfgPtr[i].Loads == ANY_) || (PSCfgPtr[i].Loads >= Loads)) {
+ AddrTmgCTL = PSCfgPtr[i].AddrTmg;
+ DctOdcCtl = PSCfgPtr[i].Odc;
+ break;
+ }
+ }
+ }
+ }
+ ASSERT (i == TabSize);
+ SlowMode = FALSE; // 1T
+
+ //
+ // Overrides and/or exceptions
+ //
+
+ if (QRPresent == 0x55) {
+ // QR for 4DIMM case only
+ AddrTmgCTL = 0x002F0000;
+ if (Speed >= DDR667_FREQUENCY) {
+ DctOdcCtl = 0x00331222;
+ }
+ }
+
+ if (Speed >= DDR667_FREQUENCY) {
+ if ((QRPresent != 0) || (DRx4Present != 0)) {
+ AddrTmgCTL |= 0x00002F00;
+ }
+ if (Dimms >= 3) {
+ AddrTmgCTL |= 0x0000002F;
+ }
+ if (Dimms == 3 || Dimms == 4) {
+ DctOdcCtl = 0x00331222;
+ }
+ }
+
+ // Adjust Processor ODT
+ if (Dimms == 1) {
+ DctOdcCtl |= 0x20000000; // 75ohms
+ } else {
+ DctOdcCtl |= 0x10000000; // 150ohms
+ }
+
+ CurrentChannel->MemClkDisMap = (UINT8 *) DrRDdr2CLKDis;
+ CurrentChannel->CKETriMap = (UINT8 *) DrRDdr2CKETri;
+ CurrentChannel->ChipSelTriMap = (UINT8 *) DrRDdr2CSTri;
+
+ switch (MaxDimmPerCH) {
+ case 3:
+ CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri3D;
+ break;
+ case 4:
+ CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri4D;
+ break;
+ default:
+ CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri2D;
+ }
+
+ CurrentChannel->DctEccDqsLike = 0x0504;
+ CurrentChannel->DctEccDqsScale = 0;
+ CurrentChannel->DctAddrTmg = AddrTmgCTL;
+ CurrentChannel->DctOdcCtl = DctOdcCtl;
+ CurrentChannel->SlowMode = SlowMode;
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr3.c
new file mode 100755
index 0000000000..d6addd6787
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr3.c
@@ -0,0 +1,424 @@
+/**
+ * @file
+ *
+ * mardr3.c
+ *
+ * Memory Controller, registered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "ma.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_DR_MARDR3_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA DrRDdr3CLKDis[] = {0x00, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0x00};
+
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA DrRDdr3CKETri[] = {0x55, 0xAA};
+
+// 2 dimms per channel
+// Dimm 0: BP_MEMODTx[2,0]
+// Dimm 1: BP_MEMODTx[3,1]
+STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
+// 3 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[3,1]
+// Dimm 2: BP_MEMODTx[2]
+STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
+// 4 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[1]
+// Dimm 2: BP_MEMODTx[2]
+// Dimm 3: BP_MEMODTx[3]
+STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
+
+// BIOS must not tri-state chip select pin corresponding to the second chip
+// select of a single rank registered dimm
+STATIC CONST UINT8 ROMDATA DrRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This is function sets the platform specific settings for DR DDR3 L1 system
+ *
+ * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
+ * @param[in] SocketID Socket number
+ * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return AGESA_SUCCESS
+ * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
+ * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
+ * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
+ * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
+ * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
+ * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
+ * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
+ * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
+ * @return CurrentChannel->SlowMode Slow Mode
+ *
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgRDr3 (
+ IN OUT MEM_DATA_STRUCT *MemData,
+ IN UINT8 SocketID,
+ IN OUT CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = {
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x00000000, 0x0000, 1},
+ {DDR800_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+ 0x00000000, 0x0040, 1},
+ {DDR800_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+ 0x00000000, 0x4004, 2},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x003C3C3C, 0x0000,1},
+ {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+ 0x003C3C3C, 0x0040, 1},
+ {DDR1066_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+ 0x003A3C3A, 0x4004, 2},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x003A3A3A, 0x0000, 1},
+ {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+ 0x003A3A3A, 0x0040, 1},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x00383A38, 0x4040, 2},
+ {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+ 0x00383A38, 0x4004, 2},
+ {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x00373937, 0x0000, 1},
+ {DDR1600_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+ 0x00373937, 0x0040, 1},
+ {DDR1600_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+ 0x00353935, 0x4004, 2}
+ };
+
+ STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = {
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x0000, 1},
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x4040, 2},
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00380038, 0x4004, 3},
+ {DDR800_FREQUENCY, QR_DIMM1, \
+ 0x00000000, 0x0040, 1},
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x4004, 2},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x003C3C3C, 0x0000, 1},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x003A3C3A, 0x4040, 2},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00373C37, 0x4040, 3},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00373C37, 0x4004, 3},
+ {DDR1066_FREQUENCY, QR_DIMM1, \
+ 0x003C3C3C, 0x0040, 1},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x003A3C3A, 0x4004, 2},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x003A3A3A, 0x0000, 1},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00383A38, 0x4040, 2},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00343A34, 0x4004, 3},
+ {DDR1333_FREQUENCY, QR_DIMM1, \
+ 0x003A3A3A, 0x0040, 1},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00383A38, 0x4004, 2},
+ {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00393939, 0x0000, 1},
+ {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00363936, 0x4040, 2},
+ {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00303930, 0x4004, 3},
+ {DDR1600_FREQUENCY, QR_DIMM1, \
+ 0x00393939, 0x0040, 1},
+ {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00363936, 0x4004, 2}
+ };
+
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
+ {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
+ {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
+ {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
+ {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
+ {QR_DIMM1, {0x00, 0x0A, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2},
+ {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+ {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+ {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
+ {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
+ {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2}
+ };
+
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
+ {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
+ {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1},
+ {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2},
+ {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+ {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3}
+ };
+
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = {
+ {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1},
+ {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2},
+ {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3},
+ {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4}
+ };
+ UINT16 i;
+ UINT16 j;
+ UINT8 MaxDimmPerCH;
+ UINT8 Dimms;
+ UINT16 Speed;
+ UINT16 DIMMRankType;
+ UINT16 _DIMMRankType;
+ UINT8 DimmTpMatch;
+ UINT32 AddrTmgCTL;
+ UINT32 DctOdcCtl;
+ UINT16 RC2RC8;
+ BOOLEAN SlowMode;
+ UINT8 PSCfgSize;
+ UINT8 PSCfgWlODTSize;
+ UINT8 PhyWLODT[4];
+ CONST ADV_R_PSCFG_ENTRY *PSCfgPtr;
+ CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
+ UINT8 *DimmsPerChPtr;
+
+ AddrTmgCTL = 0;
+ DctOdcCtl = 0;
+ RC2RC8 = 0;
+ SlowMode = FALSE;
+ ASSERT (MemData != NULL);
+ PhyWLODT[0] = 0x0F;
+ PhyWLODT[1] = 0x0F;
+ PhyWLODT[2] = 0x0F;
+ PhyWLODT[3] = 0x0F;
+ if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->RegDimmPresent != CurrentChannel->ChDimmValid) {
+ return AGESA_UNSUPPORTED;
+ }
+ // Prepare inputs
+ Dimms = CurrentChannel->Dimms;
+ Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+ DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+ if (DimmsPerChPtr != NULL) {
+ MaxDimmPerCH = *DimmsPerChPtr;
+ } else {
+ MaxDimmPerCH = 2;
+ }
+
+ DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+ if (MaxDimmPerCH == 4) {
+ PSCfgPtr = NULL;
+ PSCfgSize = NULL;
+ PSCfgWlODTPtr = PSCfg4DIMMsWlODT;
+ PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+ } else if (MaxDimmPerCH == 3) {
+ PSCfgPtr = PSCfg3DIMMs;
+ PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
+ PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
+ PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+ } else {
+ PSCfgPtr = PSCfg2DIMMs;
+ PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
+ PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
+ PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+ }
+
+ // AddrTmgCTL and DctOdcCtl
+ if (MaxDimmPerCH != 4) {
+ for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) {
+ if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgPtr->Dimms) {
+ AddrTmgCTL = PSCfgPtr->AddrTmg;
+ DctOdcCtl = 0x00223222;
+ RC2RC8 = PSCfgPtr->RC2RC8;
+ break;
+ }
+ }
+ }
+
+ //
+ // Overrides and/or exceptions
+ //
+ DimmTpMatch = 0;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (MaxDimmPerCH == 4) {
+ if (DimmTpMatch > 0) {
+ DctOdcCtl = 0x00223222;
+ if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) {
+ DctOdcCtl = 0x00113222;
+ }
+ }
+ if (DimmTpMatch >= 3) {
+ AddrTmgCTL |= 0x002F0000;
+ }
+ if (DimmTpMatch >= 2) {
+ RC2RC8 = 0x4040;
+ }
+ } else {
+ if ((Dimms == 1) && (DimmTpMatch == 1)) {
+ DctOdcCtl = 0x00113222;
+ }
+ }
+
+ //RC2 and RC8
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution.
+ if (CurrentChannel->CtrlWrd02[j] > 0) {
+ if (CurrentChannel->CtrlWrd02[j] == 1) {
+ // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s).
+ CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F;
+ CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F;
+ } else {
+ // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s).
+ CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F;
+ CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F;
+ }
+ }
+ }
+
+
+ //WLODT
+ for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
+ if (Dimms != PSCfgWlODTPtr->Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
+ PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
+ PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
+ PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
+ PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
+ break;
+ }
+ }
+
+ // Set ProcODT
+ DctOdcCtl |= 0x20000000;
+
+ CurrentChannel->MemClkDisMap = (UINT8 *) DrRDdr3CLKDis;
+ CurrentChannel->CKETriMap = (UINT8 *) DrRDdr3CKETri;
+ CurrentChannel->ChipSelTriMap = (UINT8 *) DrRDdr3CSTri;
+
+ switch (MaxDimmPerCH) {
+ case 3:
+ CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri3D;
+ break;
+ case 4:
+ CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri4D;
+ break;
+ default:
+ CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri2D;
+ }
+
+ CurrentChannel->DctAddrTmg = AddrTmgCTL;
+ CurrentChannel->DctOdcCtl = DctOdcCtl;
+ for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+ CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+ }
+ CurrentChannel->SlowMode = SlowMode;
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/maudr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/maudr3.c
new file mode 100755
index 0000000000..4e4fca27d5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/maudr3.c
@@ -0,0 +1,255 @@
+/*
+ * @file
+ *
+ * maudr3.c
+ *
+ * Platform specific settings for DR DDR3 unbuffered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_DR_MAUDR3_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA DrUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA DrUDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA DrUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA DrUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This is function sets the platform specific settings for DR DDR3 Unbuffered dimms
+ *
+ *
+ * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
+ * @param[in] SocketID Socket number
+ * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return AGESA_SUCCESS
+ * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
+ * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
+ * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
+ * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
+ * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
+ * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
+ * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
+ * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
+ * @return CurrentChannel->SlowMode Slow Mode
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgUDr3 (
+ IN OUT MEM_DATA_STRUCT *MemData,
+ IN UINT8 SocketID,
+ IN OUT CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
+ {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
+ {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
+ {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
+ {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
+ };
+ STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
+ {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
+ {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
+ {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
+ {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
+ };
+
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
+ {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
+ {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
+ {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
+ {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+ };
+
+ UINT16 i;
+ UINT16 j;
+ UINT8 Loads;
+ UINT8 Dimms;
+ UINT16 Speed;
+ UINT16 DIMMRankType;
+ UINT16 _DIMMRankType;
+ UINT32 AddrTmgCTL;
+ UINT32 DctOdcCtl;
+ UINT8 PhyWLODT[4];
+ BOOLEAN SlowMode;
+ UINT8 DimmTpMatch;
+
+ ASSERT (MemData != 0);
+ ASSERT (CurrentChannel != 0);
+ AddrTmgCTL = 0;
+ DctOdcCtl = 0;
+ PhyWLODT[0] = 0x0F;
+ PhyWLODT[1] = 0x0F;
+ PhyWLODT[2] = 0x0F;
+ PhyWLODT[3] = 0x0F;
+
+ if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->RegDimmPresent != 0) {
+ return AGESA_UNSUPPORTED;
+ }
+ // Prepare inputs
+ Loads = CurrentChannel->Loads;
+ Dimms = CurrentChannel->Dimms;
+ Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+ DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+ if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
+ SlowMode = TRUE; // 2T
+ } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
+ SlowMode = TRUE; // 2T
+ } else {
+ SlowMode = FALSE; // 1T
+ }
+
+ if (Dimms == 1) {
+ for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
+ if (Speed == PSCfg1Dimm[i].Speed) {
+ if (Loads >= PSCfg1Dimm[i].Loads) {
+ AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
+ DctOdcCtl = PSCfg1Dimm[i].Odc;
+ } else {
+ DctOdcCtl = 0x20113222;
+ }
+ break;
+ }
+ }
+ ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
+ } else {
+ for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
+ if (Speed == PSCfg2Dimm[i].Speed) {
+ if (Loads <= PSCfg2Dimm[i].Loads) {
+ AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
+ DctOdcCtl = PSCfg2Dimm[i].Odc;
+ break;
+ }
+ }
+ }
+ ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
+ }
+
+ // WL ODT
+ for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
+ if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
+ PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
+ PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
+ PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
+ PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
+ break;
+ }
+ }
+
+ CurrentChannel->MemClkDisMap = (UINT8 *) DrUDdr3CLKDis;
+ CurrentChannel->CKETriMap = (UINT8 *) DrUDdr3CKETri;
+ CurrentChannel->ODTTriMap = (UINT8 *) DrUDdr3ODTTri;
+ CurrentChannel->ChipSelTriMap = (UINT8 *) DrUDdr3CSTri;
+
+ CurrentChannel->DctEccDqsLike = 0x0403;
+ CurrentChannel->DctEccDqsScale = 0x70;
+ CurrentChannel->DctAddrTmg = AddrTmgCTL;
+ CurrentChannel->DctOdcCtl = DctOdcCtl;
+ for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+ CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+ }
+ CurrentChannel->SlowMode = SlowMode;
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/marhy3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/marhy3.c
new file mode 100755
index 0000000000..cfeb0dceb6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/marhy3.c
@@ -0,0 +1,561 @@
+/**
+ * @file
+ *
+ * marhy3.c
+ *
+ * Memory Controller, registered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "ma.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_HY_MARHY3_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA HyRDdr3CLKDis[] = {0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00};
+
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA HyRDdr3CKETri[] = {0x55, 0xAA};
+
+// 2 dimms per channel
+// Dimm 0: BP_MEMODTx[2,0]
+// Dimm 1: BP_MEMODTx[3,1]
+STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
+// 3 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[3,1]
+// Dimm 2: BP_MEMODTx[2]
+STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
+// 4 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[1]
+// Dimm 2: BP_MEMODTx[2]
+// Dimm 3: BP_MEMODTx[3]
+STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
+
+// BIOS must not tri-state chip select pin corresponding to the second chip
+// select of a single rank registered dimm
+STATIC CONST UINT8 ROMDATA HyRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This is function sets the platform specific settings for HY DDR3 L1 system
+ *
+ * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
+ * @param[in] SocketID Socket number
+ * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return AGESA_SUCCESS
+ * @return CurrentChannel->MemClkDisMap Points this pointer to HY MemClkDis table
+ * @return CurrentChannel->ChipSelTriMap Points this pointer to HY CS table
+ * @return CurrentChannel->CKETriMap Points this pointer to HY ODT table
+ * @return CurrentChannel->ODTTriMap Points this pointer to HY CKE table
+ * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
+ * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
+ * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
+ * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
+ * @return CurrentChannel->SlowMode Slow Mode
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgRHy3 (
+ IN OUT MEM_DATA_STRUCT *MemData,
+ IN UINT8 SocketID,
+ IN OUT CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ //
+ // Address Timings and Drive Strengths for 1 DIMM per channel or 2 Dimms per Channel
+ //
+ // Code searches table for matching speed, then matches the current dimm
+ // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
+ //
+ // Frequency, Dimm Config ,
+ // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
+ //
+ STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = {
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x00000000, 0x0000, 1},
+ {DDR800_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+ 0x00000000, 0x0040, 1},
+ {DDR800_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+ 0x00000000, 0x4004, 2},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x003C3C3C, 0x0000,1},
+ {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+ 0x003C3C3C, 0x0040, 1},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x003A3C3A, 0x4004, 2},
+ {DDR1066_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \
+ 0x003A3C3A, 0x4004, 2},
+ {DDR1066_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \
+ 0x003A3C3A, 0x4004, 2},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x003A3A3A, 0x0000, 1},
+ {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+ 0x003A3A3A, 0x0040, 1},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x00383A38, 0x4040, 2},
+ {DDR1333_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \
+ 0x00383A38, 0x4004, 2},
+ {DDR1333_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \
+ 0x00383A38, 0x4004, 2},
+ {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x00373937, 0x0000, 1},
+ {DDR1600_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+ 0x00373937, 0x0040, 1},
+ {DDR1600_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+ 0x00353935, 0x4004, 2}
+ };
+ //
+ // Address Timings and Drive Strengths for 3 DIMMs per channel
+ //
+ // Code searches table for matching speed, then matches the current dimm
+ // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
+ //
+ // Frequency, Dimm Config ,
+ // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
+ //
+ STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = {
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x0000, 1},
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x4040, 2},
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00380038, 0x4004, 3},
+ {DDR800_FREQUENCY, QR_DIMM1, \
+ 0x00000000, 0x0040, 1},
+ {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x4004, 2},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x003C3C3C, 0x0000, 1},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x003A3C3A, 0x4040, 2},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00373C37, 0x4040, 3},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00373C37, 0x4004, 3},
+ {DDR1066_FREQUENCY, QR_DIMM1, \
+ 0x003C3C3C, 0x0040, 1},
+ {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x003A3C3A, 0x4004, 2},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x003A3A3A, 0x0000, 1},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00383A38, 0x4040, 2},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00343A34, 0x4004, 3},
+ {DDR1333_FREQUENCY, QR_DIMM1, \
+ 0x003A3A3A, 0x0040, 1},
+ {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00383A38, 0x4004, 2},
+ {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00393939, 0x0000, 1},
+ {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00363936, 0x4040, 2},
+ {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00303930, 0x4004, 3},
+ {DDR1600_FREQUENCY, QR_DIMM1, \
+ 0x00393939, 0x0040, 1},
+ {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x00363936, 0x4004, 2}
+ };
+ //
+ // DIMM ODT Pattern (1 or 2 DIMMs per channel)
+ //
+ // Dimm Config ,
+ // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
+ //
+ STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
+ {SR_DIMM0, \
+ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
+ {DR_DIMM0, \
+ 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
+ {QR_DIMM0, \
+ 0x00000000, 0x00000000, 0x00000505, 0x00000505, 1},
+ {SR_DIMM1, \
+ 0x00000000, 0x00000000, 0x00020000, 0x00000000, 1},
+ {DR_DIMM1, \
+ 0x00000000, 0x00000000, 0x02080000, 0x00000000, 1},
+ {QR_DIMM1, \
+ 0x00000000, 0x00000000, 0x0A0A0000, 0x0A0A0000, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x01010202, 0x00000000, 0x09030603, 0x00000000, 2},
+ {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
+ 0x01010A0A, 0x01010000, 0x01030E0B, 0x01090000, 2},
+ {QR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+ 0x05050202, 0x00000202, 0x0D070203, 0x00000206, 2},
+ {QR_DIMM0 + QR_DIMM1, \
+ 0x05050A0A, 0x05050A0A, 0x05070A0B, 0x050D0A0E, 2}
+ };
+ // DIMM ODT Pattern (3 DIMMs per channel)
+ //
+ // Dimm Config ,
+ // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
+ //
+ STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
+ {SR_DIMM2 + DR_DIMM2, \
+ 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
+ {SR_DIMM0 + DR_DIMM0, \
+ 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
+ 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
+ {QR_DIMM1, \
+ 0x00000000, 0x00000000, 0x080A0000, 0x020A0000, 1},
+ {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x04040000, 0x04040A0A, 0x04060000, 0x040C0A0E, 2},
+ {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
+ 0x01010A0A, 0x01010000, 0x01030A0B, 0x01090000, 2},
+ {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+ 0x05050E0E, 0x05050B0B, 0x05070E0F, 0x050D0B0F, 3}
+ };
+ //
+ // DIMM ODT Pattern (4 DIMMs per channel)
+ //
+ // Dimm Config ,
+ // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
+ //
+ STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg4DIMMsODT[] = {
+ {ANY_DIMM3, \
+ 0x00000000, 0x00000000, 0x00000000, 0x08080000, 1},
+ {ANY_DIMM2 + ANY_DIMM3, \
+ 0x00000000, 0x04040808, 0x00000000, 0x0C0C0C0C, 2},
+ {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
+ 0x0C0C0000, 0x06060A0A, 0x0E0E0000, 0x0E0E0E0E, 3},
+ {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
+ 0x0D0D0E0E, 0x07070B0B, 0x0F0F0F0F, 0x0F0F0F0F, 4}
+ };
+ //
+ // DIMM Write Leveling ODT Pattern for 1 or 2 Dimms Per Channel
+ //
+ // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
+ //
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
+ {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
+ {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
+ {QR_DIMM0, {0x05, 0x00, 0x00, 0x00}, 1},
+ {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
+ {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
+ {QR_DIMM1, {0x00, 0x0A, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2},
+ {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+ {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+ {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
+ {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
+ {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2}
+ };
+ //
+ // DIMM Write Leveling ODT Pattern 3 Dimms Per Channel
+ //
+ // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
+ //
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
+ {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
+ {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1},
+ {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2},
+ {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+ {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3}
+ };
+ //
+ // DIMM Write Leveling ODT Pattern 4 Dimms Per Channel
+ //
+ // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
+ //
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = {
+ {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1},
+ {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2},
+ {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3},
+ {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4}
+ };
+
+ UINT16 i;
+ UINT16 j;
+ UINT8 MaxDimmPerCH;
+ UINT8 Dimms;
+ UINT16 Speed;
+ UINT16 DIMMRankType;
+ UINT16 _DIMMRankType;
+ UINT8 DimmTpMatch;
+ UINT32 AddrTmgCTL;
+ UINT32 DctOdcCtl;
+ UINT16 RC2RC8;
+ UINT32 PhyRODTCSLow;
+ UINT32 PhyRODTCSHigh;
+ UINT32 PhyWODTCSLow;
+ UINT32 PhyWODTCSHigh;
+ BOOLEAN SlowMode;
+ UINT8 PSCfgSize;
+ UINT8 PSCfgODTSize;
+ UINT8 PSCfgWlODTSize;
+ UINT8 PhyWLODT[4];
+
+ CONST ADV_R_PSCFG_ENTRY *PSCfgPtr;
+ CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
+ CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
+ UINT8 *DimmsPerChPtr;
+
+ ASSERT (MemData != NULL);
+ ASSERT (CurrentChannel != NULL);
+
+ AddrTmgCTL = 0;
+ DctOdcCtl = 0;
+ RC2RC8 = 0;
+ PhyRODTCSLow = 0;
+ PhyRODTCSHigh = 0;
+ PhyWODTCSLow = 0;
+ PhyWODTCSHigh = 0;
+ SlowMode = FALSE;
+ PhyWLODT[0] = 0x0F;
+ PhyWLODT[1] = 0x0F;
+ PhyWLODT[2] = 0x0F;
+ PhyWLODT[3] = 0x0F;
+ // Prepare inputs
+ Dimms = CurrentChannel->Dimms;
+ Speed = CurrentChannel->DCTPtr->Timings.Speed;
+ DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+ if (DimmsPerChPtr != NULL) {
+ MaxDimmPerCH = *DimmsPerChPtr;
+ } else {
+ MaxDimmPerCH = 2;
+ }
+
+ DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+ if (MaxDimmPerCH == 4) {
+ PSCfgPtr = NULL;
+ PSCfgSize = 0;
+ PSCfgODTPtr = PSCfg4DIMMsODT;
+ PSCfgWlODTPtr = PSCfg4DIMMsWlODT;
+ PSCfgODTSize = sizeof (PSCfg4DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+ PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+ } else if (MaxDimmPerCH == 3) {
+ PSCfgPtr = PSCfg3DIMMs;
+ PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
+ PSCfgODTPtr = PSCfg3DIMMsODT;
+ PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
+ PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+ PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+ } else {
+ PSCfgPtr = PSCfg2DIMMs;
+ PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
+ PSCfgODTPtr = PSCfg2DIMMsODT;
+ PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
+ PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+ PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+ }
+
+ // AddrTmgCTL and DctOdcCtl
+ if (MaxDimmPerCH != 4) {
+ for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) {
+ if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgPtr->Dimms) {
+ AddrTmgCTL = PSCfgPtr->AddrTmg;
+ DctOdcCtl = 0x00223222;
+ RC2RC8 = PSCfgPtr->RC2RC8;
+ break;
+ }
+ }
+ }
+
+ //
+ // Overrides and/or exceptions
+ //
+ DimmTpMatch = 0;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (MaxDimmPerCH == 4) {
+ if (DimmTpMatch > 0) {
+ DctOdcCtl = 0x00223222;
+ if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) {
+ DctOdcCtl = 0x00113222;
+ }
+ }
+ if (DimmTpMatch >= 3) {
+ AddrTmgCTL |= 0x002F0000;
+ }
+ if (DimmTpMatch >= 2) {
+ RC2RC8 = 0x4040;
+ }
+ } else if ((MaxDimmPerCH == 3) && (CurrentChannel->Dimms == 3)) {
+ DctOdcCtl = 0x00113222;
+ } else {
+ if ((Dimms == 1) && (DimmTpMatch == 1)) {
+ DctOdcCtl = 0x00113222;
+ }
+ }
+
+ //RC2 and RC8
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution.
+ if (CurrentChannel->CtrlWrd02[j] > 0) {
+ if (CurrentChannel->CtrlWrd02[j] == 1) {
+ // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s).
+ CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F;
+ CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F;
+ } else {
+ // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s).
+ CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F;
+ CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F;
+ }
+ }
+ }
+
+ //Programmable ODT
+ for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) {
+ if (Dimms != PSCfgODTPtr->Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgODTPtr->Dimms) {
+ PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
+ PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
+ PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
+ PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
+ break;
+ }
+ }
+
+ //WLODT
+ for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
+ if (Dimms != PSCfgWlODTPtr->Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
+ PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
+ PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
+ PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
+ PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
+ break;
+ }
+ }
+
+ // Set ProcODT
+ DctOdcCtl |= 0x20000000;
+
+ CurrentChannel->MemClkDisMap = (UINT8 *) HyRDdr3CLKDis;
+ CurrentChannel->CKETriMap = (UINT8 *) HyRDdr3CKETri;
+ CurrentChannel->ChipSelTriMap = (UINT8 *) HyRDdr3CSTri;
+
+ switch (MaxDimmPerCH) {
+ case 3:
+ CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri3D;
+ break;
+ case 4:
+ CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri4D;
+ break;
+ default:
+ CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri2D; // Most conservative
+ }
+
+ CurrentChannel->DctAddrTmg = AddrTmgCTL;
+ CurrentChannel->DctOdcCtl = DctOdcCtl;
+ CurrentChannel->PhyRODTCSLow = PhyRODTCSLow;
+ CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
+ CurrentChannel->PhyWODTCSLow = PhyWODTCSLow;
+ CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
+ for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+ CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+ }
+ CurrentChannel->SlowMode = SlowMode;
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/mauhy3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/mauhy3.c
new file mode 100755
index 0000000000..b9422999a3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/mauhy3.c
@@ -0,0 +1,352 @@
+/**
+ * @file
+ *
+ * mauhy3.c
+ *
+ * Platform specific settings for HY DDR3 unbuffered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_HY_MAUHY3_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA HyUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA HyUDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri2D[] = {0x01, 0x04, 0x02, 0x08};
+// 3 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[3,1]
+// Dimm 2: BP_MEMODTx[2]
+STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA HyUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This is function sets the platform specific settings for HY DDR3 unbuffered dimms
+ *
+ *
+ * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
+ * @param[in] SocketID Socket number
+ * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return AGESA_SUCCESS
+ * @return CurrentChannel->MemClkDisMap Points this pointer to HY MemClkDis table
+ * @return CurrentChannel->ChipSelTriMap Points this pointer to HY CS table
+ * @return CurrentChannel->CKETriMap Points this pointer to HY ODT table
+ * @return CurrentChannel->ODTTriMap Points this pointer to HY CKE table
+ * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
+ * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
+ * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
+ * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
+ * @return CurrentChannel->SlowMode Slow Mode
+ *
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgUHy3 (
+ IN OUT MEM_DATA_STRUCT *MemData,
+ IN UINT8 SocketID,
+ IN OUT CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ STATIC CONST PSCFG_ENTRY PSCfg[] = {
+ {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
+ {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
+ {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
+ {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
+ };
+
+ STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
+ {SR_DIMM0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
+ {DR_DIMM0, 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
+ {SR_DIMM1, 0x00000000,0x00000000,0x00020000, 0x00000000, 1},
+ {DR_DIMM1, 0x00000000,0x00000000,0x02080000, 0x00000000, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x01010202,0x00000000,0x09030603, 0x00000000, 2},
+ };
+
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
+ {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
+ {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
+ {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
+ {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+ };
+
+ STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
+ {SR_DIMM2 + DR_DIMM2, 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
+ //{SR_DIMM0 + DR_DIMM0, 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
+ //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
+ };
+
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
+ {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
+ //{SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
+ //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
+ };
+
+ UINT16 i;
+ UINT16 j;
+ UINT8 MaxDimmPerCH;
+ UINT8 Loads;
+ UINT8 Dimms;
+ UINT16 Speed;
+ UINT16 DIMMRankType;
+ UINT16 _DIMMRankType;
+ UINT32 AddrTmgCTL;
+ UINT32 DctOdcCtl;
+ UINT32 PhyRODTCSLow;
+ UINT32 PhyRODTCSHigh;
+ UINT32 PhyWODTCSLow;
+ UINT32 PhyWODTCSHigh;
+ UINT8 PhyWLODT[4];
+ UINT8 PSCfgODTSize;
+ UINT8 PSCfgWlODTSize;
+ BOOLEAN SlowMode;
+ UINT8 DimmTpMatch;
+ CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
+ CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
+ UINT8 *DimmsPerChPtr;
+
+ ASSERT (MemData != NULL);
+ ASSERT (CurrentChannel != NULL);
+
+ AddrTmgCTL = 0;
+ DctOdcCtl = 0;
+ PhyRODTCSLow = 0;
+ PhyRODTCSHigh = 0;
+ PhyWODTCSLow = 0;
+ PhyWODTCSHigh = 0;
+ PhyWLODT[0] = 0x0F;
+ PhyWLODT[1] = 0x0F;
+ PhyWLODT[2] = 0x0F;
+ PhyWLODT[3] = 0x0F;
+
+ if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->RegDimmPresent) {
+ return AGESA_UNSUPPORTED;
+ }
+ // Prepare inputs
+
+ DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+ if (DimmsPerChPtr != NULL) {
+ MaxDimmPerCH = *DimmsPerChPtr;
+ } else {
+ MaxDimmPerCH = 2;
+ }
+
+ Loads = CurrentChannel->Loads;
+ Dimms = CurrentChannel->Dimms;
+ Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+ DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+ if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
+ SlowMode = TRUE; // 2T
+ } else {
+ SlowMode = FALSE; // 1T
+ }
+
+ for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
+ if (Speed == PSCfg[i].Speed) {
+ if (Loads <= PSCfg[i].Loads) {
+ AddrTmgCTL = PSCfg[i].AddrTmg;
+ DctOdcCtl = PSCfg[i].Odc;
+ break;
+ }
+ }
+ }
+
+ ASSERT (i < GET_SIZE_OF (PSCfg));
+
+ if (MaxDimmPerCH == 3) {
+ PSCfgODTPtr = PSCfg3DIMMsODT;
+ PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
+ PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+ PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+ } else {
+ PSCfgODTPtr = PSCfg2DIMMsODT;
+ PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
+ PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+ PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+ }
+
+ // Programmable ODT
+ for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) {
+ if (Dimms != PSCfgODTPtr->Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgODTPtr->Dimms) {
+ PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
+ PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
+ PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
+ PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
+ break;
+ }
+ }
+
+ // WL ODT
+ for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
+ if (Dimms != PSCfgWlODTPtr->Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
+ PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
+ PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
+ PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
+ PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
+ break;
+ }
+ }
+
+ //
+ // Overrides and/or exceptions
+ //
+ if (Dimms == 1) {
+ if (Loads >= 16) {
+ if (Speed == DDR800_FREQUENCY) {
+ AddrTmgCTL = 0x003B0000;
+ } else if (Speed == DDR1066_FREQUENCY) {
+ AddrTmgCTL = 0x00380000;
+ } else if (Speed == DDR1333_FREQUENCY) {
+ AddrTmgCTL = 0x00360000;
+ } else {
+ AddrTmgCTL = 0x00340000;
+ SlowMode = TRUE;
+ }
+ } else {
+ AddrTmgCTL = 0;
+ }
+ DctOdcCtl = 0x20113222;
+ }
+
+ CurrentChannel->MemClkDisMap = (UINT8 *) HyUDdr3CLKDis;
+ CurrentChannel->CKETriMap = (UINT8 *) HyUDdr3CKETri;
+ CurrentChannel->ChipSelTriMap = (UINT8 *) HyUDdr3CSTri;
+
+ switch (MaxDimmPerCH) {
+ case 3:
+ CurrentChannel->ODTTriMap = (UINT8 *) HyUDdr3ODTTri3D;
+ break;
+ default:
+ CurrentChannel->ODTTriMap = (UINT8 *) HyUDdr3ODTTri2D; // Most conservative
+ }
+
+ CurrentChannel->DctEccDqsLike = 0x0403;
+ CurrentChannel->DctEccDqsScale = 0x70;
+ CurrentChannel->DctAddrTmg = AddrTmgCTL;
+ CurrentChannel->DctOdcCtl = DctOdcCtl;
+ CurrentChannel->PhyRODTCSLow = PhyRODTCSLow;
+ CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
+ CurrentChannel->PhyWODTCSLow = PhyWODTCSLow;
+ CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
+ for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+ CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+ }
+ CurrentChannel->SlowMode = SlowMode;
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/masNi3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/masNi3.c
new file mode 100755
index 0000000000..4af0889a9a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/masNi3.c
@@ -0,0 +1,256 @@
+/*
+ * @file
+ *
+ * masNi3.c
+ *
+ * Platform specific settings for Ni DDR3 SO-dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/* This file contains routine that add platform specific support ASB2 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "ma.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_NI_MASNI3_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA NiSDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA NiSDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA NiSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA NiSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This is function sets the platform specific settings for Ni DDR3 SO-dimms
+ *
+ *
+ * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
+ * @param[in] SocketID Socket number
+ * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return AGESA_SUCCESS
+ * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
+ * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
+ * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
+ * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
+ * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
+ * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
+ * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
+ * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
+ * @return CurrentChannel->SlowMode Slow Mode
+ *
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgSNi3 (
+ IN OUT MEM_DATA_STRUCT *MemData,
+ IN UINT8 SocketID,
+ IN OUT CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ STATIC CONST PSCFG_ENTRY PSCfg[] = {
+ {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222},
+ {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222},
+ {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222},
+ };
+
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
+ {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
+ {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+ };
+
+ UINT16 i;
+ UINT16 j;
+ UINT8 Loads;
+ UINT8 Dimms;
+ UINT16 Speed;
+ UINT32 AddrTmgCTL;
+ UINT32 DctOdcCtl;
+ UINT8 PhyWLODT[4];
+ BOOLEAN SlowMode;
+ UINT8 MaxDimmPerCH;
+ UINT8 *DimmsPerChPtr;
+ UINT16 DIMMRankType;
+ UINT16 _DIMMRankType;
+ UINT8 DimmTpMatch;
+
+ ASSERT (MemData != 0);
+ ASSERT (CurrentChannel != 0);
+
+ AddrTmgCTL = 0;
+ DctOdcCtl = 0;
+ PhyWLODT[0] = 0x0F;
+ PhyWLODT[1] = 0x0F;
+ PhyWLODT[2] = 0x0F;
+ PhyWLODT[3] = 0x0F;
+ SlowMode = FALSE; // 1T
+ if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
+ return AGESA_UNSUPPORTED;
+ }
+ // Prepare inputs
+ Loads = CurrentChannel->Loads;
+ Dimms = CurrentChannel->Dimms;
+ Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+ DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+ DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+ if (DimmsPerChPtr != NULL) {
+ MaxDimmPerCH = *DimmsPerChPtr;
+ } else {
+ MaxDimmPerCH = 2;
+ }
+
+ for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
+ if (Speed == PSCfg[i].Speed) {
+ if (Loads <= PSCfg[i].Loads) {
+ AddrTmgCTL = PSCfg[i].AddrTmg;
+ DctOdcCtl = PSCfg[i].Odc;
+ break;
+ }
+ }
+ }
+
+ // WL ODT
+ for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
+ if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
+ PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
+ PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
+ PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
+ PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
+ break;
+ }
+ }
+
+ //
+ // Overrides and/or exceptions
+ //
+ if (MaxDimmPerCH == 2) {
+ if (Dimms == 2) {
+ DctOdcCtl = 0x20223323;
+ SlowMode = TRUE;
+ if (Speed == DDR800_FREQUENCY) {
+ AddrTmgCTL = 0x00000039;
+ } else if (Speed == DDR1066_FREQUENCY) {
+ AddrTmgCTL = 0x00000037;
+ }
+ } else {
+ DctOdcCtl = 0x20113222;
+ }
+ } else {
+ if (CurrentChannel->DimmSRPresent != 0) {
+ PhyWLODT[0] = 1;
+ } else if (CurrentChannel->DimmDrPresent != 0) {
+ PhyWLODT[0] = 4;
+ }
+ }
+
+ CurrentChannel->MemClkDisMap = (UINT8 *) NiSDdr3CLKDis;
+ CurrentChannel->CKETriMap = (UINT8 *) NiSDdr3CKETri;
+ CurrentChannel->ODTTriMap = (UINT8 *) NiSDdr3ODTTri;
+ CurrentChannel->ChipSelTriMap = (UINT8 *) NiSDdr3CSTri;
+
+ CurrentChannel->DctAddrTmg = AddrTmgCTL;
+ CurrentChannel->DctOdcCtl = DctOdcCtl;
+ for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+ CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+ }
+ CurrentChannel->SlowMode = SlowMode;
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/mauNi3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/mauNi3.c
new file mode 100755
index 0000000000..375802923f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/mauNi3.c
@@ -0,0 +1,255 @@
+/*
+ * @file
+ *
+ * mauNi3.c
+ *
+ * Platform specific settings for Ni DDR3 unbuffered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_NI_MAUNI3_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA NiUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA NiUDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA NiUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA NiUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This is function sets the platform specific settings for Ni DDR3 Unbuffered dimms
+ *
+ *
+ * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
+ * @param[in] SocketID Socket number
+ * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return AGESA_SUCCESS
+ * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
+ * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
+ * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
+ * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
+ * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
+ * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
+ * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
+ * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
+ * @return CurrentChannel->SlowMode Slow Mode
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgUNi3 (
+ IN OUT MEM_DATA_STRUCT *MemData,
+ IN UINT8 SocketID,
+ IN OUT CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
+ {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
+ {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
+ {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
+ {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
+ };
+ STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
+ {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
+ {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
+ {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
+ {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
+ };
+
+ STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
+ {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
+ {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
+ {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
+ {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
+ {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+ };
+
+ UINT16 i;
+ UINT16 j;
+ UINT8 Loads;
+ UINT8 Dimms;
+ UINT16 Speed;
+ UINT16 DIMMRankType;
+ UINT16 _DIMMRankType;
+ UINT32 AddrTmgCTL;
+ UINT32 DctOdcCtl;
+ UINT8 PhyWLODT[4];
+ BOOLEAN SlowMode;
+ UINT8 DimmTpMatch;
+
+ ASSERT (MemData != 0);
+ ASSERT (CurrentChannel != 0);
+
+ AddrTmgCTL = 0;
+ DctOdcCtl = 0;
+ PhyWLODT[0] = 0x0F;
+ PhyWLODT[1] = 0x0F;
+ PhyWLODT[2] = 0x0F;
+ PhyWLODT[3] = 0x0F;
+
+ if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+ return AGESA_UNSUPPORTED;
+ }
+ if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+ return AGESA_UNSUPPORTED;
+ }
+ if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
+ return AGESA_UNSUPPORTED;
+ }
+ // Prepare inputs
+ Loads = CurrentChannel->Loads;
+ Dimms = CurrentChannel->Dimms;
+ Speed = CurrentChannel->DCTPtr->Timings.Speed;
+ DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+ if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
+ SlowMode = TRUE; // 2T
+ } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
+ SlowMode = TRUE; // 2T
+ } else {
+ SlowMode = FALSE; // 1T
+ }
+
+ if (Dimms == 1) {
+ for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
+ if (Speed == PSCfg1Dimm[i].Speed) {
+ if (Loads >= PSCfg1Dimm[i].Loads) {
+ AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
+ DctOdcCtl = PSCfg1Dimm[i].Odc;
+ } else {
+ DctOdcCtl = 0x20113222;
+ }
+ break;
+ }
+ }
+ ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
+ } else {
+ for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
+ if (Speed == PSCfg2Dimm[i].Speed) {
+ if (Loads <= PSCfg2Dimm[i].Loads) {
+ AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
+ DctOdcCtl = PSCfg2Dimm[i].Odc;
+ break;
+ }
+ }
+ }
+ ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
+ }
+
+ // WL ODT
+ for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
+ if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
+ continue;
+ }
+ DimmTpMatch = 0;
+ _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+ DimmTpMatch++;
+ }
+ }
+ if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
+ PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
+ PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
+ PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
+ PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
+ break;
+ }
+ }
+
+ CurrentChannel->MemClkDisMap = (UINT8 *) NiUDdr3CLKDis;
+ CurrentChannel->CKETriMap = (UINT8 *) NiUDdr3CKETri;
+ CurrentChannel->ODTTriMap = (UINT8 *) NiUDdr3ODTTri;
+ CurrentChannel->ChipSelTriMap = (UINT8 *) NiUDdr3CSTri;
+
+ CurrentChannel->DctEccDqsLike = 0x0403;
+ CurrentChannel->DctEccDqsScale = 0x70;
+ CurrentChannel->DctAddrTmg = AddrTmgCTL;
+ CurrentChannel->DctOdcCtl = DctOdcCtl;
+ for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+ CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+ }
+ CurrentChannel->SlowMode = SlowMode;
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/ma.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/ma.c
new file mode 100755
index 0000000000..0396ebb06e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/ma.c
@@ -0,0 +1,136 @@
+/**
+ * @file
+ *
+ * ma.c
+ *
+ * Initializes ARDK Block
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of Advanced Micro Devices, Inc. nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ * MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "ma.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_MA_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This is the default return function of the ARDK block. The function always
+ * returns AGESA_UNSUPPORTED
+ *
+ * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
+ * @param[in] SocketID Socket number
+ * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return AGESA_UNSUPPORTED AGESA status indicating that default is unsupported
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgDef (
+ IN OUT MEM_DATA_STRUCT *MemData,
+ IN UINT8 SocketID,
+ IN OUT CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ return AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This function returns the rank type map of a channel.
+ *
+ * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
+ *
+ * @return UINT16 - The map of rank type.
+ *
+ */
+UINT16
+MemAGetPsRankType (
+ IN CH_DEF_STRUCT *CurrentChannel
+ )
+{
+ UINT8 i;
+ UINT16 DIMMRankType;
+
+ DIMMRankType = 0;
+ for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+ if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) {
+ if (i < 2) {
+ DIMMRankType |= (UINT16) 4 << (i << 2);
+ }
+ } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) {
+ DIMMRankType |= (UINT16) 2 << (i << 2);
+ } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) {
+ DIMMRankType |= (UINT16) 1 << (i << 2);
+ }
+ }
+ return DIMMRankType;
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 09:22:58 +0000