diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f10')
| -rw-r--r-- | src/vendorcode/amd/agesa/f10/AGESA.h | 8 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h | 2 |
2 files changed, 3 insertions, 7 deletions
diff --git a/src/vendorcode/amd/agesa/f10/AGESA.h b/src/vendorcode/amd/agesa/f10/AGESA.h index c38bf40a54..a12811604a 100644 --- a/src/vendorcode/amd/agesa/f10/AGESA.h +++ b/src/vendorcode/amd/agesa/f10/AGESA.h @@ -1012,12 +1012,8 @@ typedef enum { ///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010 -#ifndef TOP_MEM - #define TOP_MEM 0xC001001A -#endif -#ifndef TOP_MEM2 - #define TOP_MEM2 0xC001001D -#endif +#define TOP_MEM 0xC001001Aul +#define TOP_MEM2 0xC001001Dul #define HWCR 0xC0010015 #define NB_CFG 0xC001001F diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h index 34d256801c..1777c5d979 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h @@ -92,7 +92,7 @@ #define NorthbridgeCapabilities 0xE8 #define DRAMBase0 0x40 #define MMIOBase0 0x80 -#define TOP_MEM 0xC001001A +#define TOP_MEM 0xC001001Aul #define LOW_NODE_DEVICEID 24 #define LOW_APICID 0 |