diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f12')
-rw-r--r-- | src/vendorcode/amd/agesa/f12/AGESA.h | 8 | ||||
-rw-r--r-- | src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h | 2 |
2 files changed, 3 insertions, 7 deletions
diff --git a/src/vendorcode/amd/agesa/f12/AGESA.h b/src/vendorcode/amd/agesa/f12/AGESA.h index 9660f35965..abe72b61b6 100644 --- a/src/vendorcode/amd/agesa/f12/AGESA.h +++ b/src/vendorcode/amd/agesa/f12/AGESA.h @@ -1279,12 +1279,8 @@ typedef enum { ///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010 -#ifndef TOP_MEM -#define TOP_MEM 0xC001001A -#endif -#ifndef TOP_MEM2 -#define TOP_MEM2 0xC001001D -#endif +#define TOP_MEM 0xC001001Aul +#define TOP_MEM2 0xC001001Dul #define HWCR 0xC0010015 #define NB_CFG 0xC001001F diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h index 29f4070375..b871845870 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h @@ -101,7 +101,7 @@ AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE); #define NorthbridgeCapabilities 0xE8 #define DRAMBase0 0x40 #define MMIOBase0 0x80 -#define TOP_MEM 0xC001001A +#define TOP_MEM 0xC001001Aul #define LOW_NODE_DEVICEID 24 #define LOW_APICID 0 |