diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c')
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c new file mode 100644 index 0000000000..f81615d47f --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c @@ -0,0 +1,144 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Cache Flush On Halt Function. + * + * Contains code to Level the Feature in a multi-socket system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x10/DA + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "GeneralServices.h" +#include "cpuPostInit.h" +#include "cpuFeatures.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P U B L I C F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * Enable DA-C Cpu Cache Flush On Halt Function + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + */ +VOID +SetF10DaCacheFlushOnHaltRegister ( + IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CoreCount; + UINT32 AndMask; + UINT32 OrMask; + PCI_ADDR PciAddress; + CPU_LOGICAL_ID LogicalId; + + if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) { + // F3xDC[25:19] = 04h + // F3xDC[18:16] = 111b + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG; + AndMask = 0xFC00FFFF; + OrMask = 0x00270000; + + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + if (LogicalId.Revision == AMD_F10_DA_C2) { + //For DA_C2 single Core, F3xDC[18:16] = 0 + GetActiveCoresInCurrentSocket (&CoreCount, StdHeader); + if (CoreCount == 1) { + OrMask = 0x00200000; + } + } + + IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader); + ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC + } +} + +CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt = +{ + 0, + SetF10DaCacheFlushOnHaltRegister +};
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