diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE')
9 files changed, 2573 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c new file mode 100644 index 0000000000..857e9d5ac6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c @@ -0,0 +1,1040 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Microcode patch. + * + * Fam10 Microcode Patch rev 010000bf for 10a0 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10/REVC + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +// Patch code 010000bf for 10a0 and equivalent +CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000bf = +{ +0x10, +0x20, +0x17, +0x02, +0xbf, +0x00, +0x00, +0x01, +0x00, +0x80, +0x20, +0x00, +0x42, +0x82, +0x02, +0x39, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0xa0, +0x10, +0x00, +0x00, +0x00, +0xaa, +0xaa, +0xaa, +0x74, +0x0f, +0x00, +0x00, +0xbe, +0x01, +0x00, +0x00, +0x33, +0x0e, +0x00, +0x00, +0xa9, +0x01, +0x00, +0x00, +0x75, +0x00, +0x00, +0x00, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xff, +0xa0, +0xfd, +0xff, +0x28, +0xc3, +0x3f, +0xc0, +0xcf, +0xff, +0x07, +0xe2, +0x01, +0x0f, +0xde, +0x50, +0xfe, +0xf2, +0xdf, +0xff, +0x0f, +0x3b, +0xfc, +0x01, +0xc5, +0x40, +0x03, +0xd4, +0x00, +0x80, +0xff, +0xfe, +0x7f, +0xfe, +0xe1, +0x1b, +0xc8, +0x5b, +0xf6, +0xff, +0xff, +0x7b, +0x87, +0x5f, +0xad, +0x6b, +0xf9, +0x6f, +0xfe, +0xfa, +0x1f, +0xfe, +0xb5, +0x00, +0x40, +0x11, +0x6a, +0x0e, +0xc0, +0x9b, +0x56, +0xe8, +0x75, +0xe0, +0x0f, +0x38, +0x00, +0xcf, +0xcc, +0xa0, +0xd7, +0x83, +0x3f, +0xff, +0x7b, +0xfc, +0xbf, +0x00, +0x3f, +0x0f, +0xff, +0x35, +0x00, +0x80, +0xd0, +0x18, +0x07, +0x60, +0x19, +0x07, +0xf4, +0x7a, +0xf0, +0xa6, +0x1c, +0x00, +0x38, +0x1f, +0xc0, +0xe7, +0xa0, +0xff, +0xff, +0x51, +0x9e, +0x7f, +0x80, +0x9f, +0x87, +0x80, +0x0a, +0x00, +0x60, +0xd3, +0xe0, +0x4f, +0x10, +0xfc, +0x32, +0xd8, +0x3a, +0x49, +0xff, +0x7f, +0xcb, +0xf0, +0x0f, +0xf0, +0xf3, +0x8c, +0xff, +0xff, +0x00, +0xc3, +0x31, +0x17, +0xfd, +0x2c, +0x47, +0x0d, +0x00, +0xd0, +0x32, +0xf0, +0x27, +0x1d, +0x7e, +0x19, +0x6c, +0x60, +0xf1, +0xff, +0x1f, +0x7f, +0x38, +0xe6, +0xa2, +0x16, +0x35, +0xff, +0xff, +0xe7, +0xe1, +0x1f, +0xe0, +0x00, +0xfe, +0xbf, +0x07, +0xbb, +0x9c, +0xf4, +0xff, +0x3f, +0x0f, +0xff, +0x00, +0x07, +0xf8, +0xdf, +0x8d, +0x0b, +0x3e, +0x78, +0x73, +0x3f, +0x8b, +0xff, +0xff, +0x70, +0xe5, +0xf0, +0x0b, +0x03, +0x00, +0x0f, +0x50, +0xff, +0x52, +0xfe, +0xbb, +0xaf, +0xfa, +0x87, +0x7f, +0xff, +0x07, +0xc0, +0xff, +0xa5, +0x14, +0x1f, +0xbe, +0xff, +0x9f, +0xc5, +0xff, +0xc4, +0xaa, +0x72, +0xf8, +0xef, +0x01, +0x80, +0xff, +0xeb, +0xff, +0x00, +0x43, +0x37, +0x96, +0xfd, +0xc3, +0xf6, +0xff, +0xab, +0x80, +0xff, +0x00, +0x3f, +0x0f, +0xff, +0xff, +0x8f, +0xe2, +0xfc, +0x02, +0x54, +0x39, +0xda, +0xd5, +0x00, +0x80, +0xff, +0x68, +0x3c, +0xe0, +0xc1, +0x9b, +0xca, +0xfe, +0xe4, +0xff, +0xff, +0x09, +0x87, +0x5f, +0x06, +0x5b, +0xfe, +0x0f, +0xc4, +0x03, +0x1e, +0xfa, +0xa9, +0x7c, +0xe0, +0xff, +0x7b, +0x00, +0xc0, +0x7f, +0xe0, +0x1f, +0xdf, +0xf0, +0x0f, +0xe0, +0x00, +0xff, +0x81, +0x7f, +0x7f, +0xc3, +0x3f, +0x80, +0x01, +0xfc, +0x07, +0xfe, +0xfe, +0x0d, +0xff, +0x00, +0x00, +0xf0, +0xff, +0x3d, +0x0f, +0xe0, +0x3f, +0xf0, +0xf0, +0x6f, +0xf8, +0x07, +0x3f, +0x80, +0xff, +0xc0, +0xc0, +0xbf, +0xe1, +0x1f, +0xff, +0x00, +0xfe, +0x03, +0x00, +0xff, +0x86, +0x7f, +0x1e, +0x00, +0xf8, +0xff, +0xf8, +0x07, +0xf0, +0x1f, +0x03, +0xf8, +0x37, +0xfc, +0xe0, +0x1f, +0xc0, +0x7f, +0x0f, +0xe0, +0xdf, +0xf0, +0x81, +0x7f, +0x00, +0xff, +0x3f, +0x80, +0x7f, +0xc3, +0x7f, +0x0f, +0x00, +0xfc, +0x0f, +0xfc, +0x03, +0xf8, +0xfe, +0x01, +0xfc, +0x1b, +0x3f, +0xf0, +0x0f, +0xe0, +0xf8, +0x07, +0xf0, +0x6f, +0xff, +0xc0, +0x3f, +0x80, +0xe1, +0x1f, +0xc0, +0xbf, +0xfe, +0xbf, +0x07, +0x00, +0xfc, +0x07, +0xfe, +0x01, +0x0d, +0xff, +0x00, +0xfe, +0xf0, +0x1f, +0xf8, +0x07, +0x37, +0xfc, +0x03, +0xf8, +0xc0, +0x7f, +0xe0, +0x1f, +0xdf, +0xf0, +0x0f, +0xe0, +0x00, +0xff, +0xdf, +0x03, +0x00, +0xfe, +0x03, +0xff, +0xff, +0x86, +0x7f, +0x00, +0x03, +0xf8, +0x0f, +0xfc, +0xfc, +0x1b, +0xfe, +0x01, +0x0f, +0xe0, +0x3f, +0xf0, +0xf0, +0x6f, +0xf8, +0x07, +0x01, +0x80, +0xff, +0xef, +0x7f, +0xbf, +0xff, +0x81, +0xdf, +0x95, +0xc1, +0xaf, +0xff, +0x91, +0xfc, +0x2f, +0x48, +0x57, +0x06, +0xbf, +0xff, +0x4f, +0xb0, +0xff, +0x32, +0xd8, +0x3a, +0xfc, +0xd7, +0x00, +0x40, +0x95, +0x81, +0xff, +0x94, +0x01, +0x1f, +0xe0, +0xe7, +0xe1, +0xff, +0xff, +0x53, +0xce, +0x7f, +0xa9, +0xeb, +0x83, +0xff, +0xef, +0x4b, +0xfd, +0xfc, +0xbd, +0xbd, +0x0e, +0xff, +0x7b, +0x00, +0xe0, +0x9c, +0x56, +0x0e, +0x00, +0xd0, +0x0f, +0xe0, +0x73, +0xff, +0x81, +0x7f, +0x00, +0xc3, +0x3f, +0x80, +0x7f, +0xfc, +0x07, +0xfe, +0x01, +0x0d, +0xff, +0x00, +0xfe, +0xe0, +0xfd, +0x35, +0x00, +0xe0, +0x0d, +0x2b, +0x07, +0x3a, +0xf0, +0x07, +0xf4, +0x96, +0xff, +0xed, +0x3f, +0xff, +0xe1, +0x1f, +0xab, +0x5b, +0x02, +0x00, +0xfe, +0xfb, +0x87, +0x7f, +0xac, +0x00, +0xa8, +0xcd, +0x1a, +0x6f, +0x72, +0xc0, +0xff, +0xfc, +0x3c, +0xfc, +0x03, +0x1f, +0xc0, +0x7f, +0xe0, +0xe0, +0xdf, +0xf0, +0x0f, +0x7f, +0x00, +0xff, +0x81, +0x80, +0x7f, +0xc3, +0x3f, +0x0f, +0x00, +0xfc, +0x7f, +0xff, +0x7f, +0x79, +0xfc, +0x01, +0x7e, +0x1e, +0xfe, +0x2b, +0x07, +0xe0, +0xfe, +0x07, +0xf0, +0x39, +0xe8, +0xc0, +0x3f, +0x80, +0xff, +0x1f, +0xc0, +0xbf, +0xe1, +0xb9, +0x06, +0x00, +0x78, +0xf6, +0xff, +0xbf, +0x80, +0xff, +0x00, +0x3f, +0x0f, +0xff, +0xff, +0x8f, +0xe2, +0xfc, +0x03, +0xfc, +0x3c, +0x7f, +0x34, +0x1e, +0xf0, +0xd0, +0xef, +0xe5, +0xf3, +0xff, +0xdf, +0x03, +0x00, +0xee, +0xa3, +0x72, +0x00, +0x83, +0x7e, +0x00, +0x9f, +0xf8, +0xfd, +0xff, +0x07, +0x1f, +0xbe, +0xb1, +0xec, +0x65, +0x97, +0xff, +0x1f, +0x79, +0xf8, +0x07, +0xf8, +0x80, +0xc4, +0x97, +0x01, +0x00, +0xff, +0x81, +0x7f, +0x7f, +0xc3, +0x3f, +0x80, +0x01, +0xfc, +0x07, +0xfe, +0xfe, +0x0d, +0xff, +0x00, +0x07, +0xf0, +0x1f, +0xf8, +0xf8, +0x37, +0xfc, +0x03, +0x00, +0xc0, +0xff, +0xf7, +0x3f, +0x80, +0xff, +0xc0, +0xc0, +0xbf, +0xe1, +0x1f, +0xff, +0x00, +0xfe, +0x03, +0x00, +0xff, +0x86, +0x7f, +0xfc, +0x03, +0xf8, +0x0f, +0x01, +0xfc, +0x1b, +0xfe, +0x7b, +0x00, +0xe0, +0xff, +0xe0, +0x1f, +0xc0, +0x7f, +0x0f, +0xe0, +0xdf, +0xf0, +0x81, +0x7f, +0x00, +0xff, +0x3f, +0x80, +0x7f, +0xc3, +0x07, +0xfe, +0x01, +0xfc, +0xff, +0x00, +0xfe, +0x0d, +0xff, +0x3d, +0x00, +0xf0, +0x3f, +0xf0, +0x0f, +0xe0, +0xf8, +0x07, +0xf0, +0x6f, +0xff, +0xc0, +0x3f, +0x80, +0xe1, +0x1f, +0xc0, +0xbf, +0xfe, +0x03, +0xff, +0x00, +0x86, +0x7f, +0x00, +0xff, +0xf8, +0xff, +0x1e, +0x00, +0xf0, +0x1f, +0xf8, +0x07, +0x37, +0xfc, +0x03, +0xf8, +0xc0, +0x7f, +0xe0, +0x1f, +0xdf, +0xf0, +0x0f, +0xe0, +0x00, +0xff, +0x81, +0x7f, +0x7f, +0xc3, +0x3f, +0x80, +0x00, +0xfc, +0x7f, +0x0f, +0x03, +0xf8, +0x0f, +0xfc, +0xfc, +0x1b, +0xfe, +0x01, +0x0f, +0xe0, +0x3f, +0xf0, +0xf0, +0x6f, +0xf8, +0x07, +0x3f, +0x80, +0xff, +0xc0, +0xc0, +0xbf, +0xe1, +0x1f, +0x07, +0x00, +0xfe, +0xbf, +0xfe, +0x01, +0xfc, +0x07, +0x00, +0xfe, +0x0d, +0xff, +0xf8, +0x07, +0xf0, +0x1f, +0x03, +0xf8, +0x37, +0xfc, +0xe0, +0x1f, +0xc0, +0x7f, +0x0f, +0xe0, +0xdf, +0xf0, +0xdf, +0x03, +0x00, +0xff, +0x03, +0xff, +0x00, +0xfe, +0x7f, +0x00, +0xff, +0x86, +0x0f, +0xfc, +0x03, +0xf8, +0xfe, +0x01, +0xfc, +0x1b, +0x3f, +0xf0, +0x0f, +0xe0, +0xf8, +0x07, +0xf0, +0x6f, +0xff, +0xef, +0x01, +0x80 +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c new file mode 100644 index 0000000000..3ec04e077d --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c @@ -0,0 +1,374 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Rev E HT PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// HT Phy T a b l e s +// ------------------------- +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevEHtPhyRegisters[] = +{ +// 0x60:0x68 + { + HtPhyRangeRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL0_ALL, // + 0x60, 0x68, // Address range + 0x00000040, // regData + 0x00000040, // regMask + } + }, +// 0x70:0x78 + { + HtPhyRangeRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL1_ALL, // + 0x70, 0x78, // Address range + 0x00000040, // regData + 0x00000040, // regMask + } + }, +// 0xC0 + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL0_ALL, // + 0xC0, // Address + 0x40040000, // regData + 0xe01F0000, // regMask + } + }, +// 0xD0 + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL1_ALL, // + 0xD0, // Address + 0x40040000, // regData + 0xe01F0000, // regMask + } + }, +// 0x520A + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL0_ALL, // + 0x520A, // Address + 0x00004000, // regData + 0x00006000, // regMask + } + }, +// 0x530A + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL1_ALL, // + 0x530A, // Address + 0x00004000, // regData + 0x00006000, // regMask + } + }, + + +// +// Deemphasis Settings +// + +// For C3, also set [7]TxLs23ClkGateEn. +//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6] +// No deemphasis 00h 00h 00h 0 0 0 0 +// -3dB postcursor 12h 00h 00h 1 0 0 0 +// -6dB postcursor 1Fh 00h 00h 1 0 0 0 +// -8dB postcursor 1Fh 06h 00h 1 1 0 1 +// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1 +// -11dB postcursor with +// -8dB precursor 1Fh 06h 07h 1 1 1 1 + + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL_NONE, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0x00000080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL_NONE, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0x00000080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__3, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0x80120080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__3, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0x80120080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__6, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0x801F0080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__6, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0x801F0080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__8, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0xC01F06C0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__8, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0xC01F06C0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0xC01F0DC0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0xC01F0DC0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11_8, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0xE01F06C7, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11_8, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0xE01F06C7, // regData + 0xE01F1FDF, // regMask + } + }, +}; + +CONST REGISTER_TABLE ROMDATA F10RevEHtPhyRegisterTable = { + PrimaryCores, + (sizeof (F10RevEHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F10RevEHtPhyRegisters +}; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c new file mode 100644 index 0000000000..cdfe9ad37e --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c @@ -0,0 +1,135 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Rev E, MSR tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RevEMsrRegisters[] = +{ +// M S R T a b l e s +// ---------------------- +// MSR_LS_CFG (0xC0011020) +// bit[1] = 0 + { + MsrRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MSR_LS_CFG, // MSR Address + 0x0000000000000000, // OR Mask + (1 << 1), // NAND Mask + } + }, + +// MSR_BU_CFG (0xC0011023) +// bit[21] = 1 + { + MsrRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MSR_BU_CFG, // MSR Address + (1 << 21), // OR Mask + (1 << 21), // NAND Mask + } + }, + +// MSR_BU_CFG2 (0xC001102A) +// bit[50] = 1 +// For GH rev C1 and later [RdMmExtCfgQwEn]=1 + { + MsrRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MSR_BU_CFG2, // MSR Address + 0x0004000000000000, // OR Mask + 0x0004000000000000, // NAND Mask + } + }, +}; + +CONST REGISTER_TABLE ROMDATA F10RevEMsrRegisterTable = { + AllCores, + (sizeof (F10RevEMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F10RevEMsrRegisters, +}; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c new file mode 100644 index 0000000000..333c830e21 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c @@ -0,0 +1,227 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Rev E PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10/RevE + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "F10PackageType.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// P C I T a b l e s +// ---------------------- + +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevEPciRegisters[] = +{ +// F0x68 - +// BufRelPri for rev E +// bits[14:13] BufRelPri = 1 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO(0, 0, 24, FUNC_0, 0x68), // Address + 0x00002000, // regData + 0x00006000, // regMask + } + }, + +// F0x16C - Link Global Extended Control Register +// bit[7:6] InLnSt = 0x01 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_SINGLE_LINK, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address + 0x0000C026, // regData + 0x0000E03F, // regMask + } + }, +// F0x16C - Link Global Extended Control Register +// bit[15:13] ForceFullT0 = 6 +// bit[9] RXCalEn = 1 +// bit[5:0] T0Time = 0x26 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_SINGLE_LINK, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address + 0x0000C226, // regData + 0x0000E23F, // regMask + } + }, +// F3x80 - ACPI Power State Control +// ACPI State C2 +// bits[0] CpuPrbEn = 1 +// bits[1] NbLowPwrEn = 0 +// bits[2] NbGateEn = 0 +// bits[3] NbCofChg = 0 +// bits[4] AltVidEn = 0 +// bits[7:5] ClkDivisor = 1 +// ACPI State C3, C1E or Link init +// bits[0] CpuPrbEn = 0 +// bits[1] NbLowPwrEn = 1 +// bits[2] NbGateEn = 1 +// bits[3] NbCofChg = 0 +// bits[4] AltVidEn = 0 +// bits[7:5] ClkDivisor = 7 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address + 0x0000E681, // regData + 0x0000FFFF, // regMask + } + }, +// F3xDC - Clock Power Timing Control 2 +// bits[14:12] NbsynPtrAdj = 6 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address + 0x00006000, // regData + 0x00007000, // regMask + } + }, +// F3x1C4 - L3 Power Control Register +// bits[8] L3PwrSavEn = 1 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1C4), // Address + 0x00000100, // regData + 0x00000100, // regMask + } + }, +// F3x188 - NB Extended Configuration Low Register +// bit[4] = EnStpGntOnFlushMaskWakeup + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address + 0x00000010, // regData + 0x00000010, // regMask + } + }, +// F4x15C - Core Performance Boost Control +// bits[1:0] BoostSrc = 0 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Ex // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address + 0x00000000, // regData + 0x00000003, // regMask + } + }, +}; + +CONST REGISTER_TABLE ROMDATA F10RevEPciRegisterTable = { + PrimaryCores, + (sizeof (F10RevEPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F10RevEPciRegisters, +}; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c new file mode 100644 index 0000000000..635c424131 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c @@ -0,0 +1,370 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 revision Ex specific utility functions. + * + * Provides numerous utility functions specific to family 10h rev E. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/F10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "cpuF10PowerMgmt.h" +#include "GeneralServices.h" +#include "cpuEarlyInit.h" +#include "cpuRegisters.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Set down core register on a revision E processor. + * + * This function set F3x190 Downcore Control Register[5:0] + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] Socket Socket ID. + * @param[in] Module Module ID in socket. + * @param[in] LeveledCores Number of core. + * @param[in] CoreLevelMode Core level mode. + * @param[in] StdHeader Header for library and services. + * + * @retval TRUE Down Core register is updated. + * @retval FALSE Down Core register is not updated. + */ +BOOLEAN +F10CommonRevESetDownCoreRegister ( + IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, + IN UINT32 *Socket, + IN UINT32 *Module, + IN UINT32 *LeveledCores, + IN CORE_LEVELING_TYPE CoreLevelMode, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempVar32_a; + UINT32 CoreDisableBits; + PCI_ADDR PciAddress; + BOOLEAN IsUpdated; + AGESA_STATUS AgesaStatus; + + IsUpdated = FALSE; + + switch (*LeveledCores) { + case 1: + CoreDisableBits = DOWNCORE_MASK_SINGLE; + break; + case 2: + CoreDisableBits = DOWNCORE_MASK_DUAL; + break; + case 3: + CoreDisableBits = DOWNCORE_MASK_TRI; + break; + case 4: + CoreDisableBits = DOWNCORE_MASK_FOUR; + break; + case 5: + CoreDisableBits = DOWNCORE_MASK_FIVE; + break; + default: + CoreDisableBits = 0; + break; + } + + if (CoreDisableBits != 0) { + if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) { + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG; + + LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); + TempVar32_a = ((TempVar32_a >> 12) & 0x3) | ((TempVar32_a >> 13) & 0x4); + if (TempVar32_a == 0) { + CoreDisableBits &= 0x1; + } else if (TempVar32_a == 1) { + CoreDisableBits &= 0x3; + } else if (TempVar32_a == 2) { + CoreDisableBits &= 0x7; + } else if (TempVar32_a == 3) { + CoreDisableBits &= 0x0F; + } else if (TempVar32_a == 4) { + CoreDisableBits &= 0x1F; + } else if (TempVar32_a == 5) { + CoreDisableBits &= 0x3F; + } + PciAddress.Address.Register = DOWNCORE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); + if ((TempVar32_a | CoreDisableBits) != TempVar32_a) { + TempVar32_a |= CoreDisableBits; + LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); + IsUpdated = TRUE; + } + } + } + + return IsUpdated; +} + + +CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling = +{ + 0, + F10CommonRevESetDownCoreRegister +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * Get CPU pstate current on a revision E processor. + * + * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}. + * + * This function returns the ProcIddMax. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] Pstate The P-state to check. + * @param[out] ProcIddMax P-state current in mA. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE P-state is enabled + * @retval FALSE P-state is disabled + */ +BOOLEAN +F10CommonRevEGetProcIddMax ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 Pstate, + OUT UINT32 *ProcIddMax, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 IddDiv; + UINT32 CmpCap; + UINT32 PciRegister; + UINT32 Socket; + UINT32 Module; + UINT32 Ignored; + UINT32 MsrAddress; + UINT32 MultiNodeCpu; + UINT64 PstateMsr; + BOOLEAN IsPstateEnabled; + PCI_ADDR PciAddress; + AGESA_STATUS IgnoredSts; + + IsPstateEnabled = FALSE; + + MsrAddress = (UINT32) (Pstate + PS_REG_BASE); + ASSERT (MsrAddress <= PS_MAX_REG); + + LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader); + if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) { + IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts); + GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); + + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = NB_CAPS_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8 + + switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) { + case 0: + IddDiv = 1000; + break; + case 1: + IddDiv = 100; + break; + case 2: + IddDiv = 10; + break; + default: // IddDiv = 3 is reserved. Use 10 + ASSERT (FALSE); + IddDiv = 10; + break; + } + MultiNodeCpu = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->MultiNodeCpu + 1); + CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapHi << 2); + CmpCap |= (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo); + CmpCap++; + *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap * MultiNodeCpu; + IsPstateEnabled = TRUE; + } + return IsPstateEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Determines the NB clock on the desired node. + * + * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. + * @param[in] NbPstate The NB P-state number to check. + * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz. + * @param[out] FreqDivisor The desired node's frequency divisor. + * @param[out] VoltageInuV The desired node's voltage in microvolts. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE NbPstate is valid + * @retval FALSE NbPstate is disabled or invalid + */ +BOOLEAN +F10CommonRevEGetNbPstateInfo ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR *PciAddress, + IN UINT32 NbPstate, + OUT UINT32 *FreqNumeratorInMHz, + OUT UINT32 *FreqDivisor, + OUT UINT32 *VoltageInuV, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 PciRegister; + UINT64 MsrRegister; + BOOLEAN PstateIsValid; + + PstateIsValid = FALSE; + if (NbPstate == 0) { + PciAddress->Address.Function = FUNC_3; + PciAddress->Address.Register = CPTC0_REG; + LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader); + *FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid + 4) * 200); + *FreqDivisor = 1; + LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); + *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid))); + PstateIsValid = TRUE; + } + return PstateIsValid; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns whether or not BIOS is responsible for configuring the NB COFVID. + * + * @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PciAddress The northbridge to query by pci base address. + * @param[out] NbVidUpdateAll Do all NbVids need to be updated + * @param[in] StdHeader Header for library and services + * + * @retval TRUE Perform northbridge frequency and voltage config. + * @retval FALSE Do not configure them. + */ +BOOLEAN +F10CommonRevEGetNbCofVidUpdate ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PCI_ADDR *PciAddress, + OUT BOOLEAN *NbVidUpdateAll, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ProductInfoRegister; + + PciAddress->Address.Register = PRCT_INFO_REG; + PciAddress->Address.Function = FUNC_3; + LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader); + *NbVidUpdateAll = (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbVidUpdateAll == 1); + return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get number of processor cores to be used in determining the brand string. + * + * @CpuServiceMethod{::F_CPU_NUMBER_OF_BRANDSTRING_CORES}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @return The number of cores to be used in brand string calculation. + */ +UINT8 +F10CommonRevEGetNumberOfCoresForBrandstring ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CmpCap; + UINT32 Socket; + UINT32 Module; + UINT32 Core; + UINT32 PciRegister; + PCI_ADDR PciAddress; + AGESA_STATUS IgnoredSts; + + IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); + GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = NB_CAPS_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); + CmpCap = (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapHi << 2); + CmpCap |= (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo); + + return (UINT8) (CmpCap + 1); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c new file mode 100644 index 0000000000..5e2724c716 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c @@ -0,0 +1,106 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Pharaoh Hound Equivalence Table related data + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + + +#define FILECODE PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST UINT16 ROMDATA CpuF10PhMicrocodeEquivalenceTable[] = +{ + 0x10a0, 0x10a0 +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the appropriate microcode patch equivalent ID table. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] PhEquivalenceTablePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF10PhMicrocodeEquivalenceTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **PhEquivalenceTablePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = ((sizeof (CpuF10PhMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); + *PhEquivalenceTablePtr = CpuF10PhMicrocodeEquivalenceTable; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c new file mode 100644 index 0000000000..131a10b5e2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c @@ -0,0 +1,118 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Pharaoh Hound Ht Phy tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// HT Phy T a b l e s +// ------------------------- +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10PhHtPhyRegisters[] = +{ +// 0x520A + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_PH_E0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL0_ALL, // + 0x520A, // Address + 0x00004000, // regData + 0x00006000, // regMask + } + }, +// 0x530A + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_PH_E0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL1_ALL, // + 0x530A, // Address + 0x00004000, // regData + 0x00006000, // regMask + } + }, +}; + +CONST REGISTER_TABLE ROMDATA F10PhHtPhyRegisterTable = { + PrimaryCores, + (sizeof (F10PhHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F10PhHtPhyRegisters, +}; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c new file mode 100644 index 0000000000..fdc83acd4f --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c @@ -0,0 +1,97 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Pharaoh Hound Logical ID Table + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10PhLogicalIdAndRevArray[] = +{ + { + 0x10a0, + AMD_F10_PH_E0 + }, +}; + +VOID +GetF10PhLogicalIdAndRev ( + OUT CONST CPU_LOGICAL_ID_XLAT **PhIdPtr, + OUT UINT8 *NumberOfElements, + OUT UINT64 *LogicalFamily, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = (sizeof (CpuF10PhLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)); + *PhIdPtr = CpuF10PhLogicalIdAndRevArray; + *LogicalFamily = AMD_FAMILY_10_PH; +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c new file mode 100644 index 0000000000..2748cb8640 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c @@ -0,0 +1,106 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Pharaoh Hound PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +extern CONST MICROCODE_PATCHES ROMDATA *CpuF10PhMicroCodePatchArray[]; +extern CONST UINT8 ROMDATA CpuF10PhNumberOfMicrocodePatches; + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns a table containing the appropriate microcode patches. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] PhUcodePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF10PhMicroCodePatchesStruct ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **PhUcodePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = CpuF10PhNumberOfMicrocodePatches; + *PhUcodePtr = &CpuF10PhMicroCodePatchArray[0]; +} + |