diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/HT/Fam10')
11 files changed, 2134 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.c new file mode 100644 index 0000000000..a346e514f9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.c @@ -0,0 +1,163 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Coherent Family 10h Routines. + * + * Coherent feature Northbridge implementation specific to Family 10h processors. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: HyperTransport + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Topology.h" +#include "htFeat.h" +#include "htNb.h" +#include "htNbHardwareFam10.h" +#include "htNbCoherentFam10.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Return whether the current configuration exceeds the capability. + * + * @HtNbMethod{::F_IS_EXCEEDED_CAPABLE}. + * + * Get Node capability and update the minimum supported system capability. + * + * @param[in] Node the Node + * @param[in] State sysMpCap (updated) and NodesDiscovered + * @param[in] Nb this northbridge + * + * @retval TRUE system is not capable of current config. + * @retval FALSE system is capable of current config. + */ +BOOLEAN +Fam10IsExceededCapable ( + IN UINT8 Node, + IN STATE_DATA *State, + IN NORTHBRIDGE *Nb + ) +{ + UINT32 Temp; + UINT8 MaxNodes; + PCI_ADDR Reg; + + ASSERT (Node < MAX_NODES); + + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_NB_FUNC_03, + REG_NB_CAPABILITY_3XE8); + + LibAmdPciReadBits (Reg, 18, 16, &Temp, Nb->ConfigHandle); + + if (Temp != 0) { + MaxNodes = (UINT8) (1 << (~Temp & 0x3)); // That is, 1, 2, 4, or 8 + } else { + MaxNodes = 8; + } + if (State->SysMpCap > MaxNodes) { + State->SysMpCap = MaxNodes; + } + // Note since sysMpCap is one based and NodesDiscovered is zero based, equal returns true + // + return ((BOOLEAN) (State->SysMpCap <= State->NodesDiscovered)); +} + +/** + * Stop a link, so that it is isolated from a connected device. + * + * @HtNbMethod{::F_STOP_LINK}. + * + * Use is for fatal incompatible configurations, or for user interface + * request to power off a link (IgnoreLink, SkipRegang). + * Set ConnDly to make the power effective at the warm reset. + * Set XMT and RCV off. + * + * @param[in] Node the node to stop a link on. + * @param[in] Link the link to stop. + * @param[in] State access to special routine for writing link control register + * @param[in] Nb this northbridge. + */ +VOID +Fam10StopLink ( + IN UINT8 Node, + IN UINT8 Link, + IN STATE_DATA *State, + IN NORTHBRIDGE *Nb + ) +{ + UINT32 Temp; + PCI_ADDR Reg; + + // Set ConnDly + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_HTNB_FUNC_00, + REG_LINK_GLOBAL_EXT_CONTROL_0x16C); + Temp = 1; + LibAmdPciWriteBits (Reg, 8, 8, &Temp, Nb->ConfigHandle); + // Set TransOff and EndOfChain + Reg = Nb->MakeLinkBase (Node, Link, Nb); + Reg.Address.Register += HTHOST_LINK_CONTROL_REG; + Temp = 3; + State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.h b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.h new file mode 100644 index 0000000000..747ffa3871 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.h @@ -0,0 +1,67 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Coherent Family 10h specific Routines. + * + * Coherent feature Northbridge implementation specific to Family 10h processors. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: HyperTransport + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/** + * Return whether the current configuration exceeds the capability. + * + */ +BOOLEAN +Fam10IsExceededCapable ( + IN UINT8 Node, + IN STATE_DATA *State, + IN NORTHBRIDGE *Nb + ); + +/** + * Stop a link, so that it is isolated from a connected device. + */ +VOID +Fam10StopLink ( + IN UINT8 Node, + IN UINT8 Link, + IN STATE_DATA *State, + IN NORTHBRIDGE *Nb + ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbFam10.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbFam10.c new file mode 100644 index 0000000000..b3c6702462 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbFam10.c @@ -0,0 +1,362 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initializers for Family 10h northbridge support. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: HyperTransport + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "OptionsHt.h" +#include "Ids.h" +#include "Topology.h" +#include "htFeat.h" +#include "htNb.h" +#include "CommonReturns.h" +#include "htNbCoherent.h" +#include "htNbCoherentFam10.h" +#include "htNbNonCoherent.h" +#include "htNbNonCoherentFam10.h" +#include "htNbOptimization.h" +#include "htNbOptimizationFam10.h" +#include "htNbSystemFam10.h" +#include "htNbUtilities.h" +#include "htNbUtilitiesFam10.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_HT_FAM10_HTNBFAM10_FILECODE + +extern OPTION_HT_CONFIGURATION OptionHtConfiguration; + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*************************************************************************** + *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** + ***************************************************************************/ + +/** + * Map Northbridge links to package links for Family 10h, Rev D, multi-module. + * + * Unfortunately, there is no way to do this except to type the BKDG text into this data structure. + * Note that there is one entry per package external sublink and each connected internal link. + */ +CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[] = +{ + {0, 0, 0}, ///< Module zero, link 0: package link 0 + {4, 0, 4}, ///< Module zero, link 4: package link 4 + {0, 1, 1}, ///< Module one, link 0: package link 1 + {4, 1, 5}, ///< Module one, link 4: package link 5 + {3, 0, 2}, ///< Module zero, link 3: package link 2 + {7, 0, 6}, ///< Module zero, link 7: package link 6 + {2, 0, 3}, ///< Module zero, link 2: package link 3 + {1, 1, 7}, ///< Module one, link 1: package link 7 + {1, 0, HT_LIST_MATCH_INTERNAL_LINK_0}, ///< Internal Link + {5, 0, HT_LIST_MATCH_INTERNAL_LINK_1}, ///< Internal Link + {6, 0, HT_LIST_MATCH_INTERNAL_LINK_2}, ///< Internal Link + {2, 1, HT_LIST_MATCH_INTERNAL_LINK_0}, ///< Internal Link + {6, 1, HT_LIST_MATCH_INTERNAL_LINK_1}, ///< Internal Link + {5, 1, HT_LIST_MATCH_INTERNAL_LINK_2}, ///< Internal Link + {HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL}, ///< End +}; + +/** + * A default Ignore Link list for rev D to power off the 3rd internal sublink. + */ +STATIC CONST IGNORE_LINK ROMDATA Fam10RevDIgnoreLinkList[] = { + HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK_2, POWERED_OFF, + HT_LIST_TERMINAL +}; + +/** + * Initial construction data for Family 10h North Bridge, default, full features. + */ +CONST NORTHBRIDGE ROMDATA HtFam10NbDefault = +{ + 8, + WriteRoutingTable, + WriteNodeID, + ReadDefaultLink, + EnableRoutingTables, + DisableRoutingTables, + VerifyLinkIsCoherent, + ReadToken, + WriteToken, + WriteFullRoutingTable, + IsIllegalTypeMix, + Fam10IsExceededCapable, + Fam10StopLink, + (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, + HandleSpecialNodeCase, + ReadSouthbridgeLink, + VerifyLinkIsNonCoherent, + Fam10SetConfigAddrMap, + Fam10NorthBridgeFreqMask, + GatherLinkFeatures, + SetLinkRegang, + SetLinkFrequency, + SetLinkUnitIdClumping, + Fam10WriteTrafficDistribution, + Fam10WriteLinkPairDistribution, + Fam10BufferOptimizations, + Fam10GetNumCoresOnNode, + SetTotalNodesAndCores, + GetNodeCount, + LimitNodes, + ReadTrueLinkFailStatus, + Fam10GetNextLink, + GetPackageLink, + MakeLinkBase, + Fam10GetModuleInfo, + Fam10PostMailbox, + Fam10RetrieveMailbox, + Fam10GetSocket, + (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, + (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, + 0x00000001, + 0x00000200, + 18, + TRUE, + TRUE, + ((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)), + NULL, + 0, + NULL, + MakeKey, + NULL +}; + +/** + * Initial construction data for Family 10h North Bridge, default, full features. + */ +CONST NORTHBRIDGE ROMDATA HtFam10RevDNbDefault = +{ + 8, + WriteRoutingTable, + WriteNodeID, + ReadDefaultLink, + EnableRoutingTables, + DisableRoutingTables, + VerifyLinkIsCoherent, + ReadToken, + WriteToken, + WriteFullRoutingTable, + IsIllegalTypeMix, + Fam10IsExceededCapable, + Fam10StopLink, + (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, + HandleSpecialNodeCase, + ReadSouthbridgeLink, + VerifyLinkIsNonCoherent, + Fam10SetConfigAddrMap, + Fam10RevDNorthBridgeFreqMask, + GatherLinkFeatures, + SetLinkRegang, + SetLinkFrequency, + SetLinkUnitIdClumping, + Fam10WriteTrafficDistribution, + Fam10WriteLinkPairDistribution, + Fam10RevDBufferOptimizations, + Fam10RevDGetNumCoresOnNode, + SetTotalNodesAndCores, + GetNodeCount, + LimitNodes, + ReadTrueLinkFailStatus, + Fam10GetNextLink, + GetPackageLink, + MakeLinkBase, + Fam10GetModuleInfo, + Fam10PostMailbox, + Fam10RetrieveMailbox, + Fam10RevDGetSocket, + (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, + (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, + 0x00000001, + 0x00000200, + 18, + TRUE, + TRUE, + (AMD_FAMILY_10_HY | AMD_FAMILY_10_PH), + (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap, + 0, + (IGNORE_LINK *)&Fam10RevDIgnoreLinkList, + MakeKey, + NULL +}; + +/** + * Initial construction data for Family 10h North Bridge, for non-coherent only builds. + */ +CONST NORTHBRIDGE ROMDATA HtFam10NbNonCoherentOnly = +{ + 8, + (PF_WRITE_ROUTING_TABLE)CommonVoid, + (PF_WRITE_NODEID)CommonVoid, + (PF_READ_DEFAULT_LINK)CommonReturnZero8, + (PF_ENABLE_ROUTING_TABLES)CommonVoid, + (PF_DISABLE_ROUTING_TABLES)CommonVoid, + (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse, + (PF_READ_TOKEN)CommonReturnZero8, + (PF_WRITE_TOKEN)CommonVoid, + (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid, + (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse, + (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse, + (PF_STOP_LINK)CommonVoid, + (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, + (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse, + ReadSouthbridgeLink, + VerifyLinkIsNonCoherent, + Fam10SetConfigAddrMap, + Fam10NorthBridgeFreqMask, + GatherLinkFeatures, + SetLinkRegang, + SetLinkFrequency, + SetLinkUnitIdClumping, + (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid, + (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid, + Fam10BufferOptimizations, + Fam10GetNumCoresOnNode, + SetTotalNodesAndCores, + GetNodeCount, + LimitNodes, + ReadTrueLinkFailStatus, + Fam10GetNextLink, + GetPackageLink, + MakeLinkBase, + Fam10GetModuleInfo, + Fam10PostMailbox, + Fam10RetrieveMailbox, + Fam10GetSocket, + (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, + (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, + 0x00000001, + 0x00000200, + 18, + TRUE, + TRUE, + ((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)), + NULL, + 0, + NULL, + MakeKey, + NULL +}; + +/** + * Initial construction data for Family 10h North Bridge, for RevD compatible non-coherent only builds. + */ +CONST NORTHBRIDGE ROMDATA HtFam10RevDNbNonCoherentOnly = +{ + 8, + (PF_WRITE_ROUTING_TABLE)CommonVoid, + (PF_WRITE_NODEID)CommonVoid, + (PF_READ_DEFAULT_LINK)CommonReturnZero8, + (PF_ENABLE_ROUTING_TABLES)CommonVoid, + (PF_DISABLE_ROUTING_TABLES)CommonVoid, + (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse, + (PF_READ_TOKEN)CommonReturnZero8, + (PF_WRITE_TOKEN)CommonVoid, + (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid, + (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse, + (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse, + (PF_STOP_LINK)CommonVoid, + (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, + (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse, + ReadSouthbridgeLink, + VerifyLinkIsNonCoherent, + Fam10SetConfigAddrMap, + Fam10RevDNorthBridgeFreqMask, + GatherLinkFeatures, + SetLinkRegang, + SetLinkFrequency, + SetLinkUnitIdClumping, + (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid, + (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid, + Fam10BufferOptimizations, + Fam10RevDGetNumCoresOnNode, + SetTotalNodesAndCores, + GetNodeCount, + LimitNodes, + ReadTrueLinkFailStatus, + Fam10GetNextLink, + GetPackageLink, + MakeLinkBase, + Fam10GetModuleInfo, + Fam10PostMailbox, + Fam10RetrieveMailbox, + Fam10GetSocket, + (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, + (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, + 0x00000001, + 0x00000200, + 18, + TRUE, + TRUE, + (AMD_FAMILY_10_HY | AMD_FAMILY_10_PH), + NULL, + 0, + NULL, + MakeKey, + NULL +}; diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.c new file mode 100644 index 0000000000..18d6da33bb --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.c @@ -0,0 +1,121 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Northbridge non-coherent support for Family 10h processors. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: HyperTransport + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Topology.h" +#include "htFeat.h" +#include "htNb.h" +#include "htNbHardwareFam10.h" +#include "htNbNonCoherentFam10.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable config access to a non-coherent chain for the given bus range. + * + * @HtNbMethod{::F_SET_CONFIG_ADDR_MAP} + * + * @param[in] ConfigMapIndex the map entry to set + * @param[in] SecBus The secondary bus number to use + * @param[in] SubBus The subordinate bus number to use + * @param[in] TargetNode The Node that shall be the recipient of the traffic + * @param[in] TargetLink The Link that shall be the recipient of the traffic + * @param[in] State our global state + * @param[in] Nb this northbridge + */ +VOID +Fam10SetConfigAddrMap ( + IN UINT8 ConfigMapIndex, + IN UINT8 SecBus, + IN UINT8 SubBus, + IN UINT8 TargetNode, + IN UINT8 TargetLink, + IN STATE_DATA *State, + IN NORTHBRIDGE *Nb + ) +{ + UINT8 CurNode; + PCI_ADDR Reg; + UINT32 Temp; + + Reg = Nb->MakeLinkBase (TargetNode, TargetLink, Nb); + + ASSERT (SecBus <= SubBus); + ASSERT (TargetNode <= State->NodesDiscovered); + ASSERT (TargetLink < Nb->MaxLinks); + Temp = SecBus; + Reg.Address.Register += HTHOST_ISOC_REG; + LibAmdPciWriteBits (Reg, 15, 8, &Temp, Nb->ConfigHandle); + + Temp = ((UINT32)SubBus << 24) + ((UINT32)SecBus << 16) + ((UINT32)TargetLink << 8) + + ((UINT32)TargetNode << 4) + (UINT32)3; + for (CurNode = 0; CurNode < (State->NodesDiscovered + 1); CurNode++) { + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (CurNode), + MakePciBusFromNode (CurNode), + MakePciDeviceFromNode (CurNode), + CPU_ADDR_FUNC_01, + REG_ADDR_CONFIG_MAP0_1XE0 + (4 * ConfigMapIndex)); + LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle); + } +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.h b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.h new file mode 100644 index 0000000000..3eb1350a6d --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.h @@ -0,0 +1,58 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Northbridge non-coherent support for Family 10h processors. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: HyperTransport + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/** + * Enable config access to a non-coherent chain for the given bus range. + * + */ +VOID +Fam10SetConfigAddrMap ( + IN UINT8 ConfigMapIndex, + IN UINT8 SecBus, + IN UINT8 SubBus, + IN UINT8 TargetNode, + IN UINT8 TargetLink, + IN STATE_DATA *State, + IN NORTHBRIDGE *Nb + ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbOptimizationFam10.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbOptimizationFam10.c new file mode 100644 index 0000000000..2ae1676e7e --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbOptimizationFam10.c @@ -0,0 +1,222 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Link optimization support specific to family 10h processors. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: HyperTransport + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "Topology.h" +#include "htFeat.h" +#include "htInterface.h" +#include "htNb.h" +#include "htNbOptimizationFam10.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Northbridge specific Frequency limit. + * + * @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK} + * + * Return a mask that eliminates HT frequencies that cannot be used due to a slow + * northbridge frequency. + * + * @param[in] Node Result could (later) be for a specific Node + * @param[in] Interface Access to non-HT support functions. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] Nb this northbridge + * + * @return Frequency mask + */ +UINT32 +Fam10NorthBridgeFreqMask ( + IN UINT8 Node, + IN HT_INTERFACE *Interface, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN NORTHBRIDGE *Nb + ) +{ + UINT32 NbCoreFreq; + UINT32 Supported; + + ASSERT (Node < MAX_NODES); + ASSERT (Interface != NULL); + // The interface to power management will return a system based result. + // So we only need to call it once, not on every link. Save the answer, + // and check to see if we can use a saved answer on subsequent calls. + // + if (Nb->CoreFrequency == 0) { + NbCoreFreq = Interface->GetMinNbCoreFreq (PlatformConfig, Nb->ConfigHandle); + NbCoreFreq = (NbCoreFreq / 100); + ASSERT (NbCoreFreq != 0); + Nb->CoreFrequency = NbCoreFreq; + } else { + NbCoreFreq = Nb->CoreFrequency; + } + + // + // NbCoreFreq is minimum northbridge speed in hundreds of MHz. + // HT can not go faster than the minimum speed of the northbridge. + // + if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) { + // Convert frequency to bit and all less significant bits, + // by setting next power of 2 and subtracting 1. + // + Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1; + } else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) { + // Convert frequency to bit and all less significant bits, + // by setting next power of 2 and subtracting 1, noting that + // next power of two is two greater than non-extended frequencies + // (because of the register break). + // + Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1; + } else if (NbCoreFreq > 32) { + Supported = HT_FREQUENCY_LIMIT_MAX; + } else if (NbCoreFreq == 4) { + // unlikely cases, but include as a defensive measure, also avoid trick above + Supported = HT_FREQUENCY_LIMIT_400M; + } else if (NbCoreFreq == 2) { + Supported = HT_FREQUENCY_LIMIT_200M; + } else { + ASSERT (FALSE); + Supported = HT_FREQUENCY_LIMIT_200M; + } + + return (Supported); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Northbridge specific Frequency limit. + * + * @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK} + * + * Return a mask that eliminates HT frequencies that cannot be used due to a slow + * northbridge frequency. + * + * @param[in] Node Result could (later) be for a specific Node + * @param[in] Interface Access to non-HT support functions. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] Nb this northbridge + * + * @return Frequency mask + */ +UINT32 +Fam10RevDNorthBridgeFreqMask ( + IN UINT8 Node, + IN HT_INTERFACE *Interface, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN NORTHBRIDGE *Nb + ) +{ + UINT32 NbCoreFreq; + UINT32 Supported; + + ASSERT (Node < MAX_NODES); + ASSERT (Interface != NULL); + // The interface to power management will return a system based result. + // So we only need to call it once, not on every link. Save the answer, + // and check to see if we can use a saved answer on subsequent calls. + // + if (Nb->CoreFrequency == 0) { + NbCoreFreq = Interface->GetMinNbCoreFreq (PlatformConfig, Nb->ConfigHandle); + NbCoreFreq = (NbCoreFreq / 100); + ASSERT (NbCoreFreq != 0); + Nb->CoreFrequency = NbCoreFreq; + } else { + NbCoreFreq = Nb->CoreFrequency; + } + + // For Rev D, the Ht frequency can go twice the Nb COF, as long as it's HT3. + // (side note: we are not speculatively upgrading HT1 at 6 .. 10 to HT3, + // to avoid complicated recovery if the final speed is HT1.) + if (NbCoreFreq > 10) { + NbCoreFreq = NbCoreFreq * 2; + } + // + // NbCoreFreq is minimum northbridge speed in hundreds of MHz. + // HT can not go faster than the minimum speed of the northbridge. + // + if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) { + // Convert frequency to bit and all less significant bits, + // by setting next power of 2 and subtracting 1. + // + Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1; + } else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) { + // Convert frequency to bit and all less significant bits, + // by setting next power of 2 and subtracting 1, noting that + // next power of two is two greater than non-extended frequencies + // (because of the register break). + // + Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1; + } else if (NbCoreFreq > 32) { + Supported = HT_FREQUENCY_LIMIT_MAX; + } else if (NbCoreFreq == 4) { + // unlikely cases, but include as a defensive measure, also avoid trick above + Supported = HT_FREQUENCY_LIMIT_400M; + } else if (NbCoreFreq == 2) { + Supported = HT_FREQUENCY_LIMIT_200M; + } else { + ASSERT (FALSE); + Supported = HT_FREQUENCY_LIMIT_200M; + } + + return (Supported); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbOptimizationFam10.h b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbOptimizationFam10.h new file mode 100644 index 0000000000..4442141dab --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbOptimizationFam10.h @@ -0,0 +1,74 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Link optimization support specific to family 10h processors. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: HyperTransport + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +/** + * Northbridge specific Frequency limit. + * + */ +UINT32 +Fam10NorthBridgeFreqMask ( + IN UINT8 Node, + IN HT_INTERFACE *Interface, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN NORTHBRIDGE *Nb + ); + +/** + * Northbridge specific Frequency limit. + * + */ +UINT32 +Fam10RevDNorthBridgeFreqMask ( + IN UINT8 Node, + IN HT_INTERFACE *Interface, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN NORTHBRIDGE *Nb + ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c new file mode 100644 index 0000000000..5fee550fea --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c @@ -0,0 +1,402 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * System Tuning Family 10h specific routines + * + * Support for Traffic Distribution and buffer tunings which + * can not be done in a register table. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: HyperTransport + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Topology.h" +#include "htFeat.h" +#include "htInterface.h" +#include "htNb.h" +#include "htNbHardwareFam10.h" +#include "htNbSystemFam10.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/** + * Register Fields for an individual link pair. + */ +typedef struct { + UINT32 Enable:1; ///< Enable distribution on this pair. + UINT32 Asymmetric:1; ///< Links are different widths. + UINT32 MasterSelect:3; ///< The master link. + UINT32 AlternateSelect:3; ///< The alternate link. +} PAIR_SELECT_FIELDS; + +/** + * Register access union for ::PAIR_SELECT_FIELDS. + */ +typedef union { + UINT32 Value; ///< access as a 32 bit value or register. + PAIR_SELECT_FIELDS Fields; ///< access individual fields. +} PAIR_SELECT; + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*************************************************************************** + *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** + ***************************************************************************/ + +/*----------------------------------------------------------------------------------------*/ +/** + * Set the traffic distribution register for the Links provided. + * + * @HtNbMethod{::F_WRITE_TRAFFIC_DISTRIBUTION} + * + * @param[in] Links01 coherent Links from Node 0 to 1 + * @param[in] Links10 coherent Links from Node 1 to 0 + * @param[in] Nb this northbridge + */ +VOID +Fam10WriteTrafficDistribution ( + IN UINT32 Links01, + IN UINT32 Links10, + IN NORTHBRIDGE *Nb + ) +{ + UINT32 Temp; + PCI_ADDR TrafficDistReg; + + TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0), + MakePciBusFromNode (0), + MakePciDeviceFromNode (0), + CPU_HTNB_FUNC_00, + REG_HT_TRAFFIC_DIST_0X164); + + // Node 0 + // DstLnk + LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links01, Nb->ConfigHandle); + // DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 + Temp = 0x0107; + LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle); + + TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (1), + MakePciBusFromNode (1), + MakePciDeviceFromNode (1), + CPU_HTNB_FUNC_00, + REG_HT_TRAFFIC_DIST_0X164); + + // Node 1 + // DstLnk + LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links10, Nb->ConfigHandle); + // DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 + Temp = 0x0007; + LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write a link pair to the link pair distribution and fixups. + * + * @HtNbMethod{::F_WRITE_LINK_PAIR_DISTRIBUTION} + * + * Set the links as a pair using the link pair index provided. Set asymmetric attribute as + * provided. If the Master Link is not currently used as the route, fixup the routes for all + * nodes which specify the alternate link. + * + * @param[in] Node Set the pair on this node + * @param[in] ConnectedNode The Node to which this link pair directly connects. + * @param[in] Pair Using this pair set in the register + * @param[in] Asymmetric True if different widths + * @param[in] MasterLink Set this as the master link and in the route + * @param[in] AlternateLink Set this as the alternate link + * @param[in] Nb this northbridge + * + */ +VOID +Fam10WriteLinkPairDistribution ( + IN UINT8 Node, + IN UINT8 ConnectedNode, + IN UINT8 Pair, + IN BOOLEAN Asymmetric, + IN UINT8 MasterLink, + IN UINT8 AlternateLink, + IN NORTHBRIDGE *Nb + ) +{ + PCI_ADDR Reg; + UINT32 CurrentRoute; + UINT32 MasterRoute; + UINT32 AlternateRoute; + PAIR_SELECT Selection; + UINT32 RouteIndex; + + ASSERT ((Node < MAX_NODES) && (ConnectedNode < MAX_NODES)); + ASSERT (Pair < MAX_LINK_PAIRS); + ASSERT (MasterLink < Nb->MaxLinks); + ASSERT (AlternateLink < Nb->MaxLinks); + + // Make the master link the route for all routes to or through NodeB, by replacing all occurrences of + // Alternate link with Master link. If routing used the master link, no update is necessary. + MasterRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (MasterLink + 1)); + AlternateRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (AlternateLink + 1)); + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_HTNB_FUNC_00, + REG_ROUTE0_0X40); + for (RouteIndex = 0; RouteIndex < MAX_NODES; RouteIndex++) { + Reg.Address.Register = REG_ROUTE0_0X40 + (RouteIndex * 4); + LibAmdPciReadBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle); + if ((CurrentRoute & AlternateRoute) != 0) { + // Since Master and Alternate are redundant, the route must use one or the other but not both. + ASSERT ((CurrentRoute & MasterRoute) == 0); + // Set the master route for Request, Response or Broadcast only if the alternate was used for that case. + // Example, use of a link as a broadcast link is typically not the same route register as its use for Request, Response. + CurrentRoute = ((CurrentRoute & ~AlternateRoute) | + ((((CurrentRoute & AlternateRoute) >> (AlternateLink + 1)) << (MasterLink + 1)) & MasterRoute)); + LibAmdPciWriteBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle); + } + } + + // Set the Link Pair and Enable it + Selection.Fields.Enable = 1; + Selection.Fields.Asymmetric = Asymmetric; + Selection.Fields.MasterSelect = MasterLink; + Selection.Fields.AlternateSelect = AlternateLink; + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_HTNB_FUNC_00, + REG_HT_LINK_PAIR_DIST_0X1E0); + LibAmdPciWriteBits ( + Reg, + ((PAIR_SELECT_OFFSET * (Pair + 1)) - 1), + (PAIR_SELECT_OFFSET * Pair), + &Selection.Value, + Nb->ConfigHandle + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Family 10h specific tunings. + * + * @HtNbMethod{::F_BUFFER_OPTIMIZATIONS} + * + * Buffer tunings are inherently northbridge specific. Check for specific configs + * which require adjustments and apply any standard workarounds to this Node. + * + * @param[in] Node the Node to tune + * @param[in] State global state + * @param[in] Nb this northbridge + */ +VOID +Fam10BufferOptimizations ( + IN UINT8 Node, + IN STATE_DATA *State, + IN NORTHBRIDGE *Nb + ) +{ + UINT32 Temp; + PCI_ADDR currentPtr; + PCI_ADDR GangedReg; + UINT8 i; + + ASSERT (Node < MAX_NODES); + + // + // Link to XCS Token Count Tuning + // + // For each active Link that we reganged (so this unfortunately can't go into the PCI reg + // table), we have to switch the Link to XCS Token Counts to the ganged state. + // We do this here for the non - uma case, which is to write the values that would have + // been power on defaults if the Link was ganged at cold reset. + // + for (i = 0; i < (State->TotalLinks * 2); i++) { + if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) { + // If the Link is greater than 4, this is a subLink 1, so it is not reganged. + if ((*State->PortList)[i].Link < 4) { + currentPtr.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_NB_FUNC_03, + REG_NB_LINK_XCS_TOKEN0_3X148 + (4 * (*State->PortList)[i].Link) + ); + if ((*State->PortList)[i].SelRegang) { + // Handle all the regang Token count adjustments + + // SubLink 0: [Probe0tok] = 2 [Rsp0tok] = 2 [PReq0tok] = 2 [Req0tok] = 2 + Temp = 0xAA; + LibAmdPciWriteBits (currentPtr, 7, 0, &Temp, Nb->ConfigHandle); + // SubLink 1: [Probe1tok] = 0 [Rsp1tok] = 0 [PReq1tok] = 0 [Req1tok] = 0 + Temp = 0; + LibAmdPciWriteBits (currentPtr, 23, 16, &Temp, Nb->ConfigHandle); + // [FreeTok] = 3 + Temp = 3; + LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle); + + } else { + // Read the regang bit in hardware + GangedReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode ((*State->PortList)[i].NodeID), + MakePciBusFromNode ((*State->PortList)[i].NodeID), + MakePciDeviceFromNode ((*State->PortList)[i].NodeID), + CPU_HTNB_FUNC_00, + REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link)); + LibAmdPciReadBits (GangedReg, 0, 0, &Temp, Nb->ConfigHandle); + if (Temp == 1) { + // handle a minor adjustment for strapped ganged Links. If SelRegang is false we + // didn't do the regang, so if the bit is on then it's hardware strapped. + // + + // [FreeTok] = 3 + Temp = 3; + LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle); + } + } + } + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Family 10h specific tunings. + * + * @HtNbMethod{::F_BUFFER_OPTIMIZATIONS} + * + * Buffer tunings are inherently northbridge specific. Check for specific configs + * which require adjustments and apply any standard workarounds to this Node. + * + * @param[in] Node the Node to tune + * @param[in] State global state + * @param[in] Nb this northbridge + */ +VOID +Fam10RevDBufferOptimizations ( + IN UINT8 Node, + IN STATE_DATA *State, + IN NORTHBRIDGE *Nb + ) +{ + UINT32 Temp; + PCI_ADDR Reg; + UINT8 i; + FINAL_LINK_STATE FinalLinkState; + UINT32 WidthIn; + UINT32 WidthOut; + + ASSERT (Node < MAX_NODES); + + // + // Internal link fixup. + // When powering off internal link 2, a performance optimization may be possible where its buffers + // can be made available to the external paired sublink. If the conditions are met, do the fix up here. + // + for (i = 0; i < (State->TotalLinks * 2); i++) { + if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) { + // Is this a sublink 0 paired with internal link 2? + if (((*State->PortList)[i].Link < 4) && + (Nb->GetPackageLink (Node, ((*State->PortList)[i].Link + 4), Nb) == HT_LIST_MATCH_INTERNAL_LINK_2)) { + FinalLinkState = State->HtInterface->GetIgnoreLink (Node, ((*State->PortList)[i].Link + 4), Nb->DefaultIgnoreLinkList, State); + // Are we ignoring the internal link 2 with Power Off? + if (FinalLinkState == POWERED_OFF) { + // Read the regang bit in hardware. + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_HTNB_FUNC_00, + REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link)); + LibAmdPciReadBits (Reg, 0, 0, &Temp, Nb->ConfigHandle); + // If it's already ganged, skip to the width fix up. + if (Temp == 0) { + // Clear EndOfChain / XmitOff on internal sublink + Reg = Nb->MakeLinkBase (Node, ((*State->PortList)[i].Link + 4), Nb); + Reg.Address.Register += HTHOST_LINK_CONTROL_REG; + Temp = 0; + State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State); + + // Gang the link + Nb->SetLinkRegang (Node, (*State->PortList)[i].Link, Nb); + } + + // Set InLnSt = PHY_OFF in register table. + // Set sublink 0 widths to 8 bits + if ((*State->PortList)[i].SelWidthOut > 8) { + (*State->PortList)[i].SelWidthOut = 8; + } + if ((*State->PortList)[i].SelWidthIn > 8) { + (*State->PortList)[i].SelWidthIn = 8; + } + WidthOut = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthOut); + WidthIn = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthIn); + Temp = (WidthIn & 7) | ((WidthOut & 7) << 4); + Reg = Nb->MakeLinkBase (Node, (*State->PortList)[i].Link, Nb); + Reg.Address.Register += HTHOST_LINK_CONTROL_REG; + State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State); + } + } + } + } +} + diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.h b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.h new file mode 100644 index 0000000000..50b7820f95 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.h @@ -0,0 +1,91 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * System Tuning Family 10h specific routines + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: HyperTransport + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/** + * Set the traffic distribution register for the Links provided. + * + */ +VOID +Fam10WriteTrafficDistribution ( + IN UINT32 Links01, + IN UINT32 Links10, + IN NORTHBRIDGE *Nb + ); + +/** + * Write a link pair to the link pair distribution and fixups. + * + */ +VOID +Fam10WriteLinkPairDistribution ( + IN UINT8 Node, + IN UINT8 ConnectedNode, + IN UINT8 Pair, + IN BOOLEAN Asymmetric, + IN UINT8 MasterLink, + IN UINT8 AlternateLink, + IN NORTHBRIDGE *Nb + ); + +/** + * Family 10h specific tunings. + * + */ +VOID +Fam10BufferOptimizations ( + IN UINT8 Node, + IN STATE_DATA *State, + IN NORTHBRIDGE *Nb + ); + +/** + * Family 10h Rev D specific tunings. + * + */ +VOID +Fam10RevDBufferOptimizations ( + IN UINT8 Node, + IN STATE_DATA *State, + IN NORTHBRIDGE *Nb + ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.c new file mode 100644 index 0000000000..5a089e150a --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.c @@ -0,0 +1,445 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Northbridge utility routines. + * + * These routines are needed for support of more than one feature area. + * Collect them in this file so build options don't remove them. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: HyperTransport + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Topology.h" +#include "htFeat.h" +#include "htNb.h" +#include "htNbHardwareFam10.h" +#include "htNbUtilitiesFam10.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Return the number of cores (1 based count) on Node. + * + * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE} + * + * @param[in] Node the Node that will be examined + * @param[in] Nb this northbridge + * + * @return the number of cores + */ +UINT8 +Fam10GetNumCoresOnNode ( + IN UINT8 Node, + IN NORTHBRIDGE *Nb + ) +{ + UINT32 Result; + UINT32 Leveling; + UINT32 Cores; + UINT8 i; + PCI_ADDR Reg; + + ASSERT ((Node < MAX_NODES)); + // Read CmpCap + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_NB_FUNC_03, + REG_NB_CAPABILITY_3XE8); + + LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle); + + // Support Downcoring + Result = Cores; + Cores++; + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_NB_FUNC_03, + REG_NB_DOWNCORE_3X190); + LibAmdPciReadBits (Reg, 3, 0, &Leveling, Nb->ConfigHandle); + for (i = 0; i < Cores; i++) { + if ((Leveling & ((UINT32) 1 << i)) != 0) { + Result--; + } + } + return (UINT8) (Result + 1); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Return the number of cores (1 based count) on Node. + * + * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}. + * + * @param[in] Node the Node that will be examined + * @param[in] Nb this northbridge + * + * @return the number of cores + */ +UINT8 +Fam10RevDGetNumCoresOnNode ( + IN UINT8 Node, + IN NORTHBRIDGE *Nb + ) +{ + UINT32 Result; + UINT32 Leveling; + UINT32 Cores; + UINT32 Cores2; + UINT8 i; + PCI_ADDR Reg; + + ASSERT ((Node < MAX_NODES)); + // Read CmpCap + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_NB_FUNC_03, + REG_NB_CAPABILITY_3XE8); + + LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle); + LibAmdPciReadBits (Reg, 15, 15, &Cores2, Nb->ConfigHandle); + Cores = Cores + (Cores2 << 2); + + // Support Downcoring + Result = Cores; + Cores++; + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_NB_FUNC_03, + REG_NB_DOWNCORE_3X190); + LibAmdPciReadBits (Reg, 5, 0, &Leveling, Nb->ConfigHandle); + for (i = 0; i < Cores; i++) { + if ((Leveling & ((UINT32) 1 << i)) != 0) { + Result--; + } + } + return (UINT8) (Result + 1); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the next link for iterating over the links on a node in the correct order. + * + * @HtNbMethod{::F_GET_NEXT_LINK} + * + * Family 10h specific implementation use the Internal Link field in + * the northbridge to prioritize internal links in the order. + * + * @param[in] Node The node on which to iterate links. + * @param[in,out] Link IN: the current iteration context, OUT: the next link. + * @param[in] Nb This Northbridge, access to config pointer. + * + * @retval LinkIteratorExternal The current Link is an external link. + * @retval LinkIteratorInternal The current Link is an internal link. + * @retval LinkIteratorEnd There is no next link (Link is back to BEGIN). + * + */ +LINK_ITERATOR_STATUS +Fam10GetNextLink ( + IN UINT8 Node, + IN OUT UINT8 *Link, + IN NORTHBRIDGE *Nb + ) +{ + PCI_ADDR Reg; + UINT32 InternalLinks; + UINT32 ExternalLinks; + UINT32 HigherLinks; + BOOLEAN IsInternalLink; + LINK_ITERATOR_STATUS Status; + + ASSERT ((Node < MAX_NODES)); + ASSERT ((*Link < Nb->MaxLinks) || (*Link == LINK_ITERATOR_BEGIN)); + InternalLinks = 0; + ExternalLinks = 0; + + // Read IntLnkRoute from the Link Initialization Status register. + // (Note that this register field is not reserved prior to rev D, but should be zero.) + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_HTNB_FUNC_00, + REG_HT_LINK_INITIALIZATION_0X1A0); + + LibAmdPciReadBits (Reg, 23, 16, &InternalLinks, Nb->ConfigHandle); + // The external links are all possible links which are not Internal + ExternalLinks = (((1 << Nb->MaxLinks) - 1) ^ InternalLinks); + // Can't have no possible links! + ASSERT ((ExternalLinks != 0) || (InternalLinks != 0)); + + + if (*Link == LINK_ITERATOR_BEGIN) { + // If the request is for the first link (BEGIN), get it + if (InternalLinks != 0) { + *Link = LibAmdBitScanForward (InternalLinks); + Status = LinkIteratorInternal; + } else { + *Link = LibAmdBitScanForward (ExternalLinks); + Status = LinkIteratorExternal; + } + } else { + // If the iterator is not at the beginning, search for the next Link starting from the + // current link. + HigherLinks = InternalLinks & ~((1 << (*Link + 1)) - 1); + IsInternalLink = (BOOLEAN) ((InternalLinks & (1 << *Link)) != 0); + if (IsInternalLink && (HigherLinks != 0)) { + // We are still on internal links and there are more to do. + *Link = LibAmdBitScanForward (HigherLinks); + Status = LinkIteratorInternal; + } else { + if (IsInternalLink) { + // We are transitioning now from internal to external, so get the first external link + HigherLinks = ExternalLinks; + } else { + // We are already iterating over external links, so get the next one + HigherLinks = ExternalLinks & ~((1 << (*Link + 1)) - 1); + } + if (HigherLinks != 0) { + *Link = LibAmdBitScanForward (HigherLinks); + Status = LinkIteratorExternal; + } else { + // The end of all links + *Link = LINK_ITERATOR_BEGIN; + Status = LinkIteratorEnd; + } + } + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Info about Module Type of this northbridge + * + * @HtNbMethod{::F_GET_MODULE_INFO} + * + * Provide the Processor module type, single or multi, and the node's module id. + * + * @param[in] Node the Node + * @param[out] ModuleType 0 for Single, 1 for Multi + * @param[out] Module The module number of this node (0 if Single) + * @param[in] Nb this northbridge + * + */ +VOID +Fam10GetModuleInfo ( + IN UINT8 Node, + OUT UINT8 *ModuleType, + OUT UINT8 *Module, + IN NORTHBRIDGE *Nb + ) +{ + PCI_ADDR Reg; + UINT32 MultNodeCpu; + UINT32 IntNodeNum; + + ASSERT (Node < MAX_NODES); + + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_NB_FUNC_03, + REG_NB_CAPABILITY_3XE8); + LibAmdPciReadBits (Reg, 29, 29, &MultNodeCpu, Nb->ConfigHandle); + LibAmdPciReadBits (Reg, 31, 30, &IntNodeNum, Nb->ConfigHandle); + + *ModuleType = (UINT8) MultNodeCpu; + *Module = (UINT8) IntNodeNum; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. + * + * @HtNbMethod{::F_GET_SOCKET} + * + * The hardware socket naming method is not available for Family 10h prior to rev D. + * + * @param[in] Node The node for which we want the socket id. + * @param[in] TempNode The temporary node id route where the node can be accessed. + * @param[in] Nb Our Northbridge. + * + * @return The Socket Id + */ +UINT8 +Fam10GetSocket ( + IN UINT8 Node, + IN UINT8 TempNode, + IN NORTHBRIDGE *Nb + ) +{ + ASSERT ((Node < MAX_NODES)); + ASSERT (TempNode < MAX_NODES); + ASSERT (Nb != NULL); + return (Node); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. + * + * @HtNbMethod{::F_GET_SOCKET} + * + * The Socket Id is strapped to the Sbi Control Register, F3X1E4[6:4]SbiAddr. + * + * @param[in] Node The node for which we want the socket id. + * @param[in] TempNode The temporary node id route where the node can be accessed. + * @param[in] Nb Our Northbridge. + * + * @return The Socket Id + */ +UINT8 +Fam10RevDGetSocket ( + IN UINT8 Node, + IN UINT8 TempNode, + IN NORTHBRIDGE *Nb + ) +{ + UINT32 Socket; + PCI_ADDR Reg; + + ASSERT ((TempNode < MAX_NODES)); + ASSERT ((Node < MAX_NODES)); + // Read SbiAddr + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (TempNode), + MakePciBusFromNode (TempNode), + MakePciDeviceFromNode (TempNode), + CPU_NB_FUNC_03, + REG_NB_SBI_CONTROL_3X1E4); + LibAmdPciReadBits (Reg, 6, 4, &Socket, Nb->ConfigHandle); + return ((UINT8) Socket); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Post info to AP cores via a mailbox. + * + * @HtNbMethod{::F_POST_MAILBOX} + * + * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id, + * and module info. + * + * @param[in] Node the Node + * @param[in] ApMailboxes The info to post + * @param[in] Nb this northbridge + * + */ +VOID +Fam10PostMailbox ( + IN UINT8 Node, + IN AP_MAILBOXES ApMailboxes, + IN NORTHBRIDGE *Nb + ) +{ + PCI_ADDR Reg; + + ASSERT (Node < MAX_NODES); + + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_NB_FUNC_03, + REG_NB_MCA_LINK_THRESHOLD_3X168); + LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailInfo.Info, Nb->ConfigHandle); + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_NB_FUNC_03, + REG_NB_MCA_L3_THRESHOLD_3X170); + LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Retrieve info from a node's mailbox. + * + * @HtNbMethod{::F_RETRIEVE_MAILBOX} + * + * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id, + * and module info. + * + * @param[in] Node the Node + * @param[in] Nb this northbridge + * + * @return The ap mailbox info + * + */ +AP_MAIL_INFO +Fam10RetrieveMailbox ( + IN UINT8 Node, + IN NORTHBRIDGE *Nb + ) +{ + PCI_ADDR Reg; + AP_MAIL_INFO ApMailInfo; + + ASSERT (Node < MAX_NODES); + + Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), + MakePciBusFromNode (Node), + MakePciDeviceFromNode (Node), + CPU_NB_FUNC_03, + REG_NB_MCA_LINK_THRESHOLD_3X168); + LibAmdPciReadBits (Reg, 11, 0, &ApMailInfo.Info, Nb->ConfigHandle); + return ApMailInfo; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.h b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.h new file mode 100644 index 0000000000..5b3e561958 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.h @@ -0,0 +1,129 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Northbridge utility routines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: HyperTransport + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/** + * Return the number of cores (1 based count) on Node. + * + */ +UINT8 +Fam10GetNumCoresOnNode ( + IN UINT8 Node, + IN NORTHBRIDGE *Nb + ); + +/** + * Return the number of cores (1 based count) on Node. + * + */ +UINT8 +Fam10RevDGetNumCoresOnNode ( + IN UINT8 Node, + IN NORTHBRIDGE *Nb + ); + +/** + * Get the next link for iterating over the links on a node in the correct order. + * + */ +LINK_ITERATOR_STATUS +Fam10GetNextLink ( + IN UINT8 Node, + IN OUT UINT8 *Link, + IN NORTHBRIDGE *Nb + ); + +/** + * Get Info about Module Type of this northbridge + * + */ +VOID +Fam10GetModuleInfo ( + IN UINT8 Node, + OUT UINT8 *ModuleType, + OUT UINT8 *Module, + IN NORTHBRIDGE *Nb + ); + +/** + * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. + * + */ +UINT8 +Fam10GetSocket ( + IN UINT8 Node, + IN UINT8 TempNode, + IN NORTHBRIDGE *Nb + ); + +/** + * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. + * + */ +UINT8 +Fam10RevDGetSocket ( + IN UINT8 Node, + IN UINT8 TempNode, + IN NORTHBRIDGE *Nb + ); + +/** + * Post info to AP cores via a mailbox. + * + */ +VOID +Fam10PostMailbox ( + IN UINT8 Node, + IN AP_MAILBOXES ApMailboxes, + IN NORTHBRIDGE *Nb + ); + +/** + * Retrieve info from a node's mailbox. + * + */ +AP_MAIL_INFO +Fam10RetrieveMailbox ( + IN UINT8 Node, + IN NORTHBRIDGE *Nb + ); |