diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c')
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c index 6e62cc0f08..41f0df01df 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/Ps/ON) - * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $ + * @e \$Revision: 46937 $ @e \$Date: 2011-02-11 08:50:58 -0700 (Fri, 11 Feb 2011) $ * **/ /* @@ -132,7 +132,14 @@ MemPConstructPsUON3 ( return AGESA_UNSUPPORTED; } PsPtr->MemPDoPs = MemPDoPsUON3; + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) == 0) { PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUON3; + } else { + // Do not force frequency limit for Rev C + PsPtr->MemPGetPORFreqLimit = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + } + return AGESA_SUCCESS; } |