diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family')
10 files changed, 1510 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c new file mode 100644 index 0000000000..d3fc9b4231 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c @@ -0,0 +1,71 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB EHCI controller + * + * Init USB EHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIENVSERVICE_FILECODE diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c new file mode 100644 index 0000000000..91122ff7b0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c @@ -0,0 +1,74 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB EHCI controller + * + * Init USB EHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCILATESERVICE_FILECODE +// +// Declaration of local functions +// diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c new file mode 100644 index 0000000000..31b1079eff --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c @@ -0,0 +1,210 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB EHCI controller + * + * Init USB EHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIMIDSERVICE_FILECODE +// +// Declaration of local functions +// + +/** + * FchEhciInitAfterPciInit - Config USB controller after PCI emulation + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * @param[in] FchDataPtr Fch configuration structure pointer. + */ +VOID +FchEhciInitAfterPciInit ( + IN UINT32 Value, + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + UINT32 BarAddress; + UINT32 Var; + + // + //Get BAR address + // + ReadPci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, FchDataPtr->StdHeader); + if ( (BarAddress != - 1) && (BarAddress != 0) ) { + // + //Enable Memory access + // + RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, FchDataPtr->StdHeader); + if (FchDataPtr->Usb.EhciSsid != 0 ) { + RwPci ((UINT32) Value + FCH_EHCI_REG2C, AccessWidth32, 0x00, FchDataPtr->Usb.EhciSsid, FchDataPtr->StdHeader); + } + // + //USB Common PHY CAL & Control Register setting + // + Var = 0x00020F00; + WriteMem (BarAddress + 0x0C0 , AccessWidth32, &Var); + // + // IN AND OUT DATA PACKET FIFO THRESHOLD + // EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40 + // + RwMem (BarAddress + FCH_EHCI_BAR_REGA4, AccessWidth32, 0xFF00FF00, 0x00400040); + // + // EHCI Dynamic Clock Gating Feature + // Enable Global Clock Gating (BIT14) + // + RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, (UINT32)~( BIT12 + BIT14), (UINT32)(BIT12 + BIT14)); + RwMem (BarAddress + 0x0B0 , AccessWidth32, (UINT32)~BIT5, (UINT32)BIT5); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth16, (UINT32)~BIT12, (UINT32)BIT12); + //RPR 8.26 Incorrect gated signals in xhc_to_s5 + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, (UINT32)~BIT16, (UINT32)BIT16); + // + // Enable adding extra flops to PHY rsync path + // Step 1: + // EHCI_BAR 0xB4 [6] = 1 + // EHCI_BAR 0xB4 [7] = 0 + // EHCI_BAR 0xB4 [12] = 0 ("VLoad") + // All other bit field untouched + // Step 2: + // EHCI_BAR 0xB4[12] = 1 + // + // USB 2.0 Ports Driving Strength + // Step1 is done by default + // Step2 + RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, (UINT32)~BIT12, (UINT32)BIT12); + // Step3 + RwMem (BarAddress + FCH_EHCI_BAR_REGC4, AccessWidth32, (UINT32) (~ 0x00000f00), 0x00000200); + RwMem (BarAddress + 0x0C0 , AccessWidth32, (UINT32) (~ 0x0000ff00), 0x00000f00); + + //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support + RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x01 << 6)), (UINT32) (0x01 << 6), FchDataPtr->StdHeader); + // EHCI Async Park Mode + //Set EHCI_pci_configx50[11:8]=0x1 + //Set EHCI_pci_configx50[15:12]=0x1 + //Set EHCI_pci_configx50[17]=0x1 + RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x0F << 8)), (UINT32) (0x01 << 8), FchDataPtr->StdHeader); + RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x0F << 12)), (UINT32) (0x01 << 12), FchDataPtr->StdHeader); + RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x01 << 17)), (UINT32) (0x01 << 17), FchDataPtr->StdHeader); + //RPR 7.14 Extend InterPacket Gap + RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x01 << 21)), (UINT32) (0x01 << 21), FchDataPtr->StdHeader); + + // Enabling EHCI Async Stop Enhancement + //Set EHCI_pci_configx50[29]='1' to disableEnabling EHCI Async Stop Enhancement + // + RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x01 << 29)), (UINT32) (0x01 << 29), FchDataPtr->StdHeader); + // + // recommended setting "EHCI Advance PHY Power Savings" + // Set EHCI_pci_configx50[31]='1' + // Fix for EHCI controller driver yellow sign issue under device manager + // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1 + // Disable USB data cache to resolve USB controller hang issue with Lan adaptor. + // EHCI PCI config register 50h bit 26 to `1'. + // + RwPci ((UINT32) Value + 0x50 + 2, AccessWidth16, (UINT16)0xFFFF, BIT16 + BIT10, FchDataPtr->StdHeader); + // + // USB Delay A-Link Express L1 State + // PING Response Fix Enable EHCI_PCI_Config x54[1] = 1 + // Enable empty list mode. x54[3] + // Enable "L1 Early Exit" functionality. 0x54 [6:5] = 0x3 0x54 [9:7] = 0x4 + // + RwPci ((UINT32) Value + 0x54 , AccessWidth32, (UINT32)~BIT0, 0x0000027b, FchDataPtr->StdHeader); + RwAlink ((FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFEFFFF, (UINT32)BIT16, FchDataPtr->StdHeader); + if ( FchDataPtr->Usb.UsbMsiEnable) { + RwPci ((UINT32) Value + 0x50 , AccessWidth32, (UINT32)~BIT6, 0x00, FchDataPtr->StdHeader); + } + // Long Delay on Framelist Read Causing EHCI DMA to Address 0 - Fix + // RWPCI ((UINT32) Value + 0x54 , AccWidthUint32 | S3_SAVE, ~BIT13, BIT13); + // LS connection can't wake up system from S3/S4/S5 when EHCI owns the port - Fix + RwPci ((UINT32) Value + 0x54 , AccessWidth32, (UINT32)~BIT4, (UINT32)BIT4, FchDataPtr->StdHeader); + // EHCI lMU Hangs when Run/Stop is Set First and PDC is Enabled Near End uFrame 7 - Fix Enable + RwPci ((UINT32) Value + 0x54 , AccessWidth32, (UINT32)~BIT11, (UINT32)BIT11, FchDataPtr->StdHeader); + // RPR 7.25 SB02674 + RwPci ((UINT32) Value + 0x54 , AccessWidth16, (UINT16)0x5FFF, BIT13 + BIT15, FchDataPtr->StdHeader); + // RPR 7.26 SB02684 + RwPci ((UINT32) Value + 0x50 + 2, AccessWidth16, (UINT32)~BIT3, (UINT32)BIT3, FchDataPtr->StdHeader); + // RPR 7.26 SB02687 + RwPci ((UINT32) Value + 0x54 + 2, AccessWidth16, (UINT16)0xFFFC, BIT0 + BIT1, FchDataPtr->StdHeader); + // RPR 7.28 SB02700 + RwPci ((UINT32) Value + 0x54 + 2, AccessWidth16, (UINT16)0xFFFB, BIT2, FchDataPtr->StdHeader); + // RPR 7.29 SB02703 + RwPci ((UINT32) Value + 0x54 + 2, AccessWidth16, (UINT16)0xFFF7, BIT3, FchDataPtr->StdHeader); + } else { + // + // Fake Bar + // + BarAddress = FCH_FAKE_USB_BAR_ADDRESS; + WritePci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, FchDataPtr->StdHeader); + // + //Enable Memory access + // + RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, FchDataPtr->StdHeader); + // + // Enable Global Clock Gating (BIT14) + // + RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, (UINT32)~( BIT12 + BIT14), (UINT32)(BIT12 + BIT14)); + RwMem (BarAddress + 0x0B0 , AccessWidth32, (UINT32)~BIT5, (UINT32)BIT5); + RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, 0, FchDataPtr->StdHeader); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c new file mode 100644 index 0000000000..3d40cb455f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c @@ -0,0 +1,130 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH USB OHCI controller + * + * Init USB OHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIENVSERVICE_FILECODE +// +// Declaration of local functions +// +// +// Declaration of local functions +// +/** + * FchSetUsbEnableReg + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchSetUsbEnableReg ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + UINT8 UsbModeReg; + UINT8 XhciReg00; + UsbModeReg = 0; + + // Overwrite EHCI3/OHCI3 by Xhci1Enable + ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth8, &XhciReg00); + if (XhciReg00 & BIT0) { + FchDataPtr->Usb.Ohci3Enable = FALSE; + FchDataPtr->Usb.Ehci3Enable = FALSE; + UsbModeReg |= 0x80; + } else { + UsbModeReg &= 0x7F; + } + + if ( FchDataPtr->Usb.Ohci1Enable ) { + UsbModeReg |= 0x01; + } + if ( FchDataPtr->Usb.Ehci1Enable ) { + UsbModeReg |= 0x02; + } + if ( FchDataPtr->Usb.Ohci2Enable ) { + UsbModeReg |= 0x04; + } + if ( FchDataPtr->Usb.Ehci2Enable ) { + UsbModeReg |= 0x08; + } + if ( FchDataPtr->Usb.Ohci3Enable ) { + UsbModeReg |= 0x10; + } + if ( FchDataPtr->Usb.Ehci3Enable ) { + UsbModeReg |= 0x20; + } + if ( FchDataPtr->Usb.Ohci4Enable ) { + UsbModeReg |= 0x40; + } + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEF , AccessWidth8, 0, UsbModeReg); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c new file mode 100644 index 0000000000..b1498a4242 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c @@ -0,0 +1,75 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH USB OHCI controller + * + * Init USB OHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCILATESERVICE_FILECODE +// +// Declaration of local functions +// + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c new file mode 100644 index 0000000000..1fd30353b5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c @@ -0,0 +1,133 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH USB OHCI controller + * + * Init USB OHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIMIDSERVICE_FILECODE +// +// Declaration of local functions +// + +/** + * FchOhciInitAfterPciInit - Config USB OHCI controller after + * PCI emulation + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * @param[in] FchDataPtr Fch configuration structure pointer. + */ +VOID +FchOhciInitAfterPciInit ( + IN UINT32 Value, + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + // + // Disable the MSI capability of USB host controllers + // + RwPci ((UINT32) Value + FCH_OHCI_REG40 + 1, AccessWidth8, 0xFF, BIT0, FchDataPtr->StdHeader); + RwPci ((UINT32) Value + 0x50 , AccessWidth8, (UINT32)~(BIT0 + BIT5 + BIT12), 0, FchDataPtr->StdHeader); + // + // USB SMI Handshake + // + RwPci ((UINT32) Value + 0x50 + 1, AccessWidth8, (UINT32)~BIT4, 0x00, FchDataPtr->StdHeader); + + if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) { + if ( FchDataPtr->Usb.OhciSsid != 0 ) { + RwPci ((UINT32) Value + FCH_OHCI_REG2C, AccessWidth32, 0x00, FchDataPtr->Usb.OhciSsid, FchDataPtr->StdHeader); + } + } + // + // recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices + //OHCI 0_PCI_Config 0x50[30] = 1 + // + RwPci ((UINT32) Value + 0x50 + 3, AccessWidth8, (UINT32)~BIT6, (UINT32)BIT6, FchDataPtr->StdHeader); + // + // L1 Early Exit + // Set OHCI Arbiter Mode. + // Set Enable Global Clock Gating. + // + RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth8, (UINT32)~(BIT0 + BIT4 + BIT5 + BIT6 + BIT7), (UINT32)(BIT0 + BIT4 + BIT7), FchDataPtr->StdHeader); + RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth16, (UINT32)~(BIT4 + BIT5 + BIT8), (UINT32)(BIT4 + BIT5 + BIT8), FchDataPtr->StdHeader); + // + // Enable OHCI SOF Synchronization. + // Enable OHCI Periodic List Advance. + // + RwPci ((UINT32) Value + 0x50 + 2, AccessWidth8, (UINT32)~(BIT3 + BIT4 + BIT6 + BIT7), (UINT32)(BIT3 + BIT4 + BIT6 + BIT7), FchDataPtr->StdHeader); + if ( FchDataPtr->Usb.UsbMsiEnable) { + RwPci ((UINT32) Value + FCH_OHCI_REG40 + 1, AccessWidth8, (UINT32)~BIT0, 0x00, FchDataPtr->StdHeader); + RwPci ((UINT32) Value + 0x50 , AccessWidth8, (UINT32)~BIT5, (UINT32)BIT5, FchDataPtr->StdHeader); + } + // full-speed false crc errors detected. Issue - fix enable + RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth32, (UINT32) (~(0x01 << 10)), (UINT32) (0x01 << 10), FchDataPtr->StdHeader); + // SB02643 + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGB4, AccessWidth8, (UINT32)~BIT7, (UINT32)BIT7); + // RPR 7.27 SB02686 + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, (UINT32)~BIT2, (UINT32)BIT2); + // SB02698 + RwPci ((UINT32) Value + 0x50 , AccessWidth8, (UINT32)~BIT0, 0, FchDataPtr->StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c new file mode 100644 index 0000000000..26f9626e2d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c @@ -0,0 +1,432 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH USB3 controller + * + * Init USB3 features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 65854 $ @e \$Date: 2012-02-26 01:52:07 -0600 (Sun, 26 Feb 2012) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIENVSERVICE_FILECODE + +// +// Declaration of local functions +// + +/** + * FchXhciInitIndirectReg - Config XHCI Indirect Registers + * + * + * + * @param[in] StdHeader AMD Standard Header + * + */ +VOID +FchXhciInitIndirectReg ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 DrivingStrength; + UINT32 Port; + UINT32 Register; + UINT32 RegValue; + UINT8 Index; + DrivingStrength = 0; + Port = 0; + // + // SuperSpeed PHY Configuration (adaptation mode setting) + // + RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader); + RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader); + // + // SuperSpeed PHY Configuration (CR phase and frequency filter settings) + // + RwXhciIndReg ( FCH_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A, StdHeader); + RwXhciIndReg ( FCH_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A, StdHeader); + // + // BLM Meaasge + // + RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader); + // + // xHCI USB 2.0 PHY Settings + // Step 1 is done by hardware default + // Step 2 + for (Port = 0; Port < 4; Port ++) { + DrivingStrength = BIT2; + if (Port < 2) { + RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, (Port << 13) + DrivingStrength, StdHeader); + RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, (Port << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader); + RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0E78, (Port << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader); + Register = FCH_XHCI_IND60_REG00; + Index = 0; + do { + WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader); + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader); + Index++; + FchStall (10, StdHeader); + } while ((RegValue & BIT17) && (Index < 10 )); + RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000, StdHeader); + } else { + RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, ((Port - 2) << 13) + DrivingStrength, StdHeader); + RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, ((Port - 2) << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader); + RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0E78, ((Port - 2) << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader); + Register = FCH_XHCI_IND60_REG00; + Index = 0; + do { + WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader); + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader); + Index++; + FchStall (10, StdHeader); + } while ((RegValue & BIT17) && (Index < 10 )); + RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000, StdHeader); + } + } + + // Step 3 + RwXhciIndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader); + RwXhciIndReg ( FCH_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)), StdHeader); +} + +/** + * XhciA12Fix - Config XHCI A12 Fix + * + * + */ +STATIC +VOID +XhciA12Fix ( + OUT VOID + ) +{ + // + // PLUG/UNPLUG of USB 2.0 devices make the XHCI USB 2.0 ports unfunctional - fix enable + // ACPI_USB3.0_REG 0x20[12:11] = 2'b11 + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x3 << 11)), (UINT32) (0x3 << 11)); + // + // XHC 2 USB2 ports interactional issue - fix enable + // ACPI_USB3.0_REG 0x20[16] = 1'b1 + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 16)), (UINT32) (0x1 << 16)); + // + // XHC USB2.0 Ports suspend Enhancement + // ACPI_USB3.0_REG 0x20[15] = 1'b1 + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 15)), (UINT32) (0x1 << 15)); + // + // XHC HS/FS IN Data Buffer Underflow issue - fix enable + // ACPI_USB3.0_REG 0x20[20:18] = 0x7 + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x7 << 18)), (UINT32) (0x7 << 18)); + // + // XHC stuck in U3 after system resuming from S3 -fix enable + // ACPI_USB3.0_REG 0x98[19] = 1'b1 + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccessWidth32, ~((UINT32) (0x1 << 19)), (UINT32) (0x1 << 19)); + // + // Change XHC1 ( Dev 16 function 1) Interrupt Pin register to INTB# - Fix enable + // ACPI_PMIO_F0[18] =1 + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 18)), (UINT32) (0x1 << 18)); + // + // EHCI3/OHCI3 blocks Blink Global Clock Gating when EHCI/OHCI Dev 22 fn 0/2 are disabled + // ACPI_PMIO_F0[13] =1 + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 13)), (UINT32) (0x1 << 13)); + // + // Access register through JTAG fail when switch from XHCI to EHCI/OHCI - Fix enable + // ACPI_PMIO_F0[17] =1 + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 17)), (UINT32) (0x1 << 17)); + // + // USB leakage current on differential lines when ports are switched to XHCI - Fix enable + // ACPI_PMIO_F0[14] =1 + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 14)), (UINT32) (0x1 << 14)); +} + +/** + * IsLpcRom - Is LPC Rom? + * + * + * @retval TRUE or FALSE + * + */ +BOOLEAN +IsLpcRom ( + OUT VOID + ) +{ + return ( (BOOLEAN) ((ACPIMMIO32 (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80) & BIT1) == 0) ); +} + +/** + * FchXhciInitBeforePciInit - Config XHCI controller before PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchXhciInitBeforePciInit ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + UINT16 BcdAddress; + UINT16 BcdSize; + UINT16 AcdAddress; + UINT16 AcdSize; + UINT16 FwAddress; + UINT16 FwSize; + UINTN XhciFwStarting; + UINT32 SpiValidBase; + UINT32 RegData; + UINT16 Index; + BOOLEAN Xhci0Enable; + BOOLEAN Xhci1Enable; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + Xhci0Enable = LocalCfgPtr->Usb.Xhci0Enable; + Xhci1Enable = LocalCfgPtr->Usb.Xhci1Enable; + + if (( Xhci0Enable == 0 ) && (Xhci1Enable == 0)) { + return; + } + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0x00000000, 0x00400700); + FchStall (20, StdHeader); + + if ( LocalCfgPtr->Usb.UserDefineXhciRomAddr == 0 ) { + // + // Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address) + // + GetRomSigPtr (&XhciFwStarting, StdHeader); + + if (XhciFwStarting == 0) { + return; + } + XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET); + } else { + XhciFwStarting = ( UINTN ) LocalCfgPtr->Usb.UserDefineXhciRomAddr; + } + if (IsLpcRom ()) { + // + // XHCI firmware re-load + // + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, (UINT32)~BIT2, (UINT32)(BIT2 + BIT1 + BIT0), StdHeader); + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, 0x00000FFF, (UINT32) (XhciFwStarting), StdHeader); + } + + // + // Enable SuperSpeed receive special error case logic. 0x20 bit8 + // Enable USB2.0 RX_Valid Synchronization. 0x20 bit9 + // Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10 + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, 0xFFFFF8FF, 0x00000700); + // + // SuperSpeed PHY Configuration (adaptation timer setting) + // XHC U1 LFPS Exit time + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xCFF00000, 0x000AAAAA); + //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccessWidth32, 0xFFF00000, 0x000AAAAA); + + // + // Step 1. to enable Xhci IO and Firmware load mode + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT4 + BIT5), 0); /// Disable Device 22 + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT7), (UINT32)BIT7); /// Enable 2.0 devices + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFFFC, (Xhci0Enable + (Xhci1Enable << 1)) & 0x03); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xEFFFFFFF, 0x10000000); + + // + // Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers. + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccessWidth32, 0x00000000, (SPI_HEAD_LENGTH << 16)); + + BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET); + BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccessWidth16, 0x0000, BcdAddress); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccessWidth16, 0x0000, BcdSize); + + AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET); + AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccessWidth16, 0x0000, AcdAddress); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccessWidth16, 0x0000, AcdSize); + + SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD; + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccessWidth32, 0x00000000, SpiValidBase); + // + // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0 + // + for (Index = 0; Index < SPI_HEAD_LENGTH; Index++) { + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + Index)); + } + + for (Index = 0; Index < BcdSize; Index++) { + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + Index)); + } + + for (Index = 0; Index < AcdSize; Index++) { + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + Index)); + } + + // + // Step 3. to enable the instruction RAM preload functionality. + // + FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress)); + FwAddress += 2; + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccessWidth16, 0x0000, FwAddress); + + FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccessWidth16, 0x0000, FwSize); + // + // Set the starting address offset for Instruction RAM preload. + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccessWidth16, 0x0000, 0); + + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~BIT29, (UINT32)BIT29); + + for (;;) { + ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData); + if (RegData & BIT30) { + break; + } + } + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~BIT29, 0); + + // + // Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock. + // + + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~U3PLL_RESET, 0); ///Release U3PLLreset + for (;;) { + ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData); + if (RegData & U3PLL_LOCK) { + break; + } + } + + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~U3PHY_RESET, 0); ///Release U3PHY + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~U3CORE_RESET, 0); ///Release core reset + + // + // SuperSpeed PHY Configuration + // + //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xFFF00000, 0x000AAAAA); + //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccessWidth32, 0xFFF00000, 0x000AAAAA); + + FchXhciInitIndirectReg (StdHeader); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT4 + BIT5), 0); /// Disable Device 22 + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT7), (UINT32)BIT7); /// Enable 2.0 devices + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~(BIT21), (UINT32)BIT21); + // + // Step 5. + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~(BIT17 + BIT18 + BIT19), (UINT32)(BIT17 + BIT18)); + + XhciA12Fix (); + + // + // UMI Lane Configuration Information for XHCI Firmware to Calculate the Bandwidth for USB 3.0 ISOC Devices + // + if (!(IsUmiOneLaneGen1Mode (StdHeader))) { + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, (UINT32)~(BIT25 + BIT24), (UINT32)BIT24); + } + // RPR 8.23 FS/LS devices not functional after resume from S4 fix enable (SB02699) + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, (UINT32)~(BIT22), (UINT32)BIT22); + // RPR 8.24 XHC USB2.0 Hub disable issue fix enable (SB02702) + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, (UINT32)~(BIT20), (UINT32)BIT20); +} + +/** + * FchXhciPowerSavingProgram - Config XHCI for Power Saving mode + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchXhciPowerSavingProgram ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + UINT8 XhciEfuse; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // add Efuse checking for Xhci enable/disable + XhciEfuse = XHCI_EFUSE_LOCATION; + GetEfuseStatus (&XhciEfuse, StdHeader); + if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) { + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFBFF, 0x0); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c new file mode 100644 index 0000000000..664b7efc30 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c @@ -0,0 +1,158 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH USB3 controller + * + * Init USB3 features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCILATESERVICE_FILECODE + +// +// Declaration of local functions +// + +/** + * FchInitLateUsbXhciProgram - Config USB3 controller before OS + * Boot + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateUsbXhciProgram ( + IN VOID *FchDataPtr + ) +{ + UINT8 IndexValue; + UINT8 Value; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if ( LocalCfgPtr->Usb.Xhci1Enable == TRUE ) { + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_BAR00; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x11, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_BAR01; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x12, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_BAR02; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x13, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_BAR03; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_04H; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_0CH; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_3CH; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_BAR00; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x11, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_BAR01; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x12, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_BAR02; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x13, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_BAR03; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_04H; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_0CH; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_3CH; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + } + //RPR 8.12 xHCI controller PCI configuration space "Read Only" registers write lock enable + RwXhciIndReg ( FCH_XHCI_IND_REG04, (UINT32)~BIT8, (UINT32)BIT8, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c new file mode 100644 index 0000000000..92b292817d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c @@ -0,0 +1,75 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH USB3 controller + * + * Init USB3 features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIMIDSERVICE_FILECODE + +// +// Declaration of local functions +// diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c new file mode 100644 index 0000000000..bf5227fcd4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c @@ -0,0 +1,152 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH Xhci controller + * + * Init Xhci Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIRESETSERVICE_FILECODE + +/** + * FchInitResetXhciProgram - Config Xhci controller during + * Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetXhciProgram ( + IN VOID *FchDataPtr + ) +{ + UINT8 IndexValue; + UINT32 ValueDword; + UINT8 ValueByte; + FCH_RESET_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + BOOLEAN Xhci0Enable; + BOOLEAN Xhci1Enable; + + LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + Xhci0Enable = LocalCfgPtr->FchReset.Xhci0Enable; + Xhci1Enable = LocalCfgPtr->FchReset.Xhci1Enable; + + if ( Xhci0Enable ) { + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader); + if ( ValueDword == (FCH_USB_XHCI_DID << 16) + FCH_USB_XHCI_VID) { + // + // First Xhci controller. + // + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader); + ValueDword = 0; + + IndexValue = XHCI_REGISTER_BAR00; + ReadBiosram (IndexValue, AccessWidth32, &ValueDword, StdHeader); + WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccessWidth32, &ValueDword, StdHeader); + + IndexValue = XHCI_REGISTER_04H; + ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader); + WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &ValueByte, StdHeader); + + IndexValue = XHCI_REGISTER_0CH; + ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader); + WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &ValueByte, StdHeader); + + IndexValue = XHCI_REGISTER_3CH; + ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader); + WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader); + // + // Second Xhci controller. + // + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader); + ValueDword = 0; + + IndexValue = XHCI1_REGISTER_BAR00; + ReadBiosram (IndexValue, AccessWidth32, &ValueDword, StdHeader); + WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccessWidth32, &ValueDword, StdHeader); + + IndexValue = XHCI1_REGISTER_04H; + ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader); + WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &ValueByte, StdHeader); + + IndexValue = XHCI1_REGISTER_0CH; + ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader); + WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &ValueByte, StdHeader); + + IndexValue = XHCI1_REGISTER_3CH; + ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader); + WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader); + } + } else { + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0x00000000, 0x00400700); + } +} + |