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Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl')
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl | 196 |
1 files changed, 196 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl new file mode 100644 index 0000000000..49bae5f302 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl @@ -0,0 +1,196 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63659 $ @e \$Date: 2012-01-03 00:42:47 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +DefinitionBlock ( + "PcieAlibSsdtTN.aml", + "SSDT", + 2, + "AMD", + "ALIB", + 0x1 + ) +{ + Scope(\_SB) { + + Name (varMaxPortIndexNumber, 6) + + include ("PcieAlibMmioData.asl") + include ("PcieAlibPciLib.asl") + include ("PcieAlibDebugLib.asl") + include ("PcieSmuServiceV4.asl") + + + Name (varBapmControl, 0) + Name (varCstateIntControlState, 0) + Name (varIsStateInitialized, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * APM/PDM stub + * + * Arg0 - AC/DC state + * + */ + Method (procApmPdmActivate, 1, NotSerialized) { + Store (Or(ShiftLeft (0x18, 3), 4), Local2) + if (LEqual (varIsStateInitialized, 0)) { + Store (procPciDwordRead (Local2, 0x124), varCstateIntControlState) + Store (1, varIsStateInitialized) + } + + Store (procPciDwordRead (Local2, 0x124), Local3) + if (LEqual (Arg0,DEF_PSPP_STATE_AC)) { + // Disable PC6 on AC + Or (Local3, And (varCstateIntControlState, 0x00400000), Local3) + } else { + // Enable PC6 on DC + And (Local3, 0xFFBFFFFF, Local3) + } + procPciDwordWrite (Local2, 0x124, Local3) + + if (LEqual (varBapmControl, 0)) { + // If GFX present driver manage BAPM if not ALIB manage BAPM + if (LEqual (procPciDwordRead (0x08, 0x00), 0xffffffff)) { + And (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), 0x2, Local1); + // check if BAPM was enable during BIOS post + if (LEqual (Local1, 0x2)) { + Store (1, varBapmControl) + } + } + } + if (LEqual (varBapmControl,1)) { + if (LEqual (Arg0,DEF_PSPP_STATE_AC)) { + // Enable BAPM on AC + Store (32, Local0) + } else { + // Disable BAPM on DC + Store (33, Local0) + } + procNbSmuServiceRequest (Local0); + } + } + + Name (varRestoreNbps, 0) + Name (varRestoreNbDpmState, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * _WAK + * + * + * + */ + Method (AWAK, 1) { + if (LEqual (Arg0, 3)) { + // Clear D18F5x170 [SwNbPstateLoDis] only if it was 0 in APTS + if (LEqual (varRestoreNbps, 1)) { + Store (procPciDwordRead (0xC5, 0x170), Local0) + procPciDwordWrite (0xC5, 0x170, And (Local0, Not (ShiftLeft (1, 14)))) + Store (0, varRestoreNbps); + } + if (LEqual (varRestoreNbDpmState, 1)) { + Store (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), Local0) + procIndirectRegisterWrite (0x0, 0xB8, 0x1F428, Or (Local0, ShiftLeft (1, 5))) + procNbSmuServiceRequest (22); + Store (0, varRestoreNbDpmState) + } + } + } + /*----------------------------------------------------------------------------------------*/ + /** + * _PTS + * + * + * + */ + Method (APTS, 1) { + if (LEqual (Arg0, 3)) { + procApmPdmActivate (DEF_PSPP_STATE_DC); + // Disable NBDPM + Store (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), Local0) + if (LNotEqual (And (Local0, ShiftLeft (1, 5)), 0)) { + // NBDPM enabled lets disable it + procIndirectRegisterWrite (0x0, 0xB8, 0x1F428, And (Local0, Not (ShiftLeft (1, 5)))) + procNbSmuServiceRequest (22); + // Indicate needs to restore NBDPM + Store (1, varRestoreNbDpmState); + } + // Save state of D18F5x170 [SwNbPstateLoDis] + Store (procPciDwordRead (0xC5, 0x170), Local0) + if (LEqual (And (Local0, ShiftLeft (1, 14)), 0)) { + // Set D18F5x170 [SwNbPstateLoDis] = 1 + procPciDwordWrite (0xC5, 0x170, Or (Local0, ShiftLeft (1, 14))) + Store (1, varRestoreNbps); + } + } + } + } //End of Scope(\_SB) +} //End of DefinitionBlock + + |