diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN')
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnS3tn.h | 111 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mndcttn.c | 906 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c | 156 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnidendimmtn.c | 172 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnmcttn.c | 562 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c | 348 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnphytn.c | 742 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c | 856 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c | 1498 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c | 618 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.h | 341 |
11 files changed, 6310 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnS3tn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnS3tn.h new file mode 100644 index 0000000000..7014b8a00c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnS3tn.h @@ -0,0 +1,111 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnS3tn.h + * + * S3 resume memory related function for TN. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/TN) + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + **/ +/***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _MNS3TN_H_ +#define _MNS3TN_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of TN +typedef enum { + PCI_LST_ESR_TN, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_TN, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_TN, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_TN, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_TN, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_TN, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_TN, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_TN ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDTN; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ +#define SET_S3_NB_PSTATE_OFFSET(Offset, NBPstate) ((NBPstate << 10) | Offset) + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3TN_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mndcttn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mndcttn.c new file mode 100644 index 0000000000..6bbcb70b93 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mndcttn.c @@ -0,0 +1,906 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mndcttn.c + * + * Northbridge DCT support for TN + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/TN) + * @e \$Revision: 63661 $ @e \$Date: 2012-01-03 01:02:47 -0600 (Tue, 03 Jan 2012) $ + * + **/ +/***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "OptionMemory.h" +#include "mntn.h" +#include "mftds.h" +#include "merrhdl.h" +#include "cpuFamRegisters.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuCommonF15Utilities.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + + +#define FILECODE PROC_MEM_NB_TN_MNDCTTN_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 +#define MAX_RD_DQS_DLY 0x1F + +CONST BIT_FIELD_NAME MemPstateBF[4] = {BFMemPstate0, BFMemPstate1, BFMemPstate2, BFMemPstate3}; +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT32 +STATIC +MemNTotalSyncComponentsTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the memory controller with configuration parameters + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value + */ + +BOOLEAN +MemNAutoConfigTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 i; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_PARAMETER_STRUCT *RefPtr; + UINT32 PowerDownMode; + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + + // + //====================================================================== + // Build Dram Config Lo Register Value + //====================================================================== + MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1); + MemNSetBitFieldNb (NBPtr, BFPendRefPaybackS3En, 1); + MemNSetBitFieldNb (NBPtr, BFStagRefEn, 1); + // + //====================================================================== + // Build Dram Config Hi Register Value + //====================================================================== + // + // + // MemClkFreq + // + MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdUnb (NBPtr, DCTPtr->Timings.Speed)); + + PowerDownMode = 1; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + MemNSetBitFieldNb (NBPtr, BFPowerDownMode, PowerDownMode); + + if (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE) { + MemNBrdcstSetNb (NBPtr, BFM1MemClkFreq, MemNGetMemClkFreqIdUnb (NBPtr, DDR667_FREQUENCY)); + MemNBrdcstSetNb (NBPtr, BFRate, MemNGetMemClkFreqIdUnb (NBPtr, DDR667_FREQUENCY) | 0x8); + MemNBrdcstSetNb (NBPtr, BFMxMrsEn, 7); + } + + MemNSetBitFieldNb (NBPtr, BFDphyMemPsSelEn, 1); + // + //====================================================================== + // Build Dram MRS Register Value + //====================================================================== + // + MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, 1); + MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 1); + + //====================================================================== + // DRAM Controller Miscellaneous 2 + //====================================================================== + MemNSetBitFieldNb (NBPtr, BFPerRankTimingEn, 1); + IDS_HDT_CONSOLE (MEM_FLOW, "\n\nEnable Per Rank Training....\n\n"); + MemNSetBitFieldNb (NBPtr, BFPrtlChPDEnhEn, 0); + MemNSetBitFieldNb (NBPtr, BFAggrPDEn, 1); + + //====================================================================== + // GMC to DCT control + //====================================================================== + MemNSetBitFieldNb (NBPtr, BFGmcTokenLimit, 4); + MemNSetBitFieldNb (NBPtr, BFMctTokenLimit, 4); + MemNSetBitFieldNb (NBPtr, BFGmcToDctControl1, 0x4444); + if ((MCTPtr->LogicalCpuid.Revision & 0x0000000000000100ull ) != 0) { + MemNSetBitFieldNb (NBPtr, BFCpuElevPrioDis, 1); + } + + //====================================================================== + // Other Registers + //====================================================================== + // + // + // Non-SPD Timings + // + MemNSetBitFieldNb (NBPtr, BFTrwtWB, 0x17); + MemNSetBitFieldNb (NBPtr, BFTrwtTO, 0x16); + MemNSetBitFieldNb (NBPtr, BFTwrrd, 0xB ); + + MemNSetBitFieldNb (NBPtr, BFTrdrdSdSc, 0xB); + MemNSetBitFieldNb (NBPtr, BFTrdrdSdDc, 0xB); + MemNSetBitFieldNb (NBPtr, BFTrdrdDd, 0xB); + + MemNSetBitFieldNb (NBPtr, BFTwrwrSdSc, 0xB); + MemNSetBitFieldNb (NBPtr, BFTwrwrSdDc, 0xB); + MemNSetBitFieldNb (NBPtr, BFTwrwrDd, 0xB); + + MemNSetBitFieldNb (NBPtr, BFWrOdtOnDuration, DEFAULT_WR_ODT_TN); + MemNSetBitFieldNb (NBPtr, BFRdOdtOnDuration, DEFAULT_RD_ODT_TN); + MemNSetBitFieldNb (NBPtr, BFWrOdtTrnOnDly, DEFAULT_RD_ODT_TRNONDLY_TN); + + for (i = 0; i < 4; i++) { + MemNSetBitFieldNb (NBPtr, BFTstag0 + i, 0x14); + } + + MemNSetBitFieldNb (NBPtr, BFTmrd, 4); + MemNSetBitFieldNb (NBPtr, BFFlushWrOnS3StpGnt, 1); + MemNSetBitFieldNb (NBPtr, BFFastSelfRefEntryDis, 0); + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function caps speed based on battery life check. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + */ +VOID +MemNCapSpeedBatteryLifeTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT16 SupportedFreq[] = { + DDR2133_FREQUENCY, + DDR1866_FREQUENCY, + DDR1600_FREQUENCY, + DDR1333_FREQUENCY, + DDR1066_FREQUENCY, + DDR800_FREQUENCY, + DDR667_FREQUENCY + }; + + UINT32 FreqNumeratorInMHz; + UINT32 FreqDivisor; + UINT32 VoltageInuV; + UINT32 NBFreq; + UINT16 DdrFreq; + UINT16 j; + INT8 NbPs; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + BOOLEAN SkipAdjustNbPs; + + FamilySpecificServices = NULL; + GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &(NBPtr->MemPtr->StdHeader)); + + + // Find the lowest supported NB Pstate + NBFreq = 0; + for (NbPs = 3; NbPs >= 0; NbPs--) { + if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices, + NBPtr->MemPtr->PlatFormConfig, + &NBPtr->PciAddr, + (UINT32) NbPs, + &FreqNumeratorInMHz, + &FreqDivisor, + &VoltageInuV, + &(NBPtr->MemPtr->StdHeader))) { + if (MemNGetBitFieldNb (NBPtr, MemPstateBF[NbPs]) == 0) { + NBFreq = FreqNumeratorInMHz / FreqDivisor; + break; + } + } + } + + ASSERT (NBFreq > 0); + + // Pick Max MEMCLK that is less than or equal to NCLK + DdrFreq = DDR800_FREQUENCY; + for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) { + if (NBFreq >= ((UINT32) SupportedFreq[j])) { + DdrFreq = SupportedFreq[j]; + break; + } + } + + // Cap MemClk frequency to lowest NCLK frequency + if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) { + NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq; + } + + // Adjust the NB P-state northbridge voltage + SkipAdjustNbPs = FALSE; + IDS_OPTION_HOOK (IDS_NBPSDIS_OVERRIDE, &SkipAdjustNbPs, &(NBPtr->MemPtr->StdHeader)); + if (SkipAdjustNbPs == FALSE) { + MemNAdjustNBPstateVolTN (NBPtr); + } + + // Initialize NbPsCtlReg + NBPtr->NbPsCtlReg = 0; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function retrieves the Max latency parameters + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @param[in] *MinDlyPtr - Pointer to variable to store the Minimum Delay value + * @param[in] *MaxDlyPtr - Pointer to variable to store the Maximum Delay value + * @param[in] *DlyBiasPtr - Pointer to variable to store Delay Bias value + * @param[in] MaxRcvEnDly - Maximum receiver enable delay value + */ + +VOID +MemNGetMaxLatParamsTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxRcvEnDly, + IN OUT UINT16 *MinDlyPtr, + IN OUT UINT16 *MaxDlyPtr, + IN OUT UINT16 *DlyBiasPtr + ) +{ + UINT32 N; + UINT32 T; + UINT32 P; + UINT32 MemClkPeriod; + + // 1. P = N = T = 0. + P = N = T = 0; + + // Get all sync components BKDG steps 3,4,6 + P = MemNTotalSyncComponentsTN (NBPtr); + + // 7. P = P + CEIL(MAX(D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] + + // D18F2x9C_x0000_0[3:0]0[7:5]_dct[1:0][RdDqsTime] PCLKs)) + 1 + P = P + (MaxRcvEnDly + 31) / 32 + 1; + + // 10. N = (P/(MemClkFreq * 2) + T) * NclkFreq; Convert from PCLKs plus time to NCLKs. + MemClkPeriod = 1000000 / ((NBPtr->MemPstate == MEMORY_PSTATE0) ? NBPtr->DCTPtr->Timings.Speed : DDR667_FREQUENCY); + N = ((((P * MemClkPeriod + 1) / 2) + T) * NBPtr->NBClkFreq + 999999) / 1000000; + + // Calculate a starting MaxRdLatency delay value with steps 5, 9, and 12 excluded + *MinDlyPtr = (UINT16) N; + + *MaxDlyPtr = 0x3FF; + + // Left edge of MaxRdLat will be added with 1 NCLK and 3 PCLK (1.5 MEMCLK) + N = 1; + P = 3; + N += (((P * MemClkPeriod + 1) / 2) * NBPtr->NBClkFreq + 999999) / 1000000; + *DlyBiasPtr = (UINT16) N; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the maximum round-trip latency in the system from the processor to the DRAM + * devices and back. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] MaxRcvEnDly - Maximum receiver enable delay value + * + */ + +VOID +MemNSetMaxLatencyTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxRcvEnDly + ) +{ + UINT32 N; + UINT32 T; + UINT32 P; + UINT32 Px2; + UINT32 MemClkPeriod; + + AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader)); + + // + // Initial value for MaxRdLat used in training + // + N = 0x55; + + if (MaxRcvEnDly != 0xFFFF) { + // 1. P = N = T = 0. + P = N = T = 0; + + // Get all sync components BKDG steps 3,4,6 + P = MemNTotalSyncComponentsTN (NBPtr); + + // 5. P = P + 5 + P += 5; + + // 7. P = P + CEIL(MAX(D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] + + // D18F2x9C_x0000_0[3:0]0[6:5]_dct[1:0][RdDqsTime] PCLKs)) + 1 + P = P + ((MaxRcvEnDly + MAX_RD_DQS_DLY) + 31) / 32 + 1; + + // 8. If (NclkFreq/MemClkFreq < 2) then P = P + 4.5 Else P = P + 2.5 + if ((NBPtr->NBClkFreq / NBPtr->DCTPtr->Timings.Speed) < 2) { + Px2 = P * 2 + 9; + } else { + Px2 = P * 2 + 5; + } + + // 9. T = T + 1050 ps + T += 1050; + + // 10. N = (P/(MemClkFreq * 2) + T) * NclkFreq; Convert from PCLKs plus time to NCLKs. + MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; + N = ((((Px2 * MemClkPeriod + 3) / 4) + T) * NBPtr->NBClkFreq + 999999) / 1000000; + + // 11. D18F2x210_dct[1:0]_nbp[3:0][MaxRdLatency] = CEIL(N) - 1 + N = N - 1; + } + + NBPtr->DCTPtr->Timings.MaxRdLat = (UINT16) N; + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRdLat: %03x\n", N); + MemNSetBitFieldNb (NBPtr, BFMaxLatency, N); +} + +/*----------------------------------------------------------------------------- + * + * + * This function set MaxRdLat after HW receiver enable training is completed + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + * ---------------------------------------------------------------------------- + */ +BOOLEAN +MemNExitPhyAssistedTrainingTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + UINT8 Dct; + UINT8 ChipSel; + MEM_TECH_BLOCK *TechPtr; + + TechPtr = NBPtr->TechPtr; + + // Calculate Max Latency for both channels to prepare for position training + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN ; Dct++) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + NBPtr->SwitchDCT (NBPtr, Dct); + + // Reset DisAutoRefresh and ZqcsInterval for position training. + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1); + MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0); + MemNSetBitFieldNb (NBPtr, BFRx4thStgEn, 0); + MemNSetBitFieldNb (NBPtr, BFRxBypass3rd4thStg, 4); + } + + if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) { + NBPtr->SetMaxLatency (NBPtr, TechPtr->MaxDlyForMaxRdLat); + } + } + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the total of sync components for Max Read Latency calculation + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Total in PCLKs + */ +UINT32 +STATIC +MemNTotalSyncComponentsTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 P; + + P = 0; + + // 3. If (D18F2x9C_x0000_0004_dct[1:0][AddrCmdSetup] = 0 & D18F2x9C_x0000_0004_dct[1:0][CsOdt- + // Setup] = 0 & D18F2x9C_x0000_0004_dct[1:0][CkeSetup] = 0) + // then P = P + 1 + // else P = P + 2 + if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) { + P += 1; + } else { + P += 2; + } + + // 4. P = P + (8 - D18F2x210_dct[1:0]_nbp[3:0][RdPtrInit]) + P = P + (8 - (UINT16) MemNGetBitFieldNb (NBPtr, BFRdPtrInit)); + + // 6. P = P + (2 * (D18F2x200_dct[1:0][Tcl] - 1 clocks)) + P = P + (2 * (MemNGetBitFieldNb (NBPtr, BFTcl) - 1)); + + return P; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates and programs NB P-state dependent registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNProgramNbPstateDependentRegistersTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 RdPtrInit; + UINT8 Dct; + MEMORY_BUS_SPEED MemClkSpeed; + + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + break; + } + } + + if (MemNGetBitFieldNb (NBPtr, MemPstateBF[MemNGetBitFieldNb (NBPtr, BFNbPsSel)]) == 0) { + MemClkSpeed = NBPtr->DCTPtr->Timings.Speed; + } else { + MemClkSpeed = MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFM1MemClkFreq)); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMemclk Freq: %d\n", MemClkSpeed); + + // NCLK:MCLK ratio DDR rate (MT/s) RdPtrInit + // < 2:1 < 2133 0011b (2.5T) + // < 2:1 2133 <= rate <= 2400 0011b (2.5T) or 0010b (3T) + // For each NB P-state, IF any D18F2x9C_x0000_0[3:0]0[2:1]_dct[1:0]_mp[MemPstate][WrDat- + // GrossDly] ==0 THEN RdPtrInit=0010b ELSE RdPtrInit=0011b + // >=2:1 < 1866 0110b + // >=2:1 1866 <= rate < 2400 0101b + // >=2:1 2400 0100b + if (NBPtr->NBClkFreq < (UINT32) (MemClkSpeed * 2)) { + RdPtrInit = ((MemClkSpeed >= DDR2133_FREQUENCY) && (NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessWrDatDly, FALSE) == 0)) ? 2 : 3; + } else { + RdPtrInit = (MemClkSpeed < DDR1866_FREQUENCY) ? 6 : ((MemClkSpeed < DDR2400_FREQUENCY) ? 5 : 4); + } + MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit); + + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + // Set ProcOdtAdv + if ((NBPtr->ChannelPtr->SODimmPresent != 0) && (NBPtr->DCTPtr->Timings.Speed <= DDR1333_FREQUENCY)) { + MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0); + } else { + MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0x4000); + } + } + } + + MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 0); + + IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader); + MemFInitTableDrive (NBPtr, MTAfterNbPstateChange); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM init + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDramInitTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + // + // 2.10.6.7 DCT Training Specific Configuration + // + MemNSetBitFieldNb (NBPtr, BFAddrCmdTriEn, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1); + MemNSetBitFieldNb (NBPtr, BFForceAutoPchg, 0); + MemNSetBitFieldNb (NBPtr, BFDynPageCloseEn, 0); + MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 0); + MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0); + MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 0); + MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0); + MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 0); + MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 0); + MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, 0); + MemNSetBitFieldNb (NBPtr, BFBankSwap, 0); + MemNSetBitFieldNb (NBPtr, BFODTSEn, 0); + MemNSetBitFieldNb (NBPtr, BFDctSelIntLvEn, 0); + MemNSetBitFieldNb (NBPtr, BFCmdThrottleMode, 0); + MemNSetBitFieldNb (NBPtr, BFBwCapEn, 0); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function modifies CS interleaving low address according to several conditions for TN. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *LowBit - Pointer to low bit + * + */ + +BOOLEAN +MemNCSIntLvLowAddrAdjTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *LowBit + ) +{ + UINT8 DctSelIntLvAddr; + + DctSelIntLvAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvAddr); + // + //D18F2x[5C:40]_dct[1:0][15:5] = BaseAddr[21:11] && + //D18F2x[6C:60]_dct[1:0][15:5] = AddrMask[21:11], so *LowBit needs to be added with 2. + // + *(UINT8 *) LowBit += 2; + + if (MemNGetBitFieldNb (NBPtr, BFBankSwap) == 1) { + if (DctSelIntLvAddr == 4) { + *(UINT8 *) LowBit = 5; + } else { + *(UINT8 *) LowBit = 6; + } + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function releases the NB P-state force. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + */ +BOOLEAN +MemNReleaseNbPstateTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); + + // 6. Restore the initial D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0] values. + MemNSetBitFieldNb (NBPtr, BFNbPstateCtlReg, (MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg) & 0xFFFF9FFF) | (NBPtr->NbPsCtlReg & 0x6000)); + // 7. Restore the initial D18F5x170[NbPstateThreshold, NbPstateHi] values. + MemNSetBitFieldNb (NBPtr, BFNbPstateCtlReg, (MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg) & 0xFFFFF13F) | (NBPtr->NbPsCtlReg & 0x0EC0)); + // 8. Restore the initial D18F5x170[NbPstateLo] values. + MemNSetBitFieldNb (NBPtr, BFNbPstateLo, (NBPtr->NbPsCtlReg >> 3) & 3); + + // Clear NbPsSel to 0 + MemNSetBitFieldNb (NBPtr, BFNbPsSel, 0); + // Update TSC rate + FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); + + if (MemNGetBitFieldNb (NBPtr, BFMemPsSel) != 0) { + MemNChangeMemPStateContextNb (NBPtr, 0); + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function handles multiple stage of training when multiple Mem Pstate is enabled + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + * + */ + +BOOLEAN +MemNMemPstateStageChangeTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + BOOLEAN RetVal; + TRN_DLY_TYPE AccessType; + UINT8 Dct; + UINT8 ChipSel; + UINT8 ByteLane; + UINT16 CsEnabled; + UINT16 TrnDly; + + RetVal = FALSE; + + if (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE) { + MemNChangeMemPStateContextNb (NBPtr, 1); + // Load memory registers in M1 context from data saved in the heap + IDS_HDT_CONSOLE (MEM_FLOW, "\nLoad Training registers for M1 with DDR667 training result\n"); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + // Save MemPstate 1 data in output data structures + LibAmdMemCopy (NBPtr->ChannelPtr->RcvEnDlysMemPs1, NBPtr->ChannelPtr->RcvEnDlys, (MAX_DIMMS * MAX_DELAYS) * 2, &(NBPtr->MemPtr->StdHeader)); + LibAmdMemCopy (NBPtr->ChannelPtr->RdDqsDlysMemPs1, NBPtr->ChannelPtr->RdDqsDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader)); + LibAmdMemCopy (NBPtr->ChannelPtr->WrDqsDlysMemPs1, NBPtr->ChannelPtr->WrDqsDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader)); + LibAmdMemCopy (NBPtr->ChannelPtr->WrDatDlysMemPs1, NBPtr->ChannelPtr->WrDatDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader)); + LibAmdMemCopy (NBPtr->ChannelPtr->RdDqs2dDlysMemPs1, NBPtr->ChannelPtr->RdDqs2dDlys, MAX_DIMMS * MAX_NUMBER_LANES, &(NBPtr->MemPtr->StdHeader)); + LibAmdMemCopy (NBPtr->ChannelPtr->RdDqsMinDlysMemPs1, NBPtr->ChannelPtr->RdDqsMinDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader)); + LibAmdMemCopy (NBPtr->ChannelPtr->RdDqsMaxDlysMemPs1, NBPtr->ChannelPtr->RdDqsMaxDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader)); + LibAmdMemCopy (NBPtr->ChannelPtr->WrDatMinDlysMemPs1, NBPtr->ChannelPtr->WrDatMinDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader)); + LibAmdMemCopy (NBPtr->ChannelPtr->WrDatMaxDlysMemPs1, NBPtr->ChannelPtr->WrDatMaxDlys, MAX_DIMMS * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader)); + LibAmdMemCopy (NBPtr->ChannelPtr->FailingBitMaskMemPs1, NBPtr->ChannelPtr->FailingBitMask, MAX_CS_PER_CHANNEL * MAX_DELAYS, &(NBPtr->MemPtr->StdHeader)); + + CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; + // Set Memory Pstate 1 training value into registers + for (AccessType = AccessRcvEnDly; AccessType <= AccessWrDqsDly; AccessType ++) { + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL_TN; ChipSel = ChipSel + NBPtr->CsPerDelay) { + if ((CsEnabled & ((UINT16) ((NBPtr->CsPerDelay == 2)? 3 : 1) << ChipSel)) != 0) { + for (ByteLane = 0; ByteLane < 8; ByteLane++) { + TrnDly = (UINT16) GetTrainDlyFromHeapNb (NBPtr, AccessType, DIMM_BYTE_ACCESS (ChipSel / NBPtr->CsPerDelay, ByteLane)); + NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (ChipSel / NBPtr->CsPerDelay, ByteLane), TrnDly); + } + } + } + } + + if (NBPtr->RefPtr->EnablePowerDown) { + MemNSetTxpNb (NBPtr); + MemNSetBitFieldNb (NBPtr, BFPchgPDEnDelay, (MAX (MAX ((NBPtr->DCTPtr->Timings.CasL + 5), + (UINT8) (MemNGetBitFieldNb (NBPtr, BFTcwl) + NBPtr->DCTPtr->Timings.Twr + 5)), + (UINT8) MemNGetBitFieldNb (NBPtr, BFTmod)))); + MemNSetBitFieldNb (NBPtr, BFAggrPDDelay, 0x20); + } + MemNSetOtherTimingTN (NBPtr); + // Save timing data structure for memory Pstate 1 + LibAmdMemCopy (NBPtr->DCTPtr->TimingsMemPs1, &(NBPtr->DCTPtr->Timings), sizeof (CH_TIMING_STRUCT), &(NBPtr->MemPtr->StdHeader)); + + MemFInitTableDrive (NBPtr, MTAfterMemPstate1PartialTrn); + } + } + + // Switch back to M0 context + MemNChangeMemPStateContextNb (NBPtr, 0); + + // Load memory registers in M1 context from data saved in the heap + IDS_HDT_CONSOLE (MEM_FLOW, "\nGoing into training stage 2. Complete training at DDR667 is done.\n"); + NBPtr->MemPstateStage = MEMORY_PSTATE_2ND_STAGE; + } else if ((NBPtr->MemPstateStage == MEMORY_PSTATE_2ND_STAGE) && (NBPtr->DCTPtr->Timings.TargetSpeed == NBPtr->DCTPtr->Timings.Speed)) { + IDS_HDT_CONSOLE (MEM_FLOW, "\nGoing into training stage 3. Partial training at all frequencies is done.\n"); + NBPtr->MemPstateStage = MEMORY_PSTATE_3RD_STAGE; + RetVal = TRUE; + } else { + // MemPstate is disabled. Do not go through the MemPstate handling flow. + RetVal = TRUE; + } + + return RetVal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function Sets Power Down options and enables Power Down + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * The following registers are set: + * BFPowerDownMode BFPrtlChPDEnhEn + * BFTxp BFAggrPDDelay + * BFTxpDll BFAggrPDEn + * BFPchgPDEnDelay BFPowerDownEn + * + * NOTE: Delay values must be set before turning on the associated Enable bit + */ +VOID +MemNPowerDownCtlTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 PowerDownMode; + UINT8 Tmod; + UINT8 Twr; + UINT8 Tcwl; + UINT8 Tcl; + + if (NBPtr->RefPtr->EnablePowerDown) { + // + // PowerDownMode + // + PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; + PowerDownMode = (!NBPtr->IsSupported[ChannelPDMode]) ? PowerDownMode : 0; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode == 1) { + MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); + } + // + // Txp + // + MemNSetTxpNb (NBPtr); + // + // PchgPDModeSel is set elswhere. + // + // PchgPDEnDelay = MAX(Tcl + 5, Tcwl + Twr + 5, Tmod) + // + Tmod = (UINT8) MemNGetBitFieldNb (NBPtr, BFTmod); + Twr = NBPtr->DCTPtr->Timings.Twr; + Tcwl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcwl); + Tcl = NBPtr->DCTPtr->Timings.CasL; + MemNSetBitFieldNb (NBPtr, BFPchgPDEnDelay, (MAX (MAX ((Tcl + 5), (Tcwl + Twr + 5)), Tmod))); + // + // Partial Channel Power Down + // + MemNSetBitFieldNb (NBPtr, BFPrtlChPDDynDly, 0); + MemNSetBitFieldNb (NBPtr, BFPrtlChPDEnhEn, 0); + // + // Aggressive PowerDown + // + MemNSetBitFieldNb (NBPtr, BFAggrPDDelay, 0x20); + MemNSetBitFieldNb (NBPtr, BFAggrPDEn, 1); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Always set upper 2 bits of CKETri bitfield + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNBeforePlatformSpecTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSetBitFieldNb (NBPtr, BFCKETri, 0xC | MemNGetBitFieldNb (NBPtr, BFCKETri)); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c new file mode 100644 index 0000000000..a00fd2fb94 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c @@ -0,0 +1,156 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnflowtn.c + * + * TN initializer for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/TN) + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + **/ +/***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mntn.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + + +#define FILECODE PROC_MEM_NB_TN_MNFLOWTN_FILECODE +/* features */ + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function selects appropriate Tech functions for the NB. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNTechBlockSwitchTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + + TechPtr = NBPtr->TechPtr; + + // Specify Dimm-Byte training for Nb + MemTDimmByteTrainInit (TechPtr); + + // Remove the following functions because they are not needed for TN + TechPtr->SetDramMode = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue; + TechPtr->SpdCalcWidth = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue; + TechPtr->SetDqsEccTmgs = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue; + TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyRdDqsDlyByteUnb; + TechPtr->ResetDCTWrPtr = MemTResetRcvFifoUnb; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnidendimmtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnidendimmtn.c new file mode 100644 index 0000000000..ea93ecfc2a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnidendimmtn.c @@ -0,0 +1,172 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnidendimmtn.c + * + * TN northbridge constructor for dimm identification translator. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/TN) + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + **/ +/***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" +#include "mntn.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + + +#define FILECODE PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemNIdentifyDimmConstructorTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + */ + +BOOLEAN +MemNIdentifyDimmConstructorTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedTN (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->NodeCount = 1; + NBPtr->DctCount = MAX_DCTS_PER_NODE_TN; + NBPtr->CsRegMsk = 0x7FF8FFE0; + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Ganged = FALSE; + MemNInitNBRegTableTN (NBPtr, NBPtr->NBRegTable); + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldTN; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnmcttn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnmcttn.c new file mode 100644 index 0000000000..def21eee36 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnmcttn.c @@ -0,0 +1,562 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnmcttn.c + * + * Northbridge TN MCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/TN) + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + **/ +/***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" +#include "mntn.h" +#include "cpuFeatures.h" +#include "Filecode.h" +#include "mftds.h" +#include "mu.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + + +#define FILECODE PROC_MEM_NB_TN_MNMCTTN_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define _16MB_RJ16 0x0100 +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function force memory Pstate to M0 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNInitializeMctTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSetBitFieldNb (NBPtr, BFMemPsSel, 0); + MemNSetBitFieldNb (NBPtr, BFEnSplitMctDatBuffers, 1); + + MemUMFenceInstr (); + MemNSetBitFieldNb (NBPtr, BFMctEccDisLatOptEn, 1); + MemUMFenceInstr (); + + MemNBrdcstSetUnConditionalNb (NBPtr, BFPStateToAccess, 0); + + MemNForcePhyToM0Unb (NBPtr); + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets final values for specific registers. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNFinalizeMctTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + MEM_PARAMETER_STRUCT *RefPtr; + DRAM_PREFETCH_MODE DramPrefetchMode; + UINT16 Speed; + UINT32 Value32; + UINT8 DcqBwThrotWm1; + UINT8 DcqBwThrotWm2; + UINT8 Dct; + + MemPtr = NBPtr->MemPtr; + RefPtr = MemPtr->ParameterListPtr; + DramPrefetchMode = MemPtr->PlatFormConfig->PlatformProfile.AdvancedPerformanceProfile.DramPrefetchMode; + Speed = NBPtr->DCTPtr->Timings.Speed; + + // + // F2x11C + // + MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, 0x0CE00F31); + if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_IO || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) { + MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 1); + } + + if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_CPU || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) { + MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 1); + } + + + if (Speed == DDR667_FREQUENCY) { + DcqBwThrotWm1 = 3; + DcqBwThrotWm2 = 4; + } else if (Speed == DDR800_FREQUENCY) { + DcqBwThrotWm1 = 3; + DcqBwThrotWm2 = 5; + } else if (Speed == DDR1066_FREQUENCY) { + DcqBwThrotWm1 = 4; + DcqBwThrotWm2 = 6; + } else if (Speed == DDR1333_FREQUENCY) { + DcqBwThrotWm1 = 5; + DcqBwThrotWm2 = 8; + } else if (Speed == DDR1600_FREQUENCY) { + DcqBwThrotWm1 = 6; + DcqBwThrotWm2 = 9; + } else if (Speed == DDR1866_FREQUENCY) { + DcqBwThrotWm1 = 7; + DcqBwThrotWm2 = 10; + } else { + DcqBwThrotWm1 = 8; + DcqBwThrotWm2 = 12; + } + // + // F2x1B0 + // + Value32 = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg); + Value32 &= 0x003FE8C0; + Value32 |= 0x0FC01001; + MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, Value32); + + // + // F2x1B4 + // + Value32 = MemNGetBitFieldNb (NBPtr, BFExtMctCfgHiReg); + Value32 &= 0xFFFFFC00; + Value32 |= (((UINT32) DcqBwThrotWm2 << 5) | (UINT32) DcqBwThrotWm1); + MemNSetBitFieldNb (NBPtr, BFExtMctCfgHiReg, Value32); + + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + // + // Phy Power Saving + // + MemNPhyPowerSavingMPstateUnb (NBPtr); + if (NBPtr->MemPstateStage == MEMORY_PSTATE_3RD_STAGE) { + MemNChangeMemPStateContextNb (NBPtr, 1); + MemNPhyPowerSavingMPstateUnb (NBPtr); + MemFInitTableDrive (NBPtr, MTAfterSettingMemoryPstate1); + MemNChangeMemPStateContextNb (NBPtr, 0); + } + // + // Power Down Enable + // + if (NBPtr->RefPtr->EnablePowerDown) { + MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); + } + } + } + + // Set LockDramCfg + if (IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { + IDS_SKIP_HOOK (IDS_LOCK_DRAM_CFG, NBPtr, &NBPtr->MemPtr->StdHeader) { + MemNSetBitFieldNb (NBPtr, BFLockDramCfg, 1); + } + } + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function create the HT memory map for TN + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNHtMemMapInitTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 WeReMask; + UINT32 BottomIo; + UINT32 HoleOffset; + UINT32 DctSelBaseAddr; + UINT32 NodeSysBase; + UINT32 NodeSysLimit; + MEM_PARAMETER_STRUCT *RefPtr; + DIE_STRUCT *MCTPtr; + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + // + // Physical addresses in this function are right adjusted by 16 bits ([47:16]) + // They are BottomIO, HoleOffset, DctSelBaseAddr, NodeSysBase, NodeSysLimit. + // + + // Enforce bottom of IO be be 128MB aligned + BottomIo = (RefPtr->BottomIo & 0xF8) << 8; + + if (MCTPtr->NodeMemSize != 0) { + NodeSysBase = 0; + NodeSysLimit = MCTPtr->NodeMemSize - 1; + DctSelBaseAddr = MCTPtr->DctData[0].Timings.DctMemSize; + + if (NodeSysLimit >= BottomIo) { + // HW Dram Remap + MCTPtr->Status[SbHWHole] = TRUE; + RefPtr->GStatus[GsbHWHole] = TRUE; + MCTPtr->NodeHoleBase = BottomIo; + RefPtr->HoleBase = BottomIo; + + HoleOffset = _4GB_RJ16 - BottomIo; + + NodeSysLimit += HoleOffset; + + if ((DctSelBaseAddr > 0) && (DctSelBaseAddr < BottomIo)) { + HoleOffset += DctSelBaseAddr; + } else { + if (DctSelBaseAddr >= BottomIo) { + DctSelBaseAddr += HoleOffset; + } + HoleOffset += NodeSysBase; + } + + MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8); + MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7); + MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1); + MemNSetBitFieldNb (NBPtr, BFDramMemHoistValid, 1); + } else { + // No Remapping. Normal Contiguous mapping + } + MCTPtr->NodeSysBase = NodeSysBase; + MCTPtr->NodeSysLimit = NodeSysLimit; + RefPtr->SysLimit = MCTPtr->NodeSysLimit; + + WeReMask = 3; + // Set the Dram base and set the WE and RE flags in the base. + MemNSetBitFieldNb (NBPtr, BFDramBaseReg0, (NodeSysBase << 8) | WeReMask); + MemNSetBitFieldNb (NBPtr, BFDramBaseHiReg0, NodeSysBase >> 24); + // Set the Dram limit and set DstNode. + MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((NodeSysLimit << 8) & 0xFFFF0000)); + MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0, NodeSysLimit >> 24); + + MemNSetBitFieldNb (NBPtr, BFDramBaseAddr, NodeSysBase >> (27 - 16)); + MemNSetBitFieldNb (NBPtr, BFDramLimitAddr, NodeSysLimit >> (27 - 16)); + + if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) { + MemNSetBitFieldNb (NBPtr, BFDctSelBaseAddr, DctSelBaseAddr >> 11); + MemNSetBitFieldNb (NBPtr, BFDctSelHiRngEn, 1); + MemNSetBitFieldNb (NBPtr, BFDctSelHi, 1); + MemNSetBitFieldNb (NBPtr, BFDctSelBaseOffset, DctSelBaseAddr >> 10); + } + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Report the Uma size that is going to be allocated. + * Total system memory UMASize + * >= 2G 512M + * >=1G 256M + * <1G 64M + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Uma size [31:0] = Addr [47:16] + */ +UINT32 +MemNGetUmaSizeTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 SysMemSize; + UINT32 SizeOfUma; + + SysMemSize = NBPtr->RefPtr->SysLimit + 1; + SysMemSize = (SysMemSize + 0x100) & 0xFFFFF000; // Ignore 16MB allocated for C6 when finding UMA size + if (SysMemSize >= 0x8000) { + SizeOfUma = 512 << (20 - 16); + } else if (SysMemSize >= 0x4000) { + SizeOfUma = 256 << (20 - 16); + } else { + SizeOfUma = 64 << (20 - 16); + } + + return SizeOfUma; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function allocates 16MB of memory for C6 storage when it is requested to be enabled + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNAllocateC6StorageTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 SysLimit; + UINT32 DramLimitReg; + + if (NBPtr->SharedPtr->C6Enabled || IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { + + SysLimit = NBPtr->RefPtr->SysLimit; + + // Calculate new SysLimit + if (!NBPtr->SharedPtr->C6Enabled) { + // System memory available is reduced by 16MB + SysLimit -= _16MB_RJ16; + + NBPtr->MCTPtr->NodeSysLimit = SysLimit; + NBPtr->RefPtr->SysLimit = SysLimit; + NBPtr->SharedPtr->C6Enabled = TRUE; + + // Set TOPMEM and MTRRs (only need to be done once for BSC) + MemNC6AdjustMSRs (NBPtr); + } + + // Set Dram Limit + DramLimitReg = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0) & 0x0000FFFF; + MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((SysLimit << 8) & 0xFFFF0000) | DramLimitReg); + MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0, SysLimit >> 24); + + MemNSetBitFieldNb (NBPtr, BFCoreStateSaveDestNode, 0); + + // Set BFCC6SaveEn + MemNSetBitFieldNb (NBPtr, BFCC6SaveEn, 1); + // LockDramCfg will be set in FinalizeMCT + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function adjusts NB pstate norbridge voltage for TN + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNAdjustNBPstateVolTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + + D0F0xBC_xE0104168_STRUCT D0F0xBC_xE0104168; + D0F0xBC_xE010416C_STRUCT D0F0xBC_xE010416C; + D0F0xBC_xE0104170_STRUCT D0F0xBC_xE0104170; + UINT8 MemClkVidHi; + UINT8 MemClkVidLo; + UINT8 MemPstate; + UINT8 NbVid; + UINT8 NbPs; + UINT8 NbPstateMaxVal; + + IDS_HDT_CONSOLE (MEM_FLOW, "\nStart NB Pstate voltage adjustment.\n"); + + GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE0104168_ADDRESS, &D0F0xBC_xE0104168.Value, 0, &(NBPtr->MemPtr->StdHeader)); + GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE010416C_ADDRESS, &D0F0xBC_xE010416C.Value, 0, &(NBPtr->MemPtr->StdHeader)); + GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE0104170_ADDRESS, &D0F0xBC_xE0104170.Value, 0, &(NBPtr->MemPtr->StdHeader)); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tD0F0xBC_xE0104168: %08x\n", D0F0xBC_xE0104168.Value); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tD0F0xBC_xE010416C: %08x\n", D0F0xBC_xE010416C.Value); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tD0F0xBC_xE0104170: %08x\n", D0F0xBC_xE0104170.Value); + + // MemClkVidHi = read D0F0xBC_xE0104168 through D0F0xBC_xE0104170 to find the VID code corresponding + // to the M0 MEMCLK. If the M0 MEMCLK is not found, use the next higher defined MEMCLK as the target. + switch (NBPtr->DCTPtr->Timings.TargetSpeed) { + case DDR667_FREQUENCY: + MemClkVidHi = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid0_7_0; + break; + case DDR800_FREQUENCY: + MemClkVidHi = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid1_7_0; + break; + case DDR1066_FREQUENCY: + MemClkVidHi = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid2_7_0; + break; + case DDR1333_FREQUENCY: + MemClkVidHi = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid3_1_0 | ((UINT8) D0F0xBC_xE010416C.Field.MemClkVid3_7_2 << 2); + break; + case DDR1600_FREQUENCY: + MemClkVidHi = (UINT8) D0F0xBC_xE010416C.Field.MemClkVid4_7_0; + break; + case DDR1866_FREQUENCY: + MemClkVidHi = (UINT8) D0F0xBC_xE010416C.Field.MemClkVid5_7_0; + break; + case DDR2100_FREQUENCY: + MemClkVidHi = (UINT8) D0F0xBC_xE010416C.Field.MemClkVid6_7_0; + break; + case DDR2133_FREQUENCY: + MemClkVidHi = (UINT8) D0F0xBC_xE010416C.Field.MemClkVid7_1_0 | ((UINT8) D0F0xBC_xE0104170.Field.MemClkVid7_7_2 << 2); + break; + case DDR2400_FREQUENCY: + MemClkVidHi = (UINT8) D0F0xBC_xE0104170.Field.MemClkVid8_7_0; + break; + default: + // If the M0 MEMCLK is greater than MemClkVid8, use the MemClkVid8 VID as the target + MemClkVidHi = (UINT8) D0F0xBC_xE0104170.Field.MemClkVid8_7_0; + } + + // MemClkVidLo = read D0F0xBC_xE0104168 through D0F0xBC_xE0104170 to find the VID code corresponding + // to the M1 MEMCLK. If the M1 MEMCLK is not found, use the next higher defined MEMCLK as the target. + MemClkVidLo = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid0_7_0; + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tOriginal MemClkVidLo: %02x\n", MemClkVidLo); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tOriginal MemClkVidHi: %02x\n", MemClkVidHi); + + // If D18F5x188[NbOffsetTrim] == 01b, MemClkVid = Fuse[MemClkVid] - 4 (-25mV offset so add 25mV to VID) + // Else if D18F5x188[NbOffsetTrim] == 11b, MemClkVid = Fuse[MemClkVid] + 4 (+25mV offset so decrease 25mV from VID) + // Else MemClkVid = Fuse[MemClkVid] + if (MemNGetBitFieldNb (NBPtr, BFNbOffsetTrim) == 1) { + MemClkVidLo -= 4; + MemClkVidHi -= 4; + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tAdd 25mV\n"); + } else if (MemNGetBitFieldNb (NBPtr, BFNbOffsetTrim) == 3) { + MemClkVidLo += 4; + MemClkVidHi += 4; + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDecrease 25mV\n"); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tAdjusted MemClkVidLo: %02x\n", MemClkVidLo); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tAdjusted MemClkVidHi: %02x\n", MemClkVidHi); + + // For each NB P-state from NBP0 through D18F5x170[NbPstateMaxVal]: + // If ((D18F5x1[6C:60][MemPstate] == 0) && (MemClkVidHi voltage > D18F5x1[6C:60][NbVid] voltage)): + // Program D18F5x1[6C:60][NbVid] == MemClkVidHi. + // If ((D18F5x1[6C:60][MemPstate] == 1) && (MemClkVidLo voltage > D18F5x1[6C:60][NbVid] voltage)): + // Program D18F5x1[6C:60][NbVid] == MemClkVidLo. + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tNBPs\tNbVid\tMemPstate\tOverride\n"); + NbPstateMaxVal = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPstateMaxVal); + for (NbPs = 0; NbPs <= NbPstateMaxVal; NbPs ++) { + NbVid = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbVid0 + (NbPs << 1)); + MemPstate = (UINT8) MemNGetBitFieldNb (NBPtr, BFMemPstate0 + NbPs); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t %01d \t %02x \t %01d \t", NbPs, NbVid, MemPstate); + // higher voltage correspond to smaller VID + if ((MemPstate == 0) && (MemClkVidHi < NbVid)) { + MemNSetBitFieldNb (NBPtr, BFNbVid0 + (NbPs << 1), MemClkVidHi); + IDS_HDT_CONSOLE (MEM_FLOW, "MemClkVidHi\n"); + } else if ((MemPstate == 1) && (MemClkVidLo < NbVid)) { + MemNSetBitFieldNb (NBPtr, BFNbVid0 + (NbPs << 1), MemClkVidLo); + IDS_HDT_CONSOLE (MEM_FLOW, "MemClkVidLo\n"); + } else { + IDS_HDT_CONSOLE (MEM_FLOW, "No change\n"); + } + } +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c new file mode 100644 index 0000000000..821bb1d63d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c @@ -0,0 +1,348 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnottn.c + * + * Northbridge Non-SPD timings for TN + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/TN) + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + **/ +/***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "OptionMemory.h" +#include "mntn.h" +#include "mu.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_MEM_NB_TN_MNOTTN_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +#if 0 +UINT32 +STATIC +MemNGetODTDelaysTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +#endif + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNOtherTimingTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Programming of Non-SPD Timings.\n"); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { + MemNSetOtherTimingTN (NBPtr); + } + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings in PCI registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSetOtherTimingTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT8 ROD; + INT8 WOD; + INT8 LD; + INT8 WrEarlyx2; + INT8 CDDTrdrdSdDc; + INT8 CDDTrdrdDd; + INT8 CDDTwrwrDd; + INT8 CDDTwrwrSdDc; + INT8 CDDTrwtTO; + INT8 CDDTwrrd; + UINT8 TrdrdSdDc; + UINT8 TrdrdDd; + UINT8 TwrwrSdDc; + UINT8 TwrwrDd; + UINT8 TrdrdSdSc; + UINT8 TwrwrSdSc; + UINT8 Twrrd; + UINT8 TrwtTO; + BOOLEAN PerRankTimingEn; + + CH_DEF_STRUCT *ChannelPtr; + ChannelPtr = NBPtr->ChannelPtr; + + PerRankTimingEn = (BOOLEAN) (MemNGetBitFieldNb (NBPtr, BFPerRankTimingEn)); + // + // Latency Difference (LD) = Tcl - Tcwl + // + LD = (INT8) (MemNGetBitFieldNb (NBPtr, BFTcl)) - (INT8) (MemNGetBitFieldNb (NBPtr, BFTcwl)); + + // + // Read ODT Delay (ROD) = MAX ( 0, (RdOdtOnDuration - 6)) + MAX ( 0, (RdOdtTrnOnDly - LD)) + // + ROD = MAX (0, (INT8) (MemNGetBitFieldNb (NBPtr, BFRdOdtOnDuration) - 6)) + + MAX ( 0, (INT8) (MemNGetBitFieldNb (NBPtr, BFRdOdtTrnOnDly) - LD)); + // + // Write ODT Delay (WOD) = MAX (0, (WrOdtOnDuration - 6)) + // + WOD = MAX (0, (INT8) (MemNGetBitFieldNb (NBPtr, BFWrOdtOnDuration) - 6)); + // + // WrEarly = ABS (WrDqDqsEarly) / 2 + // + WrEarlyx2 = (INT8) MemNGetBitFieldNb (NBPtr, BFWrDqDqsEarly); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tLD: %d ROD: %d WOD: %d WrEarlyx2: %d\n\n", LD, ROD, WOD, WrEarlyx2); + // + // Read to Read Timing (TrdrdSdSc, TrdrdScDc, TrdrdDd) + // + // TrdrdSdSc = 1. + // TrdrdSdDc (in MEMCLKs) = MAX(TrdrdSdSc, 3 + (IF (D18F2xA8_dct[1:0][PerRankTimingEn]) + // THEN CEIL(CDDTrdrdSdDc / 2 ) ELSE 0 ENDIF)). + // TrdrdDd = MAX(TrdrdSdDc, CEIL(MAX(ROD + 3, CDDTrdrdDd/2 + 3.5))) + // + TrdrdSdSc = 1; + + CDDTrdrdSdDc = (INT8) MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly, TRUE, FALSE); + TrdrdSdDc = MAX (0, PerRankTimingEn ? (3 + (CDDTrdrdSdDc + 1) / 2) : 3); + TrdrdSdDc = MAX (TrdrdSdSc, TrdrdSdDc); + + CDDTrdrdDd = (INT8) MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly, FALSE, TRUE); + TrdrdDd = MAX (ROD + 3, (CDDTrdrdDd + 7 + 1) / 2); + TrdrdDd = MAX (TrdrdSdDc, TrdrdDd); + + MemNSetBitFieldNb (NBPtr, BFTrdrdDd, (UINT32) TrdrdDd); + MemNSetBitFieldNb (NBPtr, BFTrdrdSdDc, (UINT32) TrdrdSdDc); + MemNSetBitFieldNb (NBPtr, BFTrdrdSdSc, (UINT32) TrdrdSdSc); + // + // Write to Write Timing (TwrwrSdSc, TwrwrScDc, TwrwrDd) + // + // TwrwrSdSc = 1. + // TwrwrSdDc = CEIL(MAX(WOD + 3, CDDTwrwrSdDc / 2 + + // (IF (D18F2xA8_dct[1:0][PerRankTimingEn]) THEN 3.5 ELSE 3 ENDIF))). + // + // TwrwrDd = CEIL (MAX (WOD + 3, CDDTwrwrDd / 2 + 3.5)) + // TwrwrSdSc <= TwrwrSdDc <= TwrwrDd + // + TwrwrSdSc = 1; + + CDDTwrwrSdDc = (INT8) MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessWrDqsDly, TRUE, FALSE); + TwrwrSdDc = (UINT8) MAX (WOD + 3, (CDDTwrwrSdDc + (PerRankTimingEn ? 7 : 6) + 1 ) / 2); + + CDDTwrwrDd = (INT8) MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessWrDqsDly, FALSE, TRUE); + TwrwrDd = (UINT8) MAX ((UINT8) (WOD + 3), (CDDTwrwrDd + 7 + 1) / 2); + + TwrwrSdDc = (TwrwrSdSc <= TwrwrSdDc) ? TwrwrSdDc : TwrwrSdSc; + TwrwrDd = (TwrwrSdDc <= TwrwrDd) ? TwrwrDd : TwrwrSdDc; + + MemNSetBitFieldNb (NBPtr, BFTwrwrDd, (UINT32) TwrwrDd); + MemNSetBitFieldNb (NBPtr, BFTwrwrSdDc, (UINT32) TwrwrSdDc); + MemNSetBitFieldNb (NBPtr, BFTwrwrSdSc, (UINT32) TwrwrSdSc); + // + // Write to Read DIMM Termination Turn-around + // + // Twrrd = MAX ( 1, CEIL (MAX (WOD, (CDDTwrrd / 2) + 0.5 - WrEarly) - LD + 3)) + // + CDDTwrrd = (INT8) MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessRcvEnDly, TRUE, TRUE); + Twrrd = MAX (1, MAX (WOD, (CDDTwrrd + 1 - WrEarlyx2 + 1) / 2) - LD + 3); + + MemNSetBitFieldNb (NBPtr, BFTwrrd, (UINT32) Twrrd); + // + // Read to Write Turnaround for Data, DQS Contention + // + // TrwtTO = CEIL (MAX (ROD, (CDDTrwtTO / 2) - 0.5 + WrEarly) + LD + 3) + // + CDDTrwtTO = (INT8) MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessWrDqsDly, TRUE, TRUE); + + TrwtTO = MAX ((ChannelPtr->Dimms == 1 ? 0 : ROD) , (CDDTrwtTO - 1 + WrEarlyx2 + 1) / 2) + LD + 3; + + MemNSetBitFieldNb (NBPtr, BFTrwtTO, (UINT32) TrwtTO); + // + // Read to Write Turnaround for opportunistic Write Bursting + // + // TrwtWB = TrwtTO + 1 + // + MemNSetBitFieldNb (NBPtr, BFTrwtWB, (UINT32) TrwtTO + 1); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t TrdrdSdSc : %02x\n", TrdrdSdSc); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrdrdSdDc : %02x TrdrdSdDc : %02x\n", CDDTrdrdSdDc, TrdrdSdDc); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrdrdDd : %02x TrdrdDd : %02x\n\n", CDDTrdrdDd, TrdrdDd); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t TwrwrSdSc : %02x\n", TwrwrSdSc); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrwrSdDc : %02x TwrwrSdDc : %02x\n", CDDTwrwrSdDc, TwrwrSdDc ); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrwrDd : %02x TwrwrDd : %02x\n\n", CDDTwrwrDd, TwrwrDd); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t TrwtWB : %02x\n", TrwtTO + 1); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrrd : %02x Twrrd : %02x\n", (UINT8) CDDTwrrd, (UINT8) Twrrd ); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrwtTO : %02x TrwtTO : %02x\n\n", (UINT8) CDDTrwtTO, (UINT8) TrwtTO ); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the ODT delays + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +#if 0 +UINT32 +STATIC +MemNGetODTDelaysTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT8 Ld; + UINT32 ODTDelays; + // + // The BIOS must additionally configure the ODT pattern + // and the ODT switching delays. + // + // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length. + // -Read the Burst Length from F2x[1, 0]84[BurstCtrl]. + // -Value of 2, BL = 4 else assume BL=8. + // -Initialize ODTDelays based on BL value + // -WrOdtOnDuration [14:12] = BL / 2 + 1 + // -WrOdtTrnOnDly [10:8] = 0 + // -RdOdtOnDuration [6:4] = BL / 2 + 1 + // + ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050; + + // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1) + // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0] + Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5); + if (Ld < 0) { + Ld = 0; + } + if (Ld > 7) { + Ld = 7; + } + ODTDelays += Ld; + return ODTDelays; +} +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnphytn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnphytn.c new file mode 100644 index 0000000000..8a0199420f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnphytn.c @@ -0,0 +1,742 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnphytn.c + * + * Northbridge Phy support for TN + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/TN) + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + **/ +/***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "ma.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB +#include "mntn.h" +#include "PlatformMemoryConfiguration.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + + +#define FILECODE PROC_MEM_NB_TN_MNPHYTN_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 + + +/// The structure of TxPrePN tables +typedef struct { + UINT32 Speed; ///< Applied memory speed + UINT16 TxPrePNVal[4]; ///< Table values +} TXPREPN_STRUCT; + +/// The entry of individual TxPrePN tables +typedef struct { + UINT8 TxPrePNTblSize; ///< Total Table size + CONST TXPREPN_STRUCT *TxPrePNTblPtr; ///< Pointer to the table +} TXPREPN_ENTRY; + +/// Type of an entry for processing phy init compensation for TN +typedef struct { + BIT_FIELD_NAME IndexBitField; ///< Bit field on which the value is decided + BIT_FIELD_NAME StartTargetBitField; ///< First bit field to be modified + BIT_FIELD_NAME EndTargetBitField; ///< Last bit field to be modified + UINT16 ExtraValue; ///< Extra value needed to be written to bit field + CONST TXPREPN_ENTRY *TxPrePN; ///< Pointer to slew rate table +} PHY_COMP_INIT_NB; +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemNRdPosTrnTN ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[]; +/* -----------------------------------------------------------------------------*/ + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the DDR phy compensation logic + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitPhyCompTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // + // Phy Predriver Calibration Codes for Data/DQS + // + CONST STATIC TXPREPN_STRUCT TxPrePNDataDqsV15TN[] = { + //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.5V + {DDR667 + DDR800, {0x924, 0x924, 0x924, 0x924}}, + {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xFF6}}, + {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xFF6, 0xFF6, 0xFF6}} + }; + CONST STATIC TXPREPN_STRUCT TxPrePNDataDqsV135TN[] = { + //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.35V + {DDR667 + DDR800, {0xFF6, 0xB6D, 0xB6D, 0x924}}, + {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xFF6}}, + {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xFF6, 0xFF6, 0xFF6}} + }; + CONST STATIC TXPREPN_STRUCT TxPrePNDataDqsV125TN[] = { + //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.25V + {DDR667 + DDR800, {0xFF6, 0xDAD, 0xDAD, 0x924}}, + {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xFF6}}, + {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xFF6, 0xFF6, 0xFF6}} + }; + CONST STATIC TXPREPN_ENTRY TxPrePNDataDqsTN[] = { + {GET_SIZE_OF (TxPrePNDataDqsV15TN), (TXPREPN_STRUCT *)&TxPrePNDataDqsV15TN}, + {GET_SIZE_OF (TxPrePNDataDqsV135TN), (TXPREPN_STRUCT *)&TxPrePNDataDqsV135TN}, + {GET_SIZE_OF (TxPrePNDataDqsV125TN), (TXPREPN_STRUCT *)&TxPrePNDataDqsV125TN} + }; + + // + // Phy Predriver Calibration Codes for Cmd/Addr + // + CONST STATIC TXPREPN_STRUCT TxPrePNCmdAddrV15TN[] = { + //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.5V + {DDR667 + DDR800, {0x492, 0x492, 0x492, 0x492}}, + {DDR1066 + DDR1333, {0x6DB, 0x6DB, 0x6DB, 0x6DB}}, + {DDR1600 + DDR1866 + DDR2133, {0xB6D, 0xB6D, 0xB6D, 0xB6D}} + }; + CONST STATIC TXPREPN_STRUCT TxPrePNCmdAddrV135TN[] = { + //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.35V + {DDR667 + DDR800, {0x492, 0x492, 0x492, 0x492}}, + {DDR1066 + DDR1333, {0x924, 0x6DB, 0x6DB, 0x6DB}}, + {DDR1600 + DDR1866 + DDR2133, {0xB6D, 0xB6D, 0x924, 0x924}} + }; + CONST STATIC TXPREPN_STRUCT TxPrePNCmdAddrV125TN[] = { + //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.25V + {DDR667 + DDR800, {0x492, 0x492, 0x492, 0x492}}, + {DDR1066 + DDR1333, {0xDAD, 0x924, 0x6DB, 0x492}}, + {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xDAD, 0xB64, 0xB64}} + }; + CONST STATIC TXPREPN_ENTRY TxPrePNCmdAddrTN[] = { + {GET_SIZE_OF (TxPrePNCmdAddrV15TN), (TXPREPN_STRUCT *)&TxPrePNCmdAddrV15TN}, + {GET_SIZE_OF (TxPrePNCmdAddrV135TN), (TXPREPN_STRUCT *)&TxPrePNCmdAddrV135TN}, + {GET_SIZE_OF (TxPrePNCmdAddrV125TN), (TXPREPN_STRUCT *)&TxPrePNCmdAddrV125TN} + }; + + // + // Phy Predriver Calibration Codes for Clock + // + CONST STATIC TXPREPN_STRUCT TxPrePNClockV15TN[] = { + //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.5V + {DDR667 + DDR800, {0x924, 0x924, 0x924, 0x924}}, + {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xB6D}}, + {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xFF6, 0xFF6, 0xFF6}} + }; + CONST STATIC TXPREPN_STRUCT TxPrePNClockV135TN[] = { + //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.35V + {DDR667 + DDR800, {0xDAD, 0xDAD, 0x924, 0x924}}, + {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xDAD}}, + {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xFF6, 0xFF6, 0xDAD}} + }; + CONST STATIC TXPREPN_STRUCT TxPrePNClockV125TN[] = { + //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.25V + {DDR667 + DDR800, {0xDAD, 0xDAD, 0x924, 0x924}}, + {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xFF6}}, + {DDR1600 + DDR1866 + DDR2133, {0xFF6, 0xFF6, 0xFF6, 0xFF6}} + }; + CONST STATIC TXPREPN_ENTRY TxPrePNClockTN[] = { + {GET_SIZE_OF (TxPrePNClockV15TN), (TXPREPN_STRUCT *)&TxPrePNClockV15TN}, + {GET_SIZE_OF (TxPrePNClockV135TN), (TXPREPN_STRUCT *)&TxPrePNClockV135TN}, + {GET_SIZE_OF (TxPrePNClockV125TN), (TXPREPN_STRUCT *)&TxPrePNClockV125TN} + }; + + // + // Tables to describe the relationship between drive strength bit fields, PreDriver Calibration bit fields and also + // the extra value that needs to be written to specific PreDriver bit fields + // + CONST PHY_COMP_INIT_NB PhyCompInitBitFieldTN[] = { + // 3. Program TxPreP/TxPreN for Data and DQS according toTable 25 if VDDIO is 1.5V or Table 26 if 1.35V. + // A. Program D18F2x9C_x0D0F_0[F,7:0]0[A,6]_dct[1:0]={0000b, TxPreP, TxPreN}. + // B. Program D18F2x9C_x0D0F_0[F,7:0]02_dct[1:0]={0000b, TxPreP, TxPreN}. + {BFDqsDrvStren, BFDataByteTxPreDriverCal2Pad1, BFDataByteTxPreDriverCal2Pad1, 0, TxPrePNDataDqsTN}, + {BFDataDrvStren, BFDataByteTxPreDriverCal2Pad2, BFDataByteTxPreDriverCal2Pad2, 0, TxPrePNDataDqsTN}, + {BFDataDrvStren, BFDataByteTxPreDriverCal, BFDataByteTxPreDriverCal, 8, TxPrePNDataDqsTN}, + // 4. Program TxPreP/TxPreN for Cmd/Addr according to Table 28 if VDDIO is 1.5V or Table 29 if 1.35V. + // A. Program D18F2x9C_x0D0F_[C,8][1:0][12,0E,0A,06]_dct[1:0]={0000b, TxPreP, TxPreN}. + // B. Program D18F2x9C_x0D0F_[C,8][1:0]02_dct[1:0]={1000b, TxPreP, TxPreN}. + {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCal2Pad1, BFCmdAddr0TxPreDriverCal2Pad2, 0, TxPrePNCmdAddrTN}, + {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCal2Pad1, BFAddrTxPreDriverCal2Pad4, 0, TxPrePNCmdAddrTN}, + {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCalPad0, BFCmdAddr0TxPreDriverCalPad0, 8, TxPrePNCmdAddrTN}, + {BFCkeDrvStren, BFAddrTxPreDriverCalPad0, BFAddrTxPreDriverCalPad0, 8, TxPrePNCmdAddrTN}, + {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCalPad0, BFCmdAddr1TxPreDriverCalPad0, 8, TxPrePNCmdAddrTN}, + // 5. Program TxPreP/TxPreN for Clock according to Table 31 if VDDIO is 1.5V or Table 32 if 1.35V. + // A. Program D18F2x9C_x0D0F_2[2:0]02_dct[1:0]={1000b, TxPreP, TxPreN}. + {BFClkDrvStren, BFClock0TxPreDriverCalPad0, BFClock2TxPreDriverCalPad0, 8, TxPrePNClockTN} + }; + + BIT_FIELD_NAME CurrentBitField; + UINT32 SpeedMask; + UINT8 SizeOfTable; + UINT8 Voltage; + UINT8 i; + UINT8 j; + UINT8 k; + UINT8 Dct; + CONST TXPREPN_STRUCT *TblPtr; + + Dct = NBPtr->Dct; + NBPtr->SwitchDCT (NBPtr, 0); + // 1. Program D18F2x[1,0]9C_x0000_0008[DisAutoComp, DisablePreDriverCal] = {1b, 1b}. + MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 3); + NBPtr->SwitchDCT (NBPtr, Dct); + + SpeedMask = (UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66); + Voltage = (UINT8) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage); + + for (j = 0; j < GET_SIZE_OF (PhyCompInitBitFieldTN); j ++) { + i = (UINT8) MemNGetBitFieldNb (NBPtr, PhyCompInitBitFieldTN[j].IndexBitField); + TblPtr = (PhyCompInitBitFieldTN[j].TxPrePN[Voltage]).TxPrePNTblPtr; + SizeOfTable = (PhyCompInitBitFieldTN[j].TxPrePN[Voltage]).TxPrePNTblSize; + for (k = 0; k < SizeOfTable; k++, TblPtr++) { + if ((TblPtr->Speed & SpeedMask) != 0) { + for (CurrentBitField = PhyCompInitBitFieldTN[j].StartTargetBitField; CurrentBitField <= PhyCompInitBitFieldTN[j].EndTargetBitField; CurrentBitField ++) { + MemNSetBitFieldNb (NBPtr, CurrentBitField, ((PhyCompInitBitFieldTN[j].ExtraValue << 12) | TblPtr->TxPrePNVal[i])); + } + break; + } + } + // Asserting if no table is found corresponding to current memory speed. + ASSERT (k < SizeOfTable); + } + NBPtr->SwitchDCT (NBPtr, 0); + // 6. Program D18F2x9C_x0000_0008_dct[1:0]_mp[1:0][DisAutoComp] = 0. + MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 1); + NBPtr->SwitchDCT (NBPtr, Dct); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDQSTrainingTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + MemNSetBitFieldNb (NBPtr, BFTrNibbleSel, 0); + // + // 2.10.6.9.2 - BIOS should program D18F2x210_dct[1:0]_nbp[3:0][MaxRdLatency] to 55h. + // + MemNSetBitFieldNb (NBPtr, BFMaxLatency, 0x55); + NBPtr->CsPerDelay = MemNCSPerDelayNb (NBPtr); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a function that executes after DRAM training for TN + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNAfterDQSTrainingTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + BOOLEAN DllShutDownEn; + UINT8 Dimm; + UINT8 Byte; + UINT16 Dly; + + DllShutDownEn = TRUE; + IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader)); + + MemNBrdcstSetNb (NBPtr, BFMemPhyPllPdMode, 2); + MemNBrdcstSetNb (NBPtr, BFPllLockTime, 0x190); + + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + // + // 2.10.6.7 DCT Training Specific Configuration + // + MemNSetBitFieldNb (NBPtr, BFAddrCmdTriEn, 1); + MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0); + if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) { + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); + } + MemNSetBitFieldNb (NBPtr , BFForceAutoPchg, 0); + MemNSetBitFieldNb (NBPtr , BFDynPageCloseEn, 0); + if (NBPtr->RefPtr->EnableBankSwizzle) { + MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); + } + MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0x01F); + MemNPowerDownCtlTN (NBPtr); + MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2); + MemNSetBitFieldNb (NBPtr, BFBankSwap, 1); + // + // Post Training values for BFRxMaxDurDllNoLock, BFTxMaxDurDllNoLock, + // and BFEnRxPadStandby are handled by Power savings code + // + // BFBwCapEn and BFODTSEn are handled by OnDimmThermal Code + // + // BFDctSelIntLvEn is programmed by Interleaving feature + // + } + } + // + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + if (!(NBPtr->DctCachePtr->excel846 )) { + for (Dimm = 0; Dimm < 4; Dimm++) { + for (Byte = 0; Byte < 9; Byte++) { + Dly = (UINT16) MemNGetTrainDlyNb (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, Byte)); + MemNSetTrainDlyNb (NBPtr, excel845 , DIMM_NBBL_ACCESS (Dimm, Byte * 2), Dly); + MemNSetTrainDlyNb (NBPtr, excel845 , DIMM_NBBL_ACCESS (Dimm, (Byte * 2) + 1), Dly); + } + } + } + } + } +} +/* -----------------------------------------------------------------------------*/ +/** + * + * This function overrides the seed for hardware based RcvEn training of TN. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *SeedPtr - Pointer to the seed value. + * + * @return TRUE + */ + +BOOLEAN +MemNOverrideRcvEnSeedTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *SeedPtr + ) +{ + *(UINT16 *)SeedPtr = 0x32 - (0x20 * (UINT16) MemNGetBitFieldNb (NBPtr, BFWrDqDqsEarly)); + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function choose the correct PllLockTime for TN + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *PllLockTime - Bit offset of the field to be programmed + * + * @return TRUE + */ +BOOLEAN +MemNAdjustPllLockTimeTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *PllLockTime + ) +{ + if (MemNGetBitFieldNb (NBPtr, BFMemPhyPllPdMode) == 2) { + *(UINT16*) PllLockTime = 0x190; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function overrides the seed for hardware based WL for TN. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *SeedPtr - Pointer to the seed value. + * + * @return TRUE + */ + +BOOLEAN +MemNOverrideWLSeedTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *SeedPtr + ) +{ + if (NBPtr->ChannelPtr->SODimmPresent != 0) { + *(UINT8*) SeedPtr = 0xE; + } else { + // Unbuffered dimm + *(UINT8*) SeedPtr = 0x15; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function adjusts Avg PRE value of Phy fence training for TN. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *Value16 - Pointer to the value that we want to adjust + * + */ +VOID +MemNPFenceAdjustTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT INT16 *Value16 + ) +{ + if (*Value16 < 0) { + *Value16 = 0; + } + + // This makes sure the phy fence value will be written to M1 context as well. + MULTI_MPSTATE_COPY_TSEFO (NBPtr->NBRegTable, BFPhyFence); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs Fence2RxDll for TN. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *Fence2Data - Pointer to the value of fence2 data + * + */ +BOOLEAN +MemNProgramFence2RxDllTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *Fence2Data + ) +{ + UINT8 Dct; + UINT16 Fence2RxDllTxPad; + UINT16 Fence2Value; + UINT16 Fence1; + BIT_FIELD_NAME BitField; + + Fence2Value = (UINT16) MemNGetBitFieldNb (NBPtr, BFFence2); + Fence2RxDllTxPad = (*(UINT16*) Fence2Data & 0x1F) | (((*(UINT16*) Fence2Data >> 5) & 0x1F) << 10); + + Fence2Value &= ~(UINT16) ((0x1F << 10) | 0x1F); + Fence2Value |= Fence2RxDllTxPad; + MemNSetBitFieldNb (NBPtr, BFFence2, Fence2Value); + + if (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE) { + MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 16, BFPhyFence); + BitField = (NBPtr->Dct == 0) ? BFChAM1FenceSave : BFChBM1FenceSave; + + Fence1 = (UINT16) MemNGetBitFieldNb (NBPtr, BFPhyFence); + Dct = NBPtr->Dct; + MemNSwitchDCTNb (NBPtr, 1); + MemNSetBitFieldNb (NBPtr, BitField, Fence1); + MemNSwitchDCTNb (NBPtr, Dct); + } + + return TRUE; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function checks if RdDqsDly needs to be restarted for Trinity + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *Center - Center of the data eye + * + * @return TRUE + */ + +BOOLEAN +MemNRdDqsDlyRestartChkTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *Center + ) +{ + INT8 EyeCenter; + UINT8 ByteLane; + BOOLEAN RetVal; + MEM_TECH_BLOCK *TechPtr; + CH_DEF_STRUCT *ChanPtr; + + TechPtr = NBPtr->TechPtr; + ChanPtr = NBPtr->ChannelPtr; + ByteLane = NBPtr->TechPtr->Bytelane; + RetVal = TRUE; + + // If the average value of passing read DQS delay for the lane is negative, then adjust the input receiver + // DQ delay in D18F2x9C_x0D0F_0[F,7:0][5F,1F]_dct[1:0] for the lane as follows: + + EyeCenter = ((INT8) ChanPtr->RdDqsMinDlys[ByteLane] + (INT8) ChanPtr->RdDqsMaxDlys[ByteLane] + 1) / 2; + + if ((EyeCenter < 0) && (NBPtr->RdDqsDlyRetrnStat != RDDQSDLY_RTN_SUSPEND)) { + IDS_HDT_CONSOLE (MEM_FLOW, " Negative data eye center.\n"); + + if (MemNGetBitFieldNb (NBPtr, BFRxBypass3rd4thStg) == 4) { + // IF (RxBypass3rd4thStg == 1) program RxBypass3rd4thStg=0 and repeat step 3 above for all + // ranks and lanes + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tRxByPass3rd4thStg is 1, clear it and restart RdDqsDly training on current Dct.\n"); + + MemNSetBitFieldNb (NBPtr, BFRxBypass3rd4thStg, 0); + NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_ONGOING; + + // When Retrain condition is first detected, record the current chipsel at which the retrain starts + // so we don't need to retrain RcvEnDly and WrDatDly on the chipsels that are already done with these steps. + TechPtr->RestartChipSel = (INT8) TechPtr->ChipSel; + + RetVal = FALSE; + } else if (MemNGetBitFieldNb (NBPtr, BFRx4thStgEn) == 0) { + // ELSEIF (Rx4thStgEn == 0) program Rx4thStgEn=1 and repeat step 3 above for all ranks and lanes + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tRx4thStg is 0, set it and restart RdDqsDly training on current Dct.\n"); + + MemNSetBitFieldNb (NBPtr, BFRx4thStgEn, 0x100); + NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_ONGOING; + + // If the second retrain starts beyond the chip selects that are previously trained, update the record so + // we don't need to retrain RcvEnDly and WrDatDly + if (TechPtr->RestartChipSel < ((INT8) TechPtr->ChipSel)) { + TechPtr->RestartChipSel = (INT8) TechPtr->ChipSel; + } + + RetVal = FALSE; + } else { + // ELSE program the read DQS delay for the lane with a value of zero + IDS_HDT_CONSOLE (MEM_FLOW, " "); + IDS_HDT_CONSOLE (MEM_FLOW, "Center of data eye is still negative after 2 retires. Do not restart training, just use 0\n"); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t "); + *(UINT8 *) Center = 0; + } + } + + return RetVal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes RdDQS training + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * + * @return TRUE - All bytelanes pass + * @return FALSE - Some bytelanes fail +*/ +BOOLEAN +MemNRdPosTrnTN ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + BOOLEAN RetVal; + + if (((INT8) TechPtr->ChipSel) > TechPtr->RestartChipSel) { + RetVal = MemTRdPosWithRxEnDlySeeds3 (TechPtr); + } else { + // Skip RcvEnDly cycle training when current chip select has already gone through that step. + // Because a retrain condition can only be detected on a chip select after RcvEnDly cycle training + // So when current chip select is equal to RestartChipSel, we don't need to redo RcvEnDly cycle training. + // Only redo DQS position training. + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tSkip RcvEnDly Cycle Training on Current Chip Select.\n\n"); + RetVal = MemTTrainDQSEdgeDetect (TechPtr); + } + return RetVal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function skips WrDatDly training when a retrain condition is just detected + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *ChipSel - Pointer to ChipSel + * + * @return TRUE + */ + +BOOLEAN +MemNHookBfWrDatTrnTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *ChipSel + ) +{ + BOOLEAN RetVal; + + RetVal = TRUE; + if (NBPtr->RdDqsDlyRetrnStat == RDDQSDLY_RTN_ONGOING) { + NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_NEEDED; + // Clear chipsel value to force a restart of Rd Dqs Training + if (NBPtr->CsPerDelay == 1) { + *(UINT8 *) ChipSel = 0xFF; + } else { + *(UINT8 *) ChipSel = 0xFE; + } + + RetVal = FALSE; + } else if (((INT8) NBPtr->TechPtr->ChipSel) < NBPtr->TechPtr->RestartChipSel) { + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSkip WrDatDly Training on Current Chip Select.\n\n"); + // Skip WrDatDly training when current chip select has gone through WrDatDly procedure + // A retrain is detected during RdDqsDly training, so if RestartChipSel is equal to current + // chip select, then WrDatDly has not been started for current chip select in the previous cycle. + // However, RcvEnDly cycle training has been done for current chip select. + // So we don't need to do RcvEnDly cycle training when current chip select is equal to RestartChipSel + // but we need to do WrDatDly training for current chip select. + RetVal = FALSE; + } + + // when return is FALSE, WrDatDly training will be skipped + + return RetVal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets up output driver and write leveling mode in MR1 during WL + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *Value - MR1 value + * + * @return TRUE + */ + +BOOLEAN +MemNWLMR1TN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *Value + ) +{ + BOOLEAN Target; + + // For the target rank of the target DIMM, enable write leveling mode and enable the output driver. + // For all other ranks of the target DIMM, enable write leveling mode and disable the output driver. + Target = (BOOLEAN) (*(UINT16 *) Value >> 7) & 1; + + if (NBPtr->CsPerDelay == 1) { + // Clear Qoff and reset it based on TN requirement + *(UINT16 *) Value &= ~((UINT16) 1 << 12); + + if (!Target) { + *(UINT16 *) Value |= (((UINT16) 1 << 7) | ((UINT16) 1 << 12)); + } + } + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c new file mode 100644 index 0000000000..385416575c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c @@ -0,0 +1,856 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnregtn.c + * + * Common Northbridge register related functions for TN + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/TN) + * @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $ + * + **/ +/***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbCommonLib.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mntn.h" +#include "merrhdl.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + + +#define FILECODE PROC_MEM_NB_TN_MNREGTN_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define PHY_DIRECT_ADDRESS_MASK 0x0D000000ul + +STATIC CONST UINT8 InstancesPerTypeTN[8] = {8, 3, 1, 2, 2, 0, 1, 1}; + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*-----------------------------------------------------------------------------*/ +/** + * MemNIsIdSupportedTn + * This function matches the CPU_LOGICAL_ID with certain criteria to + * determine if it is supported by this NBBlock. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID + * + * @return TRUE - This node is a TN. + * @return FALSE - This node is not a TN. + * + */ +BOOLEAN +MemNIsIdSupportedTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ) +{ + if (((LogicalIdPtr->Family & AMD_FAMILY_15_TN) != 0) + && ((LogicalIdPtr->Revision & (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) ) != 0)) { + return TRUE; + } else { + return FALSE; + } +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets or sets a value to a bit field in a PCI register. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field to be programmed + * @param[in] Field - Value to be programmed + * @param[in] IsSet - Indicates if the function will set or get + * + * @return value read, if the function is used as a "get" + */ + +UINT32 +MemNCmnGetSetFieldTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + TSEFO Address; + PCI_ADDR PciAddr; + UINT8 Type; + UINT8 IsLinked; + UINT32 Value; + UINT32 Highbit; + UINT32 Lowbit; + UINT32 Mask; + UINT8 IsPhyDirectAccess; + UINT8 IsWholeRegAccess; + UINT8 NumOfInstances; + UINT8 Instance; + UINT8 IsMultipleMPstate; + + Value = 0; + if (FieldName == BFDctAccessDone) { + // No need to poll DctAccessDone for TN due to enhancement in phy + Value = 1; + } else if ((FieldName < BFEndOfList) && (FieldName >= 0)) { + Address = NBPtr->NBRegTable[FieldName]; + if (Address) { + Lowbit = TSEFO_END (Address); + Highbit = TSEFO_START (Address); + Type = (UINT8) TSEFO_TYPE (Address); + IsLinked = (UINT8) TSEFO_LINKED (Address); + IsPhyDirectAccess = (UINT8) TSEFO_DIRECT_EN (Address); + IsWholeRegAccess = (UINT8) TSEFO_WHOLE_REG_ACCESS (Address); + if (NBPtr->MemPstate == MEMORY_PSTATE0) { + IsMultipleMPstate = TSEFO_MULTI_MPSTATE_COPY (Address); + } else { + // Do not write in both instances when context is already in MP1 + IsMultipleMPstate = 0; + } + + Address = TSEFO_OFFSET (Address); + + // By default, a bit field has only one instance + NumOfInstances = 1; + + if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) { + Address |= PHY_DIRECT_ADDRESS_MASK; + if (IsWholeRegAccess) { + // In the case of whole regiter access (bit 0 to 15), + // HW broadcast and nibble mask will be used. + Address |= Lowbit << 16; + Lowbit = 0; + Highbit = 15; + } else { + // In the case only some bits on a register is accessed, + // BIOS will do read-mod-write to all chiplets manually. + // And nibble mask will be 1111b always. + if ((Address & 0xFFFF) == 0xE008) { + // Special case for PStateToAccess, which use nibble mask + Address |= 0x00040000; + } else { + Address |= 0x000F0000; + } + Field >>= Lowbit; + if ((Address & 0x0F00) == 0x0F00) { + // Broadcast mode + // Find out how many instances to write to + NumOfInstances = InstancesPerTypeTN[(Address >> 13) & 0x7]; + if (!IsSet) { + // For read, only read from instance 0 in broadcast mode + NumOfInstances = 1; + } + } + } + } + + ASSERT (NumOfInstances > 0); + + for (Instance = 0; Instance < NumOfInstances; Instance++) { + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + Address = PciAddr.AddressValue; + LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { + IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn%d_%03x = %x\n", + NBPtr->PciAddr.Address.Device, NBPtr->Dct, + (Address >> 12) & 0xF, Address & 0xFFF, Value); + } + } else if (Type == DCT_PHY_ACCESS) { + if (IsPhyDirectAccess && (NumOfInstances > 1)) { + Address = (Address & 0x0FFFF0FF) | (((UINT32) Instance) << 8); + } + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn2_9C_%x = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, Address & 0x0FFFFFFF, Value); + } else { + // DCT_EXTRA_ACCESS is not supported on TN + ASSERT (FALSE); + } + + if (IsSet) { + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32)0xFFFFFFFF; + } + Value &= ~(Mask << Lowbit); + Value |= (Field & Mask) << Lowbit; + + do { + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { + IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn%d_%03x [%d:%d] = %x\n", + NBPtr->PciAddr.Address.Device, NBPtr->Dct, + (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + } + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn2_9C_%x [%d:%d] = %x\n", + NBPtr->PciAddr.Address.Device, NBPtr->Dct, + Address & 0x0FFFFFFF, Highbit, Lowbit, Field); + } else { + // DCT_EXTRA_ACCESS is not supported on TN + ASSERT (FALSE); + } + if (IsLinked) { + MemNCmnGetSetFieldTN (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); + } + if (IsMultipleMPstate && (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE)) { + // if there are multiple Pstate register copies, program register in M1 context when the frequency is DDR667 + if (NBPtr->MemPstate == MEMORY_PSTATE0) { + MemNChangeMemPStateContextNb (NBPtr, 1); + } else { + // Switch back to M0 context + MemNChangeMemPStateContextNb (NBPtr, 0); + } + } + } while ((NBPtr->MemPstate == MEMORY_PSTATE1) && IsMultipleMPstate && (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE)); + } else { + Value = Value >> Lowbit; // Shift + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } + if (IsLinked) { + Value |= MemNCmnGetSetFieldTN (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); + } + // For direct phy access, shift the bit back for compatibility reason. + if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) { + Value <<= Lowbit; + } + } + } + } else { + IDS_HDT_CONSOLE (MEM_UNDEF_BF, "\t\tUndefined BF enum: %x\n", FieldName); + } + } else { + ASSERT (FALSE); // Invalid bit field index + } + return Value; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes bit field translation table + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] NBRegTable[] - Pointer to the bit field data structure + * + */ + +VOID +MemNInitNBRegTableTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT TSEFO NBRegTable[] + ) +{ + UINT16 i; + + // Allocate heap for NB register table + if (!MemNAllocateNBRegTableNb (NBPtr, NbRegTabTN)) { + return; // escape if fails + } + NBRegTable = NBPtr->NBRegTable; + + for (i = 0; i < BFEndOfList; i++) { + NBRegTable[i] = 0; + } + + // --------------------------------------------------------------------------- + // + // FUNCTION 1 + // + // --------------------------------------------------------------------------- + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 0, 0, BFDramRngRE0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 1, 1, BFDramRngWE0); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 2, 0, BFDramRngDstNode0); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x10C), 5, 4, BFNbPsSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x10C), 3, 3, BFMemPsSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x10C), 0, 0, BFDctCfgSel); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr); + // --------------------------------------------------------------------------- + // + // FUNCTION 2 + // + // --------------------------------------------------------------------------- + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 17, 17, BFAddrCmdTriEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 23, 21, BFMrsChipSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 20, 18, BFMrsBank); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 17, 0, BFMrsAddress); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 16, 0, BFDramBankAddrReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 29, 24, BFMemClkDis); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 25, 25, BFPendRefPaybackS3En); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 24, 24, BFStagRefEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 20, 20, BFDynPageCloseEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 31, BFDphyMemPsSelEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 28, 24, BFDcqBypassMax); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 7, 7, BFMemClkFreqVal); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 4, 0, BFMemClkFreq); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 23, 20, BFBwCapCmdThrottleMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 11, 11, BFBwCapEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 31, BFPerRankTimingEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 29, 29, BFRefChCmdMgtDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 28, 28, BFFastSelfRefEntryDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 22, 22, BFPrtlChPDEnhEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 21, 21, BFAggrPDEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 20, 20, BFBankSwap); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 17, 16, BFMemPhyPllPdMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 0, 0, BFIntLvRgnSwapEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 9, 3, BFIntLvRgnBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 17, 11, BFIntLvRgnLmtAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 26, 20, BFIntLvRgnSize); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 9, 9, BFDctSelIntLvAddrHi); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 27, 27, BFMctEccDisLatOptEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 19, 19, BFLockDramCfg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 18, 18, BFCC6SaveEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31, 0, BFExtMctCfgLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B4), 31, 0, BFExtMctCfgHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B4), 27, 27, BFFlushWrOnS3StpGnt); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B4), 26, 26, BFEnSplitMctDatBuffers); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x200), 29, 24, BFTras); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x200), 20, 16, BFTrp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x200), 12, 8, BFTrcd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x200), 4, 0, BFTcl); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x204), 27, 24, BFTrtp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x204), 21, 16, BFFourActWindow); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x204), 11, 8, BFTrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x204), 5, 0, BFTrc); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x208), 26, 24, BFTrfc3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x208), 18, 16, BFTrfc2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x208), 10, 8, BFTrfc1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x208), 2, 0, BFTrfc0); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x20C), 17, 16, BFWrDqDqsEarly); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x20C), 11, 8, BFTwtr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x20C), 4, 0, BFTcwl); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x210), 31, 22, BFMaxLatency); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x210), 18, 16, BFDataTxFifoWrDly); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x210), 3, 0, BFRdPtrInit); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x214), 19, 16, BFTwrwrSdSc); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x214), 11, 8, BFTwrwrSdDc); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x214), 3, 0, BFTwrwrDd); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x218), 27, 24, BFTrdrdSdSc); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x218), 19, 16, BFTrdrdSdDc); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x218), 11, 8, BFTwrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x218), 3, 0, BFTrdrdDd); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x21C), 20, 16, BFTrwtWB); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x21C), 12, 8, BFTrwtTO); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x220), 12, 8, BFTmod); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x220), 3, 0, BFTmrd); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x224), 10, 8, BFTzqcs); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x224), 3, 0, BFTzqoper); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x228), 31, 24, BFTstag3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x228), 23, 16, BFTstag2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x228), 15, 8, BFTstag1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x228), 7, 0, BFTstag0); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x22C), 4, 0, BFTwrDDR3); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x230), 31, 0, BFPhyRODTCSLow); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x234), 31, 0, BFPhyRODTCSHigh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x238), 31, 0, BFPhyWODTCSLow); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x23C), 31, 0, BFPhyWODTCSHigh); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x240), 14, 12, BFWrOdtOnDuration); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x240), 10, 8, BFWrOdtTrnOnDly); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x240), 6, 4, BFRdOdtOnDuration); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x240), 3, 0, BFRdOdtTrnOnDly); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x244), 3, 0, BFPrtlChPDDynDly); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248), 31, 31, BFRxChMntClkEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248), 29, 24, BFAggrPDDelay); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248), 21, 16, BFPchgPDEnDelay); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248), 12, 8, BFTxpdll); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248), 3, 0, BFTxp); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x24C), 29, 24, BFTcksrx); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x24C), 21, 16, BFTcksre); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x24C), 13, 8, BFTckesr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x24C), 3, 0, BFTpd); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 12, 12, BFCmdSendInProg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 11, 11, BFSendCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 10, 10, BFTestStatus); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 9, 8, BFCmdTgt); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 7, 5, BFCmdType); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 4, 4, BFStopOnErr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 3, 3, BFResetAllErr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 2, 2, BFCmdTestEnable); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 13, 13, BFLfsrRollOver ); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x254), 26, 24, BFTgtChipSelectA); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x254), 23, 21, BFTgtBankA); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x254), 9, 0, BFTgtAddressA); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x258), 26, 24, BFTgtChipSelectB); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x258), 23, 21, BFTgtBankB); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x258), 9, 0, BFTgtAddressB); + + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x260), 20, 0, BFCmdCount); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x264), 31, 25, BFErrDqNum); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x264), 24, 0, BFErrCnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x268), 17, 0, BFNibbleErrSts); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x26C), 17, 0, BFNibbleErr180Sts); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x270), 18, 0, BFDataPrbsSeed); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x274), 31, 0, BFDramDqMaskLow ); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x278), 31, 0, BFDramDqMaskHigh); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 31, 31, BFSendActCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 30, 30, BFSendPchgCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 29, 22, BFCmdChipSelect); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 21, 19, BFCmdBank); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 17, 0, BFCmdAddress); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 31, 0, BFDramCommand2 ); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x290), 26, 24, BFErrBeatNum); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x290), 20, 0, BFErrCmdNum); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x294), 31, 0, BFDQErrLow); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x298), 31, 0, BFDQErrHigh); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2E0), 30, 30, BFFastMstateDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2E0), 28, 24, BFM1MemClkFreq); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2E0), 22, 20, BFMxMrsEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2E8), 31, 16, BFMxMr1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2E8), 15, 0, BFMxMr0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2EC), 15, 0, BFMxMr2); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x2F0), 0, 0, BFEffArbDis); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x400), 11, 8, BFGmcTokenLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x400), 3, 0, BFMctTokenLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x404), 16, 0, BFGmcToDctControl1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x408), 0, 0, BFCpuElevPrioDis); + + // --------------------------------------------------------------------------- + // + // DCT PHY REGISTERS + // + // --------------------------------------------------------------------------- + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 22, 20, BFDqsDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 18, 16, BFDataDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 14, 12, BFClkDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 10, 8, BFAddrCmdDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 6, 4, BFCsOdtDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 2, 0, BFCkeDrvStren); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 29, BFDisablePredriverCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 7, 6, BFFenceTrSel); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 2, 2, BFTrNibbleSel); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0B, 31, 0, BFDramPhyStatusReg); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 15, 12, BFCKETri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 25, 24, BFRxDLLWakeupTime); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 22, 20, BFRxCPUpdPeriod); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 19, 16, BFRxMaxDurDllNoLock); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 9, 8, BFTxDLLWakeupTime); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 6, 4, BFTxCPUpdPeriod); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 3, 0, BFTxMaxDurDllNoLock); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x50, 31, 0, BFRstRcvFifo); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13, 8, 8, BFRxSsbMntClkEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13, 14, 14, BFProcOdtAdv); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13, 7, 0, BFPhy0x0D0F0F13); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F30, 4, 4, BFEccDLLPwrDnConf); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE013, 15, 0, BFPllRegWaitTime); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE006, 15, 0, BFPllLockTime); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F02, 15, 0, BFDataByteTxPreDriverCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F06, 15, 0, BFDataByteTxPreDriverCal2Pad1); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0A, 15, 0, BFDataByteTxPreDriverCal2Pad2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8006, 15, 0, BFCmdAddr0TxPreDriverCal2Pad1); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F800A, 15, 0, BFCmdAddr0TxPreDriverCal2Pad2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8106, 15, 0, BFCmdAddr1TxPreDriverCal2Pad1); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F810A, 15, 0, BFCmdAddr1TxPreDriverCal2Pad2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC006, 15, 0, BFAddrTxPreDriverCal2Pad1); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00A, 15, 0, BFAddrTxPreDriverCal2Pad2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00E, 15, 0, BFAddrTxPreDriverCal2Pad3); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC012, 15, 0, BFAddrTxPreDriverCal2Pad4); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8002, 15, 0, BFCmdAddr0TxPreDriverCalPad0); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8102, 15, 0, BFCmdAddr1TxPreDriverCalPad0); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC002, 15, 0, BFAddrTxPreDriverCalPad0); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2002, 15, 0, BFClock0TxPreDriverCalPad0); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2102, 15, 0, BFClock1TxPreDriverCalPad0); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2202, 15, 0, BFClock2TxPreDriverCalPad0); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F812F, 15, 0, BFAddrCmdTri); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F10, 12, 12, BFEnRxPadStandby); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F10, 3, 0, BFDllNoLock); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D04E008, 8, 8, BFPStateToAccess); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE00A, 4, 4, BFSkewMemClk); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4003, 15, 0, BFChAM1FenceSave); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4004, 15, 0, BFChBM1FenceSave); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2030, 4, 4, BFPhyClkConfig0); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2130, 4, 4, BFPhyClkConfig1); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC000, 8, 8, BFLowPowerDrvStrengthEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE040, 3, 0, BFRate); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F, 8, 8, BFRx4thStgEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F, 4, 3, BFDataRxVioLvl); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F, 2, 2, BFRxBypass3rd4thStg); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1F, 4, 3, BFClkRxVioLvl); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4009, 3, 2, BFCsrComparator); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4009, 15, 14, BFCmpVioLvl); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F, 4, 3, BFCmdRxVioLvl); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F, 4, 3, BFAddrRxVioLvl); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F31, 9, 0, BFDataFence2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE019, 14, 0, BFFence2); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F30, 8, 8, BFBlockRxDqsLock); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F001C, 15, 0, BFDataByteDllPowerMgnByte0); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F011C, 15, 0, BFDataByteDllPowerMgnByte1); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F021C, 15, 0, BFDataByteDllPowerMgnByte2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F031C, 15, 0, BFDataByteDllPowerMgnByte3); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F041C, 15, 0, BFDataByteDllPowerMgnByte4); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F051C, 15, 0, BFDataByteDllPowerMgnByte5); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F061C, 15, 0, BFDataByteDllPowerMgnByte6); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F071C, 15, 0, BFDataByteDllPowerMgnByte7); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1C, 15, 0, BFDataByteDllPowerMgnByteAll); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE018, 8, 8, BFPhyPSMasterChannel); + + + // --------------------------------------------------------------------------- + // + // FUNCTION 4 + // + // --------------------------------------------------------------------------- + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x128), 17, 12, BFCoreStateSaveDestNode); + + // --------------------------------------------------------------------------- + // + // FUNCTION 5 + // + // --------------------------------------------------------------------------- + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x84), 20, 16, BFDdrMaxRate); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x160), 18, 18, BFMemPstate0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x164), 18, 18, BFMemPstate1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x168), 18, 18, BFMemPstate2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x16C), 18, 18, BFMemPstate3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x160), 16, 10, BFNbVid0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x164), 16, 10, BFNbVid1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x168), 16, 10, BFNbVid2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x16C), 16, 10, BFNbVid3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x160), 21, 21, BFNbVid0Hi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x164), 21, 21, BFNbVid1Hi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x168), 21, 21, BFNbVid2Hi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x16C), 21, 21, BFNbVid3Hi); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 31, 0, BFNbPstateCtlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 31, 31, BFMemPstateDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 14, 14, BFSwNbPstateLoDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 7, 6, BFNbPstateHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 4, 3, BFNbPstateLo); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 1, 0, BFNbPstateMaxVal); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x174), 24, 24, BFCurMemPstate); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x174), 20, 19, BFCurNbPstate); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x174), 0, 0, BFNbPstateDis); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x188), 1, 0, BFNbOffsetTrim); + + // --------------------------------------------------------------------------- + // + // LINK BITFIELD + // + // --------------------------------------------------------------------------- + LINK_TSEFO (NBRegTable, BFDctSelIntLvAddr, BFDctSelIntLvAddrHi); + LINK_TSEFO (NBRegTable, BFNbVid0, BFNbVid0Hi); + LINK_TSEFO (NBRegTable, BFNbVid1, BFNbVid1Hi); + LINK_TSEFO (NBRegTable, BFNbVid2, BFNbVid2Hi); + LINK_TSEFO (NBRegTable, BFNbVid3, BFNbVid3Hi); + + // --------------------------------------------------------------------------- + // + // REGISTERS WITH MULTIPLE MEMORY PSTATE COPIES + // + // --------------------------------------------------------------------------- + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFODCControl); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFDqsDrvStren); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFDataDrvStren); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFClkDrvStren); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFAddrCmdDrvStren); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFCsOdtDrvStren); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFCkeDrvStren); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFAddrTmgControl); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFDisablePredriverCal); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFProcOdtAdv); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFDataRxVioLvl); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFRx4thStgEn); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFRxBypass3rd4thStg); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTras); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTrp); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTrcd); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTcl); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTrtp); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFFourActWindow); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTrrd); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTrc); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFWrDqDqsEarly); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTwtr); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTcwl); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFTwrDDR3); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFWrOdtOnDuration); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFWrOdtTrnOnDly); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFRdOdtOnDuration); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFRdOdtTrnOnDly); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFMxMr0); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFMxMr1); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFMxMr2); + // These Phy fence registers don't have mutiple memory Pstate copies + // But they need to be written again in M1 context + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFDataFence2); + MULTI_MPSTATE_COPY_TSEFO (NBRegTable, BFFence2); + + IDS_OPTION_HOOK (IDS_INIT_MEM_REG_TABLE, NBPtr, &NBPtr->MemPtr->StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c new file mode 100644 index 0000000000..2a48eb55cf --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c @@ -0,0 +1,1498 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mns3tn.c + * + * TN memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/TN) + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + **/ +/***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mntn.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mnS3tn.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_MEM_NB_TN_MNS3TN_FILECODE +#define DCT0_MEMPSTATE_MASK 0x10 +#define DCT1_MEMPSTATE_MASK 0x20 +#define DO_NOT_CARE 0 +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstTN ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3SetDfltPhyRegTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3SetDynModeChangeTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3SetPhyStatusRegTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3DisableChannelTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3GetConPCIMaskTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +VOID +STATIC +MemNS3ChangeMemPStateContextAndFlowNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3GetCSRTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3SetCSRTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3SetPhyFenceTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); +BOOLEAN +MemS3ResumeConstructNBBlockTN ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncTN[] = { + {MemNS3GetCSRTN, MemNS3SetCSRTN}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}, + {MemNS3GetNBPStateDepRegUnb, MemNS3SetNBPStateDepRegUnb}, + { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDfltPhyRegTN}, + {MemNS3ChangeMemPStateContextAndFlowNb, MemNS3ChangeMemPStateContextAndFlowNb}, + { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDynModeChangeTN}, + { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3DisableChannelTN}, + {MemNS3SaveNBRegiserUnb, MemNS3RestoreNBRegiserUnb}, + {MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb}, + { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetPhyStatusRegTN}, + { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetMemClkFreqValUnb}, + {MemNS3ChangeMemPStateContextNb, MemNS3ChangeMemPStateContextNb}, + {MemNS3GetBitFieldNb, MemNS3SetPhyFenceTN}, + { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ReleaseNBPSUnb}, + { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ForceNBP0Unb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorTN[] = { + {{14,3, 1}, DO_NOT_CARE, 0, 0}, + {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFF8E7}, + {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF0703}, + {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF0707}, + {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF87}, + {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9}, + {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFE00}, + {{0, 0, 0}, FUNC_2, 0x118, 0xFF73FFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0xAFFFFFFF}, + {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}, + {{0, 0, 0}, FUNC_2, 0x1B4, 0xFC7FFFFF}, + {{0, 0, 0}, FUNC_2, 0xA4, 0x00F07900}, +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefTN = { + 0, + (sizeof (S3PciPreSelfRefDescriptorTN) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorTN, + PciSpecialCaseFuncTN +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorTN[] = { + // DCT 0 + {{7, 0, 1}, DCT0, 0x40, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x44, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x48, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x4C, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x50, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x54, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x58, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x5C, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x60, 0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x64, 0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x68, 0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x6C, 0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x78, 0x00020000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT0, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x84, 0x00800003, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x88, 0x3F000000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x8C, 0x00070000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x90, 0x0BF70000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0xA8, 0xBC730024, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x200, 0x3F1F1F1F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x204, 0x0F3F0F3F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x208, 0x07070707, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x20C, 0x00030F1F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 0), 0xFFC7000F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 1), 0xFFC7000F, DCT0_NBPSTATE_SUPPORT_MASK, DCT0_ANY_DIMM_MASK}, + {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 2), 0xFFC7000F, DCT0_NBPSTATE_SUPPORT_MASK, DCT0_ANY_DIMM_MASK}, + {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 3), 0xFFC7000F, DCT0_NBPSTATE_SUPPORT_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x214, 0x000F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x218, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x21C, 0x001F1F00, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT0, 0x220, 0x00001F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT0, 0x224, 0x0000070F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x228, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 1, 1}, DCT0, 0x22C, 0x0000001F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x230, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x234, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x238, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x23C, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT0, 0x240, 0x000077FF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 1, 1}, DCT0, 0x244, 0x0000000F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x248, 0xBF3F1F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x24C, 0x3F3F3F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x2E0, 0x5F700000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x2E8, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT0, 0x2EC, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 1, 1}, DCT0, 0x2F0, 0x00000001, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT0, 0x400, 0x00000F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT0, 0x404, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 1, 1}, DCT0, 0x408, 0x00000003, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT0, 0x420, 0x00000F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + + // DCT 1 + {{7, 0, 1}, DCT1, 0x40, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x44, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x48, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x4C, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x50, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x54, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x58, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x5C, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x60, 0x7FF8FFE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x64, 0x7FF8FFE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x68, 0x7FF8FFE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x6C, 0x7FF8FFE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x78, 0x00020000, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT1, 0x80, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x84, 0x00800003, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x88, 0x3F000000, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x8C, 0x00070000, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x90, 0x0BF70000, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0xA8, 0xBC730024, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x200, 0x3F1F1F1F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x204, 0x0F3F0F3F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x208, 0x07070707, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x20C, 0x00030F1F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{2, 0, 1}, DCT1, SET_S3_NB_PSTATE_OFFSET (0x210, 0), 0xFFC7000F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{2, 0, 1}, DCT1, SET_S3_NB_PSTATE_OFFSET (0x210, 1), 0xFFC7000F, DCT1_NBPSTATE_SUPPORT_MASK, DCT1_ANY_DIMM_MASK}, + {{2, 0, 1}, DCT1, SET_S3_NB_PSTATE_OFFSET (0x210, 2), 0xFFC7000F, DCT1_NBPSTATE_SUPPORT_MASK, DCT1_ANY_DIMM_MASK}, + {{2, 0, 1}, DCT1, SET_S3_NB_PSTATE_OFFSET (0x210, 3), 0xFFC7000F, DCT1_NBPSTATE_SUPPORT_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x214, 0x000F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x218, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x21C, 0x001F1F00, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT1, 0x220, 0x00001F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT1, 0x224, 0x0000070F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x228, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 1, 1}, DCT1, 0x22C, 0x0000001F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x230, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x234, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x238, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x23C, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT1, 0x240, 0x000077FF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 1, 1}, DCT1, 0x244, 0x0000000F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x248, 0xBF3F1F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x24C, 0x3F3F3F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x2E0, 0x5F700000, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x2E8, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT1, 0x2EC, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 1, 1}, DCT1, 0x2F0, 0x00000001, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT1, 0x400, 0x00000F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT1, 0x404, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 1, 1}, DCT1, 0x408, 0x00000003, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT1, 0x420, 0x00000F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + + // Phy Initialization + // 1. Program D18F2x9C_x0D0F_E013_dct[1:0] = 0118h. + {{1, 2, 1}, DCT0, BFPllRegWaitTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFPllRegWaitTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + // 2. Force the phy to M0 with the following sequence: + // A. Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 190h. + {{3, 3, 1}, DCT0, BFPllLockTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{3, 3, 1}, DCT1, BFPllLockTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + // B. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80800000h. + {{9, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{9, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + // C. Program D18F2x9C_x0D0F_E018_dct[0][PhyPSMasterChannel] = 0. + {{3, 3, 1}, DCT0, BFPhyPSMasterChannel, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + // D. Program D18F2x9C_x0000_000B_dct[0] = 40000000h. + // E. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80000000h + {{5, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{5, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + + // 3. Phy voltage related + {{1, 1, 1}, DCT0, BFDataRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFClkRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFCmpVioLvl, 0x0000C000, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFCmdRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFCsrComparator, 0x0000000C, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFAddrRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFDataRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFClkRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFCmpVioLvl, 0x0000C000, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFCmdRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFAddrRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, + + // 4. Frequency Change + // Check if a channel needs to be disabled + {{1, 1, 1}, DCT0, BFCKETri, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{6, 3, 1}, DCT0, 0, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFCKETri, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{6, 3, 1}, DCT1, 0, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFPhyClkConfig0, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFPhyClkConfig1, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFPhyClkConfig0, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFPhyClkConfig1, 0, DCT1_MASK, ANY_DIMM_MASK}, + + {{7, 0, 1}, DCT0, 0x94, 0x9FF9CC1F, DCT0_MASK, ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x94, 0x9FF9CC1F, DCT1_MASK, ANY_DIMM_MASK}, + + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFProcOdtAdv, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFProcOdtAdv, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFSkewMemClk, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFSkewMemClk, 0, DCT1_MASK, ANY_DIMM_MASK}, + + // Enable MemClk + {{10, 0, 1}, DCT0, 0x94, 0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{10, 0, 1}, DCT1, 0x94, 0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFPllLockTime, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFPllLockTime, 0, DCT1_MASK, ANY_DIMM_MASK}, + + // DCT 0 + // 5. Phy Fence + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x7FFF3FFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataFence2, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFFence2, 0x00007C1F, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x70777777, DCT0_MASK, ANY_DIMM_MASK}, + // 6. Phy Compensation Init + {{3, 3, 1}, DCT0, BFDisablePredriverCal, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT0, BFDataByteTxPreDriverCal, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad3, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad4, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT0, BFAddrTxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT0, BFClock0TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT0, BFClock1TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT0, BFClock2TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT 1 + // 5. Phy Fence + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x7FFF0FFF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataFence2, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFFence2, 0x00007C1F, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x70777777, DCT1_MASK, ANY_DIMM_MASK}, + // 6. Phy Compensation Init + {{1, 2, 1}, DCT1, BFDataByteTxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteTxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT1, BFDataByteTxPreDriverCal, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFCmdAddr0TxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFCmdAddr0TxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFCmdAddr1TxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFCmdAddr1TxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad3, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad4, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT1, BFCmdAddr0TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT1, BFCmdAddr1TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT1, BFAddrTxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT1, BFClock0TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT1, BFClock1TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{8, 2, 1}, DCT1, BFClock2TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, + + {{1, 1, 1}, DCT0, BFDisablePredriverCal, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + + // Program MemPstate 1 registers + // Switch to MemPstate context 1 + {{11, 3, 1}, DO_NOT_CARE, 1, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFRate, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFRate, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFProcOdtAdv, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFProcOdtAdv, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFDataRxVioLvl, 0x00000018, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFDataRxVioLvl, 0x00000018, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x200, 0x3F1F1F1F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x204, 0x0F3F0F3F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x208, 0x07070707, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x20C, 0x00030F1F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x214, 0x000F0F0F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x218, 0x0F0F0F0F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x21C, 0x001F1F00, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 1, 1}, DCT0, 0x22C, 0x0000001F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT0, 0x240, 0x000077FF, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x248, 0xBF3F1F0F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT0, 0x2E8, 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT0, 0x2EC, 0x0000FFFF, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x200, 0x3F1F1F1F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x204, 0x0F3F0F3F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x208, 0x07070707, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x20C, 0x00030F1F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x214, 0x000F0F0F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x218, 0x0F0F0F0F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x21C, 0x001F1F00, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 1, 1}, DCT1, 0x22C, 0x0000001F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT1, 0x240, 0x000077FF, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x248, 0xBF3F1F0F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 0, 1}, DCT1, 0x2E8, 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, + {{7, 2, 1}, DCT1, 0x2EC, 0x0000FFFF, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, + // Compute Phy fence for MemPstate 1 + // DCT 0 + {{12, 2, 1}, DCT1, BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x70777777, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + // DCT 1 + {{12, 2, 1}, DCT1, BFChBM1FenceSave, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x70777777, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + + {{1, 1, 1}, DCT0, BFDisablePredriverCal, 0, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + // Switch back to MemPstate context 0 + {{11, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + + // Set Fence back to Fence of M0 to prepare for fine delay restore for M0 + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x7FFF3FFF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataFence2, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFFence2, 0x00007C1F, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x7FFF0FFF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataFence2, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFFence2, 0x00007C1F, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefTN = { + 0, + (sizeof (S3CPciPreSelfDescriptorTN) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPreSelfDescriptorTN, + PciSpecialCaseFuncTN +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorTN[] = { + // DCT0 + {{12, 2, 1}, DCT1, BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFRx4thStgEn, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFRxBypass3rd4thStg, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x03FF03FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x03FF03FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x03FF03FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x03FF03FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x03FF03FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x03FF03FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x03FF03FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x03FF03FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x03FF03FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x03FF03FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x03FF03FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x03FF03FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x03FF03FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x03FF03FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x03FF03FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x03FF03FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3E3E3E3E, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3E3E3E3E, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3E3E3E3E, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x037F037F, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFPhy0x0D0F0F13, 0x00000083, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFRxSsbMntClkEn, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFLowPowerDrvStrengthEn, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFEnRxPadStandby, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte0, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte1, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte2, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte3, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte4, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte5, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte6, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte7, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT1 + {{12, 2, 1}, DCT1, BFChBM1FenceSave, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFRx4thStgEn, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFRxBypass3rd4thStg, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x03FF03FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x03FF03FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x03FF03FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x03FF03FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x03FF03FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x03FF03FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x03FF03FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x03FF03FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x03FF03FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x03FF03FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x03FF03FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x03FF03FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x03FF03FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x03FF03FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x03FF03FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x03FF03FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0xFFFFFFFF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0xFFFFFFFF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0xFFFFFFFF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0xFFFFFFFF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0xFFFFFFFF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0xFFFFFFFF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0xFFFFFFFF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0xFFFFFFFF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3E3E3E3E, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3E3E3E3E, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3E3E3E3E, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3E3E3E3E, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3E3E3E3E, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3E3E3E3E, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3E3E3E3E, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3E3E3E3E, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x037F037F, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFPhy0x0D0F0F13, 0x00000083, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFRxSsbMntClkEn, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFLowPowerDrvStrengthEn, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFEnRxPadStandby, 0, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte0, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte1, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte2, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte3, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte4, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte5, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte6, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte7, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, + + {{11, 3, 1}, DO_NOT_CARE, 1, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + + // DCT0 + {{12, 2, 1}, DCT1, BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFRx4thStgEn, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFRxBypass3rd4thStg, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x037F037F, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFPhy0x0D0F0F13, 0x00000083, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFRxSsbMntClkEn, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFLowPowerDrvStrengthEn, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFEnRxPadStandby, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte0, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte1, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte2, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte3, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte4, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte5, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte6, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte7, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, + + // DCT1 + {{12, 2, 1}, DCT1, BFChBM1FenceSave, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFRx4thStgEn, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFRxBypass3rd4thStg, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x037F037F, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFPhy0x0D0F0F13, 0x00000083, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFRxSsbMntClkEn, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFLowPowerDrvStrengthEn, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFEnRxPadStandby, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte0, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte1, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte2, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte3, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte4, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte5, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte6, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte7, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + + {{11, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, + + {{1, 1, 1}, DCT0, BFAddrCmdTri, 0x0000000A1, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT0, BFDisDllShutdownSR, 0, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFAddrCmdTri, 0x0000000A1, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 1, 1}, DCT1, BFDisDllShutdownSR, 0, DCT1_MASK, ANY_DIMM_MASK}, + + {{0, 0, 0}, FUNC_2, 0x118, 0x00040000, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK}, + + {{13, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefTN = { + 0, + (sizeof (S3CPciPostSelfDescriptorTN) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorTN, + PciSpecialCaseFuncTN +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorTN[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F0000}, + {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001F, 0x0044601080000600} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefTN = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorTN) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorTN, + NULL +}; + +VOID *MemS3RegListTN[] = { + (VOID *)&S3PciPreSelfRefTN, + NULL, + (VOID *)&S3CPciPreSelfRefTN, + (VOID *)&S3CPciPostSelfRefTN, + (VOID *)&S3MSRPreSelfRefTN, + NULL, + NULL, + NULL +}; + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ +BOOLEAN +MemS3ResumeConstructNBBlockTN ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedTN (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + MemNInitNBRegTableTN (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_TN; + NBPtr->DctCount = MAX_DCTS_PER_NODE_TN; + NBPtr->MemPstate = MEMORY_PSTATE0; + NBPtr->MemPstateStage = 0; + NBPtr->NbPsCtlReg = 0; + + NBPtr->IsSupported[SetDllShutDown] = TRUE; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + for (i = 0; i < NumberOfHooks; i++) { + NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldTN; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedTN; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = (VOID (*) (MEM_NB_BLOCK *, AMD_CONFIG_PARAMS *)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskTN; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeUNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = (VOID (*) (MEM_NB_BLOCK *, UINT8)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrTN; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstTN; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = 0; + NBPtr->FamilySpecificHook[DCTSelectSwitch] = MemNS3DctCfgSelectUnb; + + MemNSetBitFieldNb (NBPtr, BFDctCfgSel, 0); + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFMemPsSel, 0); + + if (MemNGetBitFieldNb (NBPtr, BFMemPstateDis) != 1) { + NBPtr->MemPstateStage = MEMORY_PSTATE_S3_STAGE; + MemNBrdcstSetUnConditionalNb (NBPtr, BFPStateToAccess, 0); + } + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for TN + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListTN[PCI_LST_ESR_TN - PCI_LST_ESR_TN + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_TN + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListTN[CPCI_LST_ESR_TN - PCI_LST_ESR_TN + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_TN + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListTN[MSR_LST_ESR_TN - PCI_LST_ESR_TN + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_TN + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListTN[CMSR_LST_ESR_TN - PCI_LST_ESR_TN + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_TN + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return AGESA_STATUS + * - AGESA_FATAL + * - AGESA_SUCCESS + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstTN ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListTN) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListTN[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListTN[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device register list error + return AGESA_FATAL; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function that set PllLockTime or PhyPSMasterChannel or disable auto compensation. + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetDfltPhyRegTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT16 RegValue; + BIT_FIELD_NAME BitField; + + IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) { + BitField = (BIT_FIELD_NAME) Address.Address.Register; + RegValue = 0; + + if (BitField == BFPllLockTime) { + RegValue = 0x190; + } else if (BitField == BFPhyPSMasterChannel) { + } else if (BitField == BFDisablePredriverCal) { + RegValue = 3; + } else { + ASSERT (FALSE); + } + MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets bit 31 [DynModeChange] of F2x9C_xB + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetDynModeChangeTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT32 RegValue; + + IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) { + if ((Address.Address.Register & 0x400) == 0) { + RegValue = 0x40000000; + MemNS3SetCSRTN (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); + } + RegValue = 0x80000000; + MemNS3SetCSRTN (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets F2x9C_xB to 0x80800000 + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetPhyStatusRegTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT32 RegValue; + + IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) { + RegValue = 0x80800000; + MemNS3SetCSRTN (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function does the channel disable sequence + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3DisableChannelTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + MEM_NB_BLOCK *NBPtr; + LOCATE_HEAP_PTR LocateBufferPtr; + S3_MEM_NB_BLOCK *S3NBPtr; + UINT32 RegValue; + UINT8 Die; + + // See which Node should be accessed + Die = (UINT8) (Address.Address.Device - 24); + + LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; + NBPtr = S3NBPtr[Die].NBPtr; + + // Function field contains the DCT number + NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function); + RegValue = MemNGetBitFieldNb (NBPtr, BFCKETri); + // if CKETri is 0b1111, this channel is disabled + if (RegValue == 0xF) { + //Wait for 24 MEMCLKs, which is 60ns under 400MHz + MemFS3Wait10ns (6, NBPtr->MemPtr); + MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); + MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); + if (NBPtr->Dct == 0) { + MemNSetBitFieldNb (NBPtr, BFPhyPSMasterChannel, 0x100); + } + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function changes memory Pstate context + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * + * @return TRUE + * ---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNS3ChangeMemPStateContextAndFlowNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + MEM_NB_BLOCK *NBPtr; + LOCATE_HEAP_PTR LocateBufferPtr; + S3_MEM_NB_BLOCK *S3NBPtr; + UINT8 Die; + + // See which Node should be accessed + Die = (UINT8) (Address.Address.Device - 24); + + LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; + + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; + NBPtr = S3NBPtr[Die].NBPtr; + if (NBPtr->MemPstate == MEMORY_PSTATE0) { + // If MemoryPstate is not disabled, switch to MemPState 1 context, and reprocess the register list + MemNChangeMemPStateContextNb (NBPtr, 1); + *(UINT32 *) Value = RESTART_FROM_BEGINNING_LIST; + } else { + // Switch back to MemPstate0 Context + MemNChangeMemPStateContextNb (NBPtr, 0); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the conditional PCI device mask + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return none + */ +VOID +STATIC +MemNS3GetConPCIMaskTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + BIT_FIELD_NAME bitfield; + UINT32 RegVal; + UINT8 DCT; + UINT8 DimmMask; + UINT8 BadDimmMask; + UINT8 NbPsCapMsk; + UINT8 MemPstateMsk; + UINT8 CsPerDelay; + + NbPsCapMsk = 0; + MemPstateMsk = 0; + DimmMask = 0; + BadDimmMask = 0; + CsPerDelay = 1; + + for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { + MemNSwitchDCTNb (NBPtr, DCT); + if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) { + if (MemNGetBitFieldNb (NBPtr, BFPerRankTimingEn) == 0) { + CsPerDelay = 2; + } + for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) { + RegVal = MemNGetBitFieldNb (NBPtr, bitfield); + if (RegVal & 0x1) { + DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) / CsPerDelay) << 1) + DCT)); + } else if (RegVal & 0x4) { + BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) / CsPerDelay) << 1) + DCT)); + } + } + } + } + // Check if the system is capable of doing NB Pstate change + if (MemNGetBitFieldNb (NBPtr, BFNbPstateDis) == 0) { + NbPsCapMsk = DCT0_NBPSTATE_SUPPORT_MASK; + } + if (MemNGetBitFieldNb (NBPtr, BFMemPstateDis) == 0) { + MemPstateMsk = DCT0_MEMPSTATE_MASK; + } + + MemNSwitchDCTNb (NBPtr, 0); + // Set channel mask + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0; + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0; + for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { + if (DimmMask & (0x55 << DCT)) { + // Set mask before exit self refresh + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= (NbPsCapMsk | MemPstateMsk | 1) << DCT; + // Set mask after exit self refresh + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (NbPsCapMsk | MemPstateMsk | 1) << DCT; + } else if (BadDimmMask & (0x55 << DCT)) { + // Need to save function 2 registers for bad dimm + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; + } + } + + // Set dimm mask + DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask; + DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function read the value of CSR register. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3GetCSRTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT8 TempValue; + UINT8 Dct; + UINT32 ExtendOffset; + UINT32 TempFunc; + + ExtendOffset = Address.Address.Register; + TempFunc = Address.Address.Function; + + // Switch Dct + Address.Address.Function = FUNC_1; + Address.Address.Register = 0x10C; + Dct = 0; + if (ExtendOffset & 0x400) { + Dct = 1; + } + LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); + TempValue = (TempValue & 0xFE) | Dct; + LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); + Address.Address.Function = TempFunc; + + Address.Address.Register = 0x98; + ExtendOffset &= 0x3FF; + LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); + IDS_OPTION_HOOK (IDS_AFTER_DCT_PHY_ACCESS, NULL, ConfigPtr); + Address.Address.Register = 0x9C; + LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function write to a CSR register + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetCSRTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT8 TempValue; + UINT8 Dct; + UINT32 ExtendOffset; + UINT32 ValueWrite; + UINT32 TempFunc; + + ExtendOffset = Address.Address.Register; + + TempFunc = Address.Address.Function; + // Switch Dct + Address.Address.Function = FUNC_1; + Address.Address.Register = 0x10C; + Dct = 0; + if (ExtendOffset & 0x400) { + Dct = 1; + } + LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); + TempValue = (TempValue & 0xFE) | Dct; + LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); + + Address.Address.Function = TempFunc; + Address.Address.Register = 0x9C; + + ExtendOffset &= 0x3FF; + ExtendOffset |= 0x40000000; + switch (AccessWidth) { + case AccessS3SaveWidth8: + ValueWrite = *(UINT8 *) Value; + break; + case AccessS3SaveWidth16: + ValueWrite = *(UINT16 *) Value; + break; + case AccessS3SaveWidth32: + ValueWrite = *(UINT32 *) Value; + break; + default: + ASSERT (FALSE); + } + LibAmdPciWrite (AccessS3SaveWidth32, Address, &ValueWrite, ConfigPtr); + Address.Address.Register = 0x98; + LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); + IDS_OPTION_HOOK (IDS_AFTER_DCT_PHY_ACCESS, NULL, ConfigPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function that set PllLockTime or PhyPSMasterChannel or disable auto compensation. + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetPhyFenceTN ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT16 FenceValue; + UINT16 Fence2Data; + UINT16 Fence2Reg; + BIT_FIELD_NAME BitField; + MEM_NB_BLOCK *NBPtr; + LOCATE_HEAP_PTR LocateBufferPtr; + S3_MEM_NB_BLOCK *S3NBPtr; + + BitField = (BIT_FIELD_NAME) Address.Address.Register; + FenceValue = *(UINT16 *) Value; + // See which Node should be accessed + + LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; + + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; + NBPtr = S3NBPtr[0].NBPtr; + + // Do nothing if currently in memory pstate 0 context + if (NBPtr->MemPstate == MEMORY_PSTATE0) { + return; + } + + if (BitField == BFChAM1FenceSave) { + MemNSwitchDCTNb (NBPtr, 0); + } else { + MemNSwitchDCTNb (NBPtr, 1); + } + MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 16, BFPhyFence); + MemNSetBitFieldNb (NBPtr, BFPhyFence, FenceValue); + + // Program Fence 2 for MState 1 + Fence2Data = 0; + if ((FenceValue & 0x1F) < 16) { + Fence2Data |= (FenceValue & 0x1F) | 0x10; + } + if (((FenceValue >> 5) & 0x1F) < 16) { + Fence2Data |= (((FenceValue >> 5) & 0x1F) | 0x10) << 10; + } + if (((FenceValue >> 10) & 0x1F) < 16) { + Fence2Data |= (((FenceValue >> 10) & 0x1F) | 0x10) << 5; + } + MemNSetBitFieldNb (NBPtr, BFDataFence2, Fence2Data); + + // Program another Fence 2 register for Mstate 1 + Fence2Reg = (UINT16) MemNGetBitFieldNb (NBPtr, BFFence2); + Fence2Reg = (Fence2Reg &~(UINT16) ((0x1F << 10) | 0x1F)) | (Fence2Data & 0x1F) | (((Fence2Data >> 5) & 0x1F) << 10); + MemNSetBitFieldNb (NBPtr, BFFence2, Fence2Reg); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c new file mode 100644 index 0000000000..63f255bc0a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c @@ -0,0 +1,618 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mntn.c + * + * Common Northbridge functions for TN + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/TN) + * @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $ + * + **/ +/***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mntn.h" +#include "mu.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_MEM_NB_TN_MNTN_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemNRegAccessFenceTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +/** + * Array for frequency change related parameters. + */ +CONST MEM_FREQ_CHANGE_PARAM FreqChangeParamTN = {0x0190, 0, 0, 0, 0, 0, 0, 0}; + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; +extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @return Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 SpdSocketIndex; + UINT8 SpdChannelIndex; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem->SocketId, &(MemPtr->DiesPerSystem->LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedTN (NBPtr, &(MemPtr->DiesPerSystem->LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = MemPtr->DiesPerSystem; + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = NodeID; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem->LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_TN * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_TN * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + sizeof (CH_TIMING_STRUCT)) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + return FALSE; + } + + MCTPtr->DctCount = MAX_DCTS_PER_NODE_TN; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_TN * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { + MCTPtr->DctData[Dct].Dct = Dct; + MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_TN; + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + MCTPtr->DctData[Dct].ChData[0].Dct = Dct; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_TN * sizeof (CH_DEF_STRUCT); + MCTPtr->DctData[Dct].TimingsMemPs1 = (CH_TIMING_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_TN * sizeof (CH_TIMING_STRUCT); + } + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { + MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]); + MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings); + MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct; + } + + MemNInitNBDataTN (NBPtr); + + FeatPtr->InitCPG (NBPtr); + FeatPtr->InitHwRxEn (NBPtr); + FeatPtr->excel221 (NBPtr); + + NBPtr->FeatPtr = FeatPtr; + + // + // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel + // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that + // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the + // dimm types(QR or not) are known. This is done in the Technology block constructor. + // + // Calculate the SpdSocketIndex separately from the SpdChannelIndex. + // This will facilitate modifications due to some processors that might + // map the DCT-CHANNEL differently. + // + SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); + // + // Traverse the Dct/Channel structures + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_TN; Channel++) { + // + // Calculate the number of Dimms on this channel using the + // die/dct/channel to Socket/channel conversion. + // + SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), + &MemPtr->StdHeader); + NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); + } + } + + // + // Initialize Dct and DctCfgSel bit + // + MemNSetBitFieldNb (NBPtr, BFDctCfgSel, 0); + MemNSwitchDCTNb (NBPtr, 0); + + if (MemNGetBitFieldNb (NBPtr, BFMemPstateDis) == 1) { + // MemPstate is disabled + NBPtr->MemPstateStage = 0; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + MemNInitNBRegTableTN (NBPtr, NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_TN; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_TN; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_TN; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_256B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR667_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0x1FF; + NBPtr->DefDctSelIntLvAddr = 4; + NBPtr->NbFreqChgState = 0; + NBPtr->FreqChangeParam = (MEM_FREQ_CHANGE_PARAM *) &FreqChangeParamTN; + NBPtr->MaxRxEnSeedTotal = 0x1FF; + NBPtr->MinRxEnSeedGross = 0; + NBPtr->CsRegMsk = 0x7FF8FFE0; + NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_NEEDED; + NBPtr->MemPstate = MEMORY_PSTATE0; + NBPtr->MemPstateStage = MEMORY_PSTATE_1ST_STAGE; + NBPtr->CsPerChannel = MAX_CS_PER_CHANNEL_TN; + NBPtr->CsPerDelay = 1; + NBPtr->TotalMaxVrefRange = 0x20; + NBPtr->TotalRdDQSDlyRange = 0x40; + NBPtr->PhaseLaneMask = 0x3FFFF; + NBPtr->MaxDiamondStep = 3; + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + MemNInitNBDataNb (NBPtr); + + NBPtr->SetMaxLatency = MemNSetMaxLatencyTN; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsTN; + NBPtr->InitializeMCT = MemNInitializeMctTN; + NBPtr->FinalizeMCT = MemNFinalizeMctTN; + NBPtr->SendMrsCmd = MemNSendMrsCmdUnb; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternTN; + NBPtr->ReadPattern = MemNReadPatternTN; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->StitchMemory = MemNStitchMemoryNb; + NBPtr->AutoConfig = MemNAutoConfigTN; + NBPtr->PlatformSpec = MemNPlatformSpecUnb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->DisableDCT = MemNDisableDCTUnb; + NBPtr->StartupDCT = MemNStartupDCTUnb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->ChangeFrequency = MemNChangeFrequencyUnb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyUnb; + NBPtr->ChangeNbFrequency = MemNChangeNbFrequencyUnb; + NBPtr->ChangeNbFrequencyWrap = MemNChangeNbFrequencyWrapUnb; + NBPtr->ProgramNbPsDependentRegs = MemNProgramNbPstateDependentRegistersTN; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsUnb; + NBPtr->SyncDctsReady = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue; + NBPtr->HtMemMapInit = MemNHtMemMapInitTN; + NBPtr->SyncAddrMapToAllNodes = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingTN; + NBPtr->AfterDqsTraining = MemNAfterDQSTrainingTN; + NBPtr->OtherTiming = MemNOtherTimingTN; + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchTN; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldTN; + NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->TrainingFlow = MemNTrainingFlowUnb; + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckNb; + NBPtr->BrdcstSet = MemNBrdcstSetNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingUnb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitTN; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyUnb; + NBPtr->MemPPhyFenceTrainingNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->MemNInitPhyComp = MemNInitPhyCompTN; + NBPtr->MemNBeforePlatformSpecNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitTblDrvNb; + NBPtr->MemNPFenceAdjustNb = MemNPFenceAdjustTN; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsUnb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeTN; + NBPtr->GetUmaSize = MemNGetUmaSizeTN; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdUnb; + NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb; + NBPtr->WaitXMemClks = MemNWaitXMemClksNb; + NBPtr->MemNGetDramTerm = MemNGetDramTermTblDrvNb; + NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermTblDrvNb; + NBPtr->MemNGetMR0CL = MemNGetMR0CLTblDrvNb; + NBPtr->MemNGetMR0WR = MemNGetMR0WRTblDrvNb; + NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; + NBPtr->MemNGetMR2CWL = MemNGetMR2CWLUnb; + NBPtr->AllocateC6Storage = MemNAllocateC6StorageTN; + NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecTN; + NBPtr->MemNGetMemoryWidth = MemNGetMemoryWidthUnb; + + NBPtr->IsSupported[SetDllShutDown] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; + NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE; + NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE; + NBPtr->IsSupported[FenceTrnBeforeDramInit] = TRUE; + NBPtr->IsSupported[UnifiedNbFence] = TRUE; + NBPtr->IsSupported[CheckODTControls] = TRUE; + NBPtr->IsSupported[CheckDramTerm] = TRUE; + NBPtr->IsSupported[CheckDramTermDyn] = TRUE; + NBPtr->IsSupported[CheckQoff] = TRUE; + NBPtr->IsSupported[CheckDrvImpCtrl] = TRUE; + NBPtr->IsSupported[CheckSetSameDctODTsEn] = TRUE; + NBPtr->IsSupported[WLSeedAdjust] = TRUE; + NBPtr->IsSupported[WLNegativeDelay] = TRUE; + NBPtr->IsSupported[TwoStageDramInit] = TRUE; + NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE; + NBPtr->IsSupported[ProgramCsrComparator] = TRUE; + NBPtr->IsSupported[AdjustTrp] = TRUE; // erratum 638 + NBPtr->IsSupported[ForcePhyToM0] = TRUE; + + NBPtr->FamilySpecificHook[ExitPhyAssistedTraining] = MemNExitPhyAssistedTrainingTN; + NBPtr->FamilySpecificHook[DCTSelectSwitch] = MemNDctCfgSelectUnb; + NBPtr->FamilySpecificHook[AfterSaveRestore] = MemNAfterSaveRestoreUnb; + NBPtr->FamilySpecificHook[OverrideRcvEnSeed] = MemNOverrideRcvEnSeedTN; + NBPtr->FamilySpecificHook[OverrideWLSeed] = MemNOverrideWLSeedTN; + NBPtr->FamilySpecificHook[CalcWrDqDqsEarly] = MemNCalcWrDqDqsEarlyUnb; + NBPtr->FamilySpecificHook[AdjustRdDqsDlyOffset] = MemNAdjustRdDqsDlyOffsetUnb; + NBPtr->FamilySpecificHook[GetDdrMaxRate] = MemNGetMaxDdrRateUnb; + NBPtr->FamilySpecificHook[SetSkewMemClk] = MemNSetSkewMemClkUnb; + NBPtr->FamilySpecificHook[AfterMemClkFreqVal] = MemNAdjustPllLockTimeTN; + NBPtr->FamilySpecificHook[AdjustCSIntLvLowAddr] = MemNCSIntLvLowAddrAdjTN; + NBPtr->FamilySpecificHook[ReleaseNbPstate] = MemNReleaseNbPstateTN; + NBPtr->FamilySpecificHook[InitializeRxEnSeedlessTraining] = MemNInitializeRxEnSeedlessTrainingUnb; + NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrNoWindBLError] = MemNTrackRxEnSeedlessRdWrNoWindBLErrorUnb; + NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrSmallWindBLError] = MemNTrackRxEnSeedlessRdWrSmallWindBLErrorUnb; + NBPtr->FamilySpecificHook[InitialzeRxEnSeedlessByteLaneError] = MemNInitialzeRxEnSeedlessByteLaneErrorUnb; + NBPtr->FamilySpecificHook[MemPstateStageChange] = MemNMemPstateStageChangeTN; + NBPtr->FamilySpecificHook[ProgramFence2RxDll] = MemNProgramFence2RxDllTN; + NBPtr->FamilySpecificHook[RdDqsDlyRestartChk] = MemNRdDqsDlyRestartChkTN; + NBPtr->FamilySpecificHook[BeforeWrDatTrn] = MemNHookBfWrDatTrnTN; + NBPtr->FamilySpecificHook[RegAccessFence] = MemNRegAccessFenceTN; + NBPtr->FamilySpecificHook[AdjustWrDqsBeforeSeedScaling] = MemNAdjustWrDqsBeforeSeedScalingUnb; + NBPtr->FamilySpecificHook[WLMR1] = MemNWLMR1TN; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ +VOID +MemNInitDefaultsTN ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + MEM_PARAMETER_STRUCT *RefPtr; + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb; + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { + MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; + } + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; + RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; + RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; + + // Vref + RefPtr->ExternalVrefCtl = UserOptions.CfgExternalVrefCtlFeature; + + //Training Mode + RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training for TN + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +memNEnableTrainSequenceTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN Retval; + Retval = TRUE; + if (!MemNIsIdSupportedTN (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { + Retval = FALSE; + } + return Retval; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function makes sure that previous phy register writes are done. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + * + */ + +BOOLEAN +STATIC +MemNRegAccessFenceTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + // If subsequent writes to this array are scheduled, such as when writing several byte lanes during dram + // training, then it is recommended to issue a dummy register read to ensure the last write. + NBPtr->GetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (0, 0)); + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.h new file mode 100644 index 0000000000..4d4316bfdb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.h @@ -0,0 +1,341 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mntn.h + * + * Northbridge TN + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/TN) + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + **/ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * *************************************************************************** + * + */ + +#ifndef _MNTN_H_ +#define _MNTN_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +#define MAX_DCTS_PER_NODE_TN 2 +#define MAX_CHANNELS_PER_DCT_TN 1 +#define MAX_NODES_SUPPORTED_TN 1 +#define MAX_CS_PER_CHANNEL_TN 4 + +#define DEFAULT_WR_ODT_TN 6 +#define DEFAULT_RD_ODT_TN 6 +#define DEFAULT_RD_ODT_TRNONDLY_TN 0 +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +MemConstructNBBlockTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitNBDataTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDefaultsTN ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +BOOLEAN +MemNInitializeMctTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNAutoConfigTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNOtherTimingTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitPhyCompTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNWritePatternTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +MemNInitNBRegTableTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT TSEFO NBRegTable[] + ); + +BOOLEAN +MemNIsIdSupportedTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ); + +UINT32 +MemNCmnGetSetFieldTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +BOOLEAN +memNEnableTrainSequenceTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNTechBlockSwitchTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNAfterDQSTrainingTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNCapSpeedBatteryLifeTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNGetMaxLatParamsTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxRcvEnDly, + IN OUT UINT16 *MinDlyPtr, + IN OUT UINT16 *MaxDlyPtr, + IN OUT UINT16 *DlyBiasPtr + ); + +VOID +MemNSetMaxLatencyTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxRcvEnDly + ); + +BOOLEAN +MemNExitPhyAssistedTrainingTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +BOOLEAN +MemNOverrideRcvEnSeedTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *SeedPtr + ); + +VOID +MemNBeforeDQSTrainingTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNProgramNbPstateDependentRegistersTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNAdjustPllLockTimeTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *PllLockTime + ); + +BOOLEAN +MemNOverrideWLSeedTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *SeedPtr + ); + +BOOLEAN +MemNFinalizeMctTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNHtMemMapInitTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemNGetUmaSizeTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNBeforeDramInitTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNCSIntLvLowAddrAdjTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *LowBit + ); + +VOID +MemNAllocateC6StorageTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNPFenceAdjustTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT INT16 *Value16 + ); + +BOOLEAN +MemNReleaseNbPstateTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +BOOLEAN +MemNMemPstateStageChangeTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +BOOLEAN +MemNProgramFence2RxDllTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *Fence2Data + ); + +VOID +MemNAdjustNBPstateVolTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNRdDqsDlyRestartChkTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *Center + ); + +BOOLEAN +MemNHookBfWrDatTrnTN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *ChipSel + ); + +VOID +MemNSetOtherTimingTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNPowerDownCtlTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNBeforePlatformSpecTN ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNWLMR1TN ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *Value + ); +#endif /* _MNTN_H_ */ |