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+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mttml.c
+ *
+ * Technology Max Latency Training support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD. This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property. Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions. If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY: The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you. Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ * MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_MEM_TECH_MTTML_FILECODE
+/*----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ * EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This function trains Max latency for all dies
+ *
+ * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
+ *
+ * @return TRUE - No fatal error occurs.
+ * @return FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTTrainMaxLatency (
+ IN OUT MEM_TECH_BLOCK *TechPtr
+ )
+{
+ UINT32 TestAddrRJ16;
+ UINT8 Dct;
+ UINT8 ChipSel;
+ UINT8 *PatternBufPtr;
+ UINT8 *TestBufferPtr;
+ UINT8 CurrentNbPstate;
+ UINT16 CalcMaxLatDly;
+ UINT16 MaxLatDly;
+ UINT16 MaxLatLimit;
+ UINT16 Margin;
+ UINT16 CurTest;
+ UINT16 _CL_;
+ UINT8 TimesFail;
+ UINT8 TimesRetrain;
+ UINT16 i;
+
+ MEM_DATA_STRUCT *MemPtr;
+ DIE_STRUCT *MCTPtr;
+ MEM_NB_BLOCK *NBPtr;
+
+ NBPtr = TechPtr->NBPtr;
+ MCTPtr = NBPtr->MCTPtr;
+ MemPtr = NBPtr->MemPtr;
+ TechPtr->TrainingType = TRN_MAX_READ_LATENCY;
+ TimesRetrain = DEFAULT_TRAINING_TIMES;
+ IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader);
+
+ IDS_HDT_CONSOLE (MEM_STATUS, "\nStart MaxRdLat training\n");
+ // Set environment settings before training
+ AGESA_TESTPOINT (TpProcMemMaxRdLatencyTraining, &(MemPtr->StdHeader));
+ MemTBeginTraining (TechPtr);
+ //
+ // Initialize the Training Pattern
+ //
+ if (AGESA_SUCCESS != NBPtr->TrainingPatternInit (NBPtr)) {
+ return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+ }
+ TechPtr->PatternLength = (MCTPtr->Status[Sb128bitmode]) ? 6 : 3;
+ //
+ // Setup hardware training engine (if applicable)
+ //
+ NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType);
+
+ MaxLatDly = 0;
+ _CL_ = TechPtr->PatternLength;
+ PatternBufPtr = TechPtr->PatternBufPtr;
+ TestBufferPtr = TechPtr->TestBufPtr;
+ //
+ // Begin max latency training
+ //
+ for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+ if (MCTPtr->Status[Sb128bitmode] && (Dct != 0)) {
+ break;
+ }
+
+ IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
+ NBPtr->SwitchDCT (NBPtr, Dct);
+
+ if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+ if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) {
+ TechPtr->ChipSel = ChipSel;
+ if (NBPtr->GetSysAddr (NBPtr, ChipSel, &TestAddrRJ16)) {
+ IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to address: %04x0000\n", TestAddrRJ16);
+
+ // Write the test patterns
+ AGESA_TESTPOINT (TpProcMemMaxRdLatWritePattern, &(MemPtr->StdHeader));
+ NBPtr->WritePattern (NBPtr, TestAddrRJ16, PatternBufPtr, _CL_);
+
+ // Sweep max latency delays
+ NBPtr->getMaxLatParams (NBPtr, TechPtr->MaxDlyForMaxRdLat, &CalcMaxLatDly, &MaxLatLimit, &Margin);
+ AGESA_TESTPOINT (TpProcMemMaxRdLatStartSweep, &(MemPtr->StdHeader));
+
+ TimesFail = 0;
+ ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain)
+ {
+ MaxLatDly = CalcMaxLatDly;
+ for (i = 0; i < (MaxLatLimit - CalcMaxLatDly); i++) {
+ NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", MaxLatDly);
+ TechPtr->ResetDCTWrPtr (TechPtr, 6);
+
+ AGESA_TESTPOINT (TpProcMemMaxRdLatReadPattern, &(MemPtr->StdHeader));
+ NBPtr->ReadPattern (NBPtr, TestBufferPtr, TestAddrRJ16, _CL_);
+ AGESA_TESTPOINT (TpProcMemMaxRdLatTestPattern, &(MemPtr->StdHeader));
+ CurTest = NBPtr->CompareTestPattern (NBPtr, TestBufferPtr, PatternBufPtr, _CL_ * 64);
+ NBPtr->FlushPattern (NBPtr, TestAddrRJ16, _CL_);
+
+ if (NBPtr->IsSupported[ReverseMaxRdLatTrain]) {
+ // Reverse training decrements MaxLatDly whenever the test passes
+ // and uses the last passing MaxLatDly as left edge
+ if (CurTest == 0xFFFF) {
+ IDS_HDT_CONSOLE (MEM_FLOW, " P");
+ if (MaxLatDly == 0) {
+ break;
+ } else {
+ MaxLatDly--;
+ }
+ }
+ } else {
+ // Traditional training increments MaxLatDly until the test passes
+ // and uses it as left edge
+ if (CurTest == 0xFFFF) {
+ IDS_HDT_CONSOLE (MEM_FLOW, " P");
+ break;
+ } else {
+ MaxLatDly++;
+ }
+ }
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+ } // End of delay sweep
+ ERROR_HANDLE_RETRAIN_END ((MaxLatDly >= MaxLatLimit), TimesFail)
+ }
+
+ AGESA_TESTPOINT (TpProcMemMaxRdLatSetDelay, &(MemPtr->StdHeader));
+
+ if (MaxLatDly >= MaxLatLimit) {
+ PutEventLog (AGESA_ERROR, MEM_ERROR_MAX_LAT_NO_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+ SetMemError (AGESA_ERROR, MCTPtr);
+ NBPtr->DCTPtr->Timings.CsTrainFail |= NBPtr->DCTPtr->Timings.CsPresent;
+ MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct;
+ if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
+ ASSERT (FALSE);
+ return FALSE;
+ }
+ } else {
+ NBPtr->FamilySpecificHook[AddlMaxRdLatTrain] (NBPtr, &TestAddrRJ16);
+
+ MaxLatDly = MaxLatDly + Margin;
+ if (NBPtr->IsSupported[ReverseMaxRdLatTrain]) {
+ MaxLatDly++; // Add 1 to get back to the last passing value
+ }
+ // Set final delays
+ CurrentNbPstate = (UINT8) MemNGetBitFieldNb (NBPtr, BFCurNbPstate);
+ ASSERT (CurrentNbPstate <= 3);
+ NBPtr->ChannelPtr->DctMaxRdLat [CurrentNbPstate] = MaxLatDly;
+ NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\tFinal MaxRdLat: %03x\n", MaxLatDly);
+
+ }
+ }
+ }
+ }
+ }
+
+ // Restore environment settings after training
+ MemTEndTraining (TechPtr);
+ IDS_HDT_CONSOLE (MEM_FLOW, "End MaxRdLat training\n\n");
+ //
+ // Finalize the Pattern
+ //
+ NBPtr->TrainingPatternFinalize (NBPtr);
+ return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
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