diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Config')
3 files changed, 78 insertions, 34 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h index 4725504159..64b71ef713 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h @@ -48,6 +48,47 @@ #define FCH_SUPPORT FALSE #endif +/* Define the default values for the FCH configuration settings */ +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +/* The AGESA likes to enable 512 bytes region on this base for LPC bus */ +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE + +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE + +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE /* ACPI block register offset definitions */ #define PM1_STATUS_OFFSET 0x00 diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h index a648cc4ec3..7b1447199a 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h @@ -160,7 +160,7 @@ #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM #define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM #else - #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard + #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed #endif #ifndef CFG_GNB_FORCE_CABLESAFE_OFF @@ -871,7 +871,7 @@ #if (AGESA_ENTRY_INIT_S3SAVE == TRUE) //--------------------------------------------------------------------------------------------------- #ifndef OPTION_GFX_INIT_SVIEW - #define OPTION_GFX_INIT_SVIEW TRUE + #define OPTION_GFX_INIT_SVIEW FALSE #endif #if (OPTION_GFX_INIT_SVIEW == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE) OPTION_GNB_FEATURE GfxInitSview; diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h index 686dfb153a..4606443632 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h @@ -310,7 +310,7 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define OPTION_ACPI_PSTATES TRUE #define OPTION_WHEA TRUE -#define OPTION_DMI TRUE +#define OPTION_DMI FALSE #define OPTION_EARLY_SAMPLES FALSE #define CFG_ACPI_PSTATES_PPC TRUE #define CFG_ACPI_PSTATES_PCT TRUE @@ -318,7 +318,7 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define CFG_ACPI_PSTATES_PSS TRUE #define CFG_ACPI_PSTATES_XPSS TRUE #define CFG_ACPI_PSTATE_PSD_INDPX FALSE -#define CFG_VRM_HIGH_SPEED_ENABLE FALSE +#define CFG_VRM_HIGH_SPEED_ENABLE TRUE #define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define OPTION_ALIB TRUE /*--------------------------------------------------------------------------- @@ -393,10 +393,11 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define OPTION_PARALLEL_TRAINING FALSE #endif #endif -#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT - #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE +/* Originally BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT, but inverted alongside the default value */ +#ifdef BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT + #if BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT == TRUE #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE FALSE + #define OPTION_ONLINE_SPARE TRUE #endif #endif #ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @@ -447,10 +448,11 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define OPTION_WHEA FALSE #endif #endif -#ifdef BLDOPT_REMOVE_DMI - #if BLDOPT_REMOVE_DMI == TRUE +/* Originally BLDOPT_REMOVE_DMI, but inverted alongside the default value */ +#ifdef BLDOPT_ENABLE_DMI + #if BLDOPT_ENABLE_DMI == TRUE #undef OPTION_DMI - #define OPTION_DMI FALSE + #define OPTION_DMI TRUE #endif #endif #ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR @@ -601,10 +603,11 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define CFG_ACPI_PSTATES_PSD_POLICY PsdPolicyProcessorDefault #endif -#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE - #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE +/* Originally BLDCFG_VRM_HIGH_SPEED_ENABLE, but inverted alongside the default value */ +#ifdef BLDCFG_VRM_HIGH_SPEED_DISABLE + #if BLDCFG_VRM_HIGH_SPEED_DISABLE == TRUE #undef CFG_VRM_HIGH_SPEED_ENABLE - #define CFG_VRM_HIGH_SPEED_ENABLE TRUE + #define CFG_VRM_HIGH_SPEED_ENABLE FALSE #endif #endif @@ -752,7 +755,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_CURRENT_LIMIT #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT #else - #define CFG_VRM_CURRENT_LIMIT 0 + #define CFG_VRM_CURRENT_LIMIT 15000 #endif #ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD @@ -764,37 +767,37 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_SLEW_RATE #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE #else - #define CFG_VRM_SLEW_RATE (5000) + #define CFG_VRM_SLEW_RATE (10000) #endif #ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT #define CFG_VRM_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT #else - #define CFG_VRM_MAXIMUM_CURRENT_LIMIT (0) + #define CFG_VRM_MAXIMUM_CURRENT_LIMIT (21000) #endif #ifdef BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT #else - #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT (0) + #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT (17000) #endif #ifdef BLDCFG_VRM_SVI_OCP_LEVEL #define CFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_SVI_OCP_LEVEL #else - #define CFG_VRM_SVI_OCP_LEVEL 0 + #define CFG_VRM_SVI_OCP_LEVEL CFG_VRM_MAXIMUM_CURRENT_LIMIT #endif #ifdef BLDCFG_VRM_NB_SVI_OCP_LEVEL #define CFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_SVI_OCP_LEVEL #else - #define CFG_VRM_NB_SVI_OCP_LEVEL 0 + #define CFG_VRM_NB_SVI_OCP_LEVEL CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT #endif #ifdef BLDCFG_VRM_NB_CURRENT_LIMIT #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT #else - #define CFG_VRM_NB_CURRENT_LIMIT (0) + #define CFG_VRM_NB_CURRENT_LIMIT (13000) #endif #ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD @@ -806,13 +809,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_NB_SLEW_RATE #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE #else - #define CFG_VRM_NB_SLEW_RATE (5000) + #define CFG_VRM_NB_SLEW_RATE CFG_VRM_SLEW_RATE #endif #ifdef BLDCFG_PLAT_NUM_IO_APICS #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS #else - #define CFG_PLAT_NUM_IO_APICS 0 + #define CFG_PLAT_NUM_IO_APICS 3 #endif #ifdef BLDCFG_MEM_INIT_PSTATE @@ -854,19 +857,19 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_PLATFORM_CSTATE_MODE #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE #else - #define CFG_CSTATE_MODE CStateModeC6 + #define CFG_CSTATE_MODE CStateModeDisabled #endif #ifdef BLDCFG_PLATFORM_CSTATE_OPDATA #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA #else - #define CFG_CSTATE_OPDATA 0 + #define CFG_CSTATE_OPDATA 0x1770 #endif #ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS #else - #define CFG_CSTATE_IO_BASE_ADDRESS 0 + #define CFG_CSTATE_IO_BASE_ADDRESS 0x1770 #endif #ifdef BLDCFG_PLATFORM_CPB_MODE @@ -878,7 +881,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_CORE_LEVELING_MODE #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE #else - #define CFG_CORE_LEVELING_MODE 0 + #define CFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #endif #ifdef BLDCFG_AMD_TDP_LIMIT @@ -896,7 +899,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT #else - #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY + #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY #endif #ifdef BLDCFG_MEMORY_MODE_UNGANGED @@ -968,13 +971,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_POWER_DOWN #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN #else - #define CFG_MEMORY_POWER_DOWN FALSE + #define CFG_MEMORY_POWER_DOWN TRUE #endif #ifdef BLDCFG_POWER_DOWN_MODE #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE #else - #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO + #define CFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT #endif #ifdef BLDCFG_ONLINE_SPARE @@ -1004,7 +1007,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_CLOCK_SELECT #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT #else - #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY + #define CFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY #endif #ifdef BLDCFG_DQS_TRAINING_CONTROL @@ -1082,7 +1085,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_ECC_SYMBOL_SIZE #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE #else - #define CFG_ECC_SYMBOL_SIZE 0 + #define CFG_ECC_SYMBOL_SIZE 4 #endif #ifdef BLDCFG_1GB_ALIGN @@ -1118,7 +1121,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_UMA_ALIGNMENT #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT #else - #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED + #define CFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #endif #ifdef BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG @@ -1172,7 +1175,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_CFG_ABM_SUPPORT #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT #else - #define CFG_ABM_SUPPORT FALSE + #define CFG_ABM_SUPPORT TRUE #endif #ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE @@ -1468,7 +1471,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_GNB_IOAPIC_ADDRESS #define CFG_GNB_IOAPIC_ADDRESS BLDCFG_GNB_IOAPIC_ADDRESS #else - #define CFG_GNB_IOAPIC_ADDRESS NULL + #define CFG_GNB_IOAPIC_ADDRESS 0xFEC20000 #endif #ifdef BLDCFG_GNB_IOMMU_ADDRESS |