diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Include')
| -rw-r--r-- | src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h (renamed from src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h) | 15 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h | 24 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h | 10 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h | 48 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h | 6 |
5 files changed, 66 insertions, 37 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h index 6b16a6c37a..a28dd5e23e 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h @@ -2,9 +2,9 @@ /** * @file * - * Install of build options for a Kerala platform solution + * Install of build options for a Kabini platform solution * - * This file generates the defaults tables for the "Kerala" platform solution + * This file generates the defaults tables for the "Kabini" platform solution * set of processors. The documented build options are imported from a user * controlled file for processing. * @@ -68,16 +68,16 @@ * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "KabiniPI " - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'K', 'a', 'b', 'i', 'n', 'i', 'P', 'I'} + // This is the delivery package title, "KabiniPI " + // This string MUST be exactly 16 characters long +#define AGESA_PACKAGE_STRING {'K', 'a', 'b', 'i', 'n', 'i', 'P', 'I', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' '} // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '1', '.', '0', ' ', ' ', ' ', ' '} +#define AGESA_VERSION_STRING {'V', '1', '.', '0', '.', '0', '.', '7', ' ', ' ', ' ', ' '} -// The Kerala solution is defined to be family 0x16 models 0x00 - 0x0F in the FT3 sockets. +// The Kabini FT3 solution is defined to be family 0x16 models 0x00 - 0x0F in the FT3 sockets. #define INSTALL_FT3_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE @@ -138,6 +138,7 @@ #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +#define OPTION_MICROSERVER TRUE // Instantiate all solution relevant data. #include "PlatformInstall.h" diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h index 92dae540fa..ae9e3ad352 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h @@ -127,6 +127,7 @@ extern F_PERFORM_EARLY_INIT_ON_CORE F16SetBrandIdRegistersAtEarly; extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly; + extern F_PERFORM_EARLY_INIT_ON_CORE F16KbLoadMicrocodePatchAtEarly; CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitBeforeApLaunchOnCoreTable[] = { @@ -143,7 +144,7 @@ {SetRegistersFromTablesAfterApLaunch, PERFORM_EARLY_ANY_CONDITION}, {F16SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, #if OPTION_EARLY_SAMPLES == FALSE - {LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {F16KbLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, #endif {NULL, 0} }; @@ -208,25 +209,24 @@ #endif #if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) - #define F16_KB_UCODE_002A - #define F16_KB_UCODE_0106 + #define F16_KB_UCODE_7000 + #define F16_KB_UCODE_7001 #if AGESA_ENTRY_INIT_EARLY == TRUE #if OPTION_EARLY_SAMPLES == TRUE + extern CONST UINT8 ROMDATA CpuF16KbId7000MicrocodePatch[]; + #undef F16_KB_UCODE_7000 + #define F16_KB_UCODE_7000 CpuF16KbId7000MicrocodePatch, #endif - extern CONST UINT8 ROMDATA arr1[]; - #undef F16_KB_UCODE_002A - #define F16_KB_UCODE_002A arr1, - - extern CONST UINT8 ROMDATA arr2[]; - #undef F16_KB_UCODE_0106 - #define F16_KB_UCODE_0106 arr2, + extern CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch[]; + #undef F16_KB_UCODE_7001 + #define F16_KB_UCODE_7001 CpuF16KbId7001MicrocodePatch, #endif CONST UINT8 ROMDATA *CpuF16KbMicroCodePatchArray[] = { - F16_KB_UCODE_0106 - F16_KB_UCODE_002A + F16_KB_UCODE_7001 + F16_KB_UCODE_7000 NULL }; diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h index 4c927af308..4725504159 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h @@ -241,6 +241,7 @@ #define FCH_NO_GPP_SUPPORT TRUE #define FCH_NO_PCIB_SUPPORT TRUE #define FCH_NO_PCIE_SUPPORT TRUE + #define BLDOPT_RTC_WORKAROUND TRUE #else #error FCH_SUPPORT: No chip type selected. #endif @@ -929,6 +930,7 @@ InstallFchInitLatePcie, InstallFchInitLatePcib, InstallFchInitLateSpi, + InstallFchInitMidUsbEhci, InstallFchInitLateUsb, InstallFchInitLateUsbEhci, InstallFchInitLateUsbOhci, @@ -1011,6 +1013,14 @@ #endif +#define DFLT_RTC_WORKAROUND FALSE +#ifdef BLDOPT_RTC_WORKAROUND + #undef CFG_FCH_RTC_WORKAROUND + #define CFG_FCH_RTC_WORKAROUND BLDOPT_RTC_WORKAROUND +#else + #undef CFG_FCH_RTC_WORKAROUND + #define CFG_FCH_RTC_WORKAROUND DFLT_RTC_WORKAROUND +#endif CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = { FP_FCH_INIT_RESET, diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h index 07becd2691..1aaa027303 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h @@ -1263,16 +1263,34 @@ BOOLEAN MemFS3DefConstructorRet ( #define PSC_TBL_KB_ODT_TRI_FT3 &KBSODdr3ODTTriEntFT3, extern PSC_TBL_ENTRY KBSODdr3CSTriEntFT3; #define PSC_TBL_KB_CS_TRI_FT3 &KBSODdr3CSTriEntFT3, + #undef PSC_TBL_KB_UDIMM3_S2D_FT3 + #ifndef extern_S2DTblEntUFT3 + #define extern_S2DTblEntUFT3 + extern PSC_TBL_ENTRY S2DTblEntUFT3; + #endif + #define PSC_TBL_KB_UDIMM3_S2D_FT3 &S2DTblEntUFT3, #endif #if OPTION_UDIMMS - extern PSC_TBL_ENTRY KBMaxFreqTblEntU; - #define PSC_TBL_KB_UDIMM3_MAX_FREQ &KBMaxFreqTblEntU, - extern PSC_TBL_ENTRY KBDramTermTblEntU; - #define PSC_TBL_KB_UDIMM3_DRAM_TERM &KBDramTermTblEntU, - extern PSC_TBL_ENTRY KBSAOTblEntU3; - #define PSC_TBL_KB_UDIMM3_SAO &KBSAOTblEntU3, + #if (OPTION_MICROSERVER == TRUE) + extern PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L; + #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntMicroSrvU6L, + #else + extern PSC_TBL_ENTRY KBMaxFreqTblEntU6L; + #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntU6L, + #endif + extern PSC_TBL_ENTRY KBMaxFreqTblEntU4L; + #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L &KBMaxFreqTblEntU4L, + #if OPTION_FT3_SOCKET_SUPPORT + extern PSC_TBL_ENTRY KBDramTermTblEntUFT3; + #define PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 &KBDramTermTblEntUFT3, + extern PSC_TBL_ENTRY KBSAOTblEntU3FT3; + #define PSC_TBL_KB_UDIMM3_SAO_FT3 &KBSAOTblEntU3FT3, + #endif #undef PSC_TBL_KB_UDIMM3_S2D_FT3 - extern PSC_TBL_ENTRY S2DTblEntUFT3; + #ifndef extern_S2DTblEntUFT3 + #define extern_S2DTblEntUFT3 + extern PSC_TBL_ENTRY S2DTblEntUFT3; + #endif #define PSC_TBL_KB_UDIMM3_S2D_FT3 &S2DTblEntUFT3, #endif #if OPTION_SODIMMS @@ -1299,10 +1317,6 @@ BOOLEAN MemFS3DefConstructorRet ( #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L &KBMaxFreqTblEntSoDwnPlusSODIMM6L, extern PSC_TBL_ENTRY KBMaxFreqTblEntSoDwn; #define PSC_TBL_KB_SODWN_MAX_FREQ &KBMaxFreqTblEntSoDwn, - extern PSC_TBL_ENTRY KBMaxFreqTblEntU6L; - #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntU6L, - extern PSC_TBL_ENTRY KBMaxFreqTblEntU4L; - #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L &KBMaxFreqTblEntU4L, #undef PSC_TBL_KB_SODIMM3_S2D_FT3 #define PSC_TBL_KB_SODIMM3_S2D_FT3 #endif @@ -1334,8 +1348,8 @@ BOOLEAN MemFS3DefConstructorRet ( #ifndef PSC_TBL_KB_UDIMM3_MAX_FREQ_4L #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L #endif - #ifndef PSC_TBL_KB_UDIMM3_DRAM_TERM - #define PSC_TBL_KB_UDIMM3_DRAM_TERM + #ifndef PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 + #define PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 #endif #ifndef PSC_TBL_KB_SODIMM3_DRAM_TERM #define PSC_TBL_KB_SODIMM3_DRAM_TERM @@ -1355,8 +1369,8 @@ BOOLEAN MemFS3DefConstructorRet ( #ifndef PSC_TBL_KB_SODWN_SAO #define PSC_TBL_KB_SODWN_SAO #endif - #ifndef PSC_TBL_KB_UDIMM3_SAO - #define PSC_TBL_KB_UDIMM3_SAO + #ifndef PSC_TBL_KB_UDIMM3_SAO_FT3 + #define PSC_TBL_KB_UDIMM3_SAO_FT3 #endif #ifndef PSC_TBL_KB_CLK_DIS_FT3 #define PSC_TBL_KB_CLK_DIS_FT3 @@ -1384,7 +1398,7 @@ BOOLEAN MemFS3DefConstructorRet ( }; PSC_TBL_ENTRY* memPSCTblDramTermArrayKB[] = { - PSC_TBL_KB_UDIMM3_DRAM_TERM + PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 PSC_TBL_KB_SODIMM3_DRAM_TERM PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM PSC_TBL_KB_SODWN_DRAM_TERM @@ -1401,7 +1415,7 @@ BOOLEAN MemFS3DefConstructorRet ( PSC_TBL_KB_SODIMM3_SAO PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO PSC_TBL_KB_SODWN_SAO - PSC_TBL_KB_UDIMM3_SAO + PSC_TBL_KB_UDIMM3_SAO_FT3 PSC_TBL_END }; diff --git a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h index 136b0f4c85..1295888f99 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h @@ -360,6 +360,9 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { #define OPTION_MEM_RESTORE TRUE #undef OPTION_DIMM_EXCLUDE #define OPTION_DIMM_EXCLUDE TRUE + #ifndef OPTION_MICROSERVER + #define OPTION_MICROSERVER FALSE + #endif #endif #endif @@ -1811,7 +1814,8 @@ FCH_PLATFORM_POLICY FchUserOptions = { CFG_FCH_SD_CLOCK_CONTROL, // CfgFchSdClockControl CFG_FCH_SCI_MAP_LIST, // *CfgFchSciMapControl CFG_FCH_SATA_PHY_LIST, // *CfgFchSataPhyControl - CFG_FCH_GPIO_CONTROL_LIST // *CfgFchGpioControl + CFG_FCH_GPIO_CONTROL_LIST, // *CfgFchGpioControl + CFG_FCH_RTC_WORKAROUND // CfgFchRtcWorkaround }; BUILD_OPT_CFG UserOptions = { |