diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family')
| -rw-r--r-- | src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c | 6 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c | 23 |
2 files changed, 19 insertions, 10 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c index 8abcac0f8a..0ae09932cf 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c @@ -210,12 +210,12 @@ FchProgramSataPhy ( SquelchValue[0] = (0x07 << 9); SquelchValue[1] = (0x07 << 9); for (PortNum = 0; PortNum < 2; PortNum ++) { - RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x130 + PortNum), StdHeader); + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x30 + PortNum), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 13)), (UINT32) (0x0 << 13), StdHeader); - RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x120 + PortNum), StdHeader); + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x20 + PortNum), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader); - RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x110 + PortNum), StdHeader); + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x10 + PortNum), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, 0x010, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c index ab3bbab37a..9f526d8837 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c @@ -165,13 +165,22 @@ FchInitMidProgramSataRegs ( FchSataMsiCapability = 0; } // + // Disable SATA FLR Capability + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x070 + 1), AccessWidth8, 0, 0, StdHeader); + // // Enabled SATA MSI capability // SATA MSI and D3 Power State Capability MMC 0x2 // - if ( !FchSataMsiCapability ) { - RwPci (((SATA_BUS_DEV_FUN << 16) + 0x70 + 1), AccessWidth8, 0, 0, StdHeader); + if ( FchSataMsiCapability ) { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x060 + 1), AccessWidth8, 0, 0x70, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x070 + 1), AccessWidth8, 0, 0x50, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x050 + 2), AccessWidth8, 0xF1, 0x06, StdHeader); + } else { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x060 + 1), AccessWidth8, 0, 0x70, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x070 + 1), AccessWidth8, 0, 0x00, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x050 + 2), AccessWidth8, 0xF1, 0x00, StdHeader); } - // // Sata Target Support 8 devices function // @@ -286,8 +295,8 @@ FchInitLateProgramSataRegs ( RwMem ((Bar5 + 0x110 + (PortNumByte * 0x80)), AccessWidth32, 0xFFFFFFFF, 0x00); } if ( LocalCfgPtr->Sata.SataDevSlpPort0 ) { - RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x3E); - RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x01); + RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x0E); + RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x02); RwMem ((Bar5 + 0x0F4), AccessWidth32, 0xFFFFFEEF, BIT4 + BIT8); } else { RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x00); @@ -297,8 +306,8 @@ FchInitLateProgramSataRegs ( } } if ( LocalCfgPtr->Sata.SataDevSlpPort1 ) { - RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x3E); - RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x01); + RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x0E); + RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x02); RwMem ((Bar5 + 0x0F4), AccessWidth32, 0xFFFFFDEF, BIT4 + BIT9); } else { RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x00); |