diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc')
8 files changed, 22 insertions, 22 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c index 6494c69407..60b1bddf36 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c @@ -261,5 +261,5 @@ GetGlobalCpuFeatureListAddress ( AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR; - *Address = (UINT64 *)(UINT32)(AddressValue); + *Address = (UINT64 *)(UINTN)(AddressValue); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c index 7feb3faee2..4b6128e245 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c @@ -215,7 +215,7 @@ SaveDeviceContext ( UINT64 EndAddress; VOID *OrMask; - StartAddress = (UINT64)(UINT32) DeviceList; + StartAddress = (UINTN) DeviceList; Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; @@ -279,7 +279,7 @@ SaveDeviceContext ( break; } } - EndAddress = (UINT64)(UINT32) OrMask; + EndAddress = (UINTN) OrMask; *ActualBufferSize = (UINT32) (EndAddress - StartAddress); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c index 605e0c4325..f1217a32c8 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c @@ -202,7 +202,7 @@ GetPstateGatherDataAddressAtPost ( AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR; - *Ptr = (UINT64 *)(UINT32)(AddressValue); + *Ptr = (UINT64 *)(UINTN)(AddressValue); return AGESA_SUCCESS; } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c index 42a6afa10f..24ee886c98 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c @@ -158,7 +158,7 @@ HeapManagerInit ( GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); - HeapBufferPtr = (UINT8 *)(UINT32) StdHeader->HeapBasePtr; + HeapBufferPtr = (UINT8 *)(UINTN) StdHeader->HeapBasePtr; // Check whether the heap manager is already initialized LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader); @@ -328,14 +328,14 @@ HeapAllocateBuffer ( // Check Heap database is valid if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); + BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader); HeapManager = (HEAP_MANAGER *) BaseAddress; if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // Heap is not available, ASSERT here ASSERT (FALSE); return AGESA_ERROR; } - StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; + StdHeader->HeapBasePtr = (UINTN)BaseAddress; } // Allocate @@ -473,14 +473,14 @@ HeapDeallocateBuffer ( // Check Heap database is valid if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); + BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader); HeapManager = (HEAP_MANAGER *) BaseAddress; if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // Heap is not available, ASSERT here ASSERT (FALSE); return AGESA_ERROR; } - StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; + StdHeader->HeapBasePtr = (UINTN)BaseAddress; } OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; @@ -602,14 +602,14 @@ HeapLocateBuffer ( // Check Heap database is valid if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); + BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader); HeapManager = (HEAP_MANAGER *) BaseAddress; if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // Heap is not available, ASSERT here ASSERT (FALSE); return AGESA_ERROR; } - StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; + StdHeader->HeapBasePtr = (UINTN)BaseAddress; } OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset; CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c index 5b30e55e20..093ab970b3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c @@ -119,7 +119,7 @@ AmdS3LateRestore ( ASSERT (S3LateParams != NULL); BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage; - S3LateParams->StdHeader.HeapBasePtr = (UINT32) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset]; + S3LateParams->StdHeader.HeapBasePtr = (UINTN) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset]; ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0); IDS_HDT_CONSOLE_INIT (&S3LateParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h index c01fd5ef98..8261a3d924 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h @@ -75,7 +75,7 @@ #define OFF 0 -#define PVOID UINT32 +#define PVOID UINTN #define STRING_TO_UINT32(a, b, c, d) ((UINT32) ((d << 24) | (c << 16) | (b << 8) | a)) diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c index 66cf992243..aee94676e9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c @@ -189,8 +189,8 @@ GfxSamuInit ( // Load boot control structure SamuBootControl = (SAMU_BOOT_CONTROL *)AlignedControlXBuffer; SamuBootControl->BootControl = 0x3; - SamuBootControl->KernelAddrLo = (UINT32) (AlignedPatchYBuffer); - SamuBootControl->KernelAddrHi = 0; //(UINT32) ((((UINT64) AlignedPatchYBuffer) >> 32) & 0xFF); + SamuBootControl->KernelAddrLo = (UINTN)AlignedPatchYBuffer; + SamuBootControl->KernelAddrHi = ((((UINT64)(UINTN)AlignedPatchYBuffer) >> 32) & 0xFF); if (SamuUseF1dPatch == TRUE) { SamuBootControl->TweakSelect = 0xBB027E1F; SamuBootControl->KeySelect = 0x8E174F83; @@ -209,7 +209,7 @@ GfxSamuInit ( // Write (physical address of boot control structure)>>8 into SAM_SAB_INIT_TLB_CONFIG (Location X >> 8) GMMx22008 = 0x4; GnbRegisterWriteKB (GnbHandle, 0x12, 0x22008, &GMMx22008, 0, GnbLibGetHeader (Gfx)); - GMMx2200C = ((UINT32) ((UINT32) AlignedControlXBuffer)) >> 8; + GMMx2200C = ((UINTN) AlignedControlXBuffer) >> 8; GnbRegisterWriteKB (GnbHandle, 0x12, 0x2200C, &GMMx2200C, 0, GnbLibGetHeader (Gfx)); // Write 0x0 to SAM_RST_HOST_SOFT_RESET diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c index bde0514528..d4d2685750 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c @@ -252,14 +252,14 @@ AmdIdsHdtOutInit ( HdtoutHeader.DataIndex = 0; HdtoutHeader.PrintCtrl = HDTOUT_PRINTCTRL_ON; HdtoutHeader.NumBreakpointUnit = 0; - HdtoutHeader.FuncListAddr = (UINT32) IDS_FUNCLIST_ADDR; + HdtoutHeader.FuncListAddr = (UINTN)IDS_FUNCLIST_ADDR; HdtoutHeader.StatusStr[0] = 0; HdtoutHeader.OutBufferMode = HDTOUT_BUFFER_MODE_ON; HdtoutHeader.EnableMask = 0; HdtoutHeader.ConsoleFilter = IDS_DEBUG_PRINT_MASK; // Trigger HDTOUT breakpoint to get inputs from script - IdsOutPort (HDTOUT_INIT, (UINT32) &HdtoutHeader, 0); + IdsOutPort (HDTOUT_INIT, (UINTN) &HdtoutHeader, 0); // Disable AP HDTOUT if set BspOnlyFlag if (HdtoutHeader.BspOnlyFlag == HDTOUT_BSP_ONLY) { if (!IsBsp (StdHeader, &IgnoreSts)) { @@ -299,7 +299,7 @@ AmdIdsHdtOutInit ( } while ((HdtoutHeader.BufferSize & 0x8000) == 0); // If the buffer have been successfully allocated? if ((HdtoutHeader.BufferSize & 0x8000) == 0) { - LibAmdWriteCpuReg (DR3_REG, (UINT32) AllocHeapParams.BufferPtr); + LibAmdWriteCpuReg (DR3_REG, (UINTN)AllocHeapParams.BufferPtr); LibAmdMemCopy (AllocHeapParams.BufferPtr, &HdtoutHeader, sizeof (HdtoutHeader) - 2, StdHeader); } else { /// Clear DR3_REG @@ -327,7 +327,7 @@ AmdIdsHdtOutBufferFlush ( if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, StdHeader)) { if ((HdtoutHeaderPtr->PrintCtrl == HDTOUT_PRINTCTRL_ON) && (HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON)) { - IdsOutPort (HDTOUT_PRINT, (UINT32) HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex); + IdsOutPort (HDTOUT_PRINT, (UINTN)HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex); HdtoutHeaderPtr->DataIndex = 0; } } @@ -355,10 +355,10 @@ AmdIdsHdtOutExitCoreTask ( if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, StdHeader)) { if ((HdtoutHeaderPtr->PrintCtrl == HDTOUT_PRINTCTRL_ON) && (HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON)) { - IdsOutPort (HDTOUT_PRINT, (UINT32) HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex); + IdsOutPort (HDTOUT_PRINT, (UINTN)HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex); } } - IdsOutPort (HDTOUT_EXIT, (UINT32) HdtoutHeaderPtr, 0); + IdsOutPort (HDTOUT_EXIT, (UINTN)HdtoutHeaderPtr, 0); AmdIdsHdtOutRegisterRestore (StdHeader); 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