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Diffstat (limited to 'src/vendorcode/amd/cimx/sb900/SbCmn.c')
-rw-r--r--src/vendorcode/amd/cimx/sb900/SbCmn.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/amd/cimx/sb900/SbCmn.c b/src/vendorcode/amd/cimx/sb900/SbCmn.c
index 29f6fd1d80..bd50ddeb22 100644
--- a/src/vendorcode/amd/cimx/sb900/SbCmn.c
+++ b/src/vendorcode/amd/cimx/sb900/SbCmn.c
@@ -398,7 +398,7 @@ commonInitEarlyBoot (
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
//Early post initialization of pci config space
programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) );
- if ( pConfig->BuildParameters.SmbusSsid != NULL ) {
+ if ( pConfig->BuildParameters.SmbusSsid != 0 ) {
RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid);
}
//Make BAR registers of smbus invisible.
@@ -408,7 +408,7 @@ commonInitEarlyBoot (
// LPC CFG programming
//
// SSID for LPC Controller
- if (pConfig->BuildParameters.LpcSsid != NULL ) {
+ if (pConfig->BuildParameters.LpcSsid != 0 ) {
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid);
}
// LPC MSI