diff options
Diffstat (limited to 'src/vendorcode/amd/cimx/sb900/Usb.c')
| -rw-r--r-- | src/vendorcode/amd/cimx/sb900/Usb.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vendorcode/amd/cimx/sb900/Usb.c b/src/vendorcode/amd/cimx/sb900/Usb.c index 2ae03b3f6d..2d635ec9ee 100644 --- a/src/vendorcode/amd/cimx/sb900/Usb.c +++ b/src/vendorcode/amd/cimx/sb900/Usb.c @@ -357,7 +357,7 @@ EhciInitAfterPciInit ( if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) { //Enable Memory access RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); - if (pConfig->BuildParameters.EhciSsid != NULL ) { + if (pConfig->BuildParameters.EhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid); } //USB Common PHY CAL & Control Register setting @@ -571,7 +571,7 @@ usb4OhciInitAfterPciInit ( UINT32 ddDeviceId; ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16); OhciInitAfterPciInit (ddDeviceId, pConfig); - if (pConfig->BuildParameters.Ohci4Ssid != NULL ) { + if (pConfig->BuildParameters.Ohci4Ssid != 0 ) { RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid); } } @@ -595,7 +595,7 @@ OhciInitAfterPciInit ( // RPR USB SMI Handshake RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00); if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) { - if ( pConfig->BuildParameters.OhciSsid != NULL ) { + if ( pConfig->BuildParameters.OhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid); } } |