diff options
Diffstat (limited to 'src/vendorcode/amd/pi/00660F01/Proc')
4 files changed, 32 insertions, 7 deletions
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h index c4be6286b6..62ef892eda 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h @@ -69,7 +69,11 @@ // Family 15h equates #define AMD_FAMILY_15_CZ 0x0004u #define AMD_FAMILY_CZ (AMD_FAMILY_15_CZ) -#define AMD_FAMILY_15 AMD_FAMILY_15_CZ + +#define AMD_FAMILY_15_ST 0x0008u +#define AMD_FAMILY_ST (AMD_FAMILY_15_ST) + +#define AMD_FAMILY_15 (AMD_FAMILY_15_CZ | AMD_FAMILY_ST) // Family Unknown #define AMD_FAMILY_UNKNOWN 0x8000u @@ -81,12 +85,23 @@ // Family 15h CZ steppings #define AMD_F15_CZ_A0 0x0001u #define AMD_F15_CZ_A1 0x0002u +#define AMD_F15_BR_A1 0x0004u + // Family 15h ST steppings +#define AMD_F15_ST_A0 0x0010u // Family 15h Unknown stepping #define AMD_F15_UNKNOWN 0x8000u -#define AMD_F15_CZ_Ax (AMD_F15_CZ_A0 | AMD_F15_CZ_A1) -#define AMD_F15_CZ_ALL (AMD_F15_CZ_Ax) + // CZ and BR +#define AMD_F15_BR_Ax (AMD_F15_BR_A1) +#define AMD_F15_BR_ALL (AMD_F15_BR_Ax) + +#define AMD_F15_CZ_Ax (AMD_F15_CZ_A0 | AMD_F15_CZ_A1 | AMD_F15_BR_Ax) +#define AMD_F15_CZ_ALL (AMD_F15_CZ_Ax | AMD_F15_BR_ALL) + + // ST +#define AMD_F15_ST_Ax (AMD_F15_ST_A0) +#define AMD_F15_ST_ALL (AMD_F15_ST_Ax) -#define AMD_F15_ALL AMD_F15_CZ_ALL +#define AMD_F15_ALL (AMD_F15_CZ_ALL | AMD_F15_ST_ALL) #endif // _CPU_FAM_REGISTERS_H_ diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h index e51a01feb5..889be764a1 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h @@ -429,14 +429,14 @@ typedef struct { #define CPUID_EXT_FAMILY_MASK 0x0FF00000ul #define CZ_SOCKET_FP4 0 +#define ST_SOCKET_FP4 0 +#define ST_SOCKET_FT4 3 #define SOCKET_IGNORE 0xF #define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull #define APIC_EXT_BRDCST_MASK 0x000E0000ul #define APIC_ENABLE_BIT 0x00000800ul -#ifndef LOCAL_APIC_ADDR #define LOCAL_APIC_ADDR 0xFEE00000ul -#endif #define INT_CMD_REG_LO 0x300 #define INT_CMD_REG_HI 0x310 #define REMOTE_MSG_REG 0x380 diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h index fb2bae22a0..35a76d20fd 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h @@ -986,6 +986,7 @@ typedef struct { VOID* OemProgrammingTablePtr; /// Pointer of ACPI OEM table UINT8 SpreadSpectrumOptions; /// SpreadSpectrumOptions - Spread Spectrum Option BOOLEAN PwrDownDisp2ClkPcieR; /// Power down DISP2_CLK and PCIE_RCLK_Output for power savings + BOOLEAN NoClearThermalTripSts; /// Skip clearing ThermalTrip status } FCH_ACPI; diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h index c18e191780..61082743de 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h @@ -68,6 +68,11 @@ #define PSP_MAILBOX_BASE 0x70 ///< Mailbox base offset on PCIe BAR #define PSP_MAILBOX_STATUS_OFFSET 0x4 ///< Staus Offset +#define PMIO_INDEX_PORT 0xCD6 ///Pmio index port +#define PMIO_DATA_PORT 0xCD7 ///Pmio data port + +#define PMIO_REG62 0x62 ///PMIOx62 + //====================================================================================== // // Define Mailbox Status field @@ -162,7 +167,7 @@ GetPspMboxStatus ( BOOLEAN -PspBarInitEarly (void); +PspBarInitEarly (VOID); VOID PspLibPciIndirectRead ( @@ -184,4 +189,8 @@ UINT8 PspLibAccessWidth ( IN ACCESS_WIDTH AccessWidth ); + +BOOLEAN +IsS3Resume (VOID); + #endif // _AMD_LIB_H_ |