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-rw-r--r--src/vendorcode/amd/agesa/f10/AGESA.h8
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h2
-rw-r--r--src/vendorcode/amd/agesa/f12/AGESA.h8
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h2
-rw-r--r--src/vendorcode/amd/agesa/f14/AGESA.h8
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h2
-rw-r--r--src/vendorcode/amd/agesa/f15/AGESA.h10
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h2
-rw-r--r--src/vendorcode/amd/agesa/f16kb/AGESA.h4
9 files changed, 12 insertions, 34 deletions
diff --git a/src/vendorcode/amd/agesa/f10/AGESA.h b/src/vendorcode/amd/agesa/f10/AGESA.h
index c38bf40a54..a12811604a 100644
--- a/src/vendorcode/amd/agesa/f10/AGESA.h
+++ b/src/vendorcode/amd/agesa/f10/AGESA.h
@@ -1012,12 +1012,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------
#define SYS_CFG 0xC0010010
-#ifndef TOP_MEM
- #define TOP_MEM 0xC001001A
-#endif
-#ifndef TOP_MEM2
- #define TOP_MEM2 0xC001001D
-#endif
+#define TOP_MEM 0xC001001Aul
+#define TOP_MEM2 0xC001001Dul
#define HWCR 0xC0010015
#define NB_CFG 0xC001001F
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h
index 34d256801c..1777c5d979 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h
@@ -92,7 +92,7 @@
#define NorthbridgeCapabilities 0xE8
#define DRAMBase0 0x40
#define MMIOBase0 0x80
-#define TOP_MEM 0xC001001A
+#define TOP_MEM 0xC001001Aul
#define LOW_NODE_DEVICEID 24
#define LOW_APICID 0
diff --git a/src/vendorcode/amd/agesa/f12/AGESA.h b/src/vendorcode/amd/agesa/f12/AGESA.h
index 9660f35965..abe72b61b6 100644
--- a/src/vendorcode/amd/agesa/f12/AGESA.h
+++ b/src/vendorcode/amd/agesa/f12/AGESA.h
@@ -1279,12 +1279,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------
#define SYS_CFG 0xC0010010
-#ifndef TOP_MEM
-#define TOP_MEM 0xC001001A
-#endif
-#ifndef TOP_MEM2
-#define TOP_MEM2 0xC001001D
-#endif
+#define TOP_MEM 0xC001001Aul
+#define TOP_MEM2 0xC001001Dul
#define HWCR 0xC0010015
#define NB_CFG 0xC001001F
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h
index 29f4070375..b871845870 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h
@@ -101,7 +101,7 @@ AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE);
#define NorthbridgeCapabilities 0xE8
#define DRAMBase0 0x40
#define MMIOBase0 0x80
-#define TOP_MEM 0xC001001A
+#define TOP_MEM 0xC001001Aul
#define LOW_NODE_DEVICEID 24
#define LOW_APICID 0
diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h
index a8ede95e7f..d997ad1636 100644
--- a/src/vendorcode/amd/agesa/f14/AGESA.h
+++ b/src/vendorcode/amd/agesa/f14/AGESA.h
@@ -1129,12 +1129,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------
#define SYS_CFG 0xC0010010
-#ifndef TOP_MEM
-#define TOP_MEM 0xC001001A
-#endif
-#ifndef TOP_MEM2
-#define TOP_MEM2 0xC001001D
-#endif
+#define TOP_MEM 0xC001001Aul
+#define TOP_MEM2 0xC001001Dul
#define HWCR 0xC0010015
#define NB_CFG 0xC001001F
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h
index 6369bfca48..a6f6c7819e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h
@@ -98,7 +98,7 @@
#define NorthbridgeCapabilities 0xE8
#define DRAMBase0 0x40
#define MMIOBase0 0x80
-#define TOP_MEM 0xC001001A
+#define TOP_MEM 0xC001001Aul
#define LOW_NODE_DEVICEID 24
#define LOW_APICID 0
diff --git a/src/vendorcode/amd/agesa/f15/AGESA.h b/src/vendorcode/amd/agesa/f15/AGESA.h
index 6b0171b269..ffa37ae577 100644
--- a/src/vendorcode/amd/agesa/f15/AGESA.h
+++ b/src/vendorcode/amd/agesa/f15/AGESA.h
@@ -1418,14 +1418,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------
#define SYS_CFG 0xC0010010
-//#define TOP_MEM 0xC001001A
-//#define TOP_MEM2 0xC001001D
-#ifndef TOP_MEM
- #define TOP_MEM 0xC001001A
-#endif
-#ifndef TOP_MEM2
- #define TOP_MEM2 0xC001001D
-#endif
+#define TOP_MEM 0xC001001Aul
+#define TOP_MEM2 0xC001001Dul
#define HWCR 0xC0010015
#define NB_CFG 0xC001001F
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h
index 050ec53b51..d0103477e7 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h
@@ -116,7 +116,7 @@ CpuLateInitApTask (
#define NorthbridgeCapabilities 0xE8
#define DRAMBase0 0x40
#define MMIOBase0 0x80
-#define TOP_MEM 0xC001001A
+#define TOP_MEM 0xC001001Aul
#define LOW_NODE_DEVICEID 24
#define LOW_APICID 0
diff --git a/src/vendorcode/amd/agesa/f16kb/AGESA.h b/src/vendorcode/amd/agesa/f16kb/AGESA.h
index 3e58d231a9..6c2f19ccf1 100644
--- a/src/vendorcode/amd/agesa/f16kb/AGESA.h
+++ b/src/vendorcode/amd/agesa/f16kb/AGESA.h
@@ -1590,12 +1590,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------
#define SYS_CFG 0xC0010010ul
-#ifndef TOP_MEM
#define TOP_MEM 0xC001001Aul
-#endif
-#ifndef TOP_MEM2
#define TOP_MEM2 0xC001001Dul
-#endif
#define HWCR 0xC0010015ul
#define NB_CFG 0xC001001Ful