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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c12
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c12
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c24
-rw-r--r--src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Base.h2
-rw-r--r--src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Base.h2
-rw-r--r--src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Base.h2
6 files changed, 30 insertions, 24 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c
index 5c5ab45e24..69a60b10c1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c
@@ -355,12 +355,12 @@ GfxGmcInitializeSequencerModel (
if (ActiveChannel == 2) {
// Both controllers enabled
- GMMx277C.Field.ActRd = MIN (DctChannel[0].D18F2x0F4_x40.Field.Trcd, DctChannel[1].D18F2x0F4_x40.Field.Trcd) + 5;
- GMMx277C.Field.RasMActRd = MIN ((DctChannel[0].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[0].D18F2x0F4_x40.Field.Trcd + 5)),
+ GMMx277C.Field.ActRd = MIN_UNSAFE (DctChannel[0].D18F2x0F4_x40.Field.Trcd, DctChannel[1].D18F2x0F4_x40.Field.Trcd) + 5;
+ GMMx277C.Field.RasMActRd = MIN_UNSAFE ((DctChannel[0].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[0].D18F2x0F4_x40.Field.Trcd + 5)),
(DctChannel[1].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[1].D18F2x0F4_x40.Field.Trcd + 5)));
- GMMx2780.Field.Ras2Ras = MIN (DctChannel[0].D18F2x0F4_x40.Field.Trc, DctChannel[1].D18F2x0F4_x40.Field.Trc) + 11 - 1;
- GMMx2780.Field.Rp = MIN (DctChannel[0].D18F2x0F4_x40.Field.Trp, DctChannel[1].D18F2x0F4_x40.Field.Trp) + 5 - 1;
- GMMx2780.Field.WrPlusRp = MIN (
+ GMMx2780.Field.Ras2Ras = MIN_UNSAFE (DctChannel[0].D18F2x0F4_x40.Field.Trc, DctChannel[1].D18F2x0F4_x40.Field.Trc) + 11 - 1;
+ GMMx2780.Field.Rp = MIN_UNSAFE (DctChannel[0].D18F2x0F4_x40.Field.Trp, DctChannel[1].D18F2x0F4_x40.Field.Trp) + 5 - 1;
+ GMMx2780.Field.WrPlusRp = MIN_UNSAFE (
((DctChannel[0].D18F2x084.Field.Twr == 0) ? 16 :
((DctChannel[0].D18F2x084.Field.Twr < 4) ? (DctChannel[0].D18F2x084.Field.Twr + 4) :
(DctChannel[0].D18F2x084.Field.Twr * 2)) + DctChannel[0].D18F2x0F4_x40.Field.Trp + 5),
@@ -368,7 +368,7 @@ GfxGmcInitializeSequencerModel (
((DctChannel[1].D18F2x084.Field.Twr < 4) ? (DctChannel[1].D18F2x084.Field.Twr + 4) :
(DctChannel[1].D18F2x084.Field.Twr * 2)) + DctChannel[1].D18F2x0F4_x40.Field.Trp + 5)
) - 1;
- GMMx2780.Field.BusTurn = (MIN (
+ GMMx2780.Field.BusTurn = (MIN_UNSAFE (
DctChannel[0].D18F2x084.Field.Tcwl + 5 +
DctChannel[0].D18F2x0F4_x41.Field.Twtr + 4 +
DctChannel[0].D18F2x08C.Field.TrwtTO + 2 ,
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c
index 7929d02415..b4fcfee133 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c
@@ -361,12 +361,12 @@ GfxGmcInitializeSequencerModel (
if (ActiveChannel == 2) {
// Both controllers enabled
- GMMx277C.Field.ActRd = MIN (DctChannel[0].D18F2x0F4_x40.Field.Trcd, DctChannel[1].D18F2x0F4_x40.Field.Trcd) + 5;
- GMMx277C.Field.RasMActRd = MIN ((DctChannel[0].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[0].D18F2x0F4_x40.Field.Trcd + 5)),
+ GMMx277C.Field.ActRd = MIN_UNSAFE (DctChannel[0].D18F2x0F4_x40.Field.Trcd, DctChannel[1].D18F2x0F4_x40.Field.Trcd) + 5;
+ GMMx277C.Field.RasMActRd = MIN_UNSAFE ((DctChannel[0].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[0].D18F2x0F4_x40.Field.Trcd + 5)),
(DctChannel[1].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[1].D18F2x0F4_x40.Field.Trcd + 5)));
- GMMx2780.Field.Ras2Ras = MIN (DctChannel[0].D18F2x0F4_x40.Field.Trc, DctChannel[1].D18F2x0F4_x40.Field.Trc) + 11 - 1;
- GMMx2780.Field.Rp = MIN (DctChannel[0].D18F2x0F4_x40.Field.Trp, DctChannel[1].D18F2x0F4_x40.Field.Trp) + 5 - 1;
- GMMx2780.Field.WrPlusRp = MIN (
+ GMMx2780.Field.Ras2Ras = MIN_UNSAFE (DctChannel[0].D18F2x0F4_x40.Field.Trc, DctChannel[1].D18F2x0F4_x40.Field.Trc) + 11 - 1;
+ GMMx2780.Field.Rp = MIN_UNSAFE (DctChannel[0].D18F2x0F4_x40.Field.Trp, DctChannel[1].D18F2x0F4_x40.Field.Trp) + 5 - 1;
+ GMMx2780.Field.WrPlusRp = MIN_UNSAFE (
((DctChannel[0].D18F2x084.Field.Twr == 0) ? 16 :
((DctChannel[0].D18F2x084.Field.Twr < 4) ? (DctChannel[0].D18F2x084.Field.Twr + 4) :
(DctChannel[0].D18F2x084.Field.Twr * 2)) + DctChannel[0].D18F2x0F4_x40.Field.Trp + 5),
@@ -374,7 +374,7 @@ GfxGmcInitializeSequencerModel (
((DctChannel[1].D18F2x084.Field.Twr < 4) ? (DctChannel[1].D18F2x084.Field.Twr + 4) :
(DctChannel[1].D18F2x084.Field.Twr * 2)) + DctChannel[1].D18F2x0F4_x40.Field.Trp + 5)
) - 1;
- GMMx2780.Field.BusTurn = (MIN (
+ GMMx2780.Field.BusTurn = (MIN_UNSAFE (
DctChannel[0].D18F2x084.Field.Tcwl + 5 +
DctChannel[0].D18F2x0F4_x41.Field.Twtr + 4 +
DctChannel[0].D18F2x08C.Field.TrwtTO + 2 ,
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
index 3e151c1fd8..75ec2fb387 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
@@ -340,30 +340,30 @@ GfxGmcInitializeSequencerTN (
GnbRegisterReadTN (TYPE_GMM , 0x27fc , &ex1061.Value, 0, GnbLibGetHeader (Gfx));
if (((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) && ((DramChannelPresent & GNB_GFX_DRAM_CH_1_PRESENT) != 0)) {
- ex1047.Field.ex1047_0 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trcd, DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100;
+ ex1047.Field.ex1047_0 = (MIN_UNSAFE (DctChannel.D18F2x200_dct0_mp0.Field.Trcd, DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100;
ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0;
- ex1047.Field.ex1047_2 = (MIN ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd),
+ ex1047.Field.ex1047_2 = (MIN_UNSAFE ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd),
(DctChannel.D18F2x204_dct1_mp0.Field.Trc - DctChannel.D18F2x200_dct1_mp0.Field.Trcd)) * scale_mp0) / 100;
ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2;
- ex1048.Field.ex1048_0 = (MIN (DctChannel.D18F2x204_dct0_mp0.Field.Trc, DctChannel.D18F2x204_dct1_mp0.Field.Trc) * scale_mp0) / 100;
- ex1048.Field.ex1048_1 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trp, DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100;
- ex1048.Field.ex1048_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp),
+ ex1048.Field.ex1048_0 = (MIN_UNSAFE (DctChannel.D18F2x204_dct0_mp0.Field.Trc, DctChannel.D18F2x204_dct1_mp0.Field.Trc) * scale_mp0) / 100;
+ ex1048.Field.ex1048_1 = (MIN_UNSAFE (DctChannel.D18F2x200_dct0_mp0.Field.Trp, DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100;
+ ex1048.Field.ex1048_2 = (MIN_UNSAFE ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp),
(DctChannel.D18F2x22C_dct1_mp0.Field.Twr + DctChannel.D18F2x200_dct1_mp0.Field.Trp)) * scale_mp0) / 100;
- ex1048.Field.ex1048_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO),
+ ex1048.Field.ex1048_3 = ((MIN_UNSAFE ((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO),
(DctChannel.D18F2x20C_dct1_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp0.Field.Twtr + DctChannel.D18F2x21C_dct1_mp0.Field.TrwtTO)) / 2) * scale_mp0) / 100;
- ex1060.Field.ex1060_0 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trcd, DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100;
+ ex1060.Field.ex1060_0 = (MIN_UNSAFE (DctChannel.D18F2x200_dct0_mp1.Field.Trcd, DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100;
ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0;
- ex1060.Field.ex1060_2 = (MIN ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd),
+ ex1060.Field.ex1060_2 = (MIN_UNSAFE ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd),
(DctChannel.D18F2x204_dct1_mp1.Field.Trc - DctChannel.D18F2x200_dct1_mp1.Field.Trcd)) * scale_mp1) / 100;
ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2;
- ex1061.Field.ex1061_0 = (MIN (DctChannel.D18F2x204_dct0_mp1.Field.Trc, DctChannel.D18F2x204_dct1_mp1.Field.Trc) * scale_mp1) / 100;
- ex1061.Field.ex1061_1 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trp, DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100;
- ex1061.Field.ex1061_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp),
+ ex1061.Field.ex1061_0 = (MIN_UNSAFE (DctChannel.D18F2x204_dct0_mp1.Field.Trc, DctChannel.D18F2x204_dct1_mp1.Field.Trc) * scale_mp1) / 100;
+ ex1061.Field.ex1061_1 = (MIN_UNSAFE (DctChannel.D18F2x200_dct0_mp1.Field.Trp, DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100;
+ ex1061.Field.ex1061_2 = (MIN_UNSAFE ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp),
(DctChannel.D18F2x22C_dct1_mp1.Field.Twr + DctChannel.D18F2x200_dct1_mp1.Field.Trp)) * scale_mp1) / 100;
- ex1061.Field.ex1061_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO),
+ ex1061.Field.ex1061_3 = ((MIN_UNSAFE ((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO),
(DctChannel.D18F2x20C_dct1_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp1.Field.Twtr + DctChannel.D18F2x21C_dct1_mp1.Field.TrwtTO)) / 2) * scale_mp1) / 100;
} else if ((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) {
diff --git a/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Base.h b/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Base.h
index 70e419758c..d0dd4c9e46 100644
--- a/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Base.h
+++ b/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Base.h
@@ -735,8 +735,10 @@ typedef UINTN *BASE_LIST;
@return The absolute value of the signed operand.
**/
+#ifndef ABS
#define ABS(a) \
(((a) < 0) ? (-(a)) : (a))
+#endif
//
// Status codes common to all execution phases
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Base.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Base.h
index 694a94dd41..3a0cdb2a13 100644
--- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Base.h
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Base.h
@@ -941,8 +941,10 @@ typedef UINTN *BASE_LIST;
@return The absolute value of the signed operand.
**/
+#ifndef ABS
#define ABS(a) \
(((a) < 0) ? (-(a)) : (a))
+#endif
//
// Status codes common to all execution phases
diff --git a/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Base.h b/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Base.h
index b7dc94d1fb..c0ea9c1db8 100644
--- a/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Base.h
+++ b/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Base.h
@@ -718,8 +718,10 @@ typedef UINTN *BASE_LIST;
@return The absolute value of the signed operand.
**/
+#ifndef ABS
#define ABS(a) \
(((a) < 0) ? (-(a)) : (a))
+#endif
//
// Status codes common to all execution phases
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-13 23:54:02 +0000