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-rw-r--r--src/vendorcode/amd/cimx/sb800/AZALIA.c2
-rw-r--r--src/vendorcode/amd/cimx/sb800/GEC.c2
-rw-r--r--src/vendorcode/amd/cimx/sb800/SATA.c14
-rw-r--r--src/vendorcode/amd/cimx/sb800/SBCMN.c4
-rw-r--r--src/vendorcode/amd/cimx/sb800/SBPOR.c2
-rw-r--r--src/vendorcode/amd/cimx/sb800/USB.c6
-rw-r--r--src/vendorcode/amd/cimx/sb900/Azalia.c2
-rw-r--r--src/vendorcode/amd/cimx/sb900/Gec.c2
-rw-r--r--src/vendorcode/amd/cimx/sb900/Sata.c2
-rw-r--r--src/vendorcode/amd/cimx/sb900/SbCmn.c4
-rw-r--r--src/vendorcode/amd/cimx/sb900/Usb.c6
11 files changed, 23 insertions, 23 deletions
diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c
index edd335f387..e402ae8083 100644
--- a/src/vendorcode/amd/cimx/sb800/AZALIA.c
+++ b/src/vendorcode/amd/cimx/sb800/AZALIA.c
@@ -284,7 +284,7 @@ azaliaInitAfterPciEnum (
if ( pConfig->AzaliaController != 1 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
- if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {
+ if ( pConfig->BuildParameters.AzaliaSsid != 0 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
}
ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
diff --git a/src/vendorcode/amd/cimx/sb800/GEC.c b/src/vendorcode/amd/cimx/sb800/GEC.c
index 6ee142f795..582181b9d9 100644
--- a/src/vendorcode/amd/cimx/sb800/GEC.c
+++ b/src/vendorcode/amd/cimx/sb800/GEC.c
@@ -113,7 +113,7 @@ gecInitAfterPciEnum (
ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar);
dbTemp = 0x07;
WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp);
- if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) {
+ if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) {
GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr;
GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase;
AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c
index 5966ec8e03..a3012086e5 100644
--- a/src/vendorcode/amd/cimx/sb800/SATA.c
+++ b/src/vendorcode/amd/cimx/sb800/SATA.c
@@ -258,7 +258,7 @@ sataInitBeforePciEnum (
UINT16 i;
SATAPHYSETTING *pPhyTable;
- ddTempVar = NULL;
+ ddTempVar = 0;
// BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h
// BIT4: Disable fast boot
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT2 + BIT4);
@@ -292,17 +292,17 @@ sataInitBeforePciEnum (
//Set PATA controller to native mode
RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
}
- if (pConfig->BuildParameters.IdeSsid != NULL ) {
+ if (pConfig->BuildParameters.IdeSsid != 0 ) {
RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid);
}
// SATA Controller Class ID & SSID
pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]);
- if ( pConfig->BuildParameters.SataIDESsid != NULL ) {
+ if ( pConfig->BuildParameters.SataIDESsid != 0 ) {
ddTempVar = pConfig->BuildParameters.SataIDESsid;
}
dwDeviceId = pDeviceIdptr[dbValue];
if ( pConfig->SataClass == RAID_MODE) {
- if ( pConfig->BuildParameters.SataRAID5Ssid != NULL ) {
+ if ( pConfig->BuildParameters.SataRAID5Ssid != 0 ) {
ddTempVar = pConfig->BuildParameters.SataRAID5Ssid;
}
dwDeviceId = V_SB_SATA_RAID5_DID;
@@ -310,19 +310,19 @@ sataInitBeforePciEnum (
getEfuseStatus (&pValue);
if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) {
dwDeviceId = V_SB_SATA_RAID_DID;
- if ( pConfig->BuildParameters.SataRAIDSsid != NULL ) {
+ if ( pConfig->BuildParameters.SataRAIDSsid != 0 ) {
ddTempVar = pConfig->BuildParameters.SataRAIDSsid;
}
}
}
if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) ||
((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) {
- if ( pConfig->BuildParameters.SataAHCISsid != NULL ) {
+ if ( pConfig->BuildParameters.SataAHCISsid != 0 ) {
ddTempVar = pConfig->BuildParameters.SataAHCISsid;
}
}
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId);
- if ( ddTempVar != NULL ) {
+ if ( ddTempVar != 0 ) {
RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar);
}
// SATA IRQ Resource
diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c
index ea1c029d1f..07adf56141 100644
--- a/src/vendorcode/amd/cimx/sb800/SBCMN.c
+++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c
@@ -378,7 +378,7 @@ commonInitEarlyBoot (
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
//Early post initialization of pci config space
programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) );
- if ( pConfig->BuildParameters.SmbusSsid != NULL ) {
+ if ( pConfig->BuildParameters.SmbusSsid != 0 ) {
RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid);
}
//Make BAR registers of smbus invisible.
@@ -388,7 +388,7 @@ commonInitEarlyBoot (
// LPC CFG programming
//
// SSID for LPC Controller
- if (pConfig->BuildParameters.LpcSsid != NULL ) {
+ if (pConfig->BuildParameters.LpcSsid != 0 ) {
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid);
}
// LPC MSI
diff --git a/src/vendorcode/amd/cimx/sb800/SBPOR.c b/src/vendorcode/amd/cimx/sb800/SBPOR.c
index daf13c719c..752c64e5bb 100644
--- a/src/vendorcode/amd/cimx/sb800/SBPOR.c
+++ b/src/vendorcode/amd/cimx/sb800/SBPOR.c
@@ -150,7 +150,7 @@ sbPowerOnInit (
cimNbSbGen2 = pConfig->NbSbGen2;
cimSataMode = pConfig->SATAMODE.SataModeReg;
// Adding Fast Read Function support
- if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) {
+ if (pConfig->BuildParameters.SpiFastReadEnable != 0 ) {
cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
} else {
cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
diff --git a/src/vendorcode/amd/cimx/sb800/USB.c b/src/vendorcode/amd/cimx/sb800/USB.c
index 0918e3acd4..c9e1b24b6a 100644
--- a/src/vendorcode/amd/cimx/sb800/USB.c
+++ b/src/vendorcode/amd/cimx/sb800/USB.c
@@ -196,7 +196,7 @@ EhciInitAfterPciInit (
if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {
//Enable Memory access
RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
- if (pConfig->BuildParameters.EhciSsid != NULL ) {
+ if (pConfig->BuildParameters.EhciSsid != 0 ) {
RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid);
}
//USB Common PHY CAL & Control Register setting
@@ -308,7 +308,7 @@ usb4OhciInitAfterPciInit (
UINT32 ddDeviceId;
ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16);
OhciInitAfterPciInit (ddDeviceId, pConfig);
- if (pConfig->BuildParameters.Ohci4Ssid != NULL ) {
+ if (pConfig->BuildParameters.Ohci4Ssid != 0 ) {
RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid);
}
}
@@ -327,7 +327,7 @@ OhciInitAfterPciInit (
// SB02186
RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, 0xFC, 0x00);
if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {
- if ( pConfig->BuildParameters.OhciSsid != NULL ) {
+ if ( pConfig->BuildParameters.OhciSsid != 0 ) {
RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid);
}
}
diff --git a/src/vendorcode/amd/cimx/sb900/Azalia.c b/src/vendorcode/amd/cimx/sb900/Azalia.c
index 3fe4647aab..7a1277cbe5 100644
--- a/src/vendorcode/amd/cimx/sb900/Azalia.c
+++ b/src/vendorcode/amd/cimx/sb900/Azalia.c
@@ -282,7 +282,7 @@ azaliaInitAfterPciEnum (
if ( pConfig->AzaliaController != 1 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
- if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {
+ if ( pConfig->BuildParameters.AzaliaSsid != 0 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
}
ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
diff --git a/src/vendorcode/amd/cimx/sb900/Gec.c b/src/vendorcode/amd/cimx/sb900/Gec.c
index cfd830d0f3..4afd6e981d 100644
--- a/src/vendorcode/amd/cimx/sb900/Gec.c
+++ b/src/vendorcode/amd/cimx/sb900/Gec.c
@@ -109,7 +109,7 @@ gecInitAfterPciEnum (
VOID* GecRomAddress;
VOID* GecShadowRomAddress;
UINT32 ddTemp;
- if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) {
+ if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) {
GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr;
GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase;
AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
diff --git a/src/vendorcode/amd/cimx/sb900/Sata.c b/src/vendorcode/amd/cimx/sb900/Sata.c
index fca8005ee0..5c3a621bb4 100644
--- a/src/vendorcode/amd/cimx/sb900/Sata.c
+++ b/src/vendorcode/amd/cimx/sb900/Sata.c
@@ -458,7 +458,7 @@ sataInitBeforePciEnum (
//Set PATA controller to native mode
RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
}
- if (pConfig->BuildParameters.IdeSsid != NULL ) {
+ if (pConfig->BuildParameters.IdeSsid != 0 ) {
RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid);
}
// SATA Controller Class ID & SSID
diff --git a/src/vendorcode/amd/cimx/sb900/SbCmn.c b/src/vendorcode/amd/cimx/sb900/SbCmn.c
index 29f6fd1d80..bd50ddeb22 100644
--- a/src/vendorcode/amd/cimx/sb900/SbCmn.c
+++ b/src/vendorcode/amd/cimx/sb900/SbCmn.c
@@ -398,7 +398,7 @@ commonInitEarlyBoot (
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
//Early post initialization of pci config space
programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) );
- if ( pConfig->BuildParameters.SmbusSsid != NULL ) {
+ if ( pConfig->BuildParameters.SmbusSsid != 0 ) {
RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid);
}
//Make BAR registers of smbus invisible.
@@ -408,7 +408,7 @@ commonInitEarlyBoot (
// LPC CFG programming
//
// SSID for LPC Controller
- if (pConfig->BuildParameters.LpcSsid != NULL ) {
+ if (pConfig->BuildParameters.LpcSsid != 0 ) {
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid);
}
// LPC MSI
diff --git a/src/vendorcode/amd/cimx/sb900/Usb.c b/src/vendorcode/amd/cimx/sb900/Usb.c
index 2ae03b3f6d..2d635ec9ee 100644
--- a/src/vendorcode/amd/cimx/sb900/Usb.c
+++ b/src/vendorcode/amd/cimx/sb900/Usb.c
@@ -357,7 +357,7 @@ EhciInitAfterPciInit (
if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {
//Enable Memory access
RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
- if (pConfig->BuildParameters.EhciSsid != NULL ) {
+ if (pConfig->BuildParameters.EhciSsid != 0 ) {
RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid);
}
//USB Common PHY CAL & Control Register setting
@@ -571,7 +571,7 @@ usb4OhciInitAfterPciInit (
UINT32 ddDeviceId;
ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16);
OhciInitAfterPciInit (ddDeviceId, pConfig);
- if (pConfig->BuildParameters.Ohci4Ssid != NULL ) {
+ if (pConfig->BuildParameters.Ohci4Ssid != 0 ) {
RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid);
}
}
@@ -595,7 +595,7 @@ OhciInitAfterPciInit (
// RPR USB SMI Handshake
RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00);
if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {
- if ( pConfig->BuildParameters.OhciSsid != NULL ) {
+ if ( pConfig->BuildParameters.OhciSsid != 0 ) {
RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid);
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-20 01:27:06 +0000