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-rw-r--r--src/vendorcode/amd/fsp/picasso/FspmUpd.h42
1 files changed, 21 insertions, 21 deletions
diff --git a/src/vendorcode/amd/fsp/picasso/FspmUpd.h b/src/vendorcode/amd/fsp/picasso/FspmUpd.h
index 56e1a5ea1b..960d0b4eb3 100644
--- a/src/vendorcode/amd/fsp/picasso/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/picasso/FspmUpd.h
@@ -18,33 +18,33 @@ typedef struct __packed {
/** Offset 0x004C**/ uint32_t serial_port_stride;
/** Offset 0x0050**/ uint32_t serial_port_baudrate;
/** Offset 0x0054**/ uint32_t serial_port_refclk;
- /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope;
- /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2;
- /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3;
- /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4;
- /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5;
+ /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope_mA;
+ /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2_mA;
+ /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3_mA;
+ /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4_mA;
+ /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5_mA;
/** Offset 0x006C**/ uint32_t telemetry_vddcr_vdd_offset;
- /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope;
+ /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope_mA;
/** Offset 0x0074**/ uint32_t telemetry_vddcr_soc_offset;
/** Offset 0x0078**/ uint8_t aa_mode_en;
/** Offset 0x0079**/ uint8_t unused2;
/** Offset 0x007A**/ uint8_t unused3;
/** Offset 0x007B**/ uint8_t unused4;
- /** Offset 0x007C**/ uint32_t fast_ppt_limit;
- /** Offset 0x0080**/ uint32_t slow_ppt_limit;
- /** Offset 0x0084**/ uint32_t slow_ppt_time_constant;
- /** Offset 0x0088**/ uint32_t psi0_current_limit;
- /** Offset 0x008C**/ uint32_t psi0_soc_current_limit;
- /** Offset 0x0090**/ uint32_t thermctl_limit;
- /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit;
- /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit;
- /** Offset 0x009C**/ uint32_t sustained_power_limit;
- /** Offset 0x00A0**/ uint32_t stapm_time_constant;
- /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time;
- /** Offset 0x00A8**/ uint32_t vrm_current_limit;
- /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit;
- /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin;
- /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin;
+ /** Offset 0x007C**/ uint32_t fast_ppt_limit_mW;
+ /** Offset 0x0080**/ uint32_t slow_ppt_limit_mW;
+ /** Offset 0x0084**/ uint32_t slow_ppt_time_constant_s;
+ /** Offset 0x0088**/ uint32_t psi0_current_limit_mA;
+ /** Offset 0x008C**/ uint32_t psi0_soc_current_limit_mA;
+ /** Offset 0x0090**/ uint32_t thermctl_limit_degreeC;
+ /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit_mA;
+ /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit_mA;
+ /** Offset 0x009C**/ uint32_t sustained_power_limit_mW;
+ /** Offset 0x00A0**/ uint32_t stapm_time_constant_s;
+ /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time_ms;
+ /** Offset 0x00A8**/ uint32_t vrm_current_limit_mA;
+ /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit_mA;
+ /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin_mV;
+ /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin_mV;
/** Offset 0x00B8**/ uint32_t smu_feature_control_defines;
/** Offset 0x00BC**/ uint32_t smu_feature_control_defines_ext;
/** Offset 0x00C0**/ uint8_t sb_tsi_alert_comparator_mode_en;