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-rw-r--r--src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat2
-rw-r--r--src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat2
-rw-r--r--src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat2
-rw-r--r--src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat2
4 files changed, 0 insertions, 8 deletions
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat
index 267673aed6..34172121f5 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat
+++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat
@@ -40,8 +40,6 @@ smm_region
smm_region_size
soc_after_ram_init
soc_display_memory_init_params
-soc_display_mtrrs
-soc_get_variable_mtrr_count
soc_memory_init_params
soc_pre_ram_init
southbridge_smi_handler
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat
index 70f204db04..08351907c7 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat
+++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat
@@ -23,8 +23,6 @@ platform_segment_loaded
save_chromeos_gpios
soc_after_ram_init
soc_display_memory_init_params
-soc_display_mtrrs
-soc_get_variable_mtrr_count
soc_memory_init_params
soc_pre_ram_init
southbridge_smi_handler
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat
index 2124f0f2e5..0910152c89 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat
+++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat
@@ -22,8 +22,6 @@ map_oprom_vendev
platform_prog_run
platform_segment_loaded
save_chromeos_gpios
-soc_display_mtrrs
-soc_get_variable_mtrr_count
stage_cache_add
stage_cache_load_stage
timestamp_get
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat
index f589eaa919..fe1f0d9d2e 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat
+++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat
@@ -9,8 +9,6 @@ mainboard_check_ec_image
mainboard_post
platform_prog_run
platform_segment_loaded
-soc_display_mtrrs
-soc_get_variable_mtrr_count
stage_cache_add
stage_cache_load_stage
timestamp_get