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-rw-r--r--src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h60
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h41
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h91
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h2
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h41
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h4
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h67
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h2
8 files changed, 200 insertions, 108 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
index 883d509bca..31472b2c2e 100644
--- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
@@ -206,8 +206,6 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
#define OPTION_SW_DRAM_INIT TRUE
#undef OPTION_S3_MEM_SUPPORT
#define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_GFX_RECOVERY
- #define OPTION_GFX_RECOVERY TRUE
#undef OPTION_C6_STATE
#define OPTION_C6_STATE TRUE
#undef OPTION_CPB
@@ -238,7 +236,7 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
#define OPTION_ACPI_PSTATES TRUE
#define OPTION_WHEA TRUE
-#define OPTION_DMI TRUE
+#define OPTION_DMI FALSE
#define OPTION_EARLY_SAMPLES FALSE
#define CFG_ACPI_PSTATES_PPC TRUE
#define CFG_ACPI_PSTATES_PCT TRUE
@@ -246,7 +244,7 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
#define CFG_ACPI_PSTATES_PSS TRUE
#define CFG_ACPI_PSTATES_XPSS TRUE
#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
-#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE TRUE
#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
#define OPTION_ALIB TRUE
/*---------------------------------------------------------------------------
@@ -312,10 +310,11 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
#define OPTION_PARALLEL_TRAINING FALSE
#endif
#endif
-#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
- #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+/* Originally BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT
+ #if BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT == TRUE
#undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE FALSE
+ #define OPTION_ONLINE_SPARE TRUE
#endif
#endif
#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
@@ -348,10 +347,11 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
#define OPTION_WHEA FALSE
#endif
#endif
-#ifdef BLDOPT_REMOVE_DMI
- #if BLDOPT_REMOVE_DMI == TRUE
+/* Originally BLDOPT_REMOVE_DMI, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_DMI
+ #if BLDOPT_ENABLE_DMI == TRUE
#undef OPTION_DMI
- #define OPTION_DMI FALSE
+ #define OPTION_DMI TRUE
#endif
#endif
#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
@@ -389,10 +389,11 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
#endif
#endif
-#ifdef BLDOPT_REMOVE_GFX_RECOVERY
- #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
+/* Originally BLDOPT_REMOVE_GFX_RECOVERY, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_GFX_RECOVERY
+ #if BLDOPT_ENABLE_GFX_RECOVERY == TRUE
#undef OPTION_GFX_RECOVERY
- #define OPTION_GFX_RECOVERY FALSE
+ #define OPTION_GFX_RECOVERY TRUE
#endif
#endif
@@ -438,10 +439,11 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
#endif
#endif
-#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
- #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+/* Originally BLDCFG_VRM_HIGH_SPEED_ENABLE, but inverted alongside the default value */
+#ifdef BLDCFG_VRM_HIGH_SPEED_DISABLE
+ #if BLDCFG_VRM_HIGH_SPEED_DISABLE == TRUE
#undef CFG_VRM_HIGH_SPEED_ENABLE
- #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
+ #define CFG_VRM_HIGH_SPEED_ENABLE FALSE
#endif
#endif
@@ -571,13 +573,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_VRM_CURRENT_LIMIT
#define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
#else
- #define CFG_VRM_CURRENT_LIMIT 0
+ #define CFG_VRM_CURRENT_LIMIT 24000
#endif
#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
#define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
#else
- #define CFG_VRM_LOW_POWER_THRESHOLD 0
+ #define CFG_VRM_LOW_POWER_THRESHOLD 24000
#endif
#ifdef BLDCFG_VRM_SLEW_RATE
@@ -589,7 +591,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
#define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT
#else
- #define CFG_VRM_INRUSH_CURRENT_LIMIT 0
+ #define CFG_VRM_INRUSH_CURRENT_LIMIT (6000)
#endif
#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
@@ -626,7 +628,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_PLAT_NUM_IO_APICS
#define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
#else
- #define CFG_PLAT_NUM_IO_APICS 0
+ #define CFG_PLAT_NUM_IO_APICS 3
#endif
#ifdef BLDCFG_MEM_INIT_PSTATE
@@ -662,19 +664,19 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_PLATFORM_CSTATE_MODE
#define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
#else
- #define CFG_CSTATE_MODE CStateModeDisabled
+ #define CFG_CSTATE_MODE CStateModeC6
#endif
#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
#define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
#else
- #define CFG_CSTATE_OPDATA 0
+ #define CFG_CSTATE_OPDATA 0x840
#endif
#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
#define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
#else
- #define CFG_CSTATE_IO_BASE_ADDRESS 0
+ #define CFG_CSTATE_IO_BASE_ADDRESS 0x840
#endif
#ifdef BLDCFG_PLATFORM_CPB_MODE
@@ -686,7 +688,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_CORE_LEVELING_MODE
#define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
#else
- #define CFG_CORE_LEVELING_MODE 0
+ #define CFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
#endif
#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
@@ -704,7 +706,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
#define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
#else
- #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
+ #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY
#endif
#ifdef BLDCFG_MEMORY_MODE_UNGANGED
@@ -770,13 +772,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_MEMORY_POWER_DOWN
#define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
#else
- #define CFG_MEMORY_POWER_DOWN FALSE
+ #define CFG_MEMORY_POWER_DOWN TRUE
#endif
#ifdef BLDCFG_POWER_DOWN_MODE
#define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
#else
- #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
+ #define CFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
#endif
#ifdef BLDCFG_ONLINE_SPARE
@@ -806,7 +808,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_MEMORY_CLOCK_SELECT
#define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
#else
- #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
+ #define CFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
#endif
#ifdef BLDCFG_DQS_TRAINING_CONTROL
@@ -878,7 +880,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_ECC_SYNC_FLOOD
#define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
#else
- #define CFG_ECC_SYNC_FLOOD 0
+ #define CFG_ECC_SYNC_FLOOD FALSE
#endif
#ifdef BLDCFG_ECC_SYMBOL_SIZE
diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h
index 4a8237a210..5ea5fd1595 100644
--- a/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h
@@ -48,6 +48,47 @@
#define FCH_SUPPORT FALSE
#endif
+/* Define the default values for the FCH configuration settings */
+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
+/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS 0xFED00000
+#define DFLT_SMI_CMD_PORT 0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+#define DFLT_GEC_BASE_ADDRESS 0xFED61000
+#define DFLT_AZALIA_SSID 0x780D1022
+#define DFLT_SMBUS_SSID 0x780B1022
+#define DFLT_IDE_SSID 0x780C1022
+#define DFLT_SATA_AHCI_SSID 0x78011022
+#define DFLT_SATA_IDE_SSID 0x78001022
+#define DFLT_SATA_RAID5_SSID 0x78031022
+#define DFLT_SATA_RAID_SSID 0x78021022
+#define DFLT_EHCI_SSID 0x78081022
+#define DFLT_OHCI_SSID 0x78071022
+#define DFLT_LPC_SSID 0x780E1022
+#define DFLT_SD_SSID 0x78061022
+#define DFLT_XHCI_SSID 0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+
+#define DFLT_FCH_GPP_LINK_CONFIG PortA4
+#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
+
+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
/* ACPI block register offset definitions */
#define PM1_STATUS_OFFSET 0x00
diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
index 1bca388000..8bdbb92165 100644
--- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
@@ -424,6 +424,7 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define OPTION_NODE_INTERLEAVE FALSE
#define OPTION_PARALLEL_TRAINING FALSE
#define OPTION_ONLINE_SPARE FALSE
+#define OPTION_ONLINE_SPARE_CAPABLE FALSE
#define OPTION_MEM_RESTORE FALSE
#define OPTION_DIMM_EXCLUDE FALSE
@@ -503,8 +504,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define OPTION_PARALLEL_TRAINING TRUE
#undef OPTION_MEM_RESTORE
#define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
+ #undef OPTION_ONLINE_SPARE_CAPABLE
+ #define OPTION_ONLINE_SPARE_CAPABLE TRUE
#undef OPTION_DIMM_EXCLUDE
#define OPTION_DIMM_EXCLUDE TRUE
#endif
@@ -579,8 +580,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define OPTION_NODE_INTERLEAVE TRUE
#undef OPTION_MEM_RESTORE
#define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
+ #undef OPTION_ONLINE_SPARE_CAPABLE
+ #define OPTION_ONLINE_SPARE_CAPABLE TRUE
#undef OPTION_DIMM_EXCLUDE
#define OPTION_DIMM_EXCLUDE TRUE
#endif
@@ -640,8 +641,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define OPTION_PARALLEL_TRAINING TRUE
#undef OPTION_MEM_RESTORE
#define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
+ #undef OPTION_ONLINE_SPARE_CAPABLE
+ #define OPTION_ONLINE_SPARE_CAPABLE TRUE
#undef OPTION_DIMM_EXCLUDE
#define OPTION_DIMM_EXCLUDE TRUE
#endif
@@ -718,8 +719,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define OPTION_NODE_INTERLEAVE TRUE
#undef OPTION_MEM_RESTORE
#define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
+ #undef OPTION_ONLINE_SPARE_CAPABLE
+ #define OPTION_ONLINE_SPARE_CAPABLE TRUE
#undef OPTION_DIMM_EXCLUDE
#define OPTION_DIMM_EXCLUDE TRUE
#endif
@@ -767,8 +768,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define OPTION_PARALLEL_TRAINING TRUE
#undef OPTION_MEM_RESTORE
#define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
+ #undef OPTION_ONLINE_SPARE_CAPABLE
+ #define OPTION_ONLINE_SPARE_CAPABLE TRUE
#undef OPTION_DIMM_EXCLUDE
#define OPTION_DIMM_EXCLUDE TRUE
#endif
@@ -1123,8 +1124,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define OPTION_DCT_INTERLEAVE TRUE
#undef OPTION_MEM_RESTORE
#define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
+ #undef OPTION_ONLINE_SPARE_CAPABLE
+ #define OPTION_ONLINE_SPARE_CAPABLE TRUE
#undef OPTION_DIMM_EXCLUDE
#define OPTION_DIMM_EXCLUDE TRUE
#endif
@@ -1301,8 +1302,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define OPTION_PARALLEL_TRAINING TRUE
#undef OPTION_MEM_RESTORE
#define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
+ #undef OPTION_ONLINE_SPARE_CAPABLE
+ #define OPTION_ONLINE_SPARE_CAPABLE TRUE
#undef OPTION_DIMM_EXCLUDE
#define OPTION_DIMM_EXCLUDE TRUE
#endif
@@ -1367,8 +1368,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define OPTION_NODE_INTERLEAVE TRUE
#undef OPTION_MEM_RESTORE
#define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
+ #undef OPTION_ONLINE_SPARE_CAPABLE
+ #define OPTION_ONLINE_SPARE_CAPABLE TRUE
#undef OPTION_DIMM_EXCLUDE
#define OPTION_DIMM_EXCLUDE TRUE
#endif
@@ -1384,7 +1385,7 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define OPTION_ACPI_PSTATES TRUE
#define OPTION_WHEA TRUE
-#define OPTION_DMI TRUE
+#define OPTION_DMI FALSE
#define OPTION_EARLY_SAMPLES FALSE
#define CFG_ACPI_PSTATES_PPC TRUE
#define CFG_ACPI_PSTATES_PCT TRUE
@@ -1392,7 +1393,7 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define CFG_ACPI_PSTATES_PSS TRUE
#define CFG_ACPI_PSTATES_XPSS TRUE
#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
-#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE TRUE
#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
#define OPTION_ALIB TRUE
/*---------------------------------------------------------------------------
@@ -1464,10 +1465,11 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define OPTION_PARALLEL_TRAINING FALSE
#endif
#endif
-#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
- #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+/* Originally BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT
+ #if BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT == TRUE
#undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE FALSE
+ #define OPTION_ONLINE_SPARE OPTION_ONLINE_SPARE_CAPABLE
#endif
#endif
#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
@@ -1506,10 +1508,11 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define OPTION_WHEA FALSE
#endif
#endif
-#ifdef BLDOPT_REMOVE_DMI
- #if BLDOPT_REMOVE_DMI == TRUE
+/* Originally BLDOPT_REMOVE_DMI, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_DMI
+ #if BLDOPT_ENABLE_DMI == TRUE
#undef OPTION_DMI
- #define OPTION_DMI FALSE
+ #define OPTION_DMI TRUE
#endif
#endif
#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
@@ -1611,10 +1614,11 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#endif
#endif
-#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
- #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+/* Originally BLDCFG_VRM_HIGH_SPEED_ENABLE, but inverted alongside the default value */
+#ifdef BLDCFG_VRM_HIGH_SPEED_DISABLE
+ #if BLDCFG_VRM_HIGH_SPEED_DISABLE == TRUE
#undef CFG_VRM_HIGH_SPEED_ENABLE
- #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
+ #define CFG_VRM_HIGH_SPEED_ENABLE FALSE
#endif
#endif
@@ -1762,7 +1766,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_VRM_CURRENT_LIMIT
#define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
#else
- #define CFG_VRM_CURRENT_LIMIT 0
+ #define CFG_VRM_CURRENT_LIMIT 90000
#endif
#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
@@ -1824,7 +1828,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
#define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
#else
- #define CFG_VRM_NB_CURRENT_LIMIT (0)
+ #define CFG_VRM_NB_CURRENT_LIMIT (60000)
#endif
#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
@@ -1842,7 +1846,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_PLAT_NUM_IO_APICS
#define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
#else
- #define CFG_PLAT_NUM_IO_APICS 0
+ #define CFG_PLAT_NUM_IO_APICS 3
#endif
#ifdef BLDCFG_MEM_INIT_PSTATE
@@ -1896,19 +1900,19 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
#define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
#else
- #define CFG_CSTATE_IO_BASE_ADDRESS 0
+ #define CFG_CSTATE_IO_BASE_ADDRESS 0x1770
#endif
#ifdef BLDCFG_PLATFORM_CPB_MODE
#define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
#else
- #define CFG_CPB_MODE CpbModeAuto
+ #define CFG_CPB_MODE CpbModeDisabled
#endif
#ifdef BLDCFG_CORE_LEVELING_MODE
#define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
#else
- #define CFG_CORE_LEVELING_MODE 0
+ #define CFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
#endif
#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
@@ -1926,7 +1930,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
#define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
#else
- #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
+ #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
#endif
#ifdef BLDCFG_MEMORY_MODE_UNGANGED
@@ -1998,13 +2002,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_MEMORY_POWER_DOWN
#define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
#else
- #define CFG_MEMORY_POWER_DOWN FALSE
+ #define CFG_MEMORY_POWER_DOWN TRUE
#endif
#ifdef BLDCFG_POWER_DOWN_MODE
#define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
#else
- #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
+ #define CFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
#endif
#ifdef BLDCFG_ONLINE_SPARE
@@ -2034,7 +2038,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_MEMORY_CLOCK_SELECT
#define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
#else
- #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
+ #define CFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
#endif
#ifdef BLDCFG_DQS_TRAINING_CONTROL
@@ -2112,7 +2116,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_ECC_SYMBOL_SIZE
#define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
#else
- #define CFG_ECC_SYMBOL_SIZE 0
+ #define CFG_ECC_SYMBOL_SIZE 4
#endif
#ifdef BLDCFG_1GB_ALIGN
@@ -2148,7 +2152,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_UMA_ALIGNMENT
#define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
#else
- #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
+ #define CFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#endif
#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
@@ -2208,7 +2212,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
#define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
#else
- #define CFG_LCD_BACK_LIGHT_CONTROL 0
+ #define CFG_LCD_BACK_LIGHT_CONTROL 200
#endif
#ifdef BLDCFG_STEREO_3D_PINOUT
@@ -2273,10 +2277,11 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
#endif
+/* PCIe Spread Spectrum default value: 0.36% */
#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
#define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
#else
- #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
+ #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 36
#endif
#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
@@ -2348,13 +2353,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
#define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
#else
- #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0
+ #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#endif
#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
#define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
#else
- #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0
+ #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
#endif
#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h
index 3e5137c655..a965a1d7d9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h
@@ -236,7 +236,7 @@ CpuLateInitApTask (
#endif
#define SCOPE_NAME_VALUE OEM_SCOPE_NAME
#else
- #define SCOPE_NAME_VALUE SCOPE_NAME_C
+ #define SCOPE_NAME_VALUE SCOPE_NAME_P
#endif // OEM_SCOPE_NAME
#ifdef OEM_SCOPE_NAME1
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h
index 4725504159..64b71ef713 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h
@@ -48,6 +48,47 @@
#define FCH_SUPPORT FALSE
#endif
+/* Define the default values for the FCH configuration settings */
+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
+/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS 0xFED00000
+#define DFLT_SMI_CMD_PORT 0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+#define DFLT_GEC_BASE_ADDRESS 0xFED61000
+#define DFLT_AZALIA_SSID 0x780D1022
+#define DFLT_SMBUS_SSID 0x780B1022
+#define DFLT_IDE_SSID 0x780C1022
+#define DFLT_SATA_AHCI_SSID 0x78011022
+#define DFLT_SATA_IDE_SSID 0x78001022
+#define DFLT_SATA_RAID5_SSID 0x78031022
+#define DFLT_SATA_RAID_SSID 0x78021022
+#define DFLT_EHCI_SSID 0x78081022
+#define DFLT_OHCI_SSID 0x78071022
+#define DFLT_LPC_SSID 0x780E1022
+#define DFLT_SD_SSID 0x78061022
+#define DFLT_XHCI_SSID 0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+
+#define DFLT_FCH_GPP_LINK_CONFIG PortA4
+#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
+
+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
/* ACPI block register offset definitions */
#define PM1_STATUS_OFFSET 0x00
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h
index a648cc4ec3..7b1447199a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h
@@ -160,7 +160,7 @@
#ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
#define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM
#else
- #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard
+ #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
#endif
#ifndef CFG_GNB_FORCE_CABLESAFE_OFF
@@ -871,7 +871,7 @@
#if (AGESA_ENTRY_INIT_S3SAVE == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_INIT_SVIEW
- #define OPTION_GFX_INIT_SVIEW TRUE
+ #define OPTION_GFX_INIT_SVIEW FALSE
#endif
#if (OPTION_GFX_INIT_SVIEW == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GfxInitSview;
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h
index 686dfb153a..4606443632 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h
@@ -310,7 +310,7 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define OPTION_ACPI_PSTATES TRUE
#define OPTION_WHEA TRUE
-#define OPTION_DMI TRUE
+#define OPTION_DMI FALSE
#define OPTION_EARLY_SAMPLES FALSE
#define CFG_ACPI_PSTATES_PPC TRUE
#define CFG_ACPI_PSTATES_PCT TRUE
@@ -318,7 +318,7 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define CFG_ACPI_PSTATES_PSS TRUE
#define CFG_ACPI_PSTATES_XPSS TRUE
#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
-#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE TRUE
#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
#define OPTION_ALIB TRUE
/*---------------------------------------------------------------------------
@@ -393,10 +393,11 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define OPTION_PARALLEL_TRAINING FALSE
#endif
#endif
-#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
- #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+/* Originally BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT
+ #if BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT == TRUE
#undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE FALSE
+ #define OPTION_ONLINE_SPARE TRUE
#endif
#endif
#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
@@ -447,10 +448,11 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define OPTION_WHEA FALSE
#endif
#endif
-#ifdef BLDOPT_REMOVE_DMI
- #if BLDOPT_REMOVE_DMI == TRUE
+/* Originally BLDOPT_REMOVE_DMI, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_DMI
+ #if BLDOPT_ENABLE_DMI == TRUE
#undef OPTION_DMI
- #define OPTION_DMI FALSE
+ #define OPTION_DMI TRUE
#endif
#endif
#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
@@ -601,10 +603,11 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define CFG_ACPI_PSTATES_PSD_POLICY PsdPolicyProcessorDefault
#endif
-#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
- #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+/* Originally BLDCFG_VRM_HIGH_SPEED_ENABLE, but inverted alongside the default value */
+#ifdef BLDCFG_VRM_HIGH_SPEED_DISABLE
+ #if BLDCFG_VRM_HIGH_SPEED_DISABLE == TRUE
#undef CFG_VRM_HIGH_SPEED_ENABLE
- #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
+ #define CFG_VRM_HIGH_SPEED_ENABLE FALSE
#endif
#endif
@@ -752,7 +755,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_VRM_CURRENT_LIMIT
#define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
#else
- #define CFG_VRM_CURRENT_LIMIT 0
+ #define CFG_VRM_CURRENT_LIMIT 15000
#endif
#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
@@ -764,37 +767,37 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_VRM_SLEW_RATE
#define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
#else
- #define CFG_VRM_SLEW_RATE (5000)
+ #define CFG_VRM_SLEW_RATE (10000)
#endif
#ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
#define CFG_VRM_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
#else
- #define CFG_VRM_MAXIMUM_CURRENT_LIMIT (0)
+ #define CFG_VRM_MAXIMUM_CURRENT_LIMIT (21000)
#endif
#ifdef BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
#define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
#else
- #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT (0)
+ #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT (17000)
#endif
#ifdef BLDCFG_VRM_SVI_OCP_LEVEL
#define CFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_SVI_OCP_LEVEL
#else
- #define CFG_VRM_SVI_OCP_LEVEL 0
+ #define CFG_VRM_SVI_OCP_LEVEL CFG_VRM_MAXIMUM_CURRENT_LIMIT
#endif
#ifdef BLDCFG_VRM_NB_SVI_OCP_LEVEL
#define CFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_SVI_OCP_LEVEL
#else
- #define CFG_VRM_NB_SVI_OCP_LEVEL 0
+ #define CFG_VRM_NB_SVI_OCP_LEVEL CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
#endif
#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
#define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
#else
- #define CFG_VRM_NB_CURRENT_LIMIT (0)
+ #define CFG_VRM_NB_CURRENT_LIMIT (13000)
#endif
#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
@@ -806,13 +809,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_VRM_NB_SLEW_RATE
#define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
#else
- #define CFG_VRM_NB_SLEW_RATE (5000)
+ #define CFG_VRM_NB_SLEW_RATE CFG_VRM_SLEW_RATE
#endif
#ifdef BLDCFG_PLAT_NUM_IO_APICS
#define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
#else
- #define CFG_PLAT_NUM_IO_APICS 0
+ #define CFG_PLAT_NUM_IO_APICS 3
#endif
#ifdef BLDCFG_MEM_INIT_PSTATE
@@ -854,19 +857,19 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_PLATFORM_CSTATE_MODE
#define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
#else
- #define CFG_CSTATE_MODE CStateModeC6
+ #define CFG_CSTATE_MODE CStateModeDisabled
#endif
#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
#define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
#else
- #define CFG_CSTATE_OPDATA 0
+ #define CFG_CSTATE_OPDATA 0x1770
#endif
#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
#define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
#else
- #define CFG_CSTATE_IO_BASE_ADDRESS 0
+ #define CFG_CSTATE_IO_BASE_ADDRESS 0x1770
#endif
#ifdef BLDCFG_PLATFORM_CPB_MODE
@@ -878,7 +881,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_CORE_LEVELING_MODE
#define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
#else
- #define CFG_CORE_LEVELING_MODE 0
+ #define CFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
#endif
#ifdef BLDCFG_AMD_TDP_LIMIT
@@ -896,7 +899,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
#define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
#else
- #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
+ #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
#endif
#ifdef BLDCFG_MEMORY_MODE_UNGANGED
@@ -968,13 +971,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_MEMORY_POWER_DOWN
#define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
#else
- #define CFG_MEMORY_POWER_DOWN FALSE
+ #define CFG_MEMORY_POWER_DOWN TRUE
#endif
#ifdef BLDCFG_POWER_DOWN_MODE
#define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
#else
- #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
+ #define CFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
#endif
#ifdef BLDCFG_ONLINE_SPARE
@@ -1004,7 +1007,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_MEMORY_CLOCK_SELECT
#define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
#else
- #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
+ #define CFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
#endif
#ifdef BLDCFG_DQS_TRAINING_CONTROL
@@ -1082,7 +1085,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_ECC_SYMBOL_SIZE
#define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
#else
- #define CFG_ECC_SYMBOL_SIZE 0
+ #define CFG_ECC_SYMBOL_SIZE 4
#endif
#ifdef BLDCFG_1GB_ALIGN
@@ -1118,7 +1121,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_UMA_ALIGNMENT
#define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
#else
- #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
+ #define CFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#endif
#ifdef BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
@@ -1172,7 +1175,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_CFG_ABM_SUPPORT
#define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
#else
- #define CFG_ABM_SUPPORT FALSE
+ #define CFG_ABM_SUPPORT TRUE
#endif
#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
@@ -1468,7 +1471,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_GNB_IOAPIC_ADDRESS
#define CFG_GNB_IOAPIC_ADDRESS BLDCFG_GNB_IOAPIC_ADDRESS
#else
- #define CFG_GNB_IOAPIC_ADDRESS NULL
+ #define CFG_GNB_IOAPIC_ADDRESS 0xFEC20000
#endif
#ifdef BLDCFG_GNB_IOMMU_ADDRESS
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h
index b27ed00057..00ea0d7e9b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h
@@ -229,7 +229,7 @@ AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE);
#endif
#define SCOPE_NAME_VALUE OEM_SCOPE_NAME
#else
- #define SCOPE_NAME_VALUE SCOPE_NAME_C
+ #define SCOPE_NAME_VALUE SCOPE_NAME_P
#endif // OEM_SCOPE_NAME
#ifdef OEM_SCOPE_NAME1