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-rw-r--r--src/mainboard/amd/dbm690t/Kconfig51
-rw-r--r--src/mainboard/amd/dbm690t/Kconfig.name2
-rw-r--r--src/mainboard/amd/dbm690t/acpi/ide.asl240
-rw-r--r--src/mainboard/amd/dbm690t/acpi/routing.asl254
-rw-r--r--src/mainboard/amd/dbm690t/acpi/sata.asl145
-rw-r--r--src/mainboard/amd/dbm690t/acpi/usb.asl157
-rw-r--r--src/mainboard/amd/dbm690t/acpi_tables.c51
-rw-r--r--src/mainboard/amd/dbm690t/board_info.txt3
-rw-r--r--src/mainboard/amd/dbm690t/cmos.layout69
-rw-r--r--src/mainboard/amd/dbm690t/devicetree.cb121
-rw-r--r--src/mainboard/amd/dbm690t/dsdt.asl1674
-rw-r--r--src/mainboard/amd/dbm690t/fadt.c197
-rw-r--r--src/mainboard/amd/dbm690t/get_bus_conf.c109
-rw-r--r--src/mainboard/amd/dbm690t/irq_tables.c107
-rw-r--r--src/mainboard/amd/dbm690t/mainboard.c190
-rw-r--r--src/mainboard/amd/dbm690t/mptable.c111
-rw-r--r--src/mainboard/amd/dbm690t/resourcemap.c274
-rw-r--r--src/mainboard/amd/dbm690t/romstage.c144
-rw-r--r--src/mainboard/amd/mahogany/Kconfig66
-rw-r--r--src/mainboard/amd/mahogany/Kconfig.name2
-rw-r--r--src/mainboard/amd/mahogany/acpi/ide.asl240
-rw-r--r--src/mainboard/amd/mahogany/acpi/routing.asl307
-rw-r--r--src/mainboard/amd/mahogany/acpi/sata.asl145
-rw-r--r--src/mainboard/amd/mahogany/acpi/usb.asl157
-rw-r--r--src/mainboard/amd/mahogany/acpi_tables.c52
-rw-r--r--src/mainboard/amd/mahogany/board_info.txt3
-rw-r--r--src/mainboard/amd/mahogany/cmos.layout69
-rw-r--r--src/mainboard/amd/mahogany/devicetree.cb121
-rw-r--r--src/mainboard/amd/mahogany/dsdt.asl1690
-rw-r--r--src/mainboard/amd/mahogany/get_bus_conf.c109
-rw-r--r--src/mainboard/amd/mahogany/irq_tables.c107
-rw-r--r--src/mainboard/amd/mahogany/mainboard.c77
-rw-r--r--src/mainboard/amd/mahogany/mptable.c112
-rw-r--r--src/mainboard/amd/mahogany/resourcemap.c274
-rw-r--r--src/mainboard/amd/mahogany/romstage.c146
-rw-r--r--src/mainboard/amd/pistachio/Kconfig59
-rw-r--r--src/mainboard/amd/pistachio/Kconfig.name2
-rw-r--r--src/mainboard/amd/pistachio/acpi/ide.asl240
-rw-r--r--src/mainboard/amd/pistachio/acpi/routing.asl254
-rw-r--r--src/mainboard/amd/pistachio/acpi/sata.asl145
-rw-r--r--src/mainboard/amd/pistachio/acpi/usb.asl159
-rw-r--r--src/mainboard/amd/pistachio/acpi_tables.c52
-rw-r--r--src/mainboard/amd/pistachio/board_info.txt1
-rw-r--r--src/mainboard/amd/pistachio/cmos.layout69
-rw-r--r--src/mainboard/amd/pistachio/devicetree.cb80
-rw-r--r--src/mainboard/amd/pistachio/dsdt.asl1695
-rw-r--r--src/mainboard/amd/pistachio/fadt.c197
-rw-r--r--src/mainboard/amd/pistachio/get_bus_conf.c109
-rw-r--r--src/mainboard/amd/pistachio/irq_tables.c107
-rw-r--r--src/mainboard/amd/pistachio/mainboard.c259
-rw-r--r--src/mainboard/amd/pistachio/mptable.c111
-rw-r--r--src/mainboard/amd/pistachio/resourcemap.c274
-rw-r--r--src/mainboard/amd/pistachio/romstage.c156
-rw-r--r--src/mainboard/amd/serengeti_cheetah/Kconfig71
-rw-r--r--src/mainboard/amd/serengeti_cheetah/Kconfig.name2
-rw-r--r--src/mainboard/amd/serengeti_cheetah/Makefile.inc3
-rw-r--r--src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl183
-rw-r--r--src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl191
-rw-r--r--src/mainboard/amd/serengeti_cheetah/acpi/amd8111_pic.asl366
-rw-r--r--src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl130
-rw-r--r--src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl125
-rw-r--r--src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl125
-rw-r--r--src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl41
-rw-r--r--src/mainboard/amd/serengeti_cheetah/acpi/pci0_hc.asl15
-rw-r--r--src/mainboard/amd/serengeti_cheetah/acpi/pci2_hc.asl14
-rw-r--r--src/mainboard/amd/serengeti_cheetah/acpi/pci3_hc.asl14
-rw-r--r--src/mainboard/amd/serengeti_cheetah/acpi/pci4_hc.asl14
-rw-r--r--src/mainboard/amd/serengeti_cheetah/acpi/superio.asl14
-rw-r--r--src/mainboard/amd/serengeti_cheetah/acpi_tables.c192
-rw-r--r--src/mainboard/amd/serengeti_cheetah/board_info.txt1
-rw-r--r--src/mainboard/amd/serengeti_cheetah/cmos.layout52
-rw-r--r--src/mainboard/amd/serengeti_cheetah/devicetree.cb147
-rw-r--r--src/mainboard/amd/serengeti_cheetah/dsdt.asl219
-rw-r--r--src/mainboard/amd/serengeti_cheetah/fadt.c162
-rw-r--r--src/mainboard/amd/serengeti_cheetah/get_bus_conf.c217
-rw-r--r--src/mainboard/amd/serengeti_cheetah/irq_tables.c158
-rw-r--r--src/mainboard/amd/serengeti_cheetah/mainboard.c28
-rw-r--r--src/mainboard/amd/serengeti_cheetah/mainboard.h14
-rw-r--r--src/mainboard/amd/serengeti_cheetah/mb_sysconf.h40
-rw-r--r--src/mainboard/amd/serengeti_cheetah/mptable.c179
-rw-r--r--src/mainboard/amd/serengeti_cheetah/readme_acpi.txt29
-rw-r--r--src/mainboard/amd/serengeti_cheetah/resourcemap.c272
-rw-r--r--src/mainboard/amd/serengeti_cheetah/romstage.c197
-rw-r--r--src/mainboard/amd/serengeti_cheetah/ssdt2.asl79
-rw-r--r--src/mainboard/amd/serengeti_cheetah/ssdt3.asl79
-rw-r--r--src/mainboard/amd/serengeti_cheetah/ssdt4.asl79
-rw-r--r--src/mainboard/asrock/939a785gmh/Kconfig64
-rw-r--r--src/mainboard/asrock/939a785gmh/Kconfig.name2
-rw-r--r--src/mainboard/asrock/939a785gmh/acpi/ide.asl0
-rw-r--r--src/mainboard/asrock/939a785gmh/acpi/routing.asl188
-rw-r--r--src/mainboard/asrock/939a785gmh/acpi/sata.asl0
-rw-r--r--src/mainboard/asrock/939a785gmh/acpi/usb.asl0
-rw-r--r--src/mainboard/asrock/939a785gmh/acpi_tables.c53
-rw-r--r--src/mainboard/asrock/939a785gmh/board_info.txt6
-rw-r--r--src/mainboard/asrock/939a785gmh/cmos.layout69
-rw-r--r--src/mainboard/asrock/939a785gmh/devicetree.cb131
-rw-r--r--src/mainboard/asrock/939a785gmh/dsdt.asl634
-rw-r--r--src/mainboard/asrock/939a785gmh/get_bus_conf.c109
-rw-r--r--src/mainboard/asrock/939a785gmh/irq_tables.c107
-rw-r--r--src/mainboard/asrock/939a785gmh/mainboard.c126
-rw-r--r--src/mainboard/asrock/939a785gmh/mptable.c110
-rw-r--r--src/mainboard/asrock/939a785gmh/resourcemap.c274
-rw-r--r--src/mainboard/asrock/939a785gmh/romstage.c212
-rw-r--r--src/mainboard/asus/a8n_e/Kconfig62
-rw-r--r--src/mainboard/asus/a8n_e/Kconfig.name2
-rw-r--r--src/mainboard/asus/a8n_e/acpi_tables.c71
-rw-r--r--src/mainboard/asus/a8n_e/board_info.txt7
-rw-r--r--src/mainboard/asus/a8n_e/cmos.default11
-rw-r--r--src/mainboard/asus/a8n_e/cmos.layout56
-rw-r--r--src/mainboard/asus/a8n_e/devicetree.cb121
-rw-r--r--src/mainboard/asus/a8n_e/dsdt.asl265
-rw-r--r--src/mainboard/asus/a8n_e/get_bus_conf.c116
-rw-r--r--src/mainboard/asus/a8n_e/irq_tables.c193
-rw-r--r--src/mainboard/asus/a8n_e/mptable.c123
-rw-r--r--src/mainboard/asus/a8n_e/romstage.c150
-rw-r--r--src/mainboard/asus/a8n_sli/Kconfig9
-rw-r--r--src/mainboard/asus/a8n_sli/Kconfig.name2
-rw-r--r--src/mainboard/asus/a8n_sli/board_info.txt7
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/Kconfig60
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/Kconfig.name2
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/acpi_tables.c65
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/board_info.txt6
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/cmos.layout52
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/devicetree.cb97
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/dsdt.asl194
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/mptable.c112
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/romstage.c206
-rw-r--r--src/mainboard/asus/a8v-e_se/Kconfig60
-rw-r--r--src/mainboard/asus/a8v-e_se/Kconfig.name2
-rw-r--r--src/mainboard/asus/a8v-e_se/acpi_tables.c67
-rw-r--r--src/mainboard/asus/a8v-e_se/board_info.txt7
-rw-r--r--src/mainboard/asus/a8v-e_se/cmos.layout52
-rw-r--r--src/mainboard/asus/a8v-e_se/devicetree.cb97
-rw-r--r--src/mainboard/asus/a8v-e_se/dsdt.asl239
-rw-r--r--src/mainboard/asus/a8v-e_se/mptable.c112
-rw-r--r--src/mainboard/asus/a8v-e_se/romstage.c206
-rw-r--r--src/mainboard/asus/k8v-x/Kconfig69
-rw-r--r--src/mainboard/asus/k8v-x/Kconfig.name2
-rw-r--r--src/mainboard/asus/k8v-x/acpi_tables.c67
-rw-r--r--src/mainboard/asus/k8v-x/board_info.txt2
-rw-r--r--src/mainboard/asus/k8v-x/cmos.layout52
-rw-r--r--src/mainboard/asus/k8v-x/devicetree.cb113
-rw-r--r--src/mainboard/asus/k8v-x/dsdt.asl176
-rw-r--r--src/mainboard/asus/k8v-x/irq_tables.c146
-rw-r--r--src/mainboard/asus/k8v-x/mainboard.c55
-rw-r--r--src/mainboard/asus/k8v-x/mptable.c112
-rw-r--r--src/mainboard/asus/k8v-x/romstage.c182
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/Kconfig98
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/Kconfig.name2
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/acpi/pm_ctrl.asl241
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c80
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/board_info.txt6
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/bootblock.c81
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/cmos.default12
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/cmos.layout117
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/devicetree.cb197
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/dsdt.asl947
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c116
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/irq_tables.c180
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/mptable.c153
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/resourcemap.c280
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/romstage.c362
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/spd_notes.txt69
-rw-r--r--src/mainboard/asus/m2n-e/Kconfig77
-rw-r--r--src/mainboard/asus/m2n-e/Kconfig.name2
-rw-r--r--src/mainboard/asus/m2n-e/Makefile.inc17
-rw-r--r--src/mainboard/asus/m2n-e/board_info.txt7
-rw-r--r--src/mainboard/asus/m2n-e/cmos.layout68
-rw-r--r--src/mainboard/asus/m2n-e/devicetree.cb117
-rw-r--r--src/mainboard/asus/m2n-e/fanctl.c60
-rw-r--r--src/mainboard/asus/m2n-e/get_bus_conf.c114
-rw-r--r--src/mainboard/asus/m2n-e/hda_verb.c79
-rw-r--r--src/mainboard/asus/m2n-e/mptable.c102
-rw-r--r--src/mainboard/asus/m2n-e/resourcemap.c277
-rw-r--r--src/mainboard/asus/m2n-e/romstage.c177
-rw-r--r--src/mainboard/asus/m2v-mx_se/Kconfig70
-rw-r--r--src/mainboard/asus/m2v-mx_se/Kconfig.name2
-rw-r--r--src/mainboard/asus/m2v-mx_se/acpi_tables.c68
-rw-r--r--src/mainboard/asus/m2v-mx_se/board_info.txt7
-rw-r--r--src/mainboard/asus/m2v-mx_se/cmos.default11
-rw-r--r--src/mainboard/asus/m2v-mx_se/cmos.layout60
-rw-r--r--src/mainboard/asus/m2v-mx_se/devicetree.cb77
-rw-r--r--src/mainboard/asus/m2v-mx_se/dsdt.asl241
-rw-r--r--src/mainboard/asus/m2v-mx_se/romstage.c183
-rw-r--r--src/mainboard/asus/m2v/Kconfig67
-rw-r--r--src/mainboard/asus/m2v/Kconfig.name2
-rw-r--r--src/mainboard/asus/m2v/acpi_tables.c69
-rw-r--r--src/mainboard/asus/m2v/board_info.txt7
-rw-r--r--src/mainboard/asus/m2v/cmos.layout52
-rw-r--r--src/mainboard/asus/m2v/devicetree.cb75
-rw-r--r--src/mainboard/asus/m2v/dsdt.asl545
-rw-r--r--src/mainboard/asus/m2v/irq_tables.c87
-rw-r--r--src/mainboard/asus/m2v/mainboard.c51
-rw-r--r--src/mainboard/asus/m2v/mptable.c143
-rw-r--r--src/mainboard/asus/m2v/romstage.c279
-rw-r--r--src/mainboard/broadcom/Kconfig16
-rw-r--r--src/mainboard/broadcom/Kconfig.name2
-rw-r--r--src/mainboard/broadcom/blast/Kconfig58
-rw-r--r--src/mainboard/broadcom/blast/Kconfig.name2
-rw-r--r--src/mainboard/broadcom/blast/board_info.txt1
-rw-r--r--src/mainboard/broadcom/blast/cmos.layout52
-rw-r--r--src/mainboard/broadcom/blast/devicetree.cb122
-rw-r--r--src/mainboard/broadcom/blast/get_bus_conf.c109
-rw-r--r--src/mainboard/broadcom/blast/irq_tables.c101
-rw-r--r--src/mainboard/broadcom/blast/mptable.c138
-rw-r--r--src/mainboard/broadcom/blast/resourcemap.c264
-rw-r--r--src/mainboard/broadcom/blast/romstage.c128
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/Kconfig65
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/Kconfig.name2
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/board_info.txt4
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/cmos.layout69
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb92
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c123
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c168
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/mptable.c115
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c278
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/romstage.c194
-rw-r--r--src/mainboard/gigabyte/m57sli/Kconfig74
-rw-r--r--src/mainboard/gigabyte/m57sli/Kconfig.name2
-rw-r--r--src/mainboard/gigabyte/m57sli/Makefile.inc16
-rw-r--r--src/mainboard/gigabyte/m57sli/acpi_tables.c82
-rw-r--r--src/mainboard/gigabyte/m57sli/board_info.txt7
-rw-r--r--src/mainboard/gigabyte/m57sli/cmos.default9
-rw-r--r--src/mainboard/gigabyte/m57sli/cmos.layout69
-rw-r--r--src/mainboard/gigabyte/m57sli/devicetree.cb154
-rw-r--r--src/mainboard/gigabyte/m57sli/dsdt.asl300
-rw-r--r--src/mainboard/gigabyte/m57sli/fanctl.c81
-rw-r--r--src/mainboard/gigabyte/m57sli/get_bus_conf.c120
-rw-r--r--src/mainboard/gigabyte/m57sli/hda_verb.c7
-rw-r--r--src/mainboard/gigabyte/m57sli/irq_tables.c111
-rw-r--r--src/mainboard/gigabyte/m57sli/mptable.c122
-rw-r--r--src/mainboard/gigabyte/m57sli/resourcemap.c278
-rw-r--r--src/mainboard/gigabyte/m57sli/romstage.c210
-rw-r--r--src/mainboard/hp/dl145_g1/Kconfig56
-rw-r--r--src/mainboard/hp/dl145_g1/Kconfig.name2
-rw-r--r--src/mainboard/hp/dl145_g1/acpi/amd8111.asl617
-rw-r--r--src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl155
-rw-r--r--src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl231
-rw-r--r--src/mainboard/hp/dl145_g1/acpi/amd8131.asl101
-rw-r--r--src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl6
-rw-r--r--src/mainboard/hp/dl145_g1/acpi_tables.c82
-rw-r--r--src/mainboard/hp/dl145_g1/board_info.txt7
-rw-r--r--src/mainboard/hp/dl145_g1/cmos.layout52
-rw-r--r--src/mainboard/hp/dl145_g1/devicetree.cb141
-rw-r--r--src/mainboard/hp/dl145_g1/dsdt.asl292
-rw-r--r--src/mainboard/hp/dl145_g1/fadt.c183
-rw-r--r--src/mainboard/hp/dl145_g1/get_bus_conf.c107
-rw-r--r--src/mainboard/hp/dl145_g1/irq_tables.c98
-rw-r--r--src/mainboard/hp/dl145_g1/mb_sysconf.h23
-rw-r--r--src/mainboard/hp/dl145_g1/mptable.c96
-rw-r--r--src/mainboard/hp/dl145_g1/resourcemap.c268
-rw-r--r--src/mainboard/hp/dl145_g1/romstage.c193
-rw-r--r--src/mainboard/hp/dl145_g3/Kconfig64
-rw-r--r--src/mainboard/hp/dl145_g3/Kconfig.name2
-rw-r--r--src/mainboard/hp/dl145_g3/board_info.txt3
-rw-r--r--src/mainboard/hp/dl145_g3/cmos.layout52
-rw-r--r--src/mainboard/hp/dl145_g3/devicetree.cb85
-rw-r--r--src/mainboard/hp/dl145_g3/get_bus_conf.c128
-rw-r--r--src/mainboard/hp/dl145_g3/irq_tables.c49
-rw-r--r--src/mainboard/hp/dl145_g3/mb_sysconf.h37
-rw-r--r--src/mainboard/hp/dl145_g3/mptable.c187
-rw-r--r--src/mainboard/hp/dl145_g3/romstage.c207
-rw-r--r--src/mainboard/iwill/Kconfig16
-rw-r--r--src/mainboard/iwill/Kconfig.name2
-rw-r--r--src/mainboard/iwill/dk8_htx/Kconfig54
-rw-r--r--src/mainboard/iwill/dk8_htx/Kconfig.name2
-rw-r--r--src/mainboard/iwill/dk8_htx/Makefile.inc4
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/amd8111.asl171
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl178
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/amd8111_pic.asl354
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/amd8131.asl119
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl114
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl114
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/amd8151.asl28
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl19
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/pci0_hc.asl2
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/pci2_hc.asl1
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/pci3_hc.asl1
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/pci4_hc.asl1
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/pci5_hc.asl1
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi/superio.asl1
-rw-r--r--src/mainboard/iwill/dk8_htx/acpi_tables.c189
-rw-r--r--src/mainboard/iwill/dk8_htx/board_info.txt3
-rw-r--r--src/mainboard/iwill/dk8_htx/cmos.layout52
-rw-r--r--src/mainboard/iwill/dk8_htx/devicetree.cb117
-rw-r--r--src/mainboard/iwill/dk8_htx/dsdt.asl206
-rw-r--r--src/mainboard/iwill/dk8_htx/fadt.c148
-rw-r--r--src/mainboard/iwill/dk8_htx/get_bus_conf.c217
-rw-r--r--src/mainboard/iwill/dk8_htx/irq_tables.c148
-rw-r--r--src/mainboard/iwill/dk8_htx/mainboard.c17
-rw-r--r--src/mainboard/iwill/dk8_htx/mainboard.h1
-rw-r--r--src/mainboard/iwill/dk8_htx/mb_sysconf.h27
-rw-r--r--src/mainboard/iwill/dk8_htx/mptable.c186
-rw-r--r--src/mainboard/iwill/dk8_htx/resourcemap.c263
-rw-r--r--src/mainboard/iwill/dk8_htx/romstage.c163
-rw-r--r--src/mainboard/iwill/dk8_htx/ssdt2.asl67
-rw-r--r--src/mainboard/iwill/dk8_htx/ssdt3.asl67
-rw-r--r--src/mainboard/iwill/dk8_htx/ssdt4.asl67
-rw-r--r--src/mainboard/iwill/dk8_htx/ssdt5.asl67
-rw-r--r--src/mainboard/kontron/kt690/Kconfig52
-rw-r--r--src/mainboard/kontron/kt690/Kconfig.name2
-rw-r--r--src/mainboard/kontron/kt690/acpi/ide.asl240
-rw-r--r--src/mainboard/kontron/kt690/acpi/routing.asl258
-rw-r--r--src/mainboard/kontron/kt690/acpi/sata.asl145
-rw-r--r--src/mainboard/kontron/kt690/acpi/usb.asl157
-rw-r--r--src/mainboard/kontron/kt690/acpi_tables.c52
-rw-r--r--src/mainboard/kontron/kt690/board_info.txt2
-rw-r--r--src/mainboard/kontron/kt690/cmos.layout69
-rw-r--r--src/mainboard/kontron/kt690/devicetree.cb125
-rw-r--r--src/mainboard/kontron/kt690/dsdt.asl1675
-rw-r--r--src/mainboard/kontron/kt690/fadt.c197
-rw-r--r--src/mainboard/kontron/kt690/get_bus_conf.c109
-rw-r--r--src/mainboard/kontron/kt690/irq_tables.c107
-rw-r--r--src/mainboard/kontron/kt690/mainboard.c190
-rw-r--r--src/mainboard/kontron/kt690/mptable.c110
-rw-r--r--src/mainboard/kontron/kt690/resourcemap.c274
-rw-r--r--src/mainboard/kontron/kt690/romstage.c148
-rw-r--r--src/mainboard/msi/ms7135/Kconfig55
-rw-r--r--src/mainboard/msi/ms7135/Kconfig.name2
-rw-r--r--src/mainboard/msi/ms7135/acpi_tables.c53
-rw-r--r--src/mainboard/msi/ms7135/board_info.txt8
-rw-r--r--src/mainboard/msi/ms7135/cmos.layout65
-rw-r--r--src/mainboard/msi/ms7135/devicetree.cb75
-rw-r--r--src/mainboard/msi/ms7135/dsdt.asl279
-rw-r--r--src/mainboard/msi/ms7135/get_bus_conf.c100
-rw-r--r--src/mainboard/msi/ms7135/irq_tables.c256
-rw-r--r--src/mainboard/msi/ms7135/mptable.c156
-rw-r--r--src/mainboard/msi/ms7135/romstage.c166
-rw-r--r--src/mainboard/msi/ms7260/Kconfig71
-rw-r--r--src/mainboard/msi/ms7260/Kconfig.name2
-rw-r--r--src/mainboard/msi/ms7260/board_info.txt7
-rw-r--r--src/mainboard/msi/ms7260/cmos.layout70
-rw-r--r--src/mainboard/msi/ms7260/devicetree.cb143
-rw-r--r--src/mainboard/msi/ms7260/get_bus_conf.c119
-rw-r--r--src/mainboard/msi/ms7260/hda_verb.c7
-rw-r--r--src/mainboard/msi/ms7260/irq_tables.c105
-rw-r--r--src/mainboard/msi/ms7260/mptable.c107
-rw-r--r--src/mainboard/msi/ms7260/resourcemap.c279
-rw-r--r--src/mainboard/msi/ms7260/romstage.c198
-rw-r--r--src/mainboard/msi/ms9185/Kconfig62
-rw-r--r--src/mainboard/msi/ms9185/Kconfig.name2
-rw-r--r--src/mainboard/msi/ms9185/board_info.txt4
-rw-r--r--src/mainboard/msi/ms9185/cmos.layout52
-rw-r--r--src/mainboard/msi/ms9185/devicetree.cb85
-rw-r--r--src/mainboard/msi/ms9185/get_bus_conf.c130
-rw-r--r--src/mainboard/msi/ms9185/irq_tables.c118
-rw-r--r--src/mainboard/msi/ms9185/mb_sysconf.h33
-rw-r--r--src/mainboard/msi/ms9185/mptable.c161
-rw-r--r--src/mainboard/msi/ms9185/resourcemap.c286
-rw-r--r--src/mainboard/msi/ms9185/romstage.c176
-rw-r--r--src/mainboard/msi/ms9282/Kconfig60
-rw-r--r--src/mainboard/msi/ms9282/Kconfig.name2
-rw-r--r--src/mainboard/msi/ms9282/board_info.txt4
-rw-r--r--src/mainboard/msi/ms9282/cmos.layout52
-rw-r--r--src/mainboard/msi/ms9282/devicetree.cb182
-rw-r--r--src/mainboard/msi/ms9282/get_bus_conf.c123
-rw-r--r--src/mainboard/msi/ms9282/irq_tables.c127
-rw-r--r--src/mainboard/msi/ms9282/mb_sysconf.h29
-rw-r--r--src/mainboard/msi/ms9282/mptable.c126
-rw-r--r--src/mainboard/msi/ms9282/resourcemap.c294
-rw-r--r--src/mainboard/msi/ms9282/romstage.c181
-rw-r--r--src/mainboard/nvidia/Kconfig16
-rw-r--r--src/mainboard/nvidia/Kconfig.name2
-rw-r--r--src/mainboard/nvidia/l1_2pvv/Kconfig75
-rw-r--r--src/mainboard/nvidia/l1_2pvv/Kconfig.name2
-rw-r--r--src/mainboard/nvidia/l1_2pvv/board_info.txt1
-rw-r--r--src/mainboard/nvidia/l1_2pvv/cmos.layout69
-rw-r--r--src/mainboard/nvidia/l1_2pvv/devicetree.cb180
-rw-r--r--src/mainboard/nvidia/l1_2pvv/get_bus_conf.c137
-rw-r--r--src/mainboard/nvidia/l1_2pvv/hda_verb.c68
-rw-r--r--src/mainboard/nvidia/l1_2pvv/irq_tables.c124
-rw-r--r--src/mainboard/nvidia/l1_2pvv/mb_sysconf.h29
-rw-r--r--src/mainboard/nvidia/l1_2pvv/mptable.c174
-rw-r--r--src/mainboard/nvidia/l1_2pvv/resourcemap.c278
-rw-r--r--src/mainboard/nvidia/l1_2pvv/romstage.c197
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/Kconfig70
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/Kconfig.name2
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/Makefile.inc18
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/acpi/debug.asl194
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/acpi/event.asl304
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/acpi/globutil.asl214
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl245
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl62
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl174
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/acpi/sata.asl145
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl87
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl95
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl150
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/acpi_tables.c102
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/board_info.txt1
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/cmos.default23
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/cmos.layout172
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/devicetree.cb134
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/dsdt.asl1211
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/fadt.c198
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c109
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/int15_func.c108
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/int15_func.h31
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/irq_tables.c132
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/mainboard.c825
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/mainboard.h1
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/mptable.c127
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/resourcemap.c274
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/romstage.c186
-rw-r--r--src/mainboard/sunw/Kconfig16
-rw-r--r--src/mainboard/sunw/Kconfig.name2
-rw-r--r--src/mainboard/sunw/ultra40/Kconfig64
-rw-r--r--src/mainboard/sunw/ultra40/Kconfig.name2
-rw-r--r--src/mainboard/sunw/ultra40/board_info.txt2
-rw-r--r--src/mainboard/sunw/ultra40/cmos.layout52
-rw-r--r--src/mainboard/sunw/ultra40/devicetree.cb151
-rw-r--r--src/mainboard/sunw/ultra40/get_bus_conf.c276
-rw-r--r--src/mainboard/sunw/ultra40/irq_tables.c212
-rw-r--r--src/mainboard/sunw/ultra40/mptable.c201
-rw-r--r--src/mainboard/sunw/ultra40/resourcemap.c265
-rw-r--r--src/mainboard/sunw/ultra40/romstage.c150
-rw-r--r--src/mainboard/sunw/ultra40m2/Kconfig79
-rw-r--r--src/mainboard/sunw/ultra40m2/Kconfig.name2
-rw-r--r--src/mainboard/sunw/ultra40m2/board_info.txt6
-rw-r--r--src/mainboard/sunw/ultra40m2/cmos.layout69
-rw-r--r--src/mainboard/sunw/ultra40m2/devicetree.cb147
-rw-r--r--src/mainboard/sunw/ultra40m2/get_bus_conf.c137
-rw-r--r--src/mainboard/sunw/ultra40m2/hda_verb.c68
-rw-r--r--src/mainboard/sunw/ultra40m2/irq_tables.c124
-rw-r--r--src/mainboard/sunw/ultra40m2/mainboard.c178
-rw-r--r--src/mainboard/sunw/ultra40m2/mb_sysconf.h29
-rw-r--r--src/mainboard/sunw/ultra40m2/mptable.c174
-rw-r--r--src/mainboard/sunw/ultra40m2/resourcemap.c278
-rw-r--r--src/mainboard/sunw/ultra40m2/romstage.c193
-rw-r--r--src/mainboard/supermicro/h8dme/Kconfig68
-rw-r--r--src/mainboard/supermicro/h8dme/Kconfig.name2
-rw-r--r--src/mainboard/supermicro/h8dme/board_info.txt2
-rw-r--r--src/mainboard/supermicro/h8dme/cmos.layout69
-rw-r--r--src/mainboard/supermicro/h8dme/devicetree.cb126
-rw-r--r--src/mainboard/supermicro/h8dme/get_bus_conf.c145
-rw-r--r--src/mainboard/supermicro/h8dme/hda_verb.c7
-rw-r--r--src/mainboard/supermicro/h8dme/irq_tables.c112
-rw-r--r--src/mainboard/supermicro/h8dme/mptable.c129
-rw-r--r--src/mainboard/supermicro/h8dme/resourcemap.c278
-rw-r--r--src/mainboard/supermicro/h8dme/romstage.c216
-rw-r--r--src/mainboard/supermicro/h8dmr/Kconfig67
-rw-r--r--src/mainboard/supermicro/h8dmr/Kconfig.name2
-rw-r--r--src/mainboard/supermicro/h8dmr/board_info.txt2
-rw-r--r--src/mainboard/supermicro/h8dmr/cmos.layout69
-rw-r--r--src/mainboard/supermicro/h8dmr/devicetree.cb146
-rw-r--r--src/mainboard/supermicro/h8dmr/get_bus_conf.c145
-rw-r--r--src/mainboard/supermicro/h8dmr/hda_verb.c7
-rw-r--r--src/mainboard/supermicro/h8dmr/irq_tables.c112
-rw-r--r--src/mainboard/supermicro/h8dmr/mptable.c130
-rw-r--r--src/mainboard/supermicro/h8dmr/resourcemap.c278
-rw-r--r--src/mainboard/supermicro/h8dmr/romstage.c193
-rw-r--r--src/mainboard/technexion/Kconfig16
-rw-r--r--src/mainboard/technexion/Kconfig.name2
-rw-r--r--src/mainboard/technexion/tim5690/Kconfig52
-rw-r--r--src/mainboard/technexion/tim5690/Kconfig.name2
-rw-r--r--src/mainboard/technexion/tim5690/Makefile.inc22
-rw-r--r--src/mainboard/technexion/tim5690/acpi/ide.asl240
-rw-r--r--src/mainboard/technexion/tim5690/acpi/routing.asl254
-rw-r--r--src/mainboard/technexion/tim5690/acpi/sata.asl145
-rw-r--r--src/mainboard/technexion/tim5690/acpi/usb.asl158
-rw-r--r--src/mainboard/technexion/tim5690/acpi_tables.c52
-rw-r--r--src/mainboard/technexion/tim5690/board_info.txt2
-rw-r--r--src/mainboard/technexion/tim5690/cmos.layout69
-rw-r--r--src/mainboard/technexion/tim5690/devicetree.cb112
-rw-r--r--src/mainboard/technexion/tim5690/dsdt.asl1674
-rw-r--r--src/mainboard/technexion/tim5690/fadt.c197
-rw-r--r--src/mainboard/technexion/tim5690/get_bus_conf.c109
-rw-r--r--src/mainboard/technexion/tim5690/irq_tables.c107
-rw-r--r--src/mainboard/technexion/tim5690/mainboard.c257
-rw-r--r--src/mainboard/technexion/tim5690/mptable.c110
-rw-r--r--src/mainboard/technexion/tim5690/resourcemap.c274
-rw-r--r--src/mainboard/technexion/tim5690/romstage.c160
-rw-r--r--src/mainboard/technexion/tim5690/speaker.c87
-rw-r--r--src/mainboard/technexion/tim5690/speaker.h21
-rw-r--r--src/mainboard/technexion/tim5690/tn_post_code.c224
-rw-r--r--src/mainboard/technexion/tim5690/tn_post_code.h29
-rw-r--r--src/mainboard/technexion/tim5690/vgabios.c75
-rw-r--r--src/mainboard/technexion/tim5690/vgabios.h33
-rw-r--r--src/mainboard/technexion/tim8690/Kconfig51
-rw-r--r--src/mainboard/technexion/tim8690/Kconfig.name2
-rw-r--r--src/mainboard/technexion/tim8690/acpi/ide.asl240
-rw-r--r--src/mainboard/technexion/tim8690/acpi/routing.asl254
-rw-r--r--src/mainboard/technexion/tim8690/acpi/sata.asl145
-rw-r--r--src/mainboard/technexion/tim8690/acpi/usb.asl157
-rw-r--r--src/mainboard/technexion/tim8690/acpi_tables.c52
-rw-r--r--src/mainboard/technexion/tim8690/board_info.txt2
-rw-r--r--src/mainboard/technexion/tim8690/cmos.layout69
-rw-r--r--src/mainboard/technexion/tim8690/devicetree.cb115
-rw-r--r--src/mainboard/technexion/tim8690/dsdt.asl1674
-rw-r--r--src/mainboard/technexion/tim8690/fadt.c197
-rw-r--r--src/mainboard/technexion/tim8690/get_bus_conf.c109
-rw-r--r--src/mainboard/technexion/tim8690/irq_tables.c107
-rw-r--r--src/mainboard/technexion/tim8690/mainboard.c149
-rw-r--r--src/mainboard/technexion/tim8690/mptable.c110
-rw-r--r--src/mainboard/technexion/tim8690/resourcemap.c274
-rw-r--r--src/mainboard/technexion/tim8690/romstage.c147
-rw-r--r--src/mainboard/tyan/s2912/Kconfig70
-rw-r--r--src/mainboard/tyan/s2912/Kconfig.name2
-rw-r--r--src/mainboard/tyan/s2912/board_info.txt4
-rw-r--r--src/mainboard/tyan/s2912/cmos.layout69
-rw-r--r--src/mainboard/tyan/s2912/devicetree.cb138
-rw-r--r--src/mainboard/tyan/s2912/get_bus_conf.c114
-rw-r--r--src/mainboard/tyan/s2912/irq_tables.c124
-rw-r--r--src/mainboard/tyan/s2912/mb_sysconf.h26
-rw-r--r--src/mainboard/tyan/s2912/mptable.c114
-rw-r--r--src/mainboard/tyan/s2912/resourcemap.c278
-rw-r--r--src/mainboard/tyan/s2912/romstage.c196
-rw-r--r--src/mainboard/winent/mb6047/Kconfig65
-rw-r--r--src/mainboard/winent/mb6047/Kconfig.name2
-rw-r--r--src/mainboard/winent/mb6047/acpi_tables.c56
-rw-r--r--src/mainboard/winent/mb6047/board_info.txt1
-rw-r--r--src/mainboard/winent/mb6047/cmos.layout53
-rw-r--r--src/mainboard/winent/mb6047/devicetree.cb120
-rw-r--r--src/mainboard/winent/mb6047/dsdt.asl206
-rw-r--r--src/mainboard/winent/mb6047/get_bus_conf.c98
-rw-r--r--src/mainboard/winent/mb6047/irq_tables.c151
-rw-r--r--src/mainboard/winent/mb6047/mainboard.c55
-rw-r--r--src/mainboard/winent/mb6047/mptable.c109
-rw-r--r--src/mainboard/winent/mb6047/romstage.c147
-rw-r--r--src/northbridge/amd/amdk8/northbridge.c19
-rw-r--r--src/northbridge/amd/amdk8/raminit_f.c2
521 files changed, 1 insertions, 68486 deletions
diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig
deleted file mode 100644
index 77bafc5cfb..0000000000
--- a/src/mainboard/amd/dbm690t/Kconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-if BOARD_AMD_DBM690T
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_S1G1
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_RS690
- select SOUTHBRIDGE_AMD_SB600
- select SUPERIO_ITE_IT8712F
- select HAVE_ACPI_TABLES
- select HAVE_MP_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_OPTION_TABLE
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select BOARD_ROMSIZE_KB_1024
- select QRANK_DIMM_SUPPORT
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default amd/dbm690t
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "DBM690T"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_AMD_DBM690T
diff --git a/src/mainboard/amd/dbm690t/Kconfig.name b/src/mainboard/amd/dbm690t/Kconfig.name
deleted file mode 100644
index cbc2900410..0000000000
--- a/src/mainboard/amd/dbm690t/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AMD_DBM690T
- bool "DBM690T (Herring)"
diff --git a/src/mainboard/amd/dbm690t/acpi/ide.asl b/src/mainboard/amd/dbm690t/acpi/ide.asl
deleted file mode 100644
index d5badfcb6b..0000000000
--- a/src/mainboard/amd/dbm690t/acpi/ide.asl
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "ide.asl"
- }
- }
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
- 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
- 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
- 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
- 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
- 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
- Field(ICRG, AnyAcc, NoLock, Preserve)
-{
- PPTS, 8, /* Primary PIO Slave Timing */
- PPTM, 8, /* Primary PIO Master Timing */
- OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
- PMTM, 8, /* Primary MWDMA Master Timing */
- OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
- OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
- PPSM, 4, /* Primary PIO slave Mode */
- OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
- OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
- PDSM, 4, /* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
- Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
- Increment(Local0)
- Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
- Increment(Local1)
- Return(Multiply(30, Add(Local0, Local1)))
-}
-
-Device(PRID)
-{
- Name (_ADR, Zero)
- Method(_GTM, 0)
- {
- NAME(OTBF, Buffer(20) { /* out buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
- CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
- /* Just return if the channel is disabled */
- If(And(PPCR, 0x01)) { /* primary PIO control */
- Return(OTBF)
- }
-
- /* Always tell them independent timing available and IOChannelReady used on both drives */
- Or(BFFG, 0x1A, BFFG)
-
- Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
- Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
-
- If(And(PDCR, 0x01)) { /* It's under UDMA mode */
- Or(BFFG, 0x01, BFFG)
- Store(DerefOf(Index(UDTT, PDMM)), DSD0)
- }
- Else {
- Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
- }
-
- If(And(PDCR, 0x02)) { /* It's under UDMA mode */
- Or(BFFG, 0x04, BFFG)
- Store(DerefOf(Index(UDTT, PDSM)), DSD1)
- }
- Else {
- Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
- }
-
- Return(OTBF) /* out buffer */
- } /* End Method(_GTM) */
-
- Method(_STM, 3, NotSerialized)
- {
- NAME(INBF, Buffer(20) { /* in buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
- CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
- Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
- Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
- Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
- Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
-
- Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
- Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
-
- If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDMM,)
- Or(PDCR, 0x01, PDCR)
- }
- Else {
- If(LNotEqual(DSD0, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTM)
- }
- }
-
- If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDSM,)
- Or(PDCR, 0x02, PDCR)
- }
- Else {
- If(LNotEqual(DSD1, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTS)
- }
- }
- /* Return(INBF) */
- } /*End Method(_STM) */
- Device(MST)
- {
- Name(_ADR, 0)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xA0, CMDA)
- Store(0xA0, CMDB)
- Store(0xA0, CMDC)
-
- Or(PPMM, 0x08, POMD)
-
- If(And(PDCR, 0x01)) {
- Or(PDMM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTM),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(MST) */
-
- Device(SLAV)
- {
- Name(_ADR, 1)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xB0, CMDA)
- Store(0xB0, CMDB)
- Store(0xB0, CMDC)
-
- Or(PPSM, 0x08, POMD)
-
- If(And(PDCR, 0x02)) {
- Or(PDSM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTS),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/dbm690t/acpi/routing.asl b/src/mainboard/amd/dbm690t/acpi/routing.asl
deleted file mode 100644
index bcb14e7e37..0000000000
--- a/src/mainboard/amd/dbm690t/acpi/routing.asl
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "routing.asl"
- }
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
- Name(PR0, Package(){
- /* NB devices */
- /* Bus 0, Dev 0 - RS690 Host Controller */
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, INTC, 0 },
- Package(){0x0002FFFF, 1, INTD, 0 },
- Package(){0x0002FFFF, 2, INTA, 0 },
- Package(){0x0002FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, INTA, 0 },
- Package(){0x0004FFFF, 1, INTB, 0 },
- Package(){0x0004FFFF, 2, INTC, 0 },
- Package(){0x0004FFFF, 3, INTD, 0 },
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- /* Package(){0x0005FFFF, 0, INTB, 0 }, */
- /* Package(){0x0005FFFF, 1, INTC, 0 }, */
- /* Package(){0x0005FFFF, 2, INTD, 0 }, */
- /* Package(){0x0005FFFF, 3, INTA, 0 }, */
- /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
- Package(){0x0006FFFF, 0, INTC, 0 },
- Package(){0x0006FFFF, 1, INTD, 0 },
- Package(){0x0006FFFF, 2, INTA, 0 },
- Package(){0x0006FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
- Package(){0x0007FFFF, 0, INTD, 0 },
- Package(){0x0007FFFF, 1, INTA, 0 },
- Package(){0x0007FFFF, 2, INTB, 0 },
- Package(){0x0007FFFF, 3, INTC, 0 },
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0012FFFF, 1, INTA, 0 },
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){0x0013FFFF, 0, INTA, 0 },
- Package(){0x0013FFFF, 1, INTB, 0 },
- Package(){0x0013FFFF, 2, INTC, 0 },
- Package(){0x0013FFFF, 3, INTD, 0 },
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
- Package(){0x0014FFFF, 0, INTA, 0 },
- Package(){0x0014FFFF, 1, INTB, 0 },
- Package(){0x0014FFFF, 2, INTC, 0 },
- Package(){0x0014FFFF, 3, INTD, 0 },
- })
-
- Name(APR0, Package(){
- /* NB devices in APIC mode */
- /* Bus 0, Dev 0 - RS690 Host Controller */
-
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Package(){0x0001FFFF, 0, 0, 18 }, */
- /* Package(){0x0001FFFF, 1, 0, 19 }, */
-
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, 0, 18 },
- /* Package(){0x0002FFFF, 1, 0, 19 }, */
- /* Package(){0x0002FFFF, 2, 0, 16 }, */
- /* Package(){0x0002FFFF, 3, 0, 17 }, */
-
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){0x0003FFFF, 0, 0, 19 },
-
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, 0, 16 },
- /* Package(){0x0004FFFF, 1, 0, 17 }, */
- /* Package(){0x0004FFFF, 2, 0, 18 }, */
- /* Package(){0x0004FFFF, 3, 0, 19 }, */
-
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- Package(){0x0005FFFF, 0, 0, 17 },
- /* Package(){0x0005FFFF, 1, 0, 18 }, */
- /* Package(){0x0005FFFF, 2, 0, 19 }, */
- /* Package(){0x0005FFFF, 3, 0, 16 }, */
-
- /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
- Package(){0x0006FFFF, 0, 0, 18 },
- /* Package(){0x0006FFFF, 1, 0, 19 }, */
- /* Package(){0x0006FFFF, 2, 0, 16 }, */
- /* Package(){0x0006FFFF, 3, 0, 17 }, */
-
- /* Bus 0, Dev 7 - PCIe Bridge for network card */
- Package(){0x0007FFFF, 0, 0, 19 },
- /* Package(){0x0007FFFF, 1, 0, 16 }, */
- /* Package(){0x0007FFFF, 2, 0, 17 }, */
- /* Package(){0x0007FFFF, 3, 0, 18 }, */
-
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices in APIC mode */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0012FFFF, 0, 0, 22 },
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){0x0013FFFF, 0, 0, 16 },
- Package(){0x0013FFFF, 1, 0, 17 },
- Package(){0x0013FFFF, 2, 0, 18 },
- Package(){0x0013FFFF, 3, 0, 19 },
- /* Package(){0x00130004, 2, 0, 18 }, */
- /* Package(){0x00130005, 3, 0, 19 }, */
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
- Package(){0x0014FFFF, 0, 0, 16 },
- Package(){0x0014FFFF, 1, 0, 17 },
- Package(){0x0014FFFF, 2, 0, 18 },
- Package(){0x0014FFFF, 3, 0, 19 },
- /* Package(){0x00140004, 2, 0, 18 }, */
- /* Package(){0x00140004, 3, 0, 19 }, */
- /* Package(){0x00140005, 1, 0, 17 }, */
- /* Package(){0x00140006, 1, 0, 17 }, */
- })
-
- Name(PR1, Package(){
- /* Internal graphics - RS690 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, INTA, 0 },
- Package(){0x0005FFFF, 1, INTB, 0 },
- Package(){0x0005FFFF, 2, INTC, 0 },
- Package(){0x0005FFFF, 3, INTD, 0 },
- })
-
- Name(APR1, Package(){
- /* Internal graphics - RS690 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, 0, 18 },
- Package(){0x0005FFFF, 1, 0, 19 },
- /* Package(){0x0005FFFF, 2, 0, 20 }, */
- /* Package(){0x0005FFFF, 3, 0, 17 }, */
- })
-
- Name(PS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, INTA, 0 },
- Package(){0x0000FFFF, 1, INTB, 0 },
- Package(){0x0000FFFF, 2, INTC, 0 },
- Package(){0x0000FFFF, 3, INTD, 0 },
- })
-
- Name(APS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, 0, 16 },
- Package(){0x0000FFFF, 1, 0, 17 },
- Package(){0x0000FFFF, 2, 0, 18 },
- Package(){0x0000FFFF, 3, 0, 19 },
- })
-
- Name(PS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, INTB, 0 },
- Package(){0x0000FFFF, 1, INTC, 0 },
- Package(){0x0000FFFF, 2, INTD, 0 },
- Package(){0x0000FFFF, 3, INTA, 0 },
- })
-
- Name(APS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
-
- Name(APS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, 0, 19 },
- Package(){0x0000FFFF, 1, 0, 16 },
- Package(){0x0000FFFF, 2, 0, 17 },
- Package(){0x0000FFFF, 3, 0, 18 },
- })
-
- Name(PCIB, Package(){
- /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
- Package(){0x0005FFFF, 0, 0, 0x14 },
- Package(){0x0005FFFF, 1, 0, 0x15 },
- Package(){0x0005FFFF, 2, 0, 0x16 },
- Package(){0x0005FFFF, 3, 0, 0x17 },
- Package(){0x0006FFFF, 0, 0, 0x15 },
- Package(){0x0006FFFF, 1, 0, 0x16 },
- Package(){0x0006FFFF, 2, 0, 0x17 },
- Package(){0x0006FFFF, 3, 0, 0x14 },
- Package(){0x0007FFFF, 0, 0, 0x16 },
- Package(){0x0007FFFF, 1, 0, 0x17 },
- Package(){0x0007FFFF, 2, 0, 0x14 },
- Package(){0x0007FFFF, 3, 0, 0x15 },
- })
-}
diff --git a/src/mainboard/amd/dbm690t/acpi/sata.asl b/src/mainboard/amd/dbm690t/acpi/sata.asl
deleted file mode 100644
index 474e5ed6d2..0000000000
--- a/src/mainboard/amd/dbm690t/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(SATA) {
- Name(_ADR, 0x00120000)
- #include "sata.asl"
- }
- }
-}
-*/
-
-Name(STTM, Buffer(20) {
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
- \_GPE._L1F()
-}
-
-Device(PMRY)
-{
- Name(_ADR, 0)
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(PMST) {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P0IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- }/* end of PMST */
-
- Device(PSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P1IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of PSLA */
-} /* end of PMRY */
-
-
-Device(SEDY)
-{
- Name(_ADR, 1) /* IDE Scondary Channel */
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(SMST)
- {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P2IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SMST */
-
- Device(SSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P3IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SSLA */
-} /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
- Method(_L1F,0x0,NotSerialized) {
- if (\_SB.P0PR) {
- if (LGreater(\_SB.P0IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P0PR)
- }
-
- if (\_SB.P1PR) {
- if (LGreater(\_SB.P1IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P1PR)
- }
-
- if (\_SB.P2PR) {
- if (LGreater(\_SB.P2IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P2PR)
- }
-
- if (\_SB.P3PR) {
- if (LGreater(\_SB.P3IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P3PR)
- }
- }
-}
diff --git a/src/mainboard/amd/dbm690t/acpi/usb.asl b/src/mainboard/amd/dbm690t/acpi/usb.asl
deleted file mode 100644
index 638690697c..0000000000
--- a/src/mainboard/amd/dbm690t/acpi/usb.asl
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "usb.asl"
- }
-*/
-Method(UCOC, 0) {
- Sleep(20)
- Store(0x13,CMTI)
- Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
- Scope (\_GPE) {
- Method (_L13) {
- UCOC()
- if(LEqual(GPB0,PLC0)) {
- Not(PLC0,PLC0)
- Store(PLC0, \_SB.PT0D)
- }
- }
- }
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
- Scope (\_GPE) {
- Method (_L14) {
- UCOC()
- if (LEqual(GPB1,PLC1)) {
- Not(PLC1,PLC1)
- Store(PLC1, \_SB.PT1D)
- }
- }
- }
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
- Scope (\_GPE) {
- Method (_L15) {
- UCOC()
- if (LEqual(GPB2,PLC2)) {
- Not(PLC2,PLC2)
- Store(PLC2, \_SB.PT2D)
- }
- }
- }
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
- Scope (\_GPE) {
- Method (_L16) {
- UCOC()
- if (LEqual(GPB3,PLC3)) {
- Not(PLC3,PLC3)
- Store(PLC3, \_SB.PT3D)
- }
- }
- }
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
- Scope (\_GPE) {
- Method (_L19) {
- UCOC()
- if (LEqual(GPB4,PLC4)) {
- Not(PLC4,PLC4)
- Store(PLC4, \_SB.PT4D)
- }
- }
- }
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
- Scope (\_GPE) {
- Method (_L1A) {
- UCOC()
- if (LEqual(GPB5,PLC5)) {
- Not(PLC5,PLC5)
- Store(PLC5, \_SB.PT5D)
- }
- }
- }
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
- Scope (\_GPE) {
- /* Method (_L1C) { */
- Method (_L06) {
- UCOC()
- if (LEqual(GPB6,PLC6)) {
- Not(PLC6,PLC6)
- Store(PLC6, \_SB.PT6D)
- }
- }
- }
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
- Scope (\_GPE) {
- /* Method (_L1D) { */
- Method (_L07) {
- UCOC()
- if (LEqual(GPB7,PLC7)) {
- Not(PLC7,PLC7)
- Store(PLC7, \_SB.PT7D)
- }
- }
- }
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
- Scope (\_GPE) {
- Method (_L17) {
- if (LEqual(G8IS,PLC8)) {
- Not(PLC8,PLC8)
- Store(PLC8, \_SB.PT8D)
- }
- }
- }
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
- Scope (\_GPE) {
- Method (_L0E) {
- if (LEqual(G9IS,0)) {
- Store(1,\_SB.PT9D)
- }
- }
- }
-}
diff --git a/src/mainboard/amd/dbm690t/acpi_tables.c b/src/mainboard/amd/dbm690t/acpi_tables.c
deleted file mode 100644
index e19969219e..0000000000
--- a/src/mainboard/amd/dbm690t/acpi_tables.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include <arch/cpu.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- get_bus_conf();
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB600 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
- IO_APIC_ADDR, 0);
-
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high */
-
- /* create all subtables for processors */
- /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
- /* 1: LINT1 connect to NMI */
-
- return current;
-}
diff --git a/src/mainboard/amd/dbm690t/board_info.txt b/src/mainboard/amd/dbm690t/board_info.txt
deleted file mode 100644
index f6b1ab16d9..0000000000
--- a/src/mainboard/amd/dbm690t/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Board name: dbM690T (Herring)
-Category: eval
-Board URL: http://support.amd.com/us/ChipsetMotherboard_TechDocs/42655A_S1DBM680T_PB.pdf
diff --git a/src/mainboard/amd/dbm690t/cmos.layout b/src/mainboard/amd/dbm690t/cmos.layout
deleted file mode 100644
index 104d51f4c2..0000000000
--- a/src/mainboard/amd/dbm690t/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-##
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb
deleted file mode 100644
index 898537b155..0000000000
--- a/src/mainboard/amd/dbm690t/devicetree.cb
+++ /dev/null
@@ -1,121 +0,0 @@
-#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_S1G1
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1022 0x3050 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on # southbridge
- chip southbridge/amd/rs690
- device pci 0.0 on end # HT 0x7910
- device pci 1.0 on # Internal Graphics P2P bridge 0x7912
- device pci 5.0 on end # Internal Graphics 0x791F
- end
- device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
- device pci 3.0 off end # PCIE P2P bridge 0x791b
- device pci 4.0 on end # PCIE P2P bridge 0x7914
- device pci 5.0 on end # PCIE P2P bridge 0x7915
- device pci 6.0 on end # PCIE P2P bridge 0x7916
- device pci 7.0 on end # PCIE P2P bridge 0x7917
- device pci 8.0 off end # NB/SB Link P2P bridge
- register "gpp_configuration" = "4"
- register "port_enable" = "0xfc"
- register "gfx_dev2_dev3" = "1"
- register "gfx_dual_slot" = "0"
- register "gfx_lane_reversal" = "0"
- register "gfx_tmds" = "0"
- register "gfx_compliance" = "0"
- register "gfx_reconfiguration" = "1"
- register "gfx_link_width" = "0"
- end
- chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
- device pci 12.0 on end # SATA 0x4380
- device pci 13.0 on end # USB 0x4387
- device pci 13.1 on end # USB 0x4388
- device pci 13.2 on end # USB 0x4389
- device pci 13.3 on end # USB 0x438a
- device pci 13.4 on end # USB 0x438b
- device pci 13.5 on end # USB 2 0x4386
- device pci 14.0 on # SM 0x4385
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 0-1-1
- device i2c 53 on end
- end
- end # SM
- device pci 14.1 on end # IDE 0x438c
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC 0x438d
- chip superio/ite/it8712f
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 off end # EC
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.6 on # Mouse
- irq 0x70 = 12
- end
- device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
- end
- device pnp 2e.8 off # MIDI
- io 0x60 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.9 off # GAME
- io 0x60 = 0x220
- end
- device pnp 2e.a off end # CIR
- end #superio/ite/it8712f
- end #LPC
- device pci 14.4 on end # PCI 0x4384
- device pci 14.5 on end # ACI 0x4382
- device pci 14.6 on end # MCI 0x438e
- register "hda_viddid" = "0x10ec0882"
- end #southbridge/amd/sb600
- end # device pci 18.0
-
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end #northbridge/amd/amdk8
- end #domain
-end #northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl
deleted file mode 100644
index 748c9fb879..0000000000
--- a/src/mainboard/amd/dbm690t/dsdt.asl
+++ /dev/null
@@ -1,1674 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <southbridge/amd/sb600/sb600.h>
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "AMD ", /* OEMID */
- "COREBOOT", /* TABLE ID */
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
-
- /* Data to be patched by the BIOS during POST */
- /* FIXME the patching is not done yet! */
- /* Memory related values */
- Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
-
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
-
- /* USB overcurrent mapping pins. */
- Name(UOM0, 0)
- Name(UOM1, 2)
- Name(UOM2, 0)
- Name(UOM3, 7)
- Name(UOM4, 2)
- Name(UOM5, 2)
- Name(UOM6, 6)
- Name(UOM7, 2)
- Name(UOM8, 6)
- Name(UOM9, 6)
-
- /* Some global data */
- Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PMOD, One) /* Assume APIC */
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- /* PCI Error control register */
- OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
- Field(PERC, ByteAcc, NoLock, Preserve) {
- SENS, 0x00000001,
- PENS, 0x00000001,
- SENE, 0x00000001,
- PENE, 0x00000001,
- }
-
- /* Client Management index/data registers */
- OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
- Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
- /* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
- }
-
- /* GPM Port register */
- OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
- Field(GPT, ByteAcc, NoLock, Preserve) {
- GPB0,1,
- GPB1,1,
- GPB2,1,
- GPB3,1,
- GPB4,1,
- GPB5,1,
- GPB6,1,
- GPB7,1,
- }
-
- /* Flash ROM program enable register */
- OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
- Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
- FLRE, 0x00000001,
- }
-
- /* PM2 index/data registers */
- OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
- Field(PM2R, ByteAcc, NoLock, Preserve) {
- PM2I, 0x00000008,
- PM2D, 0x00000008,
- }
-
- /* Power Management I/O registers */
- OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
- Field(PIOR, ByteAcc, NoLock, Preserve) {
- PIOI, 0x00000008,
- PIOD, 0x00000008,
- }
- IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
- Offset(0x00), /* MiscControl */
- , 1,
- T1EE, 1,
- T2EE, 1,
- Offset(0x01), /* MiscStatus */
- , 1,
- T1E, 1,
- T2E, 1,
- Offset(0x04), /* SmiWakeUpEventEnable3 */
- , 7,
- SSEN, 1,
- Offset(0x07), /* SmiWakeUpEventStatus3 */
- , 7,
- CSSM, 1,
- Offset(0x10), /* AcpiEnable */
- , 6,
- PWDE, 1,
- Offset(0x1C), /* ProgramIoEnable */
- , 3,
- MKME, 1,
- IO3E, 1,
- IO2E, 1,
- IO1E, 1,
- IO0E, 1,
- Offset(0x1D), /* IOMonitorStatus */
- , 3,
- MKMS, 1,
- IO3S, 1,
- IO2S, 1,
- IO1S, 1,
- IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
- APEB, 16,
- Offset(0x36), /* GEvtLevelConfig */
- , 6,
- ELC6, 1,
- ELC7, 1,
- Offset(0x37), /* GPMLevelConfig0 */
- , 3,
- PLC0, 1,
- PLC1, 1,
- PLC2, 1,
- PLC3, 1,
- PLC8, 1,
- Offset(0x38), /* GPMLevelConfig1 */
- , 1,
- PLC4, 1,
- PLC5, 1,
- , 1,
- PLC6, 1,
- PLC7, 1,
- Offset(0x3B), /* PMEStatus1 */
- GP0S, 1,
- GM4S, 1,
- GM5S, 1,
- APS, 1,
- GM6S, 1,
- GM7S, 1,
- GP2S, 1,
- STSS, 1,
- Offset(0x55), /* SoftPciRst */
- SPRE, 1,
- , 1,
- , 1,
- PNAT, 1,
- PWMK, 1,
- PWNS, 1,
-
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
-
- Offset(0x65), /* UsbPMControl */
- , 4,
- URRE, 1,
- Offset(0x68), /* MiscEnable68 */
- , 3,
- TMTE, 1,
- , 1,
- Offset(0x92), /* GEVENTIN */
- , 7,
- E7IS, 1,
- Offset(0x96), /* GPM98IN */
- G8IS, 1,
- G9IS, 1,
- Offset(0x9A), /* EnhanceControl */
- ,7,
- HPDE, 1,
- Offset(0xA8), /* PIO7654Enable */
- IO4E, 1,
- IO5E, 1,
- IO6E, 1,
- IO7E, 1,
- Offset(0xA9), /* PIO7654Status */
- IO4S, 1,
- IO5S, 1,
- IO6S, 1,
- IO7S, 1,
- }
-
- /* PM1 Event Block
- * First word is PM1_Status, Second word is PM1_Enable
- */
- OperationRegion(P1EB, SystemIO, APEB, 0x04)
- Field(P1EB, ByteAcc, NoLock, Preserve) {
- TMST, 1,
- , 3,
- BMST, 1,
- GBST, 1,
- Offset(0x01),
- PBST, 1,
- , 1,
- RTST, 1,
- , 3,
- PWST, 1,
- SPWS, 1,
- Offset(0x02),
- TMEN, 1,
- , 4,
- GBEN, 1,
- Offset(0x03),
- PBEN, 1,
- , 1,
- RTEN, 1,
- , 3,
- PWDA, 1,
- }
-
- Scope(\_SB) {
-
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
- /* Byte offsets are computed using the following technique:
- * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
- * The 8 comes from 8 functions per device, and 4096 bytes per function config space
- */
- Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
- STB5, 32,
- Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
- PT0D, 1,
- PT1D, 1,
- PT2D, 1,
- PT3D, 1,
- PT4D, 1,
- PT5D, 1,
- PT6D, 1,
- PT7D, 1,
- PT8D, 1,
- PT9D, 1,
- Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
- SBIE, 1,
- SBME, 1,
- Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
- SBRI, 8,
- Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
- SBB1, 32,
- Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
- ,14,
- P92E, 1, /* Port92 decode enable */
- }
-
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
- Field(SB5, AnyAcc, NoLock, Preserve)
- {
- /* Port 0 */
- Offset(0x120), /* Port 0 Task file status */
- P0ER, 1,
- , 2,
- P0DQ, 1,
- , 3,
- P0BY, 1,
- Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
- , 4,
- P0IS, 4,
- Offset(0x12C), /* Port 0 Serial ATA control */
- P0DI, 4,
- Offset(0x130), /* Port 0 Serial ATA error */
- , 16,
- P0PR, 1,
-
- /* Port 1 */
- offset(0x1A0), /* Port 1 Task file status */
- P1ER, 1,
- , 2,
- P1DQ, 1,
- , 3,
- P1BY, 1,
- Offset(0x1A8), /* Port 1 Serial ATA status */
- P1DD, 4,
- , 4,
- P1IS, 4,
- Offset(0x1AC), /* Port 1 Serial ATA control */
- P1DI, 4,
- Offset(0x1B0), /* Port 1 Serial ATA error */
- , 16,
- P1PR, 1,
-
- /* Port 2 */
- Offset(0x220), /* Port 2 Task file status */
- P2ER, 1,
- , 2,
- P2DQ, 1,
- , 3,
- P2BY, 1,
- Offset(0x228), /* Port 2 Serial ATA status */
- P2DD, 4,
- , 4,
- P2IS, 4,
- Offset(0x22C), /* Port 2 Serial ATA control */
- P2DI, 4,
- Offset(0x230), /* Port 2 Serial ATA error */
- , 16,
- P2PR, 1,
-
- /* Port 3 */
- Offset(0x2A0), /* Port 3 Task file status */
- P3ER, 1,
- , 2,
- P3DQ, 1,
- , 3,
- P3BY, 1,
- Offset(0x2A8), /* Port 3 Serial ATA status */
- P3DD, 4,
- , 4,
- P3IS, 4,
- Offset(0x2AC), /* Port 3 Serial ATA control */
- P3DI, 4,
- Offset(0x2B0), /* Port 3 Serial ATA error */
- , 16,
- P3PR, 1,
- }
- }
-
- #include "acpi/routing.asl"
-
- Scope(\_SB) {
-
- Method(OSFL, 0){
-
- if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
-
- if(CondRefOf(\_OSI))
- {
- Store(1, OSVR) /* Assume some form of XP */
- if (\_OSI("Windows 2006")) /* Vista */
- {
- Store(2, OSVR)
- }
- } else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSVR) /* Linux */
- } Else {
- Store(4, OSVR) /* Gotta be WinCE */
- }
- }
- Return(OSVR)
- }
-
- Method(_PIC, 0x01, NotSerialized)
- {
- If (Arg0)
- {
- \_SB.CIRQ()
- }
- Store(Arg0, PMOD)
- }
-
- Method(CIRQ, 0x00, NotSerialized)
- {
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTA._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTE._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_PRS\n") */
- Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
- } /* End Scope(_SB) */
-
- #include <southbridge/amd/common/acpi/sleepstates.asl>
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- \_SB.PCI0.SIOS (Arg0)
- } /* End Method(\_PTS) */
-
- /*
- * The following method results in a "not a valid reserved NameSeg"
- * warning so I have commented it out for the duration. It isn't
- * used, so it could be removed.
- *
- *
- * \_GTS OEM Going To Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- *
- * Method(\_GTS, 1) {
- * DBGO("\\_GTS\n")
- * DBGO("From S0 to S")
- * DBGO(Arg0)
- * DBGO("\n")
- * }
- */
-
- /*
- * \_BFS OEM Back From Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- */
- Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
- }
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- Store(1,HPDE)
-
- /* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, Local1)
- Store(Local1, PWST)
-
- /* if(DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
- * } else {
- * Store(Arg0, Index(WKST,1))
- * }
- */
- \_SB.PCI0.SIOW ()
- Return(WKST)
- } /* End Method(\_WAK) */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* General event 0 */
- /* Method(_L00) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 1 */
- /* Method(_L01) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 2 */
- /* Method(_L02) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 3 */
- Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* General event 4 */
- /* Method(_L04) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 5 */
- /* Method(_L05) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 6 - Used for GPM6, moved to USB.asl */
- /* Method(_L06) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 7 - Used for GPM7, moved to USB.asl */
- /* Method(_L07) {
- * DBGO("\\_GPE\\_L07\n")
- * }
- */
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
- }
-
- /* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
-
- /* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
-
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
-
- /* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
-
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event - Moved to USB.asl */
- /* Method(_L1A) {
- * DBGO("\\_GPE\\_L1A\n")
- * }
- */
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
-
- /* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
-
- /* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
-
- /* SATA SCI event - Moved to sata.asl */
- /* Method(_L1F) {
- * DBGO("\\_GPE\\_L1F\n")
- * }
- */
-
- } /* End Scope GPE */
-
- #include "acpi/usb.asl"
-
- /* System Bus */
- Scope(\_SB) { /* Start \_SB scope */
- #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0) {
- External (TOM1)
- External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* Dev3 is also an external GFX bridge, not used in Herring */
-
- Device(PBR4) {
- Name(_ADR, 0x00040000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR4 */
-
- Device(PBR5) {
- Name(_ADR, 0x00050000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR5 */
-
- Device(PBR6) {
- Name(_ADR, 0x00060000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR6 */
-
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR7 */
-
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
-
- /* Describe the Southbridge devices */
- Device(STCR) {
- Name(_ADR, 0x00120000)
- #include "acpi/sata.asl"
- } /* end STCR */
-
- Device(UOH1) {
- Name(_ADR, 0x00130000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH1 */
-
- Device(UOH2) {
- Name(_ADR, 0x00130001)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH2 */
-
- Device(UOH3) {
- Name(_ADR, 0x00130002)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH3 */
-
- Device(UOH4) {
- Name(_ADR, 0x00130003)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH4 */
-
- Device(UOH5) {
- Name(_ADR, 0x00130004)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UEH1) {
- Name(_ADR, 0x00130005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(SBUS) {
- Name(_ADR, 0x00140000)
- } /* end SBUS */
-
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "acpi/ide.asl"
- } /* end IDEC */
-
- Device(AZHD) {
- Name(_ADR, 0x00140002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6C),
- MMDT, 16,
- }
-
- Method(_INI) {
- If(LEqual(OSVR,3)){ /* If we are running Linux */
- Store(zero, NSEN)
- Store(one, NSDO)
- Store(one, NSDI)
- }
- }
- } /* end AZHD */
-
- Device(LIBR) {
- Name(_ADR, 0x00140003)
- /* Method(_INI) {
- * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
- } */ /* End Method(_SB.SBRDG._INI) */
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){8}
- IO(Decode16,0x0070, 0x0070, 0, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){0}
- IO(Decode16, 0x0040, 0x0040, 0, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 0, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){2}
- IO(Decode16,0x0020, 0x0020, 0, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,BusMaster,Transfer8){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
- IRQNoFlags(){13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPTM) { /* HPET */
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* HPET is visible */
- }
- Method(_CRS, 0) {
- Return(CRS)
- }
- } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
- } /* end LIBR */
-
- Device(HPBR) {
- Name(_ADR, 0x00140004)
- } /* end HostPciBr */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- } /* end Ac97modem */
-
- /* ITE IT8712F Support */
- OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
- Field (IOID, ByteAcc, NoLock, Preserve)
- {
- SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
- }
-
- IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
- {
- Offset (0x07),
- LDN, 8, /* Logical Device Number */
- Offset (0x20),
- CID1, 8, /* Chip ID Byte 1, 0x87 */
- CID2, 8, /* Chip ID Byte 2, 0x12 */
- Offset (0x30),
- ACTR, 8, /* Function activate */
- Offset (0xF0),
- APC0, 8, /* APC/PME Event Enable Register */
- APC1, 8, /* APC/PME Status Register */
- APC2, 8, /* APC/PME Control Register 1 */
- APC3, 8, /* Environment Controller Special Configuration Register */
- APC4, 8 /* APC/PME Control Register 2 */
- }
-
- /* Enter the IT8712F MB PnP Mode */
- Method (EPNP)
- {
- Store(0x87, SIOI)
- Store(0x01, SIOI)
- Store(0x55, SIOI)
- Store(0x55, SIOI) /* IT8712F magic number */
- }
- /* Exit the IT8712F MB PnP Mode */
- Method (XPNP)
- {
- Store (0x02, SIOI)
- Store (0x02, SIOD)
- }
-
- /*
- * Keyboard PME is routed to SB600 Gevent3. We can wake
- * up the system by pressing the key.
- */
- Method (SIOS, 1)
- {
- /* We only enable KBD PME for S5. */
- If (LLess (Arg0, 0x05))
- {
- EPNP()
- /* DBGO("IT8712F\n") */
-
- Store (0x4, LDN)
- Store (One, ACTR) /* Enable EC */
- /*
- Store (0x4, LDN)
- Store (0x04, APC4)
- */ /* falling edge. which mode? Not sure. */
-
- Store (0x4, LDN)
- Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
- Store (0x4, LDN)
- Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
- XPNP()
- }
- }
- Method (SIOW, 0)
- {
- EPNP()
- Store (0x4, LDN)
- Store (Zero, APC0) /* disable keyboard PME */
- Store (0x4, LDN)
- Store (0xFF, APC1) /* clear keyboard PME status */
- XPNP()
- }
-
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
-
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
- }
-
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * ShiftLeft(TOM2, 20, Local0)
- * Subtract(Local0, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-
- Return(CRES) /* note to change the Name buffer */
- } /* end of Method(_SB.PCI0._CRS) */
-
- /*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
- Method(_INI, 0) {
- /* DBGO("\\_SB\\_INI\n") */
- /* DBGO(" DSDT.ASL code from ") */
- /* DBGO(__DATE__) */
- /* DBGO(" ") */
- /* DBGO(__TIME__) */
- /* DBGO("\n Sleep states supported: ") */
- /* DBGO("\n") */
- /* DBGO(" \\_OS=") */
- /* DBGO(\_OS) */
- /* DBGO("\n \\_REV=") */
- /* DBGO(\_REV) */
- /* DBGO("\n") */
-
- /* Determine the OS we're running on */
- OSFL()
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
- * }
- */
- } /* End Method(_SB._INI) */
- } /* End Device(PCI0) */
-
- Device(PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
- } /* End \_SB scope */
-
- Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
- } /* End Scope SI */
-
- #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
-
- /* THERMAL */
- Scope(\_TZ) {
- Name (KELV, 2732)
- Name (THOT, 800)
- Name (TCRT, 850)
-
- ThermalZone(TZ00) {
- Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
- /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
- Return(Add(0, 2730))
- }
- Method(_AL0,0) { /* Returns package of cooling device to turn on */
- /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
- Return(Package() {\_TZ.TZ00.FAN0})
- }
- Device (FAN0) {
- Name(_HID, EISAID("PNP0C0B"))
- Name(_PR0, Package() {PFN0})
- }
-
- PowerResource(PFN0,0,0) {
- Method(_STA) {
- Store(0xF,Local0)
- Return(Local0)
- }
- Method(_ON) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
- }
- Method(_OFF) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
- }
- }
-
- Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
- Return (Add (THOT, KELV))
- }
- Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
- Return (Add (TCRT, KELV))
- }
- Method(_TMP,0) { /* return current temp of this zone */
- Store (SMBR (0x07, 0x4C,, 0x00), Local0)
- If (LGreater (Local0, 0x10)) {
- Store (Local0, Local1)
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400, KELV))
- }
-
- Store (SMBR (0x07, 0x4C, 0x01), Local0)
- /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
- /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
- If (LGreater (Local0, 0x10)) {
- If (LGreater (Local0, Local1)) {
- Store (Local0, Local1)
- }
-
- Multiply (Local1, 10, Local1)
- Return (Add (Local1, KELV))
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400 , KELV))
- }
- } /* end of _TMP */
- } /* end of TZ00 */
- }
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/dbm690t/fadt.c b/src/mainboard/amd/dbm690t/fadt.c
deleted file mode 100644
index b397f52aea..0000000000
--- a/src/mainboard/amd/dbm690t/fadt.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include "southbridge/amd/sb600/sb600.h"
-
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb ACPI */
-/* pm_base should be got from bar2 of rs690. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
-
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
- /* Prepare the header */
- memset((void *)fadt, 0, sizeof(acpi_fadt_t));
- memcpy(header->signature, "FACP", 4);
- header->length = 244;
- header->revision = 3;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->asl_compiler_revision = 0;
-
- fadt->firmware_ctrl = (u32) facs;
- fadt->dsdt = (u32) dsdt;
- /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
- fadt->preferred_pm_profile = 0x03;
- fadt->sci_int = 9;
- /* disable system management mode by setting to 0: */
- fadt->smi_cmd = 0;
- fadt->acpi_enable = 0xf0;
- fadt->acpi_disable = 0xf1;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0xe2;
-
- pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
-
- /* CpuControl is in \_PR.CP00, 6 bytes */
- pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
-
- pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
-
- pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
-
- pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 20-2B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
- pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
-
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
- fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
- fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
- fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
-
- fadt->cst_cnt = 0xe3;
- fadt->p_lvl2_lat = 101;
- fadt->p_lvl3_lat = 1001;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 1;
- fadt->duty_width = 3;
- fadt->day_alrm = 0; /* 0x7d these have to be */
- fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
- fadt->century = 0; /* 0x7f to make rtc alrm work */
- fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
- fadt->flags = 0x0001c1a5;/* 0x25; */
-
- fadt->res2 = 0;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 6;
- fadt->x_firmware_ctl_l = (u32) facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32) dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 4;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 2;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 32;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/amd/dbm690t/get_bus_conf.c b/src/mainboard/amd/dbm690t/get_bus_conf.c
deleted file mode 100644
index b1b7270802..0000000000
--- a/src/mainboard/amd/dbm690t/get_bus_conf.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_rs690[8];
-u8 bus_sb600[2];
-u32 apicid_sb600;
-
-/*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
-u32 pci1234x[] = {
- 0x0000ff0,
-};
-
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
- 0x20202020,
-};
-
-u32 sbdn_rs690;
-u32 sbdn_sb600;
-
-
-
-static u32 get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- u32 apicid_base;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* do it only once */
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
- sbdn_rs690 = sysconf.sbdn;
- sbdn_sb600 = 0;
-
- for (i = 0; i < 2; i++) {
- bus_sb600[i] = 0;
- }
- for (i = 0; i < 8; i++) {
- bus_rs690[i] = 0;
- }
-
- bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_sb600[0] = bus_rs690[0];
-
- /* sb600 */
- dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
- if (dev) {
- bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- /* rs690 */
- for (i = 1; i < 8; i++) {
- dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
- if (dev) {
- bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
- /* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_sb600 = apicid_base + 0;
-}
diff --git a/src/mainboard/amd/dbm690t/irq_tables.c b/src/mainboard/amd/dbm690t/irq_tables.c
deleted file mode 100644
index 4c2a48dff7..0000000000
--- a/src/mainboard/amd/dbm690t/irq_tables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern u8 bus_rs690[8];
-extern u8 bus_sb600[2];
-extern unsigned long sbdn_sb600;
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_sb600[0];
- pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c
deleted file mode 100644
index e3dfbc529a..0000000000
--- a/src/mainboard/amd/dbm690t/mainboard.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb600/sb600.h>
-
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS 0x0C /* Alert Response Address */
-#define SMBUS_IO_BASE 0x1000
-
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-#define ADT7461_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
- do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-
-
-/********************************************************
-* dbm690t uses a BCM5789 as on-board NIC.
-* It has a pin named LOW_POWER to enable it into LOW POWER state.
-* In order to run NIC, we should let it out of Low power state. This pin is
-* controlled by sb600 GPM3.
-* RRG4.2.3 GPM as GPIO
-* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
-* I/O C50, C51, C52, PM I/O94, 95, 96.
-* RRG4.2.3.1 GPM pins as Input
-* RRG4.2.3.2 GPM pins as Output
-********************************************************/
-static void enable_onboard_nic(void)
-{
- u8 byte;
-
- printk(BIOS_INFO, "%s.\n", __func__);
-
- /* set index register 0C50h to 13h (miscellaneous control) */
- outb(0x13, 0xC50); /* CMIndex */
-
- /* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
- byte = inb(0xC51);
- byte &= 0x3F;
- byte |= 0x40;
- outb(byte, 0xC51);
-
- /* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */
- byte = inb(0xC52);
- byte &= ~0x8;
- outb(byte, 0xC52);
-
- /* set CM data register 0C51h bits [7:6] to 10b to set Output state control */
- byte = inb(0xC51);
- byte &= 0x3F;
- byte |= 0x80; /* 7:6=10 */
- outb(byte, 0xC51);
-
- /* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */
- byte = inb(0xC52);
- byte &= ~0x8;
- outb(byte, 0xC52);
-}
-
-/********************************************************
-* dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
- u8 byte;
- struct device *sm_dev;
- struct device *ide_dev;
-
- printk(BIOS_INFO, "%s.\n", __func__);
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- pci_write_config8(ide_dev, 0x56, byte);
-}
-
-/*
- * set thermal config
- */
-static void set_thermal_config(void)
-{
- u8 byte;
- u16 word;
- struct device *sm_dev;
-
- /* set ADT 7461 */
- ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
- ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
- ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
- ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
-
- ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
- ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
-
- byte = ADT7461_read_byte(0x02); /* read status register to clear it */
- ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
- printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
-
- /* sb600 settings for thermal config */
- /* set SB600 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to input */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
-}
-
-/*************************************************
-* enable the dedicated function in dbm690t board.
-* This function called early than rs690_enable.
-*************************************************/
-static void mainboard_enable(struct device *dev)
-{
- printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev);
-
- enable_onboard_nic();
- get_ide_dma66();
- set_thermal_config();
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c
deleted file mode 100644
index af67c5413d..0000000000
--- a/src/mainboard/amd/dbm690t/mptable.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern u8 bus_rs690[8];
-extern u8 bus_sb600[2];
-
-extern u32 apicid_sb600;
-
-extern u32 sbdn_rs690;
-extern u32 sbdn_sb600;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- u32 dword;
- u8 byte;
-
- dev =
- dev_find_slot(bus_sb600[0],
- PCI_DEVFN(sbdn_sb600 + 0x14, 0));
- if (dev) {
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600,
- 0x11,(void *) dword);
-
- /* Initialize interrupt mapping */
- /* aza */
- byte = pci_read_config8(dev, 0x63);
- byte &= 0xf8;
- byte |= 0; /* 0: INTA, ...., 7: INTH */
- pci_write_config8(dev, 0x63, byte);
-
- /* SATA */
- dword = pci_read_config32(dev, 0xac);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
- /* dword |= 1 << 22; PIC and APIC co exists */
- pci_write_config32(dev, 0xac, dword);
-
- /*
- * 00:12.0: PROG SATA : INT F
- * 00:13.0: INTA USB_0
- * 00:13.1: INTB USB_1
- * 00:13.2: INTC USB_2
- * 00:13.3: INTD USB_3
- * 00:13.4: INTC USB_4
- * 00:13.5: INTD USB2
- * 00:14.1: INTA IDE
- * 00:14.2: Prog HDA : INT E
- * 00:14.5: INTB ACI
- * 00:14.6: INTB MCI
- */
- }
- }
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/dbm690t/resourcemap.c b/src/mainboard/amd/dbm690t/resourcemap.c
deleted file mode 100644
index 7d13a6550c..0000000000
--- a/src/mainboard/amd/dbm690t/resourcemap.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_dbm690t_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
deleted file mode 100644
index e1c92ac7b6..0000000000
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include <spd.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/early_setup.c"
-#include "southbridge/amd/sb600/early_setup.c"
-#include <northbridge/amd/amdk8/f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(u32 device, u32 address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
- int needs_reset = 0;
- u32 bsp_apicid = 0;
- msr_t msr;
- struct cpuid_result cpuid1;
- struct sys_info *sysinfo = &sysinfo_car;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- /* sb600_lpc_port80(); */
- sb600_pci_port80();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- enable_rs690_dev8();
- sb600_lpc_init();
-
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
- printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
-
- setup_dbm690t_resource_map();
-
- setup_coherent_ht_domain();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched */
- wait_all_core0_started();
- start_other_cores();
-#endif
- wait_all_aps_started(bsp_apicid);
-
- ht_setup_chains_x(sysinfo);
-
- /* run _early_setup before soft-reset. */
- rs690_early_setup();
- sb600_early_setup();
-
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- cpuid1 = cpuid(0x80000007);
- if ((cpuid1.edx & 0x6) == 0x6) {
- /* Read FIDVID_STATUS */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
-
- /* show final fid and vid */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
- } else {
- printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
- }
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- rs690_htinit();
- printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
-
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now; */
- printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
- sysinfo->nodes, sysinfo->ctrl, spd_addr);
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
- rs690_before_pci_init();
- sb600_before_pci_init();
-}
diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig
deleted file mode 100644
index 8861b4aad5..0000000000
--- a/src/mainboard/amd/mahogany/Kconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-if BOARD_AMD_MAHOGANY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_AM2
- select DIMM_DDR2
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_RS780
- select SOUTHBRIDGE_AMD_SB700
- select SUPERIO_ITE_IT8718F
- select HAVE_ACPI_TABLES
- select HAVE_MP_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_OPTION_TABLE
- select LIFT_BSP_APIC_ID
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select BOARD_ROMSIZE_KB_1024
- select GFXUMA
- select QRANK_DIMM_SUPPORT
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default amd/mahogany
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "MAHOGANY"
-
-config MAX_CPUS
- int
- default 8
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-config VGA_BIOS_ID
- string
- default "1002,9615"
-
-endif # BOARD_AMD_MAHOGANY
diff --git a/src/mainboard/amd/mahogany/Kconfig.name b/src/mainboard/amd/mahogany/Kconfig.name
deleted file mode 100644
index 5dde9cb718..0000000000
--- a/src/mainboard/amd/mahogany/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AMD_MAHOGANY
- bool "Mahogany"
diff --git a/src/mainboard/amd/mahogany/acpi/ide.asl b/src/mainboard/amd/mahogany/acpi/ide.asl
deleted file mode 100644
index 694ab235b6..0000000000
--- a/src/mainboard/amd/mahogany/acpi/ide.asl
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "ide.asl"
- }
- }
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
- 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
- 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
- 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
- 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
- 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
- Field(ICRG, AnyAcc, NoLock, Preserve)
-{
- PPTS, 8, /* Primary PIO Slave Timing */
- PPTM, 8, /* Primary PIO Master Timing */
- OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
- PMTM, 8, /* Primary MWDMA Master Timing */
- OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
- OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
- PPSM, 4, /* Primary PIO slave Mode */
- OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
- OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
- PDSM, 4, /* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
- Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
- Increment(Local0)
- Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
- Increment(Local1)
- Return(Multiply(30, Add(Local0, Local1)))
-}
-
-Device(PRID)
-{
- Name (_ADR, Zero)
- Method(_GTM, 0, Serialized)
- {
- NAME(OTBF, Buffer(20) { /* out buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
- CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
- /* Just return if the channel is disabled */
- If(And(PPCR, 0x01)) { /* primary PIO control */
- Return(OTBF)
- }
-
- /* Always tell them independent timing available and IOChannelReady used on both drives */
- Or(BFFG, 0x1A, BFFG)
-
- Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
- Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
-
- If(And(PDCR, 0x01)) { /* It's under UDMA mode */
- Or(BFFG, 0x01, BFFG)
- Store(DerefOf(Index(UDTT, PDMM)), DSD0)
- }
- Else {
- Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
- }
-
- If(And(PDCR, 0x02)) { /* It's under UDMA mode */
- Or(BFFG, 0x04, BFFG)
- Store(DerefOf(Index(UDTT, PDSM)), DSD1)
- }
- Else {
- Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
- }
-
- Return(OTBF) /* out buffer */
- } /* End Method(_GTM) */
-
- Method(_STM, 3, Serialized)
- {
- NAME(INBF, Buffer(20) { /* in buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
- CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
- Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
- Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
- Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
- Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
-
- Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
- Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
-
- If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDMM,)
- Or(PDCR, 0x01, PDCR)
- }
- Else {
- If(LNotEqual(DSD0, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTM)
- }
- }
-
- If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDSM,)
- Or(PDCR, 0x02, PDCR)
- }
- Else {
- If(LNotEqual(DSD1, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTS)
- }
- }
- /* Return(INBF) */
- } /*End Method(_STM) */
- Device(MST)
- {
- Name(_ADR, 0)
- Method(_GTF, 0, Serialized) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xA0, CMDA)
- Store(0xA0, CMDB)
- Store(0xA0, CMDC)
-
- Or(PPMM, 0x08, POMD)
-
- If(And(PDCR, 0x01)) {
- Or(PDMM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTM),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(MST) */
-
- Device(SLAV)
- {
- Name(_ADR, 1)
- Method(_GTF, 0, Serialized) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xB0, CMDA)
- Store(0xB0, CMDB)
- Store(0xB0, CMDC)
-
- Or(PPSM, 0x08, POMD)
-
- If(And(PDCR, 0x02)) {
- Or(PDSM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTS),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/mahogany/acpi/routing.asl b/src/mainboard/amd/mahogany/acpi/routing.asl
deleted file mode 100644
index ab168ce4fc..0000000000
--- a/src/mainboard/amd/mahogany/acpi/routing.asl
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "routing.asl"
- }
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
- Name(PR0, Package(){
- /* NB devices */
- /* Bus 0, Dev 0 - RS780 Host Controller */
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, INTC, 0 },
- Package(){0x0002FFFF, 1, INTD, 0 },
- Package(){0x0002FFFF, 2, INTA, 0 },
- Package(){0x0002FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, INTA, 0 },
- Package(){0x0004FFFF, 1, INTB, 0 },
- Package(){0x0004FFFF, 2, INTC, 0 },
- Package(){0x0004FFFF, 3, INTD, 0 },
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- /* Package(){0x0005FFFF, 0, INTB, 0 }, */
- /* Package(){0x0005FFFF, 1, INTC, 0 }, */
- /* Package(){0x0005FFFF, 2, INTD, 0 }, */
- /* Package(){0x0005FFFF, 3, INTA, 0 }, */
- /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
- Package(){0x0006FFFF, 0, INTC, 0 },
- Package(){0x0006FFFF, 1, INTD, 0 },
- Package(){0x0006FFFF, 2, INTA, 0 },
- Package(){0x0006FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
- Package(){0x0007FFFF, 0, INTD, 0 },
- Package(){0x0007FFFF, 1, INTA, 0 },
- Package(){0x0007FFFF, 2, INTB, 0 },
- Package(){0x0007FFFF, 3, INTC, 0 },
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0011FFFF, 0, INTA, 0 },
-
- /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
- * EHCI, dev 18, 19 func 2 */
- Package(){0x0012FFFF, 0, INTA, 0 },
- Package(){0x0012FFFF, 1, INTB, 0 },
- Package(){0x0012FFFF, 2, INTC, 0 },
-
- Package(){0x0013FFFF, 0, INTC, 0 },
- Package(){0x0013FFFF, 1, INTD, 0 },
- Package(){0x0013FFFF, 2, INTA, 0 },
-
- /* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
- Package(){0x0014FFFF, 0, INTA, 0 },
- Package(){0x0014FFFF, 1, INTB, 0 },
- Package(){0x0014FFFF, 2, INTC, 0 },
- Package(){0x0014FFFF, 3, INTD, 0 },
- })
-
- Name(APR0, Package(){
- /* NB devices in APIC mode */
- /* Bus 0, Dev 0 - RS780 Host Controller */
-
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Package(){0x0001FFFF, 0, 0, 18 }, */
- /* Package(){0x0001FFFF, 1, 0, 19 }, */
-
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, 0, 18 },
- /* Package(){0x0002FFFF, 1, 0, 19 }, */
- /* Package(){0x0002FFFF, 2, 0, 16 }, */
- /* Package(){0x0002FFFF, 3, 0, 17 }, */
-
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){0x0003FFFF, 0, 0, 19 },
-
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, 0, 16 },
- /* Package(){0x0004FFFF, 1, 0, 17 }, */
- /* Package(){0x0004FFFF, 2, 0, 18 }, */
- /* Package(){0x0004FFFF, 3, 0, 19 }, */
-
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- /* Package(){0x0005FFFF, 0, 0, 17 }, */
- /* Package(){0x0005FFFF, 1, 0, 18 }, */
- /* Package(){0x0005FFFF, 2, 0, 19 }, */
- /* Package(){0x0005FFFF, 3, 0, 16 }, */
-
- /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
- /* Package(){0x0006FFFF, 0, 0, 18 }, */
- /* Package(){0x0006FFFF, 1, 0, 19 }, */
- /* Package(){0x0006FFFF, 2, 0, 16 }, */
- /* Package(){0x0006FFFF, 3, 0, 17 }, */
-
- /* Bus 0, Dev 7 - PCIe Bridge for network card */
- /* Package(){0x0007FFFF, 0, 0, 19 }, */
- /* Package(){0x0007FFFF, 1, 0, 16 }, */
- /* Package(){0x0007FFFF, 2, 0, 17 }, */
- /* Package(){0x0007FFFF, 3, 0, 18 }, */
-
- /* Bus 0, Dev 9 - PCIe Bridge for network card */
- Package(){0x0009FFFF, 0, 0, 17 },
- /* Package(){0x0009FFFF, 1, 0, 16 }, */
- /* Package(){0x0009FFFF, 2, 0, 17 }, */
- /* Package(){0x0009FFFF, 3, 0, 18 }, */
- /* Bus 0, Dev A - PCIe Bridge for network card */
- Package(){0x000AFFFF, 0, 0, 18 },
- /* Package(){0x000AFFFF, 1, 0, 16 }, */
- /* Package(){0x000AFFFF, 2, 0, 17 }, */
- /* Package(){0x000AFFFF, 3, 0, 18 }, */
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices in APIC mode */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0011FFFF, 0, 0, 22 },
-
- /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
- * EHCI, dev 18, 19 func 2 */
- Package(){0x0012FFFF, 0, 0, 16 },
- Package(){0x0012FFFF, 1, 0, 17 },
- Package(){0x0012FFFF, 2, 0, 18 },
-
- Package(){0x0013FFFF, 0, 0, 18 },
- Package(){0x0013FFFF, 1, 0, 19 },
- Package(){0x0013FFFF, 2, 0, 16 },
-
- /* Package(){0x00140000, 0, 0, 16 }, */
-
- /* Package(){0x00130004, 2, 0, 18 }, */
- /* Package(){0x00130005, 3, 0, 19 }, */
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
- Package(){0x0014FFFF, 0, 0, 16 },
- Package(){0x0014FFFF, 1, 0, 17 },
- Package(){0x0014FFFF, 2, 0, 18 },
- Package(){0x0014FFFF, 3, 0, 19 },
- /* Package(){0x00140004, 2, 0, 18 }, */
- /* Package(){0x00140004, 3, 0, 19 }, */
- /* Package(){0x00140005, 1, 0, 17 }, */
- /* Package(){0x00140006, 1, 0, 17 }, */
- })
-
- Name(PR1, Package(){
- /* Internal graphics - RS780 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, INTA, 0 },
- Package(){0x0005FFFF, 1, INTB, 0 },
- Package(){0x0005FFFF, 2, INTC, 0 },
- Package(){0x0005FFFF, 3, INTD, 0 },
- })
-
- Name(APR1, Package(){
- /* Internal graphics - RS780 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, 0, 18 },
- Package(){0x0005FFFF, 1, 0, 19 },
- /* Package(){0x0005FFFF, 2, 0, 20 }, */
- /* Package(){0x0005FFFF, 3, 0, 17 }, */
- })
-
- Name(PS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, INTA, 0 },
- Package(){0x0000FFFF, 1, INTB, 0 },
- Package(){0x0000FFFF, 2, INTC, 0 },
- Package(){0x0000FFFF, 3, INTD, 0 },
- })
-
- Name(APS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, 0, 16 },
- Package(){0x0000FFFF, 1, 0, 17 },
- Package(){0x0000FFFF, 2, 0, 18 },
- Package(){0x0000FFFF, 3, 0, 19 },
- })
-
- Name(PS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, INTB, 0 },
- Package(){0x0000FFFF, 1, INTC, 0 },
- Package(){0x0000FFFF, 2, INTD, 0 },
- Package(){0x0000FFFF, 3, INTA, 0 },
- })
-
- Name(APS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
-
- Name(APS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, 0, 19 },
- Package(){0x0000FFFF, 1, 0, 16 },
- Package(){0x0000FFFF, 2, 0, 17 },
- Package(){0x0000FFFF, 3, 0, 18 },
- })
- Name(PS9, Package(){
- /* PCIe slot - Hooked to PCIe slot 9 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
-
- Name(APS9, Package(){
- /* PCIe slot - Hooked to PCIe slot 9 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
- Name(PSa, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
-
- Name(APSa, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PCIB, Package(){
- /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
- Package(){0x0005FFFF, 0, 0, 0x14 },
- Package(){0x0005FFFF, 1, 0, 0x15 },
- Package(){0x0005FFFF, 2, 0, 0x16 },
- Package(){0x0005FFFF, 3, 0, 0x17 },
- Package(){0x0006FFFF, 0, 0, 0x15 },
- Package(){0x0006FFFF, 1, 0, 0x16 },
- Package(){0x0006FFFF, 2, 0, 0x17 },
- Package(){0x0006FFFF, 3, 0, 0x14 },
- Package(){0x0007FFFF, 0, 0, 0x16 },
- Package(){0x0007FFFF, 1, 0, 0x17 },
- Package(){0x0007FFFF, 2, 0, 0x14 },
- Package(){0x0007FFFF, 3, 0, 0x15 },
- })
-}
diff --git a/src/mainboard/amd/mahogany/acpi/sata.asl b/src/mainboard/amd/mahogany/acpi/sata.asl
deleted file mode 100644
index cb9b221ba3..0000000000
--- a/src/mainboard/amd/mahogany/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(SATA) {
- Name(_ADR, 0x00110000)
- #include "sata.asl"
- }
- }
-}
-*/
-
-Name(STTM, Buffer(20) {
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
- \_GPE._L1F()
-}
-
-Device(PMRY)
-{
- Name(_ADR, 0)
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(PMST) {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P0IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- }/* end of PMST */
-
- Device(PSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P1IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of PSLA */
-} /* end of PMRY */
-
-
-Device(SEDY)
-{
- Name(_ADR, 1) /* IDE Scondary Channel */
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(SMST)
- {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P2IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SMST */
-
- Device(SSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P3IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SSLA */
-} /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
- Method(_L1F,0x0,NotSerialized) {
- if (\_SB.P0PR) {
- if (LGreater(\_SB.P0IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P0PR)
- }
-
- if (\_SB.P1PR) {
- if (LGreater(\_SB.P1IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P1PR)
- }
-
- if (\_SB.P2PR) {
- if (LGreater(\_SB.P2IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P2PR)
- }
-
- if (\_SB.P3PR) {
- if (LGreater(\_SB.P3IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P3PR)
- }
- }
-}
diff --git a/src/mainboard/amd/mahogany/acpi/usb.asl b/src/mainboard/amd/mahogany/acpi/usb.asl
deleted file mode 100644
index d4fc433beb..0000000000
--- a/src/mainboard/amd/mahogany/acpi/usb.asl
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "usb.asl"
- }
-*/
-Method(UCOC, 0) {
- Sleep(20)
- Store(0x13,CMTI)
- Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
- Scope (\_GPE) {
- Method (_L13) {
- UCOC()
- if(LEqual(GPB0,PLC0)) {
- Not(PLC0,PLC0)
- Store(PLC0, \_SB.PT0D)
- }
- }
- }
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
- Scope (\_GPE) {
- Method (_L14) {
- UCOC()
- if (LEqual(GPB1,PLC1)) {
- Not(PLC1,PLC1)
- Store(PLC1, \_SB.PT1D)
- }
- }
- }
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
- Scope (\_GPE) {
- Method (_L15) {
- UCOC()
- if (LEqual(GPB2,PLC2)) {
- Not(PLC2,PLC2)
- Store(PLC2, \_SB.PT2D)
- }
- }
- }
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
- Scope (\_GPE) {
- Method (_L16) {
- UCOC()
- if (LEqual(GPB3,PLC3)) {
- Not(PLC3,PLC3)
- Store(PLC3, \_SB.PT3D)
- }
- }
- }
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
- Scope (\_GPE) {
- Method (_L19) {
- UCOC()
- if (LEqual(GPB4,PLC4)) {
- Not(PLC4,PLC4)
- Store(PLC4, \_SB.PT4D)
- }
- }
- }
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
- Scope (\_GPE) {
- Method (_L1A) {
- UCOC()
- if (LEqual(GPB5,PLC5)) {
- Not(PLC5,PLC5)
- Store(PLC5, \_SB.PT5D)
- }
- }
- }
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
- Scope (\_GPE) {
- /* Method (_L1C) { */
- Method (_L06) {
- UCOC()
- if (LEqual(GPB6,PLC6)) {
- Not(PLC6,PLC6)
- Store(PLC6, \_SB.PT6D)
- }
- }
- }
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
- Scope (\_GPE) {
- /* Method (_L1D) { */
- Method (_L07) {
- UCOC()
- if (LEqual(GPB7,PLC7)) {
- Not(PLC7,PLC7)
- Store(PLC7, \_SB.PT7D)
- }
- }
- }
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
- Scope (\_GPE) {
- Method (_L17) {
- if (LEqual(G8IS,PLC8)) {
- Not(PLC8,PLC8)
- Store(PLC8, \_SB.PT8D)
- }
- }
- }
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
- Scope (\_GPE) {
- Method (_L0E) {
- if (LEqual(G9IS,0)) {
- Store(1,\_SB.PT9D)
- }
- }
- }
-}
diff --git a/src/mainboard/amd/mahogany/acpi_tables.c b/src/mainboard/amd/mahogany/acpi_tables.c
deleted file mode 100644
index 26e20221a0..0000000000
--- a/src/mainboard/amd/mahogany/acpi_tables.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include <arch/cpu.h>
-#include <southbridge/amd/sb700/sb700.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- get_bus_conf();
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB700 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
- IO_APIC_ADDR, 0);
-
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high */
-
- /* create all subtables for processors */
- /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
- /* 1: LINT1 connect to NMI */
-
- return current;
-}
diff --git a/src/mainboard/amd/mahogany/board_info.txt b/src/mainboard/amd/mahogany/board_info.txt
deleted file mode 100644
index 979c7c23b5..0000000000
--- a/src/mainboard/amd/mahogany/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Board name: DB780E (Mahogany)
-Category: eval
-ROM protocol: SPI
diff --git a/src/mainboard/amd/mahogany/cmos.layout b/src/mainboard/amd/mahogany/cmos.layout
deleted file mode 100644
index e22e68a15a..0000000000
--- a/src/mainboard/amd/mahogany/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-##
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/mahogany/devicetree.cb b/src/mainboard/amd/mahogany/devicetree.cb
deleted file mode 100644
index 56efd84247..0000000000
--- a/src/mainboard/amd/mahogany/devicetree.cb
+++ /dev/null
@@ -1,121 +0,0 @@
-#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_AM2
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1022 0x3060 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on # southbridge
- chip southbridge/amd/rs780
- device pci 0.0 on end # HT 0x9600
- device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
- device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
- device pci 3.0 on end # PCIE P2P bridge 0x960b
- device pci 4.0 on end # PCIE P2P bridge 0x9604
- device pci 5.0 off end # PCIE P2P bridge 0x9605
- device pci 6.0 off end # PCIE P2P bridge 0x9606
- device pci 7.0 off end # PCIE P2P bridge 0x9607
- device pci 8.0 off end # NB/SB Link P2P bridge
- device pci 9.0 on end #
- device pci a.0 on end #
- register "gppsb_configuration" = "1" # Configuration B
- register "gpp_configuration" = "3" # Configuration D default
- register "port_enable" = "0x6fc"
- register "gfx_dev2_dev3" = "1"
- register "gfx_dual_slot" = "1"
- register "gfx_lane_reversal" = "0"
- register "gfx_tmds" = "0"
- register "gfx_compliance" = "0"
- register "gfx_reconfiguration" = "1"
- register "gfx_link_width" = "0"
- end
- chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus
- device pci 11.0 on end # SATA
- device pci 12.0 on end # USB
- device pci 12.1 on end # USB
- device pci 12.2 on end # USB
- device pci 13.0 on end # USB
- device pci 13.1 on end # USB
- device pci 13.2 on end # USB
- device pci 14.0 on # SM
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 0-1-1
- device i2c 53 on end
- end
- end # SM
- device pci 14.1 on end # IDE 0x439c
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC 0x439d
- chip superio/ite/it8718f
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 off end # EC
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.6 on # Mouse
- irq 0x70 = 12
- end
- device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
- end
- device pnp 2e.8 off # MIDI
- io 0x60 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.9 off # GAME
- io 0x60 = 0x220
- end
- device pnp 2e.a off end # CIR
- end #superio/ite/it8718f
- end #LPC
- device pci 14.4 on end # PCI 0x4384
- device pci 14.5 on end # USB 2
- register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
- end #southbridge/amd/sb700
- end # device pci 18.0
-
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end #northbridge/amd/amdk8
- end #domain
-end #northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/amd/mahogany/dsdt.asl b/src/mainboard/amd/mahogany/dsdt.asl
deleted file mode 100644
index dfffa871e5..0000000000
--- a/src/mainboard/amd/mahogany/dsdt.asl
+++ /dev/null
@@ -1,1690 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "AMD ", /* OEMID */
- "COREBOOT", /* TABLE ID */
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
-
- /* Data to be patched by the BIOS during POST */
- /* FIXME the patching is not done yet! */
- /* Memory related values */
- Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
-
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
-
- /* USB overcurrent mapping pins. */
- Name(UOM0, 0)
- Name(UOM1, 2)
- Name(UOM2, 0)
- Name(UOM3, 7)
- Name(UOM4, 2)
- Name(UOM5, 2)
- Name(UOM6, 6)
- Name(UOM7, 2)
- Name(UOM8, 6)
- Name(UOM9, 6)
-
- /* Some global data */
- Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PMOD, One) /* Assume APIC */
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- /* PCI Error control register */
- OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
- Field(PERC, ByteAcc, NoLock, Preserve) {
- SENS, 0x00000001,
- PENS, 0x00000001,
- SENE, 0x00000001,
- PENE, 0x00000001,
- }
-
- /* Client Management index/data registers */
- OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
- Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
- /* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
- }
-
- /* GPM Port register */
- OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
- Field(GPT, ByteAcc, NoLock, Preserve) {
- GPB0,1,
- GPB1,1,
- GPB2,1,
- GPB3,1,
- GPB4,1,
- GPB5,1,
- GPB6,1,
- GPB7,1,
- }
-
- /* Flash ROM program enable register */
- OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
- Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
- FLRE, 0x00000001,
- }
-
- /* PM2 index/data registers */
- OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
- Field(PM2R, ByteAcc, NoLock, Preserve) {
- PM2I, 0x00000008,
- PM2D, 0x00000008,
- }
-
- /* Power Management I/O registers */
- OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
- Field(PIOR, ByteAcc, NoLock, Preserve) {
- PIOI, 0x00000008,
- PIOD, 0x00000008,
- }
- IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
- Offset(0x00), /* MiscControl */
- , 1,
- T1EE, 1,
- T2EE, 1,
- Offset(0x01), /* MiscStatus */
- , 1,
- T1E, 1,
- T2E, 1,
- Offset(0x04), /* SmiWakeUpEventEnable3 */
- , 7,
- SSEN, 1,
- Offset(0x07), /* SmiWakeUpEventStatus3 */
- , 7,
- CSSM, 1,
- Offset(0x10), /* AcpiEnable */
- , 6,
- PWDE, 1,
- Offset(0x1C), /* ProgramIoEnable */
- , 3,
- MKME, 1,
- IO3E, 1,
- IO2E, 1,
- IO1E, 1,
- IO0E, 1,
- Offset(0x1D), /* IOMonitorStatus */
- , 3,
- MKMS, 1,
- IO3S, 1,
- IO2S, 1,
- IO1S, 1,
- IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
- APEB, 16,
- Offset(0x36), /* GEvtLevelConfig */
- , 6,
- ELC6, 1,
- ELC7, 1,
- Offset(0x37), /* GPMLevelConfig0 */
- , 3,
- PLC0, 1,
- PLC1, 1,
- PLC2, 1,
- PLC3, 1,
- PLC8, 1,
- Offset(0x38), /* GPMLevelConfig1 */
- , 1,
- PLC4, 1,
- PLC5, 1,
- , 1,
- PLC6, 1,
- PLC7, 1,
- Offset(0x3B), /* PMEStatus1 */
- GP0S, 1,
- GM4S, 1,
- GM5S, 1,
- APS, 1,
- GM6S, 1,
- GM7S, 1,
- GP2S, 1,
- STSS, 1,
- Offset(0x55), /* SoftPciRst */
- SPRE, 1,
- , 1,
- , 1,
- PNAT, 1,
- PWMK, 1,
- PWNS, 1,
-
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
-
- Offset(0x65), /* UsbPMControl */
- , 4,
- URRE, 1,
- Offset(0x68), /* MiscEnable68 */
- , 3,
- TMTE, 1,
- , 1,
- Offset(0x92), /* GEVENTIN */
- , 7,
- E7IS, 1,
- Offset(0x96), /* GPM98IN */
- G8IS, 1,
- G9IS, 1,
- Offset(0x9A), /* EnhanceControl */
- ,7,
- HPDE, 1,
- Offset(0xA8), /* PIO7654Enable */
- IO4E, 1,
- IO5E, 1,
- IO6E, 1,
- IO7E, 1,
- Offset(0xA9), /* PIO7654Status */
- IO4S, 1,
- IO5S, 1,
- IO6S, 1,
- IO7S, 1,
- }
-
- /* PM1 Event Block
- * First word is PM1_Status, Second word is PM1_Enable
- */
- OperationRegion(P1EB, SystemIO, APEB, 0x04)
- Field(P1EB, ByteAcc, NoLock, Preserve) {
- TMST, 1,
- , 3,
- BMST, 1,
- GBST, 1,
- Offset(0x01),
- PBST, 1,
- , 1,
- RTST, 1,
- , 3,
- PWST, 1,
- SPWS, 1,
- Offset(0x02),
- TMEN, 1,
- , 4,
- GBEN, 1,
- Offset(0x03),
- PBEN, 1,
- , 1,
- RTEN, 1,
- , 3,
- PWDA, 1,
- }
-
- Scope(\_SB) {
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
- /* Byte offsets are computed using the following technique:
- * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
- * The 8 comes from 8 functions per device, and 4096 bytes per function config space
- */
- Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
- STB5, 32,
- Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
- PT0D, 1,
- PT1D, 1,
- PT2D, 1,
- PT3D, 1,
- PT4D, 1,
- PT5D, 1,
- PT6D, 1,
- PT7D, 1,
- PT8D, 1,
- PT9D, 1,
- Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
- SBIE, 1,
- SBME, 1,
- Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
- SBRI, 8,
- Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
- SBB1, 32,
- Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
- ,14,
- P92E, 1, /* Port92 decode enable */
- }
-
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
- Field(SB5, AnyAcc, NoLock, Preserve){
- /* Port 0 */
- Offset(0x120), /* Port 0 Task file status */
- P0ER, 1,
- , 2,
- P0DQ, 1,
- , 3,
- P0BY, 1,
- Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
- , 4,
- P0IS, 4,
- Offset(0x12C), /* Port 0 Serial ATA control */
- P0DI, 4,
- Offset(0x130), /* Port 0 Serial ATA error */
- , 16,
- P0PR, 1,
-
- /* Port 1 */
- offset(0x1A0), /* Port 1 Task file status */
- P1ER, 1,
- , 2,
- P1DQ, 1,
- , 3,
- P1BY, 1,
- Offset(0x1A8), /* Port 1 Serial ATA status */
- P1DD, 4,
- , 4,
- P1IS, 4,
- Offset(0x1AC), /* Port 1 Serial ATA control */
- P1DI, 4,
- Offset(0x1B0), /* Port 1 Serial ATA error */
- , 16,
- P1PR, 1,
-
- /* Port 2 */
- Offset(0x220), /* Port 2 Task file status */
- P2ER, 1,
- , 2,
- P2DQ, 1,
- , 3,
- P2BY, 1,
- Offset(0x228), /* Port 2 Serial ATA status */
- P2DD, 4,
- , 4,
- P2IS, 4,
- Offset(0x22C), /* Port 2 Serial ATA control */
- P2DI, 4,
- Offset(0x230), /* Port 2 Serial ATA error */
- , 16,
- P2PR, 1,
-
- /* Port 3 */
- Offset(0x2A0), /* Port 3 Task file status */
- P3ER, 1,
- , 2,
- P3DQ, 1,
- , 3,
- P3BY, 1,
- Offset(0x2A8), /* Port 3 Serial ATA status */
- P3DD, 4,
- , 4,
- P3IS, 4,
- Offset(0x2AC), /* Port 3 Serial ATA control */
- P3DI, 4,
- Offset(0x2B0), /* Port 3 Serial ATA error */
- , 16,
- P3PR, 1,
- }
- }
-
-
- #include "acpi/routing.asl"
-
- Scope(\_SB) {
-
- Method(OSFL, 0){
-
- if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
-
- if(CondRefOf(\_OSI))
- {
- Store(1, OSVR) /* Assume some form of XP */
- if (\_OSI("Windows 2006")) /* Vista */
- {
- Store(2, OSVR)
- }
- } else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSVR) /* Linux */
- } Else {
- Store(4, OSVR) /* Gotta be WinCE */
- }
- }
- Return(OSVR)
- }
-
- Method(_PIC, 0x01, NotSerialized)
- {
- If (Arg0)
- {
- \_SB.CIRQ()
- }
- Store(Arg0, PMOD)
- }
- Method(CIRQ, 0x00, NotSerialized){
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTA._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTE._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_PRS\n") */
- Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
- } /* End Scope(_SB) */
-
- #include <southbridge/amd/common/acpi/sleepstates.asl>
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- \_SB.PCI0.SIOS (Arg0)
- } /* End Method(\_PTS) */
-
- /*
- * The following method results in a "not a valid reserved NameSeg"
- * warning so I have commented it out for the duration. It isn't
- * used, so it could be removed.
- *
- *
- * \_GTS OEM Going To Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- *
- * Method(\_GTS, 1) {
- * DBGO("\\_GTS\n")
- * DBGO("From S0 to S")
- * DBGO(Arg0)
- * DBGO("\n")
- * }
- */
-
- /*
- * \_BFS OEM Back From Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- */
- Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
- }
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- Store(1,HPDE)
-
- /* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, Local1)
- Store(Local1, PWST)
-
- /* if(DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
- * } else {
- * Store(Arg0, Index(WKST,1))
- * }
- */
- \_SB.PCI0.SIOW ()
- Return(WKST)
- } /* End Method(\_WAK) */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* General event 0 */
- /* Method(_L00) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 1 */
- /* Method(_L01) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 2 */
- /* Method(_L02) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 3 */
- Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* General event 4 */
- /* Method(_L04) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 5 */
- /* Method(_L05) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 6 - Used for GPM6, moved to USB.asl */
- /* Method(_L06) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 7 - Used for GPM7, moved to USB.asl */
- /* Method(_L07) {
- * DBGO("\\_GPE\\_L07\n")
- * }
- */
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
- }
-
- /* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
-
- /* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
-
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
-
- /* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
-
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event - Moved to USB.asl */
- /* Method(_L1A) {
- * DBGO("\\_GPE\\_L1A\n")
- * }
- */
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
-
- /* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
-
- /* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
-
- /* SATA SCI event - Moved to sata.asl */
- /* Method(_L1F) {
- * DBGO("\\_GPE\\_L1F\n")
- * }
- */
-
- } /* End Scope GPE */
-
- #include "acpi/usb.asl"
-
- /* System Bus */
- Scope(\_SB) { /* Start \_SB scope */
- #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0) {
- External (TOM1)
- External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* Dev3 is also an external GFX bridge, not used in Herring */
-
- Device(PBR4) {
- Name(_ADR, 0x00040000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR4 */
-
- Device(PBR5) {
- Name(_ADR, 0x00050000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR5 */
-
- Device(PBR6) {
- Name(_ADR, 0x00060000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR6 */
-
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR7 */
-
- /* GPP */
- Device(PBR9) {
- Name(_ADR, 0x00090000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS9) } /* APIC mode */
- Return (PS9) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR9 */
-
- Device(PBRa) {
- Name(_ADR, 0x000A0000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APSa) } /* APIC mode */
- Return (PSa) /* PIC Mode */
- } /* end _PRT */
- } /* end PBRa */
-
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
-
- /* Describe the Southbridge devices */
- Device(STCR) {
- Name(_ADR, 0x00110000)
- #include "acpi/sata.asl"
- } /* end STCR */
-
- Device(UOH1) {
- Name(_ADR, 0x00130000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH1 */
-
- Device(UOH2) {
- Name(_ADR, 0x00130001)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH2 */
-
- Device(UOH3) {
- Name(_ADR, 0x00130002)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH3 */
-
- Device(UOH4) {
- Name(_ADR, 0x00130003)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH4 */
-
- Device(UOH5) {
- Name(_ADR, 0x00130004)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UEH1) {
- Name(_ADR, 0x00130005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(SBUS) {
- Name(_ADR, 0x00140000)
- } /* end SBUS */
-
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "acpi/ide.asl"
- } /* end IDEC */
-
- Device(AZHD) {
- Name(_ADR, 0x00140002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6C),
- MMDT, 16,
- }
-
- Method(_INI) {
- If(LEqual(OSVR,3)){ /* If we are running Linux */
- Store(zero, NSEN)
- Store(one, NSDO)
- Store(one, NSDI)
- }
- }
- } /* end AZHD */
-
- Device(LIBR) {
- Name(_ADR, 0x00140003)
- /* Method(_INI) {
- * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
- } */ /* End Method(_SB.SBRDG._INI) */
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){8}
- IO(Decode16,0x0070, 0x0070, 0, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){0}
- IO(Decode16, 0x0040, 0x0040, 0, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 0, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){2}
- IO(Decode16,0x0020, 0x0020, 0, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,BusMaster,Transfer8){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
- IRQNoFlags(){13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPTM) {
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
- }
- Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBX)
- Store(HPBA, HPBX)
- Return(CRS)
- }
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- } /* end LIBR */
-
- Device(HPBR) {
- Name(_ADR, 0x00140004)
- } /* end HostPciBr */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- } /* end Ac97modem */
-
- /* ITE8718 Support */
- OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
- Field (IOID, ByteAcc, NoLock, Preserve)
- {
- SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
- }
-
- IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
- {
- Offset (0x07),
- LDN, 8, /* Logical Device Number */
- Offset (0x20),
- CID1, 8, /* Chip ID Byte 1, 0x87 */
- CID2, 8, /* Chip ID Byte 2, 0x12 */
- Offset (0x30),
- ACTR, 8, /* Function activate */
- Offset (0xF0),
- APC0, 8, /* APC/PME Event Enable Register */
- APC1, 8, /* APC/PME Status Register */
- APC2, 8, /* APC/PME Control Register 1 */
- APC3, 8, /* Environment Controller Special Configuration Register */
- APC4, 8 /* APC/PME Control Register 2 */
- }
-
- /* Enter the 8718 MB PnP Mode */
- Method (EPNP)
- {
- Store(0x87, SIOI)
- Store(0x01, SIOI)
- Store(0x55, SIOI)
- Store(0x55, SIOI) /* 8718 magic number */
- }
- /* Exit the 8718 MB PnP Mode */
- Method (XPNP)
- {
- Store (0x02, SIOI)
- Store (0x02, SIOD)
- }
- /*
- * Keyboard PME is routed to SB700 Gevent3. We can wake
- * up the system by pressing the key.
- */
- Method (SIOS, 1)
- {
- /* We only enable KBD PME for S5. */
- If (LLess (Arg0, 0x05))
- {
- EPNP()
- /* DBGO("8718F\n") */
-
- Store (0x4, LDN)
- Store (One, ACTR) /* Enable EC */
- /*
- Store (0x4, LDN)
- Store (0x04, APC4)
- */ /* falling edge. which mode? Not sure. */
-
- Store (0x4, LDN)
- Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
- Store (0x4, LDN)
- Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
- XPNP()
- }
- }
- Method (SIOW, 0)
- {
- EPNP()
- Store (0x4, LDN)
- Store (Zero, APC0) /* disable keyboard PME */
- Store (0x4, LDN)
- Store (0xFF, APC1) /* clear keyboard PME status */
- XPNP()
- }
-
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
-
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
- }
-
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * ShiftLeft(TOM2, 20, Local0)
- * Subtract(Local0, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-
- Return(CRES) /* note to change the Name buffer */
- } /* end of Method(_SB.PCI0._CRS) */
-
- /*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
- Method(_INI, 0) {
- /* DBGO("\\_SB\\_INI\n") */
- /* DBGO(" DSDT.ASL code from ") */
- /* DBGO(__DATE__) */
- /* DBGO(" ") */
- /* DBGO(__TIME__) */
- /* DBGO("\n Sleep states supported: ") */
- /* DBGO("\n") */
- /* DBGO(" \\_OS=") */
- /* DBGO(\_OS) */
- /* DBGO("\n \\_REV=") */
- /* DBGO(\_REV) */
- /* DBGO("\n") */
-
- /* Determine the OS we're running on */
- OSFL()
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
- * }
- */
- } /* End Method(_SB._INI) */
- } /* End Device(PCI0) */
-
- Device(PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
- } /* End \_SB scope */
-
- Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
- } /* End Scope SI */
-
- #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
-
- /* THERMAL */
- Scope(\_TZ) {
- Name (KELV, 2732)
- Name (THOT, 800)
- Name (TCRT, 850)
-
- ThermalZone(TZ00) {
- Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
- /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
- Return(Add(0, 2730))
- }
- Method(_AL0,0) { /* Returns package of cooling device to turn on */
- /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
- Return(Package() {\_TZ.TZ00.FAN0})
- }
- Device (FAN0) {
- Name(_HID, EISAID("PNP0C0B"))
- Name(_PR0, Package() {PFN0})
- }
-
- PowerResource(PFN0,0,0) {
- Method(_STA) {
- Store(0xF,Local0)
- Return(Local0)
- }
- Method(_ON) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
- }
- Method(_OFF) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
- }
- }
-
- Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
- Return (Add (THOT, KELV))
- }
- Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
- Return (Add (TCRT, KELV))
- }
- Method(_TMP,0) { /* return current temp of this zone */
- Store (SMBR (0x07, 0x4C,, 0x00), Local0)
- If (LGreater (Local0, 0x10)) {
- Store (Local0, Local1)
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400, KELV))
- }
-
- Store (SMBR (0x07, 0x4C, 0x01), Local0)
- /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
- /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
- If (LGreater (Local0, 0x10)) {
- If (LGreater (Local0, Local1)) {
- Store (Local0, Local1)
- }
-
- Multiply (Local1, 10, Local1)
- Return (Add (Local1, KELV))
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400 , KELV))
- }
- } /* end of _TMP */
- } /* end of TZ00 */
- }
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/mahogany/get_bus_conf.c b/src/mainboard/amd/mahogany/get_bus_conf.c
deleted file mode 100644
index 64b3ed7032..0000000000
--- a/src/mainboard/amd/mahogany/get_bus_conf.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_rs780[11];
-u8 bus_sb700[2];
-u32 apicid_sb700;
-
-/*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
-u32 pci1234x[] = {
- 0x0000ff0,
-};
-
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
- 0x20202020,
-};
-
-u32 sbdn_rs780;
-u32 sbdn_sb700;
-
-
-
-static u32 get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- u32 apicid_base;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* do it only once */
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
- sbdn_rs780 = sysconf.sbdn;
- sbdn_sb700 = 0;
-
- for (i = 0; i < 2; i++) {
- bus_sb700[i] = 0;
- }
- for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
- bus_rs780[i] = 0;
- }
-
- bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_sb700[0] = bus_rs780[0];
-
- /* sb700 */
- dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
- if (dev) {
- bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- /* rs780 */
- for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
- dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
- if (dev) {
- bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
- /* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_sb700 = apicid_base + 0;
-}
diff --git a/src/mainboard/amd/mahogany/irq_tables.c b/src/mainboard/amd/mahogany/irq_tables.c
deleted file mode 100644
index ef2a3ec45c..0000000000
--- a/src/mainboard/amd/mahogany/irq_tables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern u8 bus_rs780[8];
-extern u8 bus_sb700[2];
-extern unsigned long sbdn_sb700;
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_sb700[0];
- pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
deleted file mode 100644
index 91b2533fe0..0000000000
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "southbridge/amd/sb700/sb700.h"
-#include "southbridge/amd/sb700/smbus.h"
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-u8 is_dev3_present(void);
-/*
- * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
- * pull it up before training the slot.
- ***/
-void set_pcie_dereset()
-{
- u16 word;
- struct device *sm_dev;
- /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- word = pci_read_config16(sm_dev, 0xA8);
- word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
-}
-
-void set_pcie_reset()
-{
- u16 word;
- struct device *sm_dev;
- /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- word = pci_read_config16(sm_dev, 0xA8);
- word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
-}
-
-u8 is_dev3_present(void)
-{
- return 0;
-}
-/*************************************************
-* enable the dedicated function in mahogany board.
-* This function called early than rs780_enable.
-*************************************************/
-static void mainboard_enable(struct device *dev)
-{
- printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c
deleted file mode 100644
index a5d66785a9..0000000000
--- a/src/mainboard/amd/mahogany/mptable.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern u8 bus_rs780[11];
-extern u8 bus_sb700[2];
-
-extern u32 apicid_sb700;
-
-extern u32 sbdn_rs780;
-extern u32 sbdn_sb700;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- u32 dword;
- u8 byte;
-
- dev =
- dev_find_slot(bus_sb700[0],
- PCI_DEVFN(sbdn_sb700 + 0x14, 0));
- if (dev) {
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700,
- 0x11,(void *) dword);
-
- /* Initialize interrupt mapping */
- /* aza */
- byte = pci_read_config8(dev, 0x63);
- byte &= 0xf8;
- byte |= 0; /* 0: INTA, ...., 7: INTH */
- pci_write_config8(dev, 0x63, byte);
-
- /* SATA */
- dword = pci_read_config32(dev, 0xac);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
- /* dword |= 1 << 22; PIC and APIC co exists */
- pci_write_config32(dev, 0xac, dword);
-
- /*
- * 00:12.0: PROG SATA : INT F
- * 00:13.0: INTA USB_0
- * 00:13.1: INTB USB_1
- * 00:13.2: INTC USB_2
- * 00:13.3: INTD USB_3
- * 00:13.4: INTC USB_4
- * 00:13.5: INTD USB2
- * 00:14.1: INTA IDE
- * 00:14.2: Prog HDA : INT E
- * 00:14.5: INTB ACI
- * 00:14.6: INTB MCI
- */
- }
- }
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/mahogany/resourcemap.c b/src/mainboard/amd/mahogany/resourcemap.c
deleted file mode 100644
index 5c2932e1e1..0000000000
--- a/src/mainboard/amd/mahogany/resourcemap.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mahogany_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
deleted file mode 100644
index 979904a06f..0000000000
--- a/src/mainboard/amd/mahogany/romstage.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8718f/it8718f.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <southbridge/amd/sb700/sb700.h>
-#include <southbridge/amd/sb700/smbus.h>
-#include <northbridge/amd/amdk8/f.h>
-
-unsigned get_sbdn(unsigned bus);
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(u32 device, u32 address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-#include <southbridge/amd/rs780/rs780.h>
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
- int needs_reset = 0;
- u32 bsp_apicid = 0;
- msr_t msr;
- struct cpuid_result cpuid1;
- struct sys_info *sysinfo = &sysinfo_car;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- /* sb7xx_51xx_lpc_port80(); */
- sb7xx_51xx_pci_port80();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- enable_rs780_dev8();
- sb7xx_51xx_lpc_init();
-
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
- printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
-
- setup_mahogany_resource_map();
-
- setup_coherent_ht_domain();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched */
- wait_all_core0_started();
- start_other_cores();
-#endif
- wait_all_aps_started(bsp_apicid);
-
- ht_setup_chains_x(sysinfo);
-
- /* run _early_setup before soft-reset. */
- rs780_early_setup();
- sb7xx_51xx_early_setup();
-
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- cpuid1 = cpuid(0x80000007);
- if ((cpuid1.edx & 0x6) == 0x6) {
- /* Read FIDVID_STATUS */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
-
- /* show final fid and vid */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
- } else {
- printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
- }
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- rs780_htinit();
- printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
-
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now; */
- printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
- sysinfo->nodes, sysinfo->ctrl, spd_addr);
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
- sb7xx_51xx_before_pci_init();
-}
diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig
deleted file mode 100644
index 2296e829ff..0000000000
--- a/src/mainboard/amd/pistachio/Kconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-if BOARD_AMD_PISTACHIO
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_AM2
- select DIMM_DDR2
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_RS690
- select SOUTHBRIDGE_AMD_SB600
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_1024
- select QRANK_DIMM_SUPPORT
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default amd/pistachio
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "Pistachio"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_AMD_PISTACHIO
diff --git a/src/mainboard/amd/pistachio/Kconfig.name b/src/mainboard/amd/pistachio/Kconfig.name
deleted file mode 100644
index bbab2bff49..0000000000
--- a/src/mainboard/amd/pistachio/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AMD_PISTACHIO
- bool "Pistachio"
diff --git a/src/mainboard/amd/pistachio/acpi/ide.asl b/src/mainboard/amd/pistachio/acpi/ide.asl
deleted file mode 100644
index d5badfcb6b..0000000000
--- a/src/mainboard/amd/pistachio/acpi/ide.asl
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "ide.asl"
- }
- }
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
- 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
- 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
- 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
- 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
- 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
- Field(ICRG, AnyAcc, NoLock, Preserve)
-{
- PPTS, 8, /* Primary PIO Slave Timing */
- PPTM, 8, /* Primary PIO Master Timing */
- OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
- PMTM, 8, /* Primary MWDMA Master Timing */
- OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
- OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
- PPSM, 4, /* Primary PIO slave Mode */
- OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
- OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
- PDSM, 4, /* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
- Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
- Increment(Local0)
- Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
- Increment(Local1)
- Return(Multiply(30, Add(Local0, Local1)))
-}
-
-Device(PRID)
-{
- Name (_ADR, Zero)
- Method(_GTM, 0)
- {
- NAME(OTBF, Buffer(20) { /* out buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
- CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
- /* Just return if the channel is disabled */
- If(And(PPCR, 0x01)) { /* primary PIO control */
- Return(OTBF)
- }
-
- /* Always tell them independent timing available and IOChannelReady used on both drives */
- Or(BFFG, 0x1A, BFFG)
-
- Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
- Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
-
- If(And(PDCR, 0x01)) { /* It's under UDMA mode */
- Or(BFFG, 0x01, BFFG)
- Store(DerefOf(Index(UDTT, PDMM)), DSD0)
- }
- Else {
- Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
- }
-
- If(And(PDCR, 0x02)) { /* It's under UDMA mode */
- Or(BFFG, 0x04, BFFG)
- Store(DerefOf(Index(UDTT, PDSM)), DSD1)
- }
- Else {
- Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
- }
-
- Return(OTBF) /* out buffer */
- } /* End Method(_GTM) */
-
- Method(_STM, 3, NotSerialized)
- {
- NAME(INBF, Buffer(20) { /* in buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
- CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
- Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
- Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
- Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
- Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
-
- Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
- Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
-
- If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDMM,)
- Or(PDCR, 0x01, PDCR)
- }
- Else {
- If(LNotEqual(DSD0, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTM)
- }
- }
-
- If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDSM,)
- Or(PDCR, 0x02, PDCR)
- }
- Else {
- If(LNotEqual(DSD1, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTS)
- }
- }
- /* Return(INBF) */
- } /*End Method(_STM) */
- Device(MST)
- {
- Name(_ADR, 0)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xA0, CMDA)
- Store(0xA0, CMDB)
- Store(0xA0, CMDC)
-
- Or(PPMM, 0x08, POMD)
-
- If(And(PDCR, 0x01)) {
- Or(PDMM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTM),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(MST) */
-
- Device(SLAV)
- {
- Name(_ADR, 1)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xB0, CMDA)
- Store(0xB0, CMDB)
- Store(0xB0, CMDC)
-
- Or(PPSM, 0x08, POMD)
-
- If(And(PDCR, 0x02)) {
- Or(PDSM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTS),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/pistachio/acpi/routing.asl b/src/mainboard/amd/pistachio/acpi/routing.asl
deleted file mode 100644
index bcb14e7e37..0000000000
--- a/src/mainboard/amd/pistachio/acpi/routing.asl
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "routing.asl"
- }
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
- Name(PR0, Package(){
- /* NB devices */
- /* Bus 0, Dev 0 - RS690 Host Controller */
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, INTC, 0 },
- Package(){0x0002FFFF, 1, INTD, 0 },
- Package(){0x0002FFFF, 2, INTA, 0 },
- Package(){0x0002FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, INTA, 0 },
- Package(){0x0004FFFF, 1, INTB, 0 },
- Package(){0x0004FFFF, 2, INTC, 0 },
- Package(){0x0004FFFF, 3, INTD, 0 },
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- /* Package(){0x0005FFFF, 0, INTB, 0 }, */
- /* Package(){0x0005FFFF, 1, INTC, 0 }, */
- /* Package(){0x0005FFFF, 2, INTD, 0 }, */
- /* Package(){0x0005FFFF, 3, INTA, 0 }, */
- /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
- Package(){0x0006FFFF, 0, INTC, 0 },
- Package(){0x0006FFFF, 1, INTD, 0 },
- Package(){0x0006FFFF, 2, INTA, 0 },
- Package(){0x0006FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
- Package(){0x0007FFFF, 0, INTD, 0 },
- Package(){0x0007FFFF, 1, INTA, 0 },
- Package(){0x0007FFFF, 2, INTB, 0 },
- Package(){0x0007FFFF, 3, INTC, 0 },
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0012FFFF, 1, INTA, 0 },
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){0x0013FFFF, 0, INTA, 0 },
- Package(){0x0013FFFF, 1, INTB, 0 },
- Package(){0x0013FFFF, 2, INTC, 0 },
- Package(){0x0013FFFF, 3, INTD, 0 },
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
- Package(){0x0014FFFF, 0, INTA, 0 },
- Package(){0x0014FFFF, 1, INTB, 0 },
- Package(){0x0014FFFF, 2, INTC, 0 },
- Package(){0x0014FFFF, 3, INTD, 0 },
- })
-
- Name(APR0, Package(){
- /* NB devices in APIC mode */
- /* Bus 0, Dev 0 - RS690 Host Controller */
-
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Package(){0x0001FFFF, 0, 0, 18 }, */
- /* Package(){0x0001FFFF, 1, 0, 19 }, */
-
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, 0, 18 },
- /* Package(){0x0002FFFF, 1, 0, 19 }, */
- /* Package(){0x0002FFFF, 2, 0, 16 }, */
- /* Package(){0x0002FFFF, 3, 0, 17 }, */
-
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){0x0003FFFF, 0, 0, 19 },
-
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, 0, 16 },
- /* Package(){0x0004FFFF, 1, 0, 17 }, */
- /* Package(){0x0004FFFF, 2, 0, 18 }, */
- /* Package(){0x0004FFFF, 3, 0, 19 }, */
-
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- Package(){0x0005FFFF, 0, 0, 17 },
- /* Package(){0x0005FFFF, 1, 0, 18 }, */
- /* Package(){0x0005FFFF, 2, 0, 19 }, */
- /* Package(){0x0005FFFF, 3, 0, 16 }, */
-
- /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
- Package(){0x0006FFFF, 0, 0, 18 },
- /* Package(){0x0006FFFF, 1, 0, 19 }, */
- /* Package(){0x0006FFFF, 2, 0, 16 }, */
- /* Package(){0x0006FFFF, 3, 0, 17 }, */
-
- /* Bus 0, Dev 7 - PCIe Bridge for network card */
- Package(){0x0007FFFF, 0, 0, 19 },
- /* Package(){0x0007FFFF, 1, 0, 16 }, */
- /* Package(){0x0007FFFF, 2, 0, 17 }, */
- /* Package(){0x0007FFFF, 3, 0, 18 }, */
-
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices in APIC mode */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0012FFFF, 0, 0, 22 },
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){0x0013FFFF, 0, 0, 16 },
- Package(){0x0013FFFF, 1, 0, 17 },
- Package(){0x0013FFFF, 2, 0, 18 },
- Package(){0x0013FFFF, 3, 0, 19 },
- /* Package(){0x00130004, 2, 0, 18 }, */
- /* Package(){0x00130005, 3, 0, 19 }, */
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
- Package(){0x0014FFFF, 0, 0, 16 },
- Package(){0x0014FFFF, 1, 0, 17 },
- Package(){0x0014FFFF, 2, 0, 18 },
- Package(){0x0014FFFF, 3, 0, 19 },
- /* Package(){0x00140004, 2, 0, 18 }, */
- /* Package(){0x00140004, 3, 0, 19 }, */
- /* Package(){0x00140005, 1, 0, 17 }, */
- /* Package(){0x00140006, 1, 0, 17 }, */
- })
-
- Name(PR1, Package(){
- /* Internal graphics - RS690 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, INTA, 0 },
- Package(){0x0005FFFF, 1, INTB, 0 },
- Package(){0x0005FFFF, 2, INTC, 0 },
- Package(){0x0005FFFF, 3, INTD, 0 },
- })
-
- Name(APR1, Package(){
- /* Internal graphics - RS690 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, 0, 18 },
- Package(){0x0005FFFF, 1, 0, 19 },
- /* Package(){0x0005FFFF, 2, 0, 20 }, */
- /* Package(){0x0005FFFF, 3, 0, 17 }, */
- })
-
- Name(PS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, INTA, 0 },
- Package(){0x0000FFFF, 1, INTB, 0 },
- Package(){0x0000FFFF, 2, INTC, 0 },
- Package(){0x0000FFFF, 3, INTD, 0 },
- })
-
- Name(APS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, 0, 16 },
- Package(){0x0000FFFF, 1, 0, 17 },
- Package(){0x0000FFFF, 2, 0, 18 },
- Package(){0x0000FFFF, 3, 0, 19 },
- })
-
- Name(PS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, INTB, 0 },
- Package(){0x0000FFFF, 1, INTC, 0 },
- Package(){0x0000FFFF, 2, INTD, 0 },
- Package(){0x0000FFFF, 3, INTA, 0 },
- })
-
- Name(APS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
-
- Name(APS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, 0, 19 },
- Package(){0x0000FFFF, 1, 0, 16 },
- Package(){0x0000FFFF, 2, 0, 17 },
- Package(){0x0000FFFF, 3, 0, 18 },
- })
-
- Name(PCIB, Package(){
- /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
- Package(){0x0005FFFF, 0, 0, 0x14 },
- Package(){0x0005FFFF, 1, 0, 0x15 },
- Package(){0x0005FFFF, 2, 0, 0x16 },
- Package(){0x0005FFFF, 3, 0, 0x17 },
- Package(){0x0006FFFF, 0, 0, 0x15 },
- Package(){0x0006FFFF, 1, 0, 0x16 },
- Package(){0x0006FFFF, 2, 0, 0x17 },
- Package(){0x0006FFFF, 3, 0, 0x14 },
- Package(){0x0007FFFF, 0, 0, 0x16 },
- Package(){0x0007FFFF, 1, 0, 0x17 },
- Package(){0x0007FFFF, 2, 0, 0x14 },
- Package(){0x0007FFFF, 3, 0, 0x15 },
- })
-}
diff --git a/src/mainboard/amd/pistachio/acpi/sata.asl b/src/mainboard/amd/pistachio/acpi/sata.asl
deleted file mode 100644
index 474e5ed6d2..0000000000
--- a/src/mainboard/amd/pistachio/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(SATA) {
- Name(_ADR, 0x00120000)
- #include "sata.asl"
- }
- }
-}
-*/
-
-Name(STTM, Buffer(20) {
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
- \_GPE._L1F()
-}
-
-Device(PMRY)
-{
- Name(_ADR, 0)
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(PMST) {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P0IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- }/* end of PMST */
-
- Device(PSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P1IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of PSLA */
-} /* end of PMRY */
-
-
-Device(SEDY)
-{
- Name(_ADR, 1) /* IDE Scondary Channel */
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(SMST)
- {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P2IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SMST */
-
- Device(SSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P3IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SSLA */
-} /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
- Method(_L1F,0x0,NotSerialized) {
- if (\_SB.P0PR) {
- if (LGreater(\_SB.P0IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P0PR)
- }
-
- if (\_SB.P1PR) {
- if (LGreater(\_SB.P1IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P1PR)
- }
-
- if (\_SB.P2PR) {
- if (LGreater(\_SB.P2IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P2PR)
- }
-
- if (\_SB.P3PR) {
- if (LGreater(\_SB.P3IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P3PR)
- }
- }
-}
diff --git a/src/mainboard/amd/pistachio/acpi/usb.asl b/src/mainboard/amd/pistachio/acpi/usb.asl
deleted file mode 100644
index a1f87b6d5b..0000000000
--- a/src/mainboard/amd/pistachio/acpi/usb.asl
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "usb.asl"
- }
-*/
-Method(UCOC, 0) {
- Sleep(20)
- Store(0x13,CMTI)
- Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
- Scope (\_GPE) {
- Method (_L13) {
- UCOC()
- if(LEqual(GPB0,PLC0)) {
- Not(PLC0,PLC0)
- Store(PLC0, \_SB.PT0D)
- }
- }
- }
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
- Scope (\_GPE) {
- Method (_L14) {
- UCOC()
- if (LEqual(GPB1,PLC1)) {
- Not(PLC1,PLC1)
- Store(PLC1, \_SB.PT1D)
- }
- }
- }
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
- Scope (\_GPE) {
- Method (_L15) {
- UCOC()
- if (LEqual(GPB2,PLC2)) {
- Not(PLC2,PLC2)
- Store(PLC2, \_SB.PT2D)
- }
- }
- }
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
- Scope (\_GPE) {
- Method (_L16) {
- UCOC()
- if (LEqual(GPB3,PLC3)) {
- Not(PLC3,PLC3)
- Store(PLC3, \_SB.PT3D)
- }
- }
- }
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
- Scope (\_GPE) {
- Method (_L19) {
- UCOC()
- if (LEqual(GPB4,PLC4)) {
- Not(PLC4,PLC4)
- Store(PLC4, \_SB.PT4D)
- }
- }
- }
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-/*
- * If (LLessEqual(UOM5,9)) {
- * Scope (\_GPE) {
- * Method (_L1A) {
- * UCOC()
- * if (LEqual(GPB5,PLC5)) {
- * Not(PLC5,PLC5)
- * Store(PLC5, \_SB.PT5D)
- * }
- * }
- * }
- * }
- */
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
- Scope (\_GPE) {
- /* Method (_L1C) { */
- Method (_L06) {
- UCOC()
- if (LEqual(GPB6,PLC6)) {
- Not(PLC6,PLC6)
- Store(PLC6, \_SB.PT6D)
- }
- }
- }
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
- Scope (\_GPE) {
- /* Method (_L1D) { */
- Method (_L07) {
- UCOC()
- if (LEqual(GPB7,PLC7)) {
- Not(PLC7,PLC7)
- Store(PLC7, \_SB.PT7D)
- }
- }
- }
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
- Scope (\_GPE) {
- Method (_L17) {
- if (LEqual(G8IS,PLC8)) {
- Not(PLC8,PLC8)
- Store(PLC8, \_SB.PT8D)
- }
- }
- }
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
- Scope (\_GPE) {
- Method (_L0E) {
- if (LEqual(G9IS,0)) {
- Store(1,\_SB.PT9D)
- }
- }
- }
-}
diff --git a/src/mainboard/amd/pistachio/acpi_tables.c b/src/mainboard/amd/pistachio/acpi_tables.c
deleted file mode 100644
index 75834b6c7f..0000000000
--- a/src/mainboard/amd/pistachio/acpi_tables.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include <arch/cpu.h>
-#include <cpu/amd/powernow.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- get_bus_conf();
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB600 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
- IO_APIC_ADDR, 0);
-
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high */
-
- /* create all subtables for processors */
- /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
- /* 1: LINT1 connect to NMI */
-
- return current;
-}
diff --git a/src/mainboard/amd/pistachio/board_info.txt b/src/mainboard/amd/pistachio/board_info.txt
deleted file mode 100644
index b351b8e696..0000000000
--- a/src/mainboard/amd/pistachio/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: eval
diff --git a/src/mainboard/amd/pistachio/cmos.layout b/src/mainboard/amd/pistachio/cmos.layout
deleted file mode 100644
index 104d51f4c2..0000000000
--- a/src/mainboard/amd/pistachio/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-##
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb
deleted file mode 100644
index 805df7cb41..0000000000
--- a/src/mainboard/amd/pistachio/devicetree.cb
+++ /dev/null
@@ -1,80 +0,0 @@
-#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_AM2
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1022 0x3050 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on # southbridge, K8 HT Configuration
- chip southbridge/amd/rs690
- device pci 0.0 on end # HT 0x7910
- # device pci 0.1 off end # CLK
- device pci 1.0 on # Internal Graphics P2P bridge 0x7912
- device pci 5.0 on end # Internal Graphics 0x791F
- end
- device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
- device pci 3.0 off end # PCIE P2P bridge 0x791b
- device pci 4.0 on end # PCIE P2P bridge 0x7914
- device pci 5.0 on end # PCIE P2P bridge 0x7915
- device pci 6.0 on end # PCIE P2P bridge 0x7916
- device pci 7.0 on end # PCIE P2P bridge 0x7917
- device pci 8.0 off end # NB/SB Link P2P bridge
- register "gpp_configuration" = "4"
- register "port_enable" = "0xfc"
- register "gfx_dev2_dev3" = "1"
- register "gfx_dual_slot" = "0"
- register "gfx_lane_reversal" = "0"
- register "gfx_tmds" = "0"
- register "gfx_compliance" = "0"
- register "gfx_reconfiguration" = "1"
- register "gfx_link_width" = "0"
- end
- chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
- device pci 12.0 on end # SATA 0x4380
- device pci 13.0 on end # USB 0x4387
- device pci 13.1 on end # USB 0x4388
- device pci 13.2 on end # USB 0x4389
- device pci 13.3 on end # USB 0x438a
- device pci 13.4 on end # USB 0x438b
- device pci 13.5 on end # USB 2 0x4386
- device pci 14.0 on # SM 0x4385
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 off end
- end
- chip drivers/generic/generic #dimm 0-1-0
- device i2c 52 off end
- end
- chip drivers/generic/generic #dimm 0-1-1
- device i2c 53 off end
- end
- end # SM
- device pci 14.1 on end # IDE 0x438c
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on end # LPC 0x438d
- device pci 14.4 on end # PCI 0x4384
- device pci 14.5 on end # ACI 0x4382
- device pci 14.6 on end # MCI 0x438e
- end #southbridge/amd/sb600
- end # device pci 18.0
-
- device pci 18.1 on end # K8 Address Map
- device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode
- device pci 18.3 on end # K8 Miscellaneous Control
- end #northbridge/amd/amdk8
- end #domain
-end #northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl
deleted file mode 100644
index 79589a85e2..0000000000
--- a/src/mainboard/amd/pistachio/dsdt.asl
+++ /dev/null
@@ -1,1695 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <southbridge/amd/sb600/sb600.h>
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "AMD ", /* OEMID */
- "COREBOOT", /* TABLE ID */
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
-
- /* Data to be patched by the BIOS during POST */
- /* FIXME the patching is not done yet! */
- /* Memory related values */
- Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
-
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
-
- /* USB overcurrent mapping pins. */
- Name(UOM0, 0)
- Name(UOM1, 2)
- Name(UOM2, 0)
- Name(UOM3, 7)
- Name(UOM4, 2)
- Name(UOM5, 2)
- Name(UOM6, 6)
- Name(UOM7, 2)
- Name(UOM8, 6)
- Name(UOM9, 6)
-
- /* Some global data */
- Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PMOD, One) /* Assume APIC */
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- /* PCI Error control register */
- OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
- Field(PERC, ByteAcc, NoLock, Preserve) {
- SENS, 0x00000001,
- PENS, 0x00000001,
- SENE, 0x00000001,
- PENE, 0x00000001,
- }
-
- /* Client Management index/data registers */
- OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
- Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
- /* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
- }
-
- /* GPM Port register */
- OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
- Field(GPT, ByteAcc, NoLock, Preserve) {
- GPB0,1,
- GPB1,1,
- GPB2,1,
- GPB3,1,
- GPB4,1,
- GPB5,1,
- GPB6,1,
- GPB7,1,
- }
-
- /* Flash ROM program enable register */
- OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
- Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
- FLRE, 0x00000001,
- }
-
- /* PM2 index/data registers */
- OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
- Field(PM2R, ByteAcc, NoLock, Preserve) {
- PM2I, 0x00000008,
- PM2D, 0x00000008,
- }
-
- /* Power Management I/O registers */
- OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
- Field(PIOR, ByteAcc, NoLock, Preserve) {
- PIOI, 0x00000008,
- PIOD, 0x00000008,
- }
- IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
- Offset(0x00), /* MiscControl */
- , 1,
- T1EE, 1,
- T2EE, 1,
- Offset(0x01), /* MiscStatus */
- , 1,
- T1E, 1,
- T2E, 1,
- Offset(0x04), /* SmiWakeUpEventEnable3 */
- , 7,
- SSEN, 1,
- Offset(0x07), /* SmiWakeUpEventStatus3 */
- , 7,
- CSSM, 1,
- Offset(0x10), /* AcpiEnable */
- , 6,
- PWDE, 1,
- Offset(0x1C), /* ProgramIoEnable */
- , 3,
- MKME, 1,
- IO3E, 1,
- IO2E, 1,
- IO1E, 1,
- IO0E, 1,
- Offset(0x1D), /* IOMonitorStatus */
- , 3,
- MKMS, 1,
- IO3S, 1,
- IO2S, 1,
- IO1S, 1,
- IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
- APEB, 16,
- Offset(0x36), /* GEvtLevelConfig */
- , 6,
- ELC6, 1,
- ELC7, 1,
- Offset(0x37), /* GPMLevelConfig0 */
- , 3,
- PLC0, 1,
- PLC1, 1,
- PLC2, 1,
- PLC3, 1,
- PLC8, 1,
- Offset(0x38), /* GPMLevelConfig1 */
- , 1,
- PLC4, 1,
- PLC5, 1,
- , 1,
- PLC6, 1,
- PLC7, 1,
- Offset(0x3B), /* PMEStatus1 */
- GP0S, 1,
- GM4S, 1,
- GM5S, 1,
- APS, 1,
- GM6S, 1,
- GM7S, 1,
- GP2S, 1,
- STSS, 1,
- Offset(0x55), /* SoftPciRst */
- SPRE, 1,
- , 1,
- , 1,
- PNAT, 1,
- PWMK, 1,
- PWNS, 1,
-
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
-
- Offset(0x65), /* UsbPMControl */
- , 4,
- URRE, 1,
- Offset(0x68), /* MiscEnable68 */
- , 3,
- TMTE, 1,
- , 1,
- Offset(0x92), /* GEVENTIN */
- , 7,
- E7IS, 1,
- Offset(0x96), /* GPM98IN */
- G8IS, 1,
- G9IS, 1,
- Offset(0x9A), /* EnhanceControl */
- ,7,
- HPDE, 1,
- Offset(0xA8), /* PIO7654Enable */
- IO4E, 1,
- IO5E, 1,
- IO6E, 1,
- IO7E, 1,
- Offset(0xA9), /* PIO7654Status */
- IO4S, 1,
- IO5S, 1,
- IO6S, 1,
- IO7S, 1,
- }
-
- /* PM1 Event Block
- * First word is PM1_Status, Second word is PM1_Enable
- */
- OperationRegion(P1EB, SystemIO, APEB, 0x04)
- Field(P1EB, ByteAcc, NoLock, Preserve) {
- TMST, 1,
- , 3,
- BMST, 1,
- GBST, 1,
- Offset(0x01),
- PBST, 1,
- , 1,
- RTST, 1,
- , 3,
- PWST, 1,
- SPWS, 1,
- Offset(0x02),
- TMEN, 1,
- , 4,
- GBEN, 1,
- Offset(0x03),
- PBEN, 1,
- , 1,
- RTEN, 1,
- , 3,
- PWDA, 1,
- }
-
- Scope(\_SB) {
-
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
- /* Byte offsets are computed using the following technique:
- * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
- * The 8 comes from 8 functions per device, and 4096 bytes per function config space
- */
- Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
- STB5, 32,
- Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
- PT0D, 1,
- PT1D, 1,
- PT2D, 1,
- PT3D, 1,
- PT4D, 1,
- PT5D, 1,
- PT6D, 1,
- PT7D, 1,
- PT8D, 1,
- PT9D, 1,
- Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
- SBIE, 1,
- SBME, 1,
- Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
- SBRI, 8,
- Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
- SBB1, 32,
- Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
- ,14,
- P92E, 1, /* Port92 decode enable */
- }
-
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
- Field(SB5, AnyAcc, NoLock, Preserve)
- {
- /* Port 0 */
- Offset(0x120), /* Port 0 Task file status */
- P0ER, 1,
- , 2,
- P0DQ, 1,
- , 3,
- P0BY, 1,
- Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
- , 4,
- P0IS, 4,
- Offset(0x12C), /* Port 0 Serial ATA control */
- P0DI, 4,
- Offset(0x130), /* Port 0 Serial ATA error */
- , 16,
- P0PR, 1,
-
- /* Port 1 */
- offset(0x1A0), /* Port 1 Task file status */
- P1ER, 1,
- , 2,
- P1DQ, 1,
- , 3,
- P1BY, 1,
- Offset(0x1A8), /* Port 1 Serial ATA status */
- P1DD, 4,
- , 4,
- P1IS, 4,
- Offset(0x1AC), /* Port 1 Serial ATA control */
- P1DI, 4,
- Offset(0x1B0), /* Port 1 Serial ATA error */
- , 16,
- P1PR, 1,
-
- /* Port 2 */
- Offset(0x220), /* Port 2 Task file status */
- P2ER, 1,
- , 2,
- P2DQ, 1,
- , 3,
- P2BY, 1,
- Offset(0x228), /* Port 2 Serial ATA status */
- P2DD, 4,
- , 4,
- P2IS, 4,
- Offset(0x22C), /* Port 2 Serial ATA control */
- P2DI, 4,
- Offset(0x230), /* Port 2 Serial ATA error */
- , 16,
- P2PR, 1,
-
- /* Port 3 */
- Offset(0x2A0), /* Port 3 Task file status */
- P3ER, 1,
- , 2,
- P3DQ, 1,
- , 3,
- P3BY, 1,
- Offset(0x2A8), /* Port 3 Serial ATA status */
- P3DD, 4,
- , 4,
- P3IS, 4,
- Offset(0x2AC), /* Port 3 Serial ATA control */
- P3DI, 4,
- Offset(0x2B0), /* Port 3 Serial ATA error */
- , 16,
- P3PR, 1,
- }
- }
-
- #include "acpi/routing.asl"
-
- Scope(\_SB) {
-
- Method(OSFL, 0){
-
- if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
-
- if(CondRefOf(\_OSI))
- {
- Store(1, OSVR) /* Assume some form of XP */
- if (\_OSI("Windows 2006")) /* Vista */
- {
- Store(2, OSVR)
- }
- } else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSVR) /* Linux */
- } Else {
- Store(4, OSVR) /* Gotta be WinCE */
- }
- }
- Return(OSVR)
- }
-
- Method(_PIC, 0x01, NotSerialized)
- {
- If (Arg0)
- {
- \_SB.CIRQ()
- }
- Store(Arg0, PMOD)
- }
-
- Method(CIRQ, 0x00, NotSerialized)
- {
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTA._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTE._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_PRS\n") */
- Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
- } /* End Scope(_SB) */
-
- #include <southbridge/amd/common/acpi/sleepstates.asl>
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- } /* End Method(\_PTS) */
-
- /*
- * The following method results in a "not a valid reserved NameSeg"
- * warning so I have commented it out for the duration. It isn't
- * used, so it could be removed.
- *
- *
- * \_GTS OEM Going To Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- *
- * Method(\_GTS, 1) {
- * DBGO("\\_GTS\n")
- * DBGO("From S0 to S")
- * DBGO(Arg0)
- * DBGO("\n")
- * }
- */
-
- /*
- * \_BFS OEM Back From Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- */
- Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
- }
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- Store(1,HPDE)
-
- /* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, Local1)
- Store(Local1, PWST)
-
- /* if(DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
- * } else {
- * Store(Arg0, Index(WKST,1))
- * }
- */
-
- Return(WKST)
- } /* End Method(\_WAK) */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* General event 0 */
- /* Method(_L00) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 1 */
- /* Method(_L01) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 2 */
- /* Method(_L02) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 3 */
- Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* General event 4 */
- /* Method(_L04) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 5 */
- /* Method(_L05) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 6 - Used for GPM6, moved to USB.asl */
- /* Method(_L06) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 7 - Used for GPM7, moved to USB.asl */
- /* Method(_L07) {
- * DBGO("\\_GPE\\_L07\n")
- * }
- */
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
- }
-
- /* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
-
- /* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
-
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
-
- /* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
-
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event */
- Method(_L1A) {
- /* DBGO("\\_GPE\\_L1A\n") */
- Notify (\_SB.SLPB, 0x80)
- }
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
-
- /* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
-
- /* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
-
- /* SATA SCI event - Moved to sata.asl */
- /* Method(_L1F) {
- * DBGO("\\_GPE\\_L1F\n")
- * }
- */
-
- } /* End Scope GPE */
-
- #include "acpi/usb.asl"
-
- /* System Bus */
- Scope(\_SB) { /* Start \_SB scope */
- #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0) {
- External (TOM1)
- External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* Dev3 is also an external GFX bridge, not used in Herring */
-
- Device(PBR4) {
- Name(_ADR, 0x00040000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR4 */
-
- Device(PBR5) {
- Name(_ADR, 0x00050000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR5 */
-
- Device(PBR6) {
- Name(_ADR, 0x00060000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR6 */
-
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR7 */
-
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
-
- /* Describe the Southbridge devices */
- Device(STCR) {
- Name(_ADR, 0x00120000)
- #include "acpi/sata.asl"
- } /* end STCR */
-
- Device(UOH1) {
- Name(_ADR, 0x00130000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH1 */
-
- Device(UOH2) {
- Name(_ADR, 0x00130001)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH2 */
-
- Device(UOH3) {
- Name(_ADR, 0x00130002)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH3 */
-
- Device(UOH4) {
- Name(_ADR, 0x00130003)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH4 */
-
- Device(UOH5) {
- Name(_ADR, 0x00130004)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UEH1) {
- Name(_ADR, 0x00130005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(SBUS) {
- Name(_ADR, 0x00140000)
- } /* end SBUS */
-
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "acpi/ide.asl"
- } /* end IDEC */
-
- Device(AZHD) {
- Name(_ADR, 0x00140002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6C),
- MMDT, 16,
- }
-
- Method(_INI) {
- If(LEqual(OSVR,3)){ /* If we are running Linux */
- Store(zero, NSEN)
- Store(one, NSDO)
- Store(one, NSDI)
- }
- }
- } /* end AZHD */
-
- Device(LIBR) {
- Name(_ADR, 0x00140003)
- /* Method(_INI) {
- * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
- } */ /* End Method(_SB.SBRDG._INI) */
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){8}
- IO(Decode16,0x0070, 0x0070, 0, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){0}
- IO(Decode16, 0x0040, 0x0040, 0, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 0, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){2}
- IO(Decode16,0x0020, 0x0020, 0, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,BusMaster,Transfer8){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
- IRQNoFlags(){13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPTM) { /* HPET */
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* HPET is visible */
- }
- Method(_CRS, 0) {
- Return(CRS)
- }
- } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
- } /* end LIBR */
-
- Device(HPBR) {
- Name(_ADR, 0x00140004)
- } /* end HostPciBr */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- } /* end Ac97modem */
-
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
-
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
- }
-
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * ShiftLeft(TOM2, 20, Local0)
- * Subtract(Local0, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-
- Return(CRES) /* note to change the Name buffer */
- } /* end of Method(_SB.PCI0._CRS) */
-
- /*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
- Method(_INI, 0) {
- /* DBGO("\\_SB\\_INI\n") */
- /* DBGO(" DSDT.ASL code from ") */
- /* DBGO(__DATE__) */
- /* DBGO(" ") */
- /* DBGO(__TIME__) */
- /* DBGO("\n Sleep states supported: ") */
- /* DBGO("\n") */
- /* DBGO(" \\_OS=") */
- /* DBGO(\_OS) */
- /* DBGO("\n \\_REV=") */
- /* DBGO(\_REV) */
- /* DBGO("\n") */
-
- /* Determine the OS we're running on */
- OSFL()
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
- * }
- */
- } /* End Method(_SB._INI) */
- } /* End Device(PCI0) */
-
- Device(PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
-
- Device (SLPB) {
- Name (_HID, EisaId ("PNP0C0E"))
- Name (_PRW, Package (0x02) {0x0F, 0x04})
- Name (_STA, 0x0B)
- }
- } /* End \_SB scope */
-
- Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
- } /* End Scope SI */
-
- OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
- Field (SMB0, ByteAcc, NoLock, Preserve) {
- HSTS, 8, /* SMBUS status */
- SSTS, 8, /* SMBUS slave status */
- HCNT, 8, /* SMBUS control */
- HCMD, 8, /* SMBUS host cmd */
- HADD, 8, /* SMBUS address */
- DAT0, 8, /* SMBUS data0 */
- DAT1, 8, /* SMBUS data1 */
- BLKD, 8, /* SMBUS block data */
- SCNT, 8, /* SMBUS slave control */
- SCMD, 8, /* SMBUS shadow cmd */
- SEVT, 8, /* SMBUS slave event */
- SDAT, 8 /* SMBUS slave data */
- }
-
- Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
- Store (0x1E, HSTS)
- Store (0xFA, Local0)
- While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
- Stall (0x64)
- Decrement (Local0)
- }
-
- Return (Local0)
- }
-
- Method (SWTC, 1, NotSerialized) {
- Store (Arg0, Local0)
- Store (0x07, Local2)
- Store (One, Local1)
- While (LEqual (Local1, One)) {
- Store (And (HSTS, 0x1E), Local3)
- If (LNotEqual (Local3, Zero)) { /* read sucess */
- If (LEqual (Local3, 0x02)) {
- Store (Zero, Local2)
- }
-
- Store (Zero, Local1)
- }
- Else {
- If (LLess (Local0, 0x0A)) { /* read failure */
- Store (0x18, Local2)
- Store (Zero, Local1)
- }
- Else {
- Sleep (0x0A) /* 10 ms, try again */
- Subtract (Local0, 0x0A, Local0)
- }
- }
- }
-
- Return (Local2)
- }
-
- Method (SMBR, 3, NotSerialized) {
- Store (0x07, Local0)
-
- Store (WCLR (), Local0) /* clear SMBUS status register before read data */
-
- Store (0x1F, HSTS)
- Store (Or (ShiftLeft (Arg1, One), One), HADD)
- Store (Arg2, HCMD)
- If (LEqual (Arg0, 0x07)) {
- Store (0x48, HCNT) /* read byte */
- }
-
- Store (SWTC (0x03E8), Local1) /* 1000 ms */
- If (LEqual (Local1, Zero)) {
- If (LEqual (Arg0, 0x07)) {
- Store (DAT0, Local0)
- }
- }
- Else {
- Store (Local1, Local0)
- }
-
- Return (Local0)
- }
-
- /* THERMAL */
- Scope(\_TZ) {
- Name (KELV, 2732)
- Name (THOT, 900)
- Name (TCRT, 950)
-
- ThermalZone(TZ00) {
- Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
- /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
- Return(Add(0, 2730))
- }
- Method(_AL0,0) { /* Returns package of cooling device to turn on */
- /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
- Return(Package() {\_TZ.TZ00.FAN0})
- }
- Device (FAN0) {
- Name(_HID, EISAID("PNP0C0B"))
- Name(_PR0, Package() {PFN0})
- }
-
- PowerResource(PFN0,0,0) {
- Method(_STA) {
- Store(0xF,Local0)
- Return(Local0)
- }
- Method(_ON) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
- }
- Method(_OFF) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
- }
- }
-
- Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
- Return (Add (THOT, KELV))
- }
- Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
- Return (Add (TCRT, KELV))
- }
- Method(_TMP,0) { /* return current temp of this zone */
- Store (SMBR (0x07, 0x2E,, 0x25), Local0)
- If (LGreater (Local0, 0x20)) {
- Store (Local0, Local1)
- }
- Else {
- Add (Local0, 0x40, Local0)
- Add (Local0, TCRT, Local0)
- Return (Add (550, KELV))
- }
-
- /* Store (SMBR (0x07, 0x2E, 0x26), Local0)
- * If (LGreater (Local0, 0x20)) {
- * If (LGreater (Local0, Local1)) {
- * Store (Local0, Local1)
- * }
- * }
- * Else {
- * Add (Local0, 0x40, Local0)
- * Add (Local0, TCRT, Local0)
- * Return (Add (Local0, KELV))
- * }
- */
-
- Store (SMBR (0x07, 0x2E, 0x27), Local0)
- If (LGreater (Local0, 0x20)) {
- If (LGreater (Local0, Local1)) {
- Store (Local0, Local1)
- }
-
- Subtract (Local1, 0x40, Local1)
- Multiply (Local1, 10, Local1)
- Return (Add (Local1, KELV))
- }
- Else {
- Add (Local0, 0x40, Local0)
- Add (Local0, TCRT, Local0)
- Return (Add (550 , KELV))
- }
- } /* end of _TMP */
- } /* end of TZ00 */
- }
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/pistachio/fadt.c b/src/mainboard/amd/pistachio/fadt.c
deleted file mode 100644
index b397f52aea..0000000000
--- a/src/mainboard/amd/pistachio/fadt.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include "southbridge/amd/sb600/sb600.h"
-
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb ACPI */
-/* pm_base should be got from bar2 of rs690. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
-
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
- /* Prepare the header */
- memset((void *)fadt, 0, sizeof(acpi_fadt_t));
- memcpy(header->signature, "FACP", 4);
- header->length = 244;
- header->revision = 3;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->asl_compiler_revision = 0;
-
- fadt->firmware_ctrl = (u32) facs;
- fadt->dsdt = (u32) dsdt;
- /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
- fadt->preferred_pm_profile = 0x03;
- fadt->sci_int = 9;
- /* disable system management mode by setting to 0: */
- fadt->smi_cmd = 0;
- fadt->acpi_enable = 0xf0;
- fadt->acpi_disable = 0xf1;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0xe2;
-
- pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
-
- /* CpuControl is in \_PR.CP00, 6 bytes */
- pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
-
- pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
-
- pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
-
- pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 20-2B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
- pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
-
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
- fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
- fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
- fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
-
- fadt->cst_cnt = 0xe3;
- fadt->p_lvl2_lat = 101;
- fadt->p_lvl3_lat = 1001;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 1;
- fadt->duty_width = 3;
- fadt->day_alrm = 0; /* 0x7d these have to be */
- fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
- fadt->century = 0; /* 0x7f to make rtc alrm work */
- fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
- fadt->flags = 0x0001c1a5;/* 0x25; */
-
- fadt->res2 = 0;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 6;
- fadt->x_firmware_ctl_l = (u32) facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32) dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 4;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 2;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 32;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/amd/pistachio/get_bus_conf.c b/src/mainboard/amd/pistachio/get_bus_conf.c
deleted file mode 100644
index b1b7270802..0000000000
--- a/src/mainboard/amd/pistachio/get_bus_conf.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_rs690[8];
-u8 bus_sb600[2];
-u32 apicid_sb600;
-
-/*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
-u32 pci1234x[] = {
- 0x0000ff0,
-};
-
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
- 0x20202020,
-};
-
-u32 sbdn_rs690;
-u32 sbdn_sb600;
-
-
-
-static u32 get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- u32 apicid_base;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* do it only once */
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
- sbdn_rs690 = sysconf.sbdn;
- sbdn_sb600 = 0;
-
- for (i = 0; i < 2; i++) {
- bus_sb600[i] = 0;
- }
- for (i = 0; i < 8; i++) {
- bus_rs690[i] = 0;
- }
-
- bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_sb600[0] = bus_rs690[0];
-
- /* sb600 */
- dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
- if (dev) {
- bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- /* rs690 */
- for (i = 1; i < 8; i++) {
- dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
- if (dev) {
- bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
- /* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_sb600 = apicid_base + 0;
-}
diff --git a/src/mainboard/amd/pistachio/irq_tables.c b/src/mainboard/amd/pistachio/irq_tables.c
deleted file mode 100644
index 456c568801..0000000000
--- a/src/mainboard/amd/pistachio/irq_tables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern u8 bus_rs690[8];
-extern u8 bus_sb600[2];
-extern u32 sbdn_sb600;
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_sb600[0];
- pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c
deleted file mode 100644
index 77fbcc1e17..0000000000
--- a/src/mainboard/amd/pistachio/mainboard.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb600/sb600.h>
-
-#define ADT7475_ADDRESS 0x2E
-#define SMBUS_IO_BASE 0x1000
-
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-#define ADT7475_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address)
-#define ADT7475_write_byte(address, val) \
- do_smbus_write_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address, val)
-
-
-/********************************************************
-* pistachio uses a BCM5787 as on-board NIC.
-* It has a pin named LOW_POWER to enable it into LOW POWER state.
-* In order to run NIC, we should let it out of Low power state. This pin is
-* controlled by GPM8.
-* RRG4.2.3 GPM as GPIO
-* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
-* I/O C50, C51, C52, PM I/O94, 95, 96.
-* RRG4.2.3.1 GPM pins as Input
-* RRG4.2.3.2 GPM pins as Output
-* The R77 (on BRASS) / R81 (on Bronze) is not load!
-* So NIC can work whether this function runs.
-********************************************************/
-static void enable_onboard_nic(void)
-{
- u8 byte;
-
- printk(BIOS_INFO, "%s.\n", __func__);
-
- /* enable GPM8 output */
- byte = pm_ioread(0x95);
- byte &= 0xfe;
- pm_iowrite(0x95, byte);
-
- /* GPM8 outputs low. */
- byte = pm_ioread(0x94);
- byte &= 0xfe;
- pm_iowrite(0x94, byte);
-}
-
-/*
- * set thermal config
- */
-static void set_thermal_config(void)
-{
- u8 byte, byte2;
- u16 word;
- u32 dword;
- struct device *sm_dev;
-
- /* set adt7475 */
- ADT7475_write_byte(0x40, 0x04);
- /* Config Register 6 */
- ADT7475_write_byte(0x10, 0x00);
- /* Config Register 7 */
- ADT7475_write_byte(0x11, 0x00);
-
- /* set Offset 64 format, enable THERM on Remote 1& Remote 2 */
- ADT7475_write_byte(0x7c, 0xa0);
- /* No offset for remote 2 */
- ADT7475_write_byte(0x72, 0x00);
- /* PWM 1 configuration register CPU fan controlled by CPU Thermal Diode */
- ADT7475_write_byte(0x5c, 0x02);
- /* PWM 3 configuration register Case fan controlled by 690 temp */
- ADT7475_write_byte(0x5e, 0x42);
-
- /* remote 1 low temp limit */
- ADT7475_write_byte(0x4e, 0x00);
- /* remote 1 High temp limit (90C) */
- ADT7475_write_byte(0x4f, 0x9a);
-
- /* remote2 Low Temp Limit */
- ADT7475_write_byte(0x52, 0x00);
- /* remote2 High Limit (90C) */
- ADT7475_write_byte(0x53, 0x9a);
-
- /* remote 1 therm temp limit (95C) */
- ADT7475_write_byte(0x6a, 0x9f);
- /* remote 2 therm temp limit (95C) */
- ADT7475_write_byte(0x6c, 0x9f);
-
- /* PWM 1 minimum duty cycle (37%) */
- ADT7475_write_byte(0x64, 0x60);
- /* PWM 1 Maximum duty cycle (100%) */
- ADT7475_write_byte(0x38, 0xff);
- /* PWM 3 minimum duty cycle (37%) */
- ADT7475_write_byte(0x66, 0x60);
- /* PWM 3 Maximum Duty Cycle (100%) */
- ADT7475_write_byte(0x3a, 0xff);
-
- /* Remote 1 temperature Tmin (32C) */
- ADT7475_write_byte(0x67, 0x60);
- /* Remote 2 temperature Tmin (32C) */
- ADT7475_write_byte(0x69, 0x60);
- /* remote 1 Trange (53C ramp range) */
- ADT7475_write_byte(0x5f, 0xe8);
- /* remote 2 Trange (53C ramp range) */
- ADT7475_write_byte(0x61, 0xe8);
-
- /* PWM2 Duty cycle */
- ADT7475_write_byte(0x65, 0x00);
- /* PWM2 Disabled */
- ADT7475_write_byte(0x5d, 0x80);
- /* PWM2 Max Duty Cycle */
- ADT7475_write_byte(0x39, 0x00);
-
- /* Config Register 3 - enable smbalert & therm */
- ADT7475_write_byte(0x78, 0x03);
- /* Config Register 4 - enable therm output */
- ADT7475_write_byte(0x7d, 0x09);
- /* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 2 fault, SmbAlert Fan for Therm Timer event */
- ADT7475_write_byte(0x75, 0x2a);
- /* Config Register 1 Set Start bit */
- ADT7475_write_byte(0x40, 0x05);
- /* Read status register to clear any old errors */
- byte2 = ADT7475_read_byte(0x42);
- byte = ADT7475_read_byte(0x41);
-
- /* remote 1 temperature offset */
- ADT7475_write_byte(0x70, 0x00);
-
- printk(BIOS_INFO, "Init adt7475 end , status 0x42 %02x, status 0x41 %02x\n",
- byte2, byte);
-
- /* sb600 setting for thermal config. Set SB600 GPM5 to trigger ACPI event */
- /* set GPM5 as GPM5, not DDR3_memory disable */
- byte = pm_ioread(0x8f);
- byte |= 1 << 6; /* enable GPE */
- pm_iowrite(0x8f, byte);
-
- /* GPM5 as GPIO not USB OC */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- dword = pci_read_config32(sm_dev, 0x64);
- dword |= 1 << 19;
- pci_write_config32(sm_dev, 0x64, dword);
-
- /* Enable Client Management Index/Data registers */
- dword = pci_read_config32(sm_dev, 0x78);
- dword |= 1 << 11; /* Cms_enable */
- pci_write_config32(sm_dev, 0x78, dword);
-
- /* MiscfuncEnable */
- byte = pci_read_config8(sm_dev, 0x41);
- byte |= (1 << 5);
- pci_write_config8(sm_dev, 0x41, byte);
-
- /* set GPM5 as input */
- /* set index register 0C50h to 13h (miscellaneous control) */
- outb(0x13, 0xC50); /* CMIndex */
- /* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
- byte = inb(0xC51); /* CMData */
- byte &= 0x3f;
- byte |= 1 << 6;
- outb(byte, 0xC51);
- /* set GPM port 0C52h bit 5 to 1 to tri-state the GPM port */
- byte = inb(0xc52); /* GpmPort */
- byte |= 1 << 5;
- outb(byte, 0xc52);
- /* set CM data register 0C51h bits [7:6] to 00b to set GPM port for read */
- byte = inb(0xc51);
- byte &= 0x3f;
- outb(byte, 0xc51);
-
- /* trigger SCI/SMI */
- byte = pm_ioread(0x34);
- byte &= 0xcf;
- pm_iowrite(0x34, byte);
-
- /* set GPM5 to not wake from s5 */
- byte = pm_ioread(0x77);
- byte &= ~(1 << 5);
- pm_iowrite(0x77, byte);
-
- /* trigger on falling edge */
- byte = pm_ioread(0x38);
- byte &= ~(1 << 2);
- pm_iowrite(0x38, byte);
-
- /* set SB600 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to input */
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
-}
-
-/*************************************************
-* enable the dedicated function in pistachio board.
-* This function called early than rs690_enable.
-*************************************************/
-static void mainboard_enable(struct device *dev)
-{
- printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev);
-
- enable_onboard_nic();
- set_thermal_config();
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c
deleted file mode 100644
index af67c5413d..0000000000
--- a/src/mainboard/amd/pistachio/mptable.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern u8 bus_rs690[8];
-extern u8 bus_sb600[2];
-
-extern u32 apicid_sb600;
-
-extern u32 sbdn_rs690;
-extern u32 sbdn_sb600;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- u32 dword;
- u8 byte;
-
- dev =
- dev_find_slot(bus_sb600[0],
- PCI_DEVFN(sbdn_sb600 + 0x14, 0));
- if (dev) {
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600,
- 0x11,(void *) dword);
-
- /* Initialize interrupt mapping */
- /* aza */
- byte = pci_read_config8(dev, 0x63);
- byte &= 0xf8;
- byte |= 0; /* 0: INTA, ...., 7: INTH */
- pci_write_config8(dev, 0x63, byte);
-
- /* SATA */
- dword = pci_read_config32(dev, 0xac);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
- /* dword |= 1 << 22; PIC and APIC co exists */
- pci_write_config32(dev, 0xac, dword);
-
- /*
- * 00:12.0: PROG SATA : INT F
- * 00:13.0: INTA USB_0
- * 00:13.1: INTB USB_1
- * 00:13.2: INTC USB_2
- * 00:13.3: INTD USB_3
- * 00:13.4: INTC USB_4
- * 00:13.5: INTD USB2
- * 00:14.1: INTA IDE
- * 00:14.2: Prog HDA : INT E
- * 00:14.5: INTB ACI
- * 00:14.6: INTB MCI
- */
- }
- }
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/pistachio/resourcemap.c b/src/mainboard/amd/pistachio/resourcemap.c
deleted file mode 100644
index d1e899b657..0000000000
--- a/src/mainboard/amd/pistachio/resourcemap.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_pistachio_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
deleted file mode 100644
index 2a4b159e6f..0000000000
--- a/src/mainboard/amd/pistachio/romstage.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include <spd.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/early_setup.c"
-#include "southbridge/amd/sb600/early_setup.c"
-#include <northbridge/amd/amdk8/f.h>
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(u32 device, u32 address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
- int needs_reset = 0;
- u32 bsp_apicid = 0;
- msr_t msr;
- struct cpuid_result cpuid1;
- struct sys_info *sysinfo = &sysinfo_car;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sb600_lpc_port80();
- /* sb600_pci_port80(); */
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- enable_rs690_dev8();
- sb600_lpc_init();
-
- /* Pistachio used a FPGA to enable serial debug instead of a SIO
- * and it doesn't require any special setup. */
-
- console_init();
-
- post_code(0x03);
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
- printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
-
- setup_pistachio_resource_map();
-
- setup_coherent_ht_domain();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched */
- wait_all_core0_started();
- start_other_cores();
-#endif
- wait_all_aps_started(bsp_apicid);
-
- /* it will set up chains and store link pair for optimization later,
- * it will init sblnk and sbbusn, nodes, sbdn */
- ht_setup_chains_x(sysinfo);
-
- /* run _early_setup before soft-reset. */
- rs690_early_setup();
- sb600_early_setup();
-
- post_code(0x04);
-
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- cpuid1 = cpuid(0x80000007);
- if ((cpuid1.edx & 0x6) == 0x6) {
- /* Read FIDVID_STATUS */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
-
- /* show final fid and vid */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
- } else {
- printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
- }
-
- post_code(0x05);
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- rs690_htinit();
- printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
-
- post_code(0x06);
-
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now; */
- printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
- sysinfo->nodes, sysinfo->ctrl, spd_addr);
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- post_code(0x07);
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
- post_code(0x08);
-
- rs690_before_pci_init();
- sb600_before_pci_init();
-}
diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig
deleted file mode 100644
index 2d2d4d172c..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/Kconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-if BOARD_AMD_SERENGETI_CHEETAH
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select SOUTHBRIDGE_AMD_AMD8132
- select SOUTHBRIDGE_AMD_AMD8151
- select CPU_AMD_SOCKET_F
- select DIMM_DDR2
- select DIMM_REGISTERED
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_AMD8111
- select SOUTHBRIDGE_AMD_AMD8131
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_WINBOND_W83627HF
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select WAIT_BEFORE_CPUS_INIT
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_512
- select QRANK_DIMM_SUPPORT
- select DRIVERS_I2C_I2CMUX
-
-config MAINBOARD_DIR
- string
- default amd/serengeti_cheetah
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x8
-
-config MAINBOARD_PART_NUMBER
- string
- default "Serengeti Cheetah"
-
-config MAX_CPUS
- int
- default 8
-
-config MAX_PHYSICAL_CPUS
- int
- default 4
-
-config MEM_TRAIN_SEQ
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x6
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0xa
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_AMD_SERENGETI_CHEETAH
diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig.name b/src/mainboard/amd/serengeti_cheetah/Kconfig.name
deleted file mode 100644
index 8a15a9bdde..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AMD_SERENGETI_CHEETAH
- bool "Serengeti Cheetah"
diff --git a/src/mainboard/amd/serengeti_cheetah/Makefile.inc b/src/mainboard/amd/serengeti_cheetah/Makefile.inc
deleted file mode 100644
index 876b3edbf4..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/Makefile.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-$(eval $(call asl_template,ssdt2))
-$(eval $(call asl_template,ssdt3))
-$(eval $(call asl_template,ssdt4))
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
deleted file mode 100644
index aaa778b7ee..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2005 AMD
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-//AMD8111
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
- })
-
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
- // Update the Device Number according to SBDN
- Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
-
- Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) {
- Return (PICM)
- }
- Else {
- Return (APIC)
- }
- }
-
- Device (SBC3)
- {
- /* ACPI smbus it should be 0x00040003 if 8131 present */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
- }
- OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
- Field (PIRQ, ByteAcc, Lock, Preserve)
- {
- PIBA, 8,
- PIDC, 8
- }
-/*
- OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
- Field (TS3_, DWordAcc, NoLock, Preserve)
- {
- PTS3, 16
- }
-*/
- }
-
- Device (HPET)
- {
- Name (HPT, 0x00)
- Name (_HID, EisaId ("PNP0103"))
- Name (_UID, 0x00)
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
- })
- Return (BUF0)
- }
- }
-
- #include "amd8111_pic.asl"
-
- #include "amd8111_isa.asl"
-
- Device (TP2P)
- {
- /* 8111 P2P and it should 0x00030000 when 8131 present*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x08, 0x03 }) }
- Else { Return (Package (0x02) { 0x08, 0x01 }) }
- }
-
- Device (USB0)
- {
- Name (_ADR, 0x00000000)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Device (USB1)
- {
- Name (_ADR, 0x00000001)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Name (APIC, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
- })
-
- Name (PICM, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
- })
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl
deleted file mode 100644
index 8ec776b477..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <cpu/x86/lapic_def.h>
-
-/*
- * Copyright 2005 AMD
- */
-//AMD8111 isa
-
- Device (ISA)
- {
- /* lpc 0x00040000 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
- }
-
- OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
- Field (PIRY, ByteAcc, NoLock, Preserve)
- {
- Z000, 2, // Parallel Port Range
- , 1,
- ECP, 1, // ECP Enable
- FDC1, 1, // Floppy Drive Controller 1
- FDC2, 1, // Floppy Drive Controller 2
- Offset (0x01),
- Z001, 3, // Serial Port A Range
- SAEN, 1, // Serial Post A Enabled
- Z002, 3, // Serial Port B Range
- SBEN, 1 // Serial Post B Enabled
- }
-
- Device (PIC)
- {
- Name (_HID, EisaId ("PNP0000"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
- IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
- IRQ (Edge, ActiveHigh, Exclusive) {2}
- })
- }
-
- Device (DMA1)
- {
- Name (_HID, EisaId ("PNP0200"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
- IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
- IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
- DMA (Compatibility, NotBusMaster, Transfer16) {4}
- })
- }
-
- Device (TMR)
- {
- Name (_HID, EisaId ("PNP0100"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
- IRQ (Edge, ActiveHigh, Exclusive) {0}
- })
- }
-
- Device (RTC)
- {
- Name (_HID, EisaId ("PNP0B00"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
- IRQ (Edge, ActiveHigh, Exclusive) {8}
- })
- }
-
- Device (SPKR)
- {
- Name (_HID, EisaId ("PNP0800"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
- })
- }
-
- Device (COPR)
- {
- Name (_HID, EisaId ("PNP0C04"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
- IRQ (Edge, ActiveHigh, Exclusive) {13}
- })
- }
-
- Device (SYSR)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x00)
- Name (SYR1, ResourceTemplate ()
- {
- IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM
- IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
- IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
- IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
- IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
- IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
- IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
- IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
- IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
- IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
- IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
- IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
- IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- })
- Method (_CRS, 0, NotSerialized)
- {
- Return (SYR1)
- }
- }
-
- Device (MEM)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
- Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404
- Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000)
- Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
- Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000)
- Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
- })
- // Read the Video Memory length
- CreateDWordField (BUF0, 0x14, CLEN)
- CreateDWordField (BUF0, 0x10, CBAS)
-
- ShiftLeft (VGA1, 0x09, Local0)
- Store (Local0, CLEN)
-
- Return (BUF0)
- }
- }
-
- Device (PS2M)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Name (_CRS, ResourceTemplate ()
- {
- IRQNoFlags () {12}
- })
- Method (_STA, 0, NotSerialized)
- {
- And (FLG0, 0x04, Local0)
- If (LEqual (Local0, 0x04)) { Return (0x0F) }
- Else { Return (0x00) }
- }
- }
-
- Device (PS2K)
- {
- Name (_HID, EisaId ("PNP0303"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- }
- #include "superio.asl"
-
- }
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_pic.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_pic.asl
deleted file mode 100644
index aa67ecb3d0..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_pic.asl
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2005 AMD
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-//AMD8111 pic LNKA B C D
-
- Device (LNKA)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x01)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
- Else { Return (0x0B) } //Enabled
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- { // Routing enable
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKB)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKC)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x03)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
-
- Device (LNKD)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x04)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl
deleted file mode 100644
index b9a6677a7a..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2005 AMD
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x14)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
-
- //Cypress Slot A - PIRQ BCDA
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
-
- //Cypress Slot B - PIRQ CDAB
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
-
- //Cypress Slot C - PIRQ DABC
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
-
- //Cypress Slot D - PIRQ ABCD
- Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
- })
- Name (PICM, Package (0x14)
- {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-
- Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
-
- Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl
deleted file mode 100644
index b0dbb450bc..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2005 AMD
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
-
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl
deleted file mode 100644
index 02b9ee21a3..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2005 AMD
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
-
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl
deleted file mode 100644
index 53fd725a31..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// AMD8151
- Device (AGPB)
- {
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/pci0_hc.asl b/src/mainboard/amd/serengeti_cheetah/acpi/pci0_hc.asl
deleted file mode 100644
index 2b21a25f5b..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/acpi/pci0_hc.asl
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
- #include "amd8111.asl" //real SB at first
- #include "amd8131.asl"
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/pci2_hc.asl b/src/mainboard/amd/serengeti_cheetah/acpi/pci2_hc.asl
deleted file mode 100644
index 5fc8c99b6d..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/acpi/pci2_hc.asl
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
- #include "amd8132_2.asl"
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/pci3_hc.asl b/src/mainboard/amd/serengeti_cheetah/acpi/pci3_hc.asl
deleted file mode 100644
index 0d9cd7ed59..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/acpi/pci3_hc.asl
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
- #include "amd8151.asl"
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/pci4_hc.asl b/src/mainboard/amd/serengeti_cheetah/acpi/pci4_hc.asl
deleted file mode 100644
index 3f04ac8704..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/acpi/pci4_hc.asl
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
- #include "amd8131_2.asl"
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/superio.asl b/src/mainboard/amd/serengeti_cheetah/acpi/superio.asl
deleted file mode 100644
index 8ce8bc00fe..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/acpi/superio.asl
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// #include "w83627hf.asl"
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
deleted file mode 100644
index 97a612e866..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
- *
- * Copyright 2005 AMD
- * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * Island Aruma ACPI support
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include <cbfs.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include "mb_sysconf.h"
-#include "mainboard.h"
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- u32 gsi_base = 0x18;
-
- struct mb_sysconf_t *m;
-
- m = sysconf.mb;
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write 8111 IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111,
- IO_APIC_ADDR, 0);
-
- /* Write all 8131 IOAPICs */
- {
- struct device *dev;
- struct resource *res;
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1,
- res->base, gsi_base);
- gsi_base+=7;
-
- }
- }
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2,
- res->base, gsi_base);
- gsi_base+=7;
- }
- }
-
- int i;
- int j = 0;
-
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- u32 d = 0;
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
- /* 8131 need to use +4 */
- switch (sysconf.hcid[i]) {
- case 1:
- d = 7;
- break;
- case 3:
- d = 4;
- break;
- }
- switch (sysconf.hcid[i]) {
- case 1:
- case 3:
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
- res->base, gsi_base);
- gsi_base+=d;
- }
- }
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
- res->base, gsi_base);
- gsi_base+=d;
-
- }
- }
- break;
- }
- j++;
- }
- }
-
- current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 5);
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high*/
-
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapic_nmis(current, 5, 1);
- /* 1: LINT1 connect to NMI */
-
- return current;
-}
-
-unsigned long mainboard_write_acpi_tables(struct device *dev, unsigned long start, acpi_rsdp_t *rsdp)
-{
- unsigned long current;
- acpi_header_t *ssdtx;
- const void *p;
- size_t p_size;
-
- int i;
-
- get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
-
- /* Align ACPI tables to 16 bytes */
- start = ALIGN(start, 16);
- current = start;
-
- /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
-
- for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
- const char *file_name;
- if ((sysconf.pci1234[i] & 1) != 1)
- continue;
- u8 c;
- if (i < 7)
- c = (u8) ('4' + i - 1);
- else
- c = (u8) ('A' + i - 1 - 6);
- current = ALIGN(current, 8);
- printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */
- ssdtx = (acpi_header_t *)current;
- switch(sysconf.hcid[i]) {
- case 1: /* 8132 */
- file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml";
- break;
- case 2: /* 8151 */
- file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml";
- break;
- case 3: /* 8131 */
- file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml";
- break;
- default:
- continue;
- }
- p = cbfs_boot_map_with_leak(
- file_name,
- CBFS_TYPE_RAW, &p_size);
- if (!p || p_size < sizeof(acpi_header_t))
- continue;
-
- memcpy(ssdtx, p, sizeof(acpi_header_t));
- current += ssdtx->length;
- memcpy(ssdtx, p, ssdtx->length);
- update_ssdtx((void *)ssdtx, i);
- ssdtx->checksum = 0;
- ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
- acpi_add_table(rsdp, ssdtx);
- }
-
- return current;
-}
diff --git a/src/mainboard/amd/serengeti_cheetah/board_info.txt b/src/mainboard/amd/serengeti_cheetah/board_info.txt
deleted file mode 100644
index 3d902b640a..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: server
diff --git a/src/mainboard/amd/serengeti_cheetah/cmos.layout b/src/mainboard/amd/serengeti_cheetah/cmos.layout
deleted file mode 100644
index 56ed652b97..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 400Mhz
-8 1 333Mhz
-8 2 266Mhz
-8 3 200Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb
deleted file mode 100644
index 8ff0e3effe..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb
+++ /dev/null
@@ -1,147 +0,0 @@
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_F
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1022 0x2b80 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on # northbridge
- # devices on link 0, link 0 == LDT 0
- chip southbridge/amd/amd8132
- # the on/off keyword is mandatory
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on end
- device pci 1.1 on end
- end
- chip southbridge/amd/amd8111
- # this "device pci 0.0" is the parent the next one
- # PCI bridge
- device pci 0.0 on
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 0.2 off end
- device pci 1.0 off end
- end
- device pci 1.0 on
- chip superio/winbond/w83627hf
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # CIR
- io 0x60 = 0x100
- end
- device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on end
- device pci 1.2 on end
- device pci 1.3 on
- chip drivers/i2c/i2cmux # pca9556 smbus mux
- device i2c 18 on #0 pca9516 1
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 0-1-1
- device i2c 53 on end
- end
- end
- device i2c 18 on #1 pca9516 2
- chip drivers/generic/generic #dimm 1-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 1-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 1-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 1-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic #dimm 1-2-0
- device i2c 54 on end
- end
- chip drivers/generic/generic #dimm 1-2-1
- device i2c 55 on end
- end
- chip drivers/generic/generic #dimm 1-3-0
- device i2c 56 on end
- end
- chip drivers/generic/generic #dimm 1-3-1
- device i2c 57 on end
- end
- end
- end
- end # acpi
- device pci 1.5 off end
- device pci 1.6 off end
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- end
- end # device pci 18.0
-
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- chip northbridge/amd/amdk8
- device pci 19.0 on # northbridge
- chip southbridge/amd/amd8151
- # the on/off keyword is mandatory
- device pci 0.0 on end
- device pci 1.0 on end
- end
- end # device pci 19.0
-
- device pci 19.0 on end
- device pci 19.0 on end
- device pci 19.1 on end
- device pci 19.2 on end
- device pci 19.3 on end
- end
-
-
- end #domain
-end
diff --git a/src/mainboard/amd/serengeti_cheetah/dsdt.asl b/src/mainboard/amd/serengeti_cheetah/dsdt.asl
deleted file mode 100644
index 7e119af5dd..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/dsdt.asl
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2005 AMD
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_PR)
- {
- Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
- Processor (CPU1, 0x01, 0x00000000, 0x00) {}
- Processor (CPU2, 0x02, 0x00000000, 0x00) {}
- Processor (CPU3, 0x03, 0x00000000, 0x00) {}
-
- }
-
- Method (FWSO, 0, NotSerialized) { }
-
-
- Scope (_SB)
- {
- Device (PCI0)
- {
- /* BUS0 root bus */
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
- External (CBST)
-
-
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00180000)
- Name (_UID, 0x01)
-
- Name (HCIN, 0x00) // HC1
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
- IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
- IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x8100, // Address Range Minimum
- 0xFFFF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x7F00,,,
- , TypeStatic) //8100h-FFFFh
-
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, // Address Space Granularity
- 0x000C0000, // Address Range Minimum
- 0x000CFFFF, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00010000,,,
- , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
-
- Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x03AF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x03B0,,,
- , TypeStatic) //0-CF7h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x03E0, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0918,,,
- , TypeStatic) //0-CF7h
- })
- \_SB.OSVR ()
- CreateDWordField (BUF0, 0x3E, VLEN)
- CreateDWordField (BUF0, 0x36, VMAX)
- CreateDWordField (BUF0, 0x32, VMIN)
- ShiftLeft (VGA1, 0x09, Local0)
- Add (VMIN, Local0, VMAX)
- Decrement (VMAX)
- Store (Local0, VLEN)
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- #include "acpi/pci0_hc.asl"
-
- }
- Device (PCI1)
- {
- Name (_HID, "PNP0A03")
- Name (_ADR, 0x00000000)
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.PCI0.CBST)
- }
- Name (_BBN, 0x00)
- }
-
-
- }
-
- Scope (_GPE)
- {
- Method (_L08, 0, NotSerialized)
- {
- Notify (\_SB.PCI0, 0x02) //PME# Wakeup
- }
-
- Method (_L0F, 0, NotSerialized)
- {
- Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
- }
-
- Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
- {
- Notify (\_SB.PCI0.PG0B, 0x02)
- }
-
- Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
- {
- Notify (\_SB.PCI0.PG0A, 0x02)
- }
- }
-
- Method (_PTS, 1, NotSerialized)
- {
- Or (Arg0, 0xF0, Local0)
- Store (Local0, DBG1)
- }
-/*
- Method (_WAK, 1, NotSerialized)
- {
- Or (Arg0, 0xE0, Local0)
- Store (Local0, DBG1)
- }
-*/
- Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
- Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
- {
- Store (Arg0, PICF)
- }
-
- OperationRegion (DEBG, SystemIO, 0x80, 0x01)
- Field (DEBG, ByteAcc, Lock, Preserve)
- {
- DBG1, 8
- }
-
- OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
- Field (EXTM, WordAcc, Lock, Preserve)
- {
- AMEM, 32
- }
-
- OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
- Field (VGAM, ByteAcc, Lock, Preserve)
- {
- VGA1, 8
- }
-
- OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
- Field (GRAM, ByteAcc, Lock, Preserve)
- {
- Offset (0x10),
- FLG0, 8
- }
-
- OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
- Field (GSTS, ByteAcc, NoLock, Preserve)
- {
- , 4,
- IRQR, 1
- }
-
- OperationRegion (Z007, SystemIO, 0x21, 0x01)
- Field (Z007, ByteAcc, NoLock, Preserve)
- {
- Z008, 8
- }
-
- OperationRegion (Z009, SystemIO, 0xA1, 0x01)
- Field (Z009, ByteAcc, NoLock, Preserve)
- {
- Z00A, 8
- }
-
- #include "northbridge/amd/amdk8/util.asl"
-
-}
diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c
deleted file mode 100644
index 6cf5197149..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/fadt.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-
-extern unsigned pm_base; /* pm_base should be set in sb ACPI */
-
-void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
-
- acpi_header_t *header=&(fadt->header);
-
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
- /* Prepare the header */
- memset((void *)fadt,0,sizeof(acpi_fadt_t));
- memcpy(header->signature,"FACP",4);
- header->length = 244;
- header->revision = 3;
- memcpy(header->oem_id,OEM_ID,6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id,ASLC,4);
- header->asl_compiler_revision = 0;
-
- fadt->firmware_ctrl=(u32)facs;
- fadt->dsdt= (u32)dsdt;
- /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
- fadt->preferred_pm_profile = 0x03;
- fadt->sci_int = 9;
- /* disable system management mode by setting to 0: */
- fadt->smi_cmd = 0;/* pm_base+0x2f */
- fadt->acpi_enable = 0xf0;
- fadt->acpi_disable = 0xf1;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0xe2;
-
- fadt->pm1a_evt_blk = pm_base;
- fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = pm_base+0x04;
- fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = 0x0000;
- fadt->pm_tmr_blk = pm_base+0x08;
- fadt->gpe0_blk = pm_base+0x20;
- fadt->gpe1_blk = pm_base+0xb0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 0;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 4;
- fadt->gpe1_blk_len = 8;
- fadt->gpe1_base = 16;
-
- fadt->cst_cnt = 0xe3;
- fadt->p_lvl2_lat = 101;
- fadt->p_lvl3_lat = 1001;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 1;
- fadt->duty_width = 3;
- fadt->day_alrm = 0; /* 0x7d these have to be */
- fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
- fadt->century = 0; /* 0x7f to make rtc alrm work */
- fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
- fadt->flags = 0x25;
-
- fadt->res2 = 0;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 6;
- fadt->x_firmware_ctl_l = (u32)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = pm_base;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 4;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = pm_base+4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 2;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = 0x0;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = pm_base+0x08;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 32;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = pm_base+0x20;
- fadt->x_gpe0_blk.addrh = 0x0;
-
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 64;
- fadt->x_gpe1_blk.bit_offset = 16;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = pm_base+0xb0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-
-}
diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
deleted file mode 100644
index dd0b43a1fc..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include <stdlib.h>
-#include "mb_sysconf.h"
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
-struct mb_sysconf_t mb_sysconf;
-
-static unsigned pci1234x[] = { /*Here you only need to set value in pci1234 for HT-IO that could be installed or not */
- /* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */
- 0x0000ff0,
- 0x0000ff0,
-};
-
-static unsigned hcdnx[] = { /* HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */
- 0x20202020,
- 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-static unsigned get_hcid(unsigned i)
-{
- unsigned id = 0;
-
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-
- unsigned devn = sysconf.hcdn[i] & 0xff;
-
- struct device *dev;
-
- dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
-
- switch (dev->device) {
- case 0x7458: /*8132 */
- id = 1;
- break;
- case 0x7454: /*8151 */
- id = 2;
- break;
- case 0x7450: /*8131 */
- id = 3;
- break;
- }
-
- /* we may need more way to find out hcid: subsystem id? GPIO read ? */
-
- /* we need use id for 1. bus num, 2. mptable, 3. ACPI table */
-
- return id;
-}
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
-
- struct device *dev;
- int i, j;
- struct mb_sysconf_t *m;
-
- if (get_bus_conf_done == 1)
- return; /* do it only once */
-
- get_bus_conf_done = 1;
-
- sysconf.mb = &mb_sysconf;
-
- m = sysconf.mb;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
- m->sbdn3 = sysconf.hcdn[0] & 0xff;
-
- m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff;
- m->bus_8111_0 = m->bus_8132_0;
-
- /* 8111 */
- dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn, 0));
- if (dev) {
- m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_8111_0, sysconf.sbdn);
- }
-
- /* 8132-1 */
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 0));
- if (dev) {
- m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_8132_0, m->sbdn3);
- }
-
- /* 8132-2 */
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3 + 1, 0));
- if (dev) {
- m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_8132_0, m->sbdn3 + 1);
- }
-
- /* HT chain 1 */
- j = 0;
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
-
- /* check hcid type here */
- sysconf.hcid[i] = get_hcid(i);
-
- switch (sysconf.hcid[i]) {
-
- case 1: /* 8132 */
- case 3: /* 8131 */
-
- m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
-
- m->sbdn3a[j] = sysconf.hcdn[i] & 0xff;
-
- /* 8132-1 */
- dev =
- dev_find_slot(m->bus_8132a[j][0],
- PCI_DEVFN(m->sbdn3a[j], 0));
- if (dev) {
- m->bus_8132a[j][1] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_8132a[j][0], m->sbdn3a[j]);
- }
-
- /* 8132-2 */
- dev =
- dev_find_slot(m->bus_8132a[j][0],
- PCI_DEVFN(m->sbdn3a[j] + 1, 0));
- if (dev) {
- m->bus_8132a[j][2] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_8132a[j][0], m->sbdn3a[j] + 1);
- }
-
- break;
-
- case 2: /* 8151 */
-
- m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
- m->sbdn5[j] = sysconf.hcdn[i] & 0xff;
- /* 8151 */
- dev =
- dev_find_slot(m->bus_8151[j][0],
- PCI_DEVFN(m->sbdn5[j] + 1, 0));
-
- if (dev) {
- m->bus_8151[j][1] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_8151[j][0], m->sbdn5[j] + 1);
- }
-
- break;
- }
-
- j++;
- }
-
-/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(3);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- m->apicid_8111 = apicid_base + 0;
- m->apicid_8132_1 = apicid_base + 1;
- m->apicid_8132_2 = apicid_base + 2;
- for (i = 0; i < j; i++) {
- m->apicid_8132a[i][0] = apicid_base + 3 + i * 2;
- m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1;
- }
-}
diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c
deleted file mode 100644
index 331ce76c5a..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
-
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
-
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
-
- uint8_t sum = 0;
- int i;
-
- struct mb_sysconf_t *m;
-
- get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
-
- m = sysconf.mb;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = m->bus_8111_0;
- pirq->rtr_devfn = ((sysconf.sbdn + 1) << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1022;
- pirq->rtr_device = 0x746b;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- {
- struct device *dev;
- dev =
- dev_find_slot(m->bus_8111_0,
- PCI_DEVFN(sysconf.sbdn + 1, 3));
- if (dev) {
- /* initialize PCI interupts - these assignments depend
- on the PCB routing of PINTA-D
-
- PINTA = IRQ3
- PINTB = IRQ5
- PINTC = IRQ10
- PINTD = IRQ11
- */
- pci_write_config16(dev, 0x56, 0xba53);
- }
- }
-
-/* pci bridge */
- printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n");
- static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 };
- pci_assign_irqs(m->bus_8111_0, sysconf.sbdn + 1, slotIrqs_1_4);
- write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-
- printk(BIOS_DEBUG, "setting Onboard AMD USB\n");
- static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11 };
- pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0);
- write_pirq_info(pirq_info, m->bus_8111_1, 0, 0, 0, 0, 0, 0, 0, 0x4,
- 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
-/* pcix bridge */
-
- int j = 0;
-
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
- unsigned devn = sysconf.hcdn[i] & 0xff;
-
- write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8,
- 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
- j++;
-
- }
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/serengeti_cheetah/mainboard.c b/src/mainboard/amd/serengeti_cheetah/mainboard.c
deleted file mode 100644
index 3c3234c3d3..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/mainboard.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/acpi.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include "mainboard.h"
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/serengeti_cheetah/mainboard.h b/src/mainboard/amd/serengeti_cheetah/mainboard.h
deleted file mode 100644
index 2613374e3c..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/mainboard.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start, acpi_rsdp_t *rsdp);
diff --git a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h
deleted file mode 100644
index 2aeede0793..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_8132_0;
- unsigned char bus_8132_1;
- unsigned char bus_8132_2;
- unsigned char bus_8111_0;
- unsigned char bus_8111_1;
-
- unsigned char bus_8132a[7][3];
-
- unsigned char bus_8151[7][2];
-
- unsigned apicid_8111;
- unsigned apicid_8132_1;
- unsigned apicid_8132_2;
- unsigned apicid_8132a[7][2];
-
- unsigned sbdn3;
- unsigned sbdn3a[7];
- unsigned sbdn5[7];
-
-};
-
-#endif
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
deleted file mode 100644
index 020e9515ee..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-#include <cpu/amd/multicore.h>
-#endif
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int i, j, bus_isa;
- struct mb_sysconf_t *m;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- m = sysconf.mb;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/* I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */
- {
- struct device *dev;
- struct resource *res;
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res)
- smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
- res2mmio(res, 0, 0));
- }
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res)
- smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
- res2mmio(res, 0, 0));
- }
-
- j = 0;
-
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
-
- switch(sysconf.hcid[i]) {
- case 1: /* 8132 */
- case 3: /* 8131 */
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res)
- smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
- res2mmio(res, 0, 0));
- }
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res)
- smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
- res2mmio(res, 0, 0));
- }
- break;
- }
- j++;
- }
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
-
-/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-/* ??? What */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
-
-/* Onboard AMD USB */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
-
-/*Slot 3 PCI 32 */
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */
-
-
-/* Slot 4 PCI 32 */
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */
-
-
-/* Slot 1 PCI-X 133/100/66 */
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4);
-
-
-/* Slot 2 PCI-X 133/100/66 */
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */
-
- j = 0;
-
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
- int ii;
- struct device *dev;
- struct resource *res;
- switch(sysconf.hcid[i]) {
- case 1:
- case 3:
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- /* Slot 1 PCI-X 133/100/66 */
- for (ii = 0; ii < 4; ii++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4);
- }
- }
-
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- /* Slot 2 PCI-X 133/100/66 */
- for (ii = 0; ii < 4; ii++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); /* 25 */
- }
- }
-
- break;
- case 2:
-
- /* Slot AGP */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
- break;
- }
-
- j++;
- }
-
-
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
deleted file mode 100644
index 0dbf303935..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-At this time, For ACPI support We got
-1. support AMK K8 SRAT --- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c)
-2. support MADT ---- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
-3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{acpi/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
-4. Chipset support: amd8111, amd8132
-
-The developers need to change for different MB
-
-Change dsdt.asl, according to MB layout
- pci1, pci2, pci3, pci4, ...., pci8
- if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c
-
-Change acpi_tables.c
- sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is coreboot run-time configurable now.
- if there is HT-IO board, need to preset pci1234 array. acpi_tables.c will decide to put the SSDT on the RSDT or not according if the HT-IO board is installed
-
-Regarding pci bridge apic and pic
- need to modify entries amd8111.asl and amd8131.asl and amd8151.asl.... acording to your MB laybout, it is like that in mptable.c
-
-About other chipsets, need to develop their special asl such as
- ck804.asl --- NB ck804
- bcm5785.asl or bcm5780.asl ---- Serverworks HT1000/HT2000
-
-use a to create hex file
-use c to delele hex file
-
-yhlu
-
-09/18/2005
diff --git a/src/mainboard/amd/serengeti_cheetah/resourcemap.c b/src/mainboard/amd/serengeti_cheetah/resourcemap.c
deleted file mode 100644
index 92eaa9c481..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/resourcemap.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, /* AMD 8111 on link0 of CPU 0 */
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, /* AMD 8151 on link0 of CPU 1 */
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
deleted file mode 100644
index 5a8b6378f0..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/early_smbus.c"
-#include <reset.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include <delay.h>
-
-#include <cpu/amd/mtrr.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <northbridge/amd/amdk8/f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-unsigned get_sbdn(unsigned bus);
-
-static void memreset_setup(void)
-{
- /* GPIO on amd8111 to enable MEMRST ???? */
- outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */
- outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#define SMBUS_HUB 0x18
- int ret,i;
- unsigned device=(ctrl->channel0[0])>>8;
- /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time */
- i = 2;
- do {
- ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- } while ((ret != 0) && (i-->0));
-
- smbus_write_byte(SMBUS_HUB, 0x03, 0);
-}
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "southbridge/amd/amd8111/early_ctrl.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-
-#define RC0 ((1 << 0)<<8)
-#define RC1 ((1 << 1)<<8)
-#define RC2 ((1 << 2)<<8)
-#define RC3 ((1 << 3)<<8)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- /* first node */
- RC0|DIMM0, RC0|DIMM2, 0, 0,
- RC0|DIMM1, RC0|DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- /* second node */
- RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
- RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
-#endif
-#if CONFIG_MAX_PHYSICAL_CPUS > 2
- /* third node */
- RC2|DIMM0, RC2|DIMM2, 0, 0,
- RC2|DIMM1, RC2|DIMM3, 0, 0,
- /* four node */
- RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
- RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
-#endif
-
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset;
- unsigned bsp_apicid = 0;
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- struct cpuid_result cpuid1;
-#endif
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
- setup_mb_resource_map();
-
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */
- setup_coherent_ht_domain(); /* routing table and start other core0 */
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched */
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- cpuid1 = cpuid(0x80000007);
- if ((cpuid1.edx & 0x6) == 0x6) {
-
- {
- /* Read FIDVID_STATUS */
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
-
- /* show final fid and vid */
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-
- } else {
- printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
- }
-#endif
-
-#if 1
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
-
- /* fidvid change will issue one LDTSTOP and the HT change will be effective too */
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
- }
-#endif
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl in sysinfo now; */
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
- memreset_setup();
-
- /* do we need apci timer, tsc...., only debug need it for better output */
- /* all ap stopped? */
- /* Need to use TMICT to synchronize FID/VID */
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt2.asl b/src/mainboard/amd/serengeti_cheetah/ssdt2.asl
deleted file mode 100644
index c18c75f3f7..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/ssdt2.asl
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2005 AMD
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- #include "acpi/pci2_hc.asl"
- }
- }
-
-}
diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt3.asl b/src/mainboard/amd/serengeti_cheetah/ssdt3.asl
deleted file mode 100644
index c17fba0cb4..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/ssdt3.asl
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2005 AMD
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- #include "acpi/pci3_hc.asl"
- }
- }
-
-}
diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt4.asl b/src/mainboard/amd/serengeti_cheetah/ssdt4.asl
deleted file mode 100644
index 68b2b665f9..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/ssdt4.asl
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2005 AMD
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- #include "acpi/pci4_hc.asl"
- }
- }
-
-}
diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig
deleted file mode 100644
index 2148385def..0000000000
--- a/src/mainboard/asrock/939a785gmh/Kconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-if BOARD_ASROCK_939A785GMH
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_939
- select K8_HT_FREQ_1G_SUPPORT
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_RS780
- select SOUTHBRIDGE_AMD_SB700
- select SUPERIO_WINBOND_W83627DHG
- select HAVE_ACPI_TABLES
- select HAVE_ACPI_RESUME
- select HAVE_MP_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_OPTION_TABLE
- select LIFT_BSP_APIC_ID
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select BOARD_ROMSIZE_KB_1024
- select GFXUMA
- select RAMINIT_SYSINFO
- select QRANK_DIMM_SUPPORT
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default asrock/939a785gmh
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "939A785GMH"
-
-config MAX_CPUS
- int
- default 8
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_ASROCK_939A785GMH
diff --git a/src/mainboard/asrock/939a785gmh/Kconfig.name b/src/mainboard/asrock/939a785gmh/Kconfig.name
deleted file mode 100644
index 270239120f..0000000000
--- a/src/mainboard/asrock/939a785gmh/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASROCK_939A785GMH
- bool "939A785GMH/128M"
diff --git a/src/mainboard/asrock/939a785gmh/acpi/ide.asl b/src/mainboard/asrock/939a785gmh/acpi/ide.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/asrock/939a785gmh/acpi/ide.asl
+++ /dev/null
diff --git a/src/mainboard/asrock/939a785gmh/acpi/routing.asl b/src/mainboard/asrock/939a785gmh/acpi/routing.asl
deleted file mode 100644
index 65afe39b7a..0000000000
--- a/src/mainboard/asrock/939a785gmh/acpi/routing.asl
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "routing.asl"
- }
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
- Name(PR0, Package(){
- /* NB devices */
- /* Bus 0, Dev 0 - RS780 Host Controller */
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-
- Package(){0x0002FFFF, 0, INTC, 0 },
- Package(){0x0002FFFF, 1, INTD, 0 },
- Package(){0x0002FFFF, 2, INTA, 0 },
- Package(){0x0002FFFF, 3, INTB, 0 },
-
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0011FFFF, 0, INTA, 0 },
-
- /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
- * EHCI, dev 18, 19 func 2 */
- Package(){0x0012FFFF, 0, INTA, 0 },
- Package(){0x0012FFFF, 1, INTB, 0 },
- Package(){0x0012FFFF, 2, INTC, 0 },
- Package(){0x0012FFFF, 3, INTD, 0 },
-
- Package(){0x0013FFFF, 0, INTC, 0 },
- Package(){0x0013FFFF, 1, INTD, 0 },
- Package(){0x0013FFFF, 2, INTA, 0 },
- Package(){0x0013FFFF, 3, INTB, 0 },
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
- Package(){0x0014FFFF, 0, INTA, 0 },
- Package(){0x0014FFFF, 1, INTB, 0 },
- Package(){0x0014FFFF, 2, INTC, 0 },
- Package(){0x0014FFFF, 3, INTD, 0 },
- })
-
- Name(APR0, Package(){
- /* NB devices in APIC mode */
- /* Bus 0, Dev 0 - RS780 Host Controller */
-
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Package(){0x0001FFFF, 0, 0, 18 }, */
- /* Package(){0x0001FFFF, 1, 0, 19 }, */
-
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, 0, 18 },
- Package(){0x0002FFFF, 1, 0, 19 },
- Package(){0x0002FFFF, 2, 0, 16 },
- Package(){0x0002FFFF, 3, 0, 17 },
-
- /* Bus 0, Dev 9 - PCIe x1 slot */
- Package(){0x0009FFFF, 0, 0, 17 },
- Package(){0x0009FFFF, 1, 0, 18 },
- Package(){0x0009FFFF, 2, 0, 19 },
- Package(){0x0009FFFF, 3, 0, 10 },
-
- /* Bus 0, Dev A - PCIe internal ethernet */
- Package(){0x000AFFFF, 0, 0, 18 },
- Package(){0x000AFFFF, 1, 0, 19 },
- Package(){0x000AFFFF, 2, 0, 16 },
- Package(){0x000AFFFF, 3, 0, 17 },
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices in APIC mode */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0011FFFF, 0, 0, 22 },
-
- /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
- * EHCI, dev 18, 19 func 2 */
- Package(){0x0012FFFF, 0, 0, 16 },
- Package(){0x0012FFFF, 1, 0, 17 },
- Package(){0x0012FFFF, 2, 0, 18 },
- Package(){0x0012FFFF, 3, 0, 19 },
-
- Package(){0x0013FFFF, 0, 0, 18 },
- Package(){0x0013FFFF, 1, 0, 19 },
- Package(){0x0013FFFF, 2, 0, 16 },
- Package(){0x0013FFFF, 3, 0, 17 },
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
- Package(){0x0014FFFF, 0, 0, 16 },
- Package(){0x0014FFFF, 1, 0, 17 },
- Package(){0x0014FFFF, 2, 0, 18 },
- Package(){0x0014FFFF, 3, 0, 19 },
- })
-
- Name(PR1, Package(){
- /* Internal graphics - RS780 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, INTC, 0 },
- Package(){0x0005FFFF, 1, INTD, 0 },
- Package(){0x0005FFFF, 2, INTA, 0 },
- Package(){0x0005FFFF, 3, INTB, 0 },
- })
-
- Name(APR1, Package(){
- /* Internal graphics - RS780 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, 0, 18 },
- Package(){0x0005FFFF, 1, 0, 19 },
- Package(){0x0005FFFF, 2, 0, 16 },
- Package(){0x0005FFFF, 3, 0, 11 },
- })
-
- Name(PS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS9, Package(){
- /* PCIe slot - Hooked to PCIe x1 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
-
- Name(APS9, Package(){
- /* PCIe slot - Hooked to PCIe x1 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
- Name(PSa, Package(){
- /* PCIe slot - Hooked to ethernet */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
-
- Name(APSa, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PCIB, Package(){
- /* PCI slots: slot 0, slot 1, behind Dev14, Fun4. */
- Package(){0x0005FFFF, 0, 0, 0x14 },
- Package(){0x0005FFFF, 1, 0, 0x15 },
- Package(){0x0005FFFF, 2, 0, 0x16 },
- Package(){0x0005FFFF, 3, 0, 0x17 },
- Package(){0x0006FFFF, 0, 0, 0x15 },
- Package(){0x0006FFFF, 1, 0, 0x16 },
- Package(){0x0006FFFF, 2, 0, 0x17 },
- Package(){0x0006FFFF, 3, 0, 0x14 },
- })
-}
diff --git a/src/mainboard/asrock/939a785gmh/acpi/sata.asl b/src/mainboard/asrock/939a785gmh/acpi/sata.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/asrock/939a785gmh/acpi/sata.asl
+++ /dev/null
diff --git a/src/mainboard/asrock/939a785gmh/acpi/usb.asl b/src/mainboard/asrock/939a785gmh/acpi/usb.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/asrock/939a785gmh/acpi/usb.asl
+++ /dev/null
diff --git a/src/mainboard/asrock/939a785gmh/acpi_tables.c b/src/mainboard/asrock/939a785gmh/acpi_tables.c
deleted file mode 100644
index 6026a68ef9..0000000000
--- a/src/mainboard/asrock/939a785gmh/acpi_tables.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include <arch/cpu.h>
-#include <cpu/amd/powernow.h>
-#include <southbridge/amd/sb700/sb700.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- get_bus_conf();
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB700 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
- IO_APIC_ADDR, 0);
-
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high */
-
- /* create all subtables for processors */
- /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
- /* 1: LINT1 connect to NMI */
-
- return current;
-}
diff --git a/src/mainboard/asrock/939a785gmh/board_info.txt b/src/mainboard/asrock/939a785gmh/board_info.txt
deleted file mode 100644
index 0335c9bec1..0000000000
--- a/src/mainboard/asrock/939a785gmh/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Board name: 939A785GMH/128M
-Category: desktop
-Board URL: http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&s=939
-ROM package: DIP8
-ROM protocol: SPI
-Release year: 2009
diff --git a/src/mainboard/asrock/939a785gmh/cmos.layout b/src/mainboard/asrock/939a785gmh/cmos.layout
deleted file mode 100644
index e22e68a15a..0000000000
--- a/src/mainboard/asrock/939a785gmh/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-##
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asrock/939a785gmh/devicetree.cb b/src/mainboard/asrock/939a785gmh/devicetree.cb
deleted file mode 100644
index 8b40b9f6d4..0000000000
--- a/src/mainboard/asrock/939a785gmh/devicetree.cb
+++ /dev/null
@@ -1,131 +0,0 @@
-#Define gppsb_configuration, A=0, B=1, C=2, D=3, E=4(default)
-#Define gpp_configuration -> device 9 1x and device a 1x is 3 and device 9 2x is 2
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot (means if GFX slot are two 2 8x slots)
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_939
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1022 0x3060 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on # southbridge
- chip southbridge/amd/rs780
- device pci 0.0 on end # HT 0x9600
- device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
- device pci 2.0 on end # PCIE P2P bridge 16x slot
- device pci 3.0 off end # used in dual slot config
- device pci 4.0 off end # GPPSB
- device pci 5.0 off end # GPPSB
- device pci 6.0 off end # GPPSB
- device pci 7.0 off end # GPPSB
- device pci 8.0 off end # NB/SB Link P2P bridge
- device pci 9.0 on end # GPP for x1 slot
- device pci a.0 on end # GPP for internal network adapter
- register "gppsb_configuration" = "4" # Configuration ?
- register "gpp_configuration" = "3" # Configuration D default
- register "port_enable" = "0x60c"
- register "gfx_dev2_dev3" = "1"
- register "gfx_dual_slot" = "0"
- register "gfx_lane_reversal" = "0"
- register "gfx_tmds" = "0"
- register "gfx_compliance" = "0"
- register "gfx_reconfiguration" = "1"
- register "gfx_link_width" = "0"
- end
- chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus
- device pci 11.0 on end # SATA
- device pci 12.0 on end # USB
- device pci 12.1 on end # USB
- device pci 12.2 on end # USB
- device pci 13.0 on end # USB
- device pci 13.1 on end # USB
- device pci 13.2 on end # USB
- device pci 14.0 on # SM
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 0-1-1
- device i2c 53 on end
- end
- end # SM
- device pci 14.1 on end # IDE 0x439c
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC 0x439d
-
- chip superio/winbond/w83627dhg
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # PS/2 keyboard & mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- #device pnp 2e.6 off # SPI
- #end
- device pnp 2e.307 off # GPIO6
- end
- device pnp 2e.8 on # WDTO#, PLED
- end
- device pnp 2e.009 on # GPIO2
- end
- device pnp 2e.109 on # GPIO3
- end
- device pnp 2e.209 on # GPIO4
- end
- device pnp 2e.309 off # GPIO5
- end
- device pnp 2e.a off # ACPI
- end
- device pnp 2e.b on # HWM
- io 0x60 = 0x290
- end
- device pnp 2e.c off # PECI, SST
- end
- end #superio/winbond/w8362
-
- end #LPC
- device pci 14.4 on end # PCI 0x4384
- device pci 14.5 on end # USB 2
- register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
- end #southbridge/amd/sb700
- end # device pci 18.0
-
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end #northbridge/amd/amdk8
- end #domain
-end #northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/asrock/939a785gmh/dsdt.asl b/src/mainboard/asrock/939a785gmh/dsdt.asl
deleted file mode 100644
index 9c50f96386..0000000000
--- a/src/mainboard/asrock/939a785gmh/dsdt.asl
+++ /dev/null
@@ -1,634 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "ASROCK", /* OEMID */
- "COREBOOT", /* TABLE ID */
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
- #include "northbridge/amd/amdk8/util.asl"
-
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
-
- Name(PMOD, One) /* Assume APIC */
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- #include "acpi/routing.asl"
-
- Scope(\_SB) {
-
- Method(_PIC, 0x01, NotSerialized)
- {
- If (Arg0)
- {
- \_SB.CIRQ()
- }
- Store(Arg0, PMOD)
- }
-
- Method(CIRQ, 0x00, NotSerialized){
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTA._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTE._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_PRS\n") */
- Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
- } /* End Scope(_SB) */
-
- #include <southbridge/amd/common/acpi/sleepstates.asl>
-
- /* Wake status package */
-
- Name(WKST,Package(){Zero, Zero})
-
- /* System Bus */
- Scope(\_SB) { /* Start \_SB scope */
- #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0) {
-
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* GPP x1 */
- Device(PBR9) {
- Name(_ADR, 0x00090000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS9) } /* APIC mode */
- Return (PS9) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR9 */
-
- /* ethernet */
- Device(PBRa) {
- Name(_ADR, 0x000A0000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APSa) } /* APIC mode */
- Return (PSa) /* PIC Mode */
- } /* end _PRT */
- } /* end PBRa */
-
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
-
- Device(LIBR) {
- Name(_ADR, 0x00140003)
- /* Method(_INI) {
- * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
- } */ /* End Method(_SB.SBRDG._INI) */
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){8}
- IO(Decode16,0x0070, 0x0070, 0, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){0}
- IO(Decode16, 0x0040, 0x0040, 0, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 0, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){2}
- IO(Decode16,0x0020, 0x0020, 0, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,BusMaster,Transfer8){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
- IRQNoFlags(){13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPTM) {
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
- }
- Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBX)
- Store(HPBA, HPBX)
- Return(CRS)
- }
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- } /* end LIBR */
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- } /* End Device(PCI0) */
-
- } /* End \_SB scope */
-}
-/* End of ASL file */
diff --git a/src/mainboard/asrock/939a785gmh/get_bus_conf.c b/src/mainboard/asrock/939a785gmh/get_bus_conf.c
deleted file mode 100644
index 64b3ed7032..0000000000
--- a/src/mainboard/asrock/939a785gmh/get_bus_conf.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_rs780[11];
-u8 bus_sb700[2];
-u32 apicid_sb700;
-
-/*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
-u32 pci1234x[] = {
- 0x0000ff0,
-};
-
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
- 0x20202020,
-};
-
-u32 sbdn_rs780;
-u32 sbdn_sb700;
-
-
-
-static u32 get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- u32 apicid_base;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* do it only once */
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
- sbdn_rs780 = sysconf.sbdn;
- sbdn_sb700 = 0;
-
- for (i = 0; i < 2; i++) {
- bus_sb700[i] = 0;
- }
- for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
- bus_rs780[i] = 0;
- }
-
- bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_sb700[0] = bus_rs780[0];
-
- /* sb700 */
- dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
- if (dev) {
- bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- /* rs780 */
- for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
- dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
- if (dev) {
- bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
- /* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_sb700 = apicid_base + 0;
-}
diff --git a/src/mainboard/asrock/939a785gmh/irq_tables.c b/src/mainboard/asrock/939a785gmh/irq_tables.c
deleted file mode 100644
index ef2a3ec45c..0000000000
--- a/src/mainboard/asrock/939a785gmh/irq_tables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern u8 bus_rs780[8];
-extern u8 bus_sb700[2];
-extern unsigned long sbdn_sb700;
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_sb700[0];
- pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
deleted file mode 100644
index 85d9060c5e..0000000000
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "southbridge/amd/sb700/sb700.h"
-#include "southbridge/amd/sb700/smbus.h"
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-u8 is_dev3_present(void);
-
-static void pcie_rst_toggle(u8 val) {
- u8 byte;
-
- byte = pm_ioread(0x8d);
- byte &= ~(3 << 1);
- pm_iowrite(0x8d, byte);
-
- byte = pm_ioread(0x94);
- /* Output enable */
- byte &= ~(3 << 2);
- /* Toggle GPM8, GPM9 */
- byte &= ~(3 << 0);
- byte |= val;
- pm_iowrite(0x94, byte);
-}
-
-void set_pcie_dereset()
-{
- pcie_rst_toggle(0x3);
-}
-
-void set_pcie_reset()
-{
- pcie_rst_toggle(0x0);
-}
-
-#if 0 /* not tested yet */
-/********************************************************
-* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
- u8 byte;
- /*u32 sm_dev, ide_dev; */
- struct device *sm_dev, ide_dev;
-
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- pci_write_config8(ide_dev, 0x56, byte);
-}
-#endif /* get_ide_dma66 */
-
-u8 is_dev3_present(void)
-{
- return 0;
-}
-
-/*************************************************
-* enable the dedicated function in mahogany board.
-* This function called early than rs780_enable.
-*************************************************/
-static void mainboard_enable(struct device *dev)
-{
- printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-/* override the default SATA PHY setup */
-void sb7xx_51xx_setup_sata_phys(struct device *dev) {
- /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
- pci_write_config16(dev, 0x86, 0x2c00);
-
- /* RPR7.6.2 SATA GENI PHY ports setting */
- pci_write_config32(dev, 0x88, 0x01B48016);
- pci_write_config32(dev, 0x8c, 0x01B48016);
- pci_write_config32(dev, 0x90, 0x01B48016);
- pci_write_config32(dev, 0x94, 0x01B48016);
- pci_write_config32(dev, 0x98, 0x01B48016);
- pci_write_config32(dev, 0x9C, 0x01B48016);
-
- /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
- pci_write_config16(dev, 0xA0, 0xA07A);
- pci_write_config16(dev, 0xA2, 0xA07A);
- pci_write_config16(dev, 0xA4, 0xA07A);
- pci_write_config16(dev, 0xA6, 0xA07A);
- pci_write_config16(dev, 0xA8, 0xA07A);
- pci_write_config16(dev, 0xAA, 0xA0FF);
-}
diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c
deleted file mode 100644
index fe104d031f..0000000000
--- a/src/mainboard/asrock/939a785gmh/mptable.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern u8 bus_rs780[11];
-extern u8 bus_sb700[2];
-
-extern u32 apicid_sb700;
-
-extern u32 sbdn_rs780;
-extern u32 sbdn_sb700;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- u32 dword;
- u8 byte;
-
- dev =
- dev_find_slot(bus_sb700[0],
- PCI_DEVFN(sbdn_sb700 + 0x14, 0));
- if (dev) {
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700,
- 0x11,(void *) dword);
-
- /* Initialize interrupt mapping */
- /* aza */
- byte = pci_read_config8(dev, 0x63);
- byte &= 0xf8;
- byte |= 0; /* 0: INTA, ...., 7: INTH */
- pci_write_config8(dev, 0x63, byte);
-
- /* SATA */
- dword = pci_read_config32(dev, 0xac);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
- /* dword |= 1 << 22; PIC and APIC co exists */
- pci_write_config32(dev, 0xac, dword);
-
- /*
- * 00:12.0: PROG SATA : INT F
- * 00:13.0: INTA USB_0
- * 00:13.1: INTB USB_1
- * 00:13.2: INTC USB_2
- * 00:13.3: INTD USB_3
- * 00:13.4: INTC USB_4
- * 00:13.5: INTD USB2
- * 00:14.1: INTA IDE
- * 00:14.2: Prog HDA : INT E
- * 00:14.5: INTB ACI
- * 00:14.6: INTB MCI
- */
- }
- }
-
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asrock/939a785gmh/resourcemap.c b/src/mainboard/asrock/939a785gmh/resourcemap.c
deleted file mode 100644
index 0f1d4cb6e6..0000000000
--- a/src/mainboard/asrock/939a785gmh/resourcemap.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_939a785gmh_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
deleted file mode 100644
index d6a85ccee8..0000000000
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <spd.h>
-#include <cpu/x86/lapic.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627dhg/w83627dhg.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <southbridge/amd/sb700/sb700.h>
-#include <southbridge/amd/sb700/smbus.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
-#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
-
-unsigned get_sbdn(unsigned bus);
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(u32 device, u32 address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-#include <southbridge/amd/rs780/rs780.h>
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_init(void)
-{
- u8 reg;
-
- pnp_enter_ext_func_mode(GPIO2345_DEV);
- pnp_set_logical_device(GPIO2345_DEV);
-
- /* Pin 119 ~ 120 is GP21, GP20 */
- reg = pnp_read_config(GPIO2345_DEV, 0x29);
- pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2));
-
- /* Turn on the Power LED ("Suspend LED" in Super I/O) */
- reg = pnp_read_config(GPIO2345_DEV, 0xf3);
- pnp_write_config(GPIO2345_DEV, 0xf3, (reg | 0x40));
-
- /* todo document this */
- pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
- pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
-
- /* GPO20 - sideport voltage 1 = 1.82 0 = 1.92
- GPI21 - unknown input (NC?)
- GPI22 - unknown input (NC?)
- GPO23 - mgpuV bit0
- GP24-27 - PS/2 mouse/keyb (only keyb is connected use flip interface for mouse)
- */
- pnp_write_config(GPIO2345_DEV, 0x30, 0x07); /* Enable GPIO 2,3,4. */
- pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6); /* dir of GPIO2 11110110*/
- pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e); /* data */
- pnp_write_config(GPIO2345_DEV, 0xe5, 0x00); /* No inversion */
-
- /* GPIO30 - unknown output, set to 0
- GPI31 - unknown input NC?
- GPI32 - unknown input NC?
- GPIO33 - unknown output, set to 0.
- GPI34 - unknown input NC?
- GPO35 - loadline control 1 = enabled (2 phase clock) 0 = disabled 4 phase clock
- GPIO36 - input = HT voltage 1.30V output (low) = HT voltage 1.35V
- GP37 - unknown input NC? */
-
- pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6); /* dir of GPIO3 11010110*/
- pnp_write_config(GPIO2345_DEV, 0xf1, 0x96); /* data */
- pnp_write_config(GPIO2345_DEV, 0xf2, 0x00); /* No inversion */
-
- /* GPO40 - mgpuV bit2
- GPO41 - mgpuV bit1
- GPO42 - IRTX
- GPO43 - IRRX
- GPIO44 - memory voltage bit2 (input/outputlow)
- GPIO45 - memory voltage bit1 (2.60 (000) - 2.95 (111))
- GPIO46 - memory voltage bit0
- GPIO47 - unknown input? */
-
- pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0); /* dir of GPIO4 11010000 */
- pnp_write_config(GPIO2345_DEV, 0xf5, 0x83); /* data */
- pnp_write_config(GPIO2345_DEV, 0xf6, 0x00); /* No inversion */
-
- pnp_write_config(GPIO2345_DEV, 0xf7, 0x00); /* MFC */
- pnp_write_config(GPIO2345_DEV, 0xf8, 0x00); /* MFC */
- pnp_write_config(GPIO2345_DEV, 0xfe, 0x07); /* trig type */
- pnp_exit_ext_func_mode(GPIO2345_DEV);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- int needs_reset = 0;
- u32 bsp_apicid = 0;
- msr_t msr;
- struct cpuid_result cpuid1;
- struct sys_info *sysinfo = &sysinfo_car;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- /* sb7xx_51xx_lpc_port80(); */
- sb7xx_51xx_pci_port80();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- enable_rs780_dev8();
- sb7xx_51xx_lpc_init();
-
- sio_init();
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
- printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
-
- setup_939a785gmh_resource_map();
-
- setup_coherent_ht_domain();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched */
- wait_all_core0_started();
- start_other_cores();
-#endif
- wait_all_aps_started(bsp_apicid);
-
- ht_setup_chains_x(sysinfo);
-
- /* run _early_setup before soft-reset. */
- rs780_early_setup();
- sb7xx_51xx_early_setup();
-
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- cpuid1 = cpuid(0x80000007);
- if ((cpuid1.edx & 0x6) == 0x6) {
- /* Read FIDVID_STATUS */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
-
- /* show final fid and vid */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
- } else {
- printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
- }
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- rs780_htinit();
- printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
-
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now; */
- printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
- sysinfo->nodes, sysinfo->ctrl, spd_addr);
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
- sb7xx_51xx_before_pci_init();
-}
diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig
deleted file mode 100644
index 1852ae45e0..0000000000
--- a/src/mainboard/asus/a8n_e/Kconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-if BOARD_ASUS_A8N_E || BOARD_ASUS_A8N_SLI
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_939
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_CK804
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_ITE_IT8712F
- select HAVE_OPTION_TABLE
- select HAVE_CMOS_DEFAULT
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_512
- select CK804_USE_NIC
- select CK804_USE_ACI
- select QRANK_DIMM_SUPPORT
- select HAVE_ACPI_TABLES
-
-config MAINBOARD_DIR
- string
- default asus/a8n_e
-
-config DCACHE_RAM_BASE
- hex
- default 0xcf000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x01000
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-if BOARD_ASUS_A8N_E
-config MAINBOARD_PART_NUMBER
- string
- default "A8N-E"
-endif
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 13
-
-endif # BOARD_ASUS_A8N_E
diff --git a/src/mainboard/asus/a8n_e/Kconfig.name b/src/mainboard/asus/a8n_e/Kconfig.name
deleted file mode 100644
index 02b00e7dd8..0000000000
--- a/src/mainboard/asus/a8n_e/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_A8N_E
- bool "A8N-E"
diff --git a/src/mainboard/asus/a8n_e/acpi_tables.c b/src/mainboard/asus/a8n_e/acpi_tables.c
deleted file mode 100644
index da90fd3ddf..0000000000
--- a/src/mainboard/asus/a8n_e/acpi_tables.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * ACPI support
- * written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
- *
- * Copyright 2005 AMD
- * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "../../../northbridge/amd/amdk8/acpi.h"
-
-/* APIC */
-unsigned long acpi_fill_madt(unsigned long current)
-{
- struct device *dev;
- struct resource *res;
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write NVIDIA CK804 IOAPIC. */
- dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
- ASSERT(dev != NULL);
-
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- ASSERT(res != NULL);
-
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
- CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0);
-
- /* Initialize interrupt mapping if mptable.c didn't. */
-#if (!CONFIG_GENERATE_MP_TABLE)
-#error untested config
- pci_write_config32(dev, 0x7c, 0x0120d218);
- pci_write_config32(dev, 0x80, 0x12008a00);
- pci_write_config32(dev, 0x84, 0x0000007d);
-#endif
-
- /* IRQ of timer */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- /* IRQ9 */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* create all subtables for processors */
- /* acpi_create_madt_lapic_nmis returns current, not size. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/a8n_e/board_info.txt b/src/mainboard/asus/a8n_e/board_info.txt
deleted file mode 100644
index 2e3e6424e0..0000000000
--- a/src/mainboard/asus/a8n_e/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_Socket_939/A8NE/
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2005
diff --git a/src/mainboard/asus/a8n_e/cmos.default b/src/mainboard/asus/a8n_e/cmos.default
deleted file mode 100644
index 84dd0274af..0000000000
--- a/src/mainboard/asus/a8n_e/cmos.default
+++ /dev/null
@@ -1,11 +0,0 @@
-boot_option=Fallback
-debug_level=Spew
-power_on_after_fail=Enable
-ECC_memory=Disable
-hw_scrubber=Enable
-interleave_chip_selects=Enable
-max_mem_clock=DDR400
-multi_core=Enable
-slow_cpu=off
-nmi=Enable
-iommu=Enable
diff --git a/src/mainboard/asus/a8n_e/cmos.layout b/src/mainboard/asus/a8n_e/cmos.layout
deleted file mode 100644
index dc2977b250..0000000000
--- a/src/mainboard/asus/a8n_e/cmos.layout
+++ /dev/null
@@ -1,56 +0,0 @@
-entries
- 0 384 r 0 reserved_memory
- 384 1 e 4 boot_option
- 386 1 e 1 ECC_memory
- 388 4 h 0 reboot_counter
-# 392 3 r 0 unused
- 395 1 e 1 hw_scrubber
- 396 1 e 1 interleave_chip_selects
- 397 2 e 8 max_mem_clock
- 399 1 e 2 multi_core
- 400 1 e 1 power_on_after_fail
- 412 4 e 6 debug_level
- 440 4 e 9 slow_cpu
- 444 1 e 1 nmi
- 445 1 e 1 iommu
- 728 256 h 0 user_data
- 984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
- 1000 24 r 0 reserved_memory1
-
-enumerations
-
-#ID value text
- 1 0 Disable
- 1 1 Enable
- 2 0 Enable
- 2 1 Disable
- 4 0 Fallback
- 4 1 Normal
-
- 6 5 Notice
- 6 6 Info
- 6 7 Debug
- 6 8 Spew
- 7 0 Network
- 7 1 HDD
- 7 2 Floppy
- 7 8 Fallback_Network
- 7 9 Fallback_HDD
- 7 10 Fallback_Floppy
- 8 0 DDR400
- 8 1 DDR333
- 8 2 DDR266
- 8 3 DDR200
- 9 0 off
- 9 1 87.5 %
- 9 2 75.0 %
- 9 3 62.5 %
- 9 4 50.0 %
- 9 5 37.5 %
- 9 6 25.0 %
- 9 7 12.5 %
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/a8n_e/devicetree.cb b/src/mainboard/asus/a8n_e/devicetree.cb
deleted file mode 100644
index bbbfeb89f2..0000000000
--- a/src/mainboard/asus/a8n_e/devicetree.cb
+++ /dev/null
@@ -1,121 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_939 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
-
- device domain 0 on # PCI domain
- subsystemid 0x1043 0x815a inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/ck804 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/ite/it8712f # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2 (N/A on this board)
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.4 on # Environment controller
- io 0x60 = 0x290
- io 0x62 = 0x0000
- irq 0x70 = 0x00
- end
- device pnp 2e.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x71 = 2
- end
- device pnp 2e.6 on # PS/2 mouse
- irq 0x70 = 12
- irq 0x71 = 2
- end
- device pnp 2e.7 on # GPIO config
- io 0x60 = 0x0800
- io 0x62 = 0x0808
- io 0x64 = 0x0810
- # Set GPIO 1 & 2
- io 0x25 = 0x0000
- # Set GPIO 3 & 4
- io 0x27 = 0x2540
- # GPIO Polarity for Set 3
- io 0xb2 = 0x2100
- # GPIO Pin Internal Pull up for Set 3
- io 0xba = 0x0100
- # Simple I/O register config
- io 0xc0 = 0x0000
- io 0xc2 = 0x2540
- io 0xc8 = 0x0000
- io 0xca = 0x0500
- end
- device pnp 2e.8 on # MIDI port
- io 0x60 = 0x300
- irq 0x70 = 10
- end
- device pnp 2e.9 on # Game port
- io 0x60 = 0x201
- end
- device pnp 2e.a off # IR (N/A on this board)
- io 0x60 = 0x310
- irq 0x70 = 11
- end
- end
- end
- device pci 1.1 on # SM 0
- # chip drivers/generic/generic # DIMM 0-0-0
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # DIMM 0-0-1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # DIMM 0-1-0
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # DIMM 0-1-1
- # device i2c 53 on end
- # end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # Onboard audio (ACI)
- device pci 4.1 off end # Onboard modem (MCI), N/A
- device pci 6.0 on end # IDE
- device pci 7.0 on end # SATA 1
- device pci 8.0 on end # SATA 0
- device pci 9.0 on end # PCI
- device pci a.0 on end # NIC
- device pci b.0 on end # PCI E 3
- device pci c.0 on end # PCI E 2
- device pci d.0 on end # PCI E 1
- device pci e.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # TODO
- # register "mac_eeprom_smbus" = "3"
- # register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/a8n_e/dsdt.asl b/src/mainboard/asus/a8n_e/dsdt.asl
deleted file mode 100644
index 45aeaf1c21..0000000000
--- a/src/mainboard/asus/a8n_e/dsdt.asl
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * Any others would involve declaring the wake up methods.
- */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
-
- Name (PICM, 0x00)
- Method (_PIC, 1, Serialized) {
- Store (Arg0, PICM)
- }
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device (CK804) */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
-#include "southbridge/nvidia/ck804/acpi/ck804.asl"
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LLAS, 0x00 },//APCS
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LLAS, 0x00 },//APCS
- Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LUOH, 0x00 },//APCF
- Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LUEH, 0x00 },//APCL
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LAUD, 0x00 },//APCJ
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LMOD, 0x00 },//APCK
- Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LPA0, 0x00 },//APCZ
- Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 },//APSI
- Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 },//APSJ
-
- Package (0x04) { 0x0009FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
-
- Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 },//APCH
-
- Package (0x04) { 0x000BFFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//APC2
- Package (0x04) { 0x000BFFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },//APC3
- Package (0x04) { 0x000BFFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },//APC4
- Package (0x04) { 0x000BFFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },//APC1
-
- Package (0x04) { 0x000CFFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//APC1
- Package (0x04) { 0x000CFFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },//APC2
- Package (0x04) { 0x000CFFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },//APC3
- Package (0x04) { 0x000CFFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },//APC4
-
- Package (0x04) { 0x000DFFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//APC4
- Package (0x04) { 0x000DFFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },//APC1
- Package (0x04) { 0x000DFFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },//APC2
- Package (0x04) { 0x000DFFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },//APC3
-
- Package (0x04) { 0x000EFFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//APC3
- Package (0x04) { 0x000EFFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },//APC4
- Package (0x04) { 0x000EFFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },//APC1
- Package (0x04) { 0x000EFFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },//APC2
- })
-
- Device (PCIC)
- {
- Name (_ADR, 0x00090000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- /* AGR slot */
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
- })
- }
-
- /* 2:00 PCIe x1 */
- Device (PEX1)
- {
- Name (_ADR, 0x000d0000)
- Name (_UID, 0x00)
- }
-
- /* 3:00 PCIe x16 */
- Device (PEX0)
- {
- Name (_ADR, 0x000e0000)
- Name (_UID, 0x00)
- }
-
- Device (LPC) {
- Name (_HID, EisaId ("PNP0A05"))
- Name (_ADR, 0x00010000)
-
- OperationRegion (CF44, PCI_Config, 0x44, 0x04)
- Field (CF44, ByteAcc, NoLock, Preserve)
- {
- ETBA, 32,
- }
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* Parallel port */
- Device (LP0)
- {
- Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- FixedIO (0x0378, 0x10)
- IRQNoFlags () {7}
- })
- Return (TMP)
- }
- }
-
- /* Floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- FixedIO (0x03F0, 0x08)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
-#if 0
- Device (HPET)
- {
- Name (_HID, EisaId ("PNP0103"))
- Name (CRS, ResourceTemplate ()
- {
- Memory32Fixed (ReadOnly,
- 0x00000000,
- 0x00001000,
- _Y02)
- })
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
- Method (_CRS, 0, NotSerialized)
- {
- CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT)
- Store (ETBA, HPT)
- Return (CRS)
- }
-
- }
-#endif
- }
- }
- }
-}
diff --git a/src/mainboard/asus/a8n_e/get_bus_conf.c b/src/mainboard/asus/a8n_e/get_bus_conf.c
deleted file mode 100644
index b1e94d8896..0000000000
--- a/src/mainboard/asus/a8n_e/get_bus_conf.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-/*
- * Global variables for MB layouts and these will be shared by irqtable,
- * mptable and acpi_tables.
- */
-/* busnum is default */
-unsigned char bus_ck804[6];
-unsigned apicid_ck804;
-
-/*
- * Here you only need to set value in pci1234 for HT-IO that could be installed
- * or not. You may need to preset pci1234 for HT-IO board, please refer to
- * src/northbridge/amd/amdk8/get_sblk_pci1234.c for details.
- */
-unsigned pci1234x[] = {
- 0x0000ff0, /* No HTIO for A8N-E */
-};
-
-/*
- * HT Chain device num, actually it is unit id base of every ht device in
- * chain, assume every chain only have 4 ht device at most.
- */
-unsigned hcdnx[] = {
- 0x20202020, /* A8N-E has only one ht-chain */
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- unsigned apicid_base, sbdn;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* Do it only once. */
-
- get_bus_conf_done = 1;
-
- /* FIXME: Is this really needed twice? */
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- sbdn = sysconf.sbdn;
-
- for (i = 0; i < 6; i++)
- bus_ck804[i] = 0;
-
- bus_ck804[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* CK804 */
- dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0));
- if (dev) {
- bus_ck804[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804[2]++;
- } else {
- printk
- (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x09);
- bus_ck804[1] = 2;
- bus_ck804[2] = 3;
- }
-
- for (i = 2; i < 6; i++) {
- dev = dev_find_slot(bus_ck804[0],
- PCI_DEVFN(sbdn + 0x0b + i - 2, 0));
- if (dev) {
- bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804[0], sbdn + 0x0b + i - 2);
- }
- }
-
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(3);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_ck804 = apicid_base + 0;
-}
diff --git a/src/mainboard/asus/a8n_e/irq_tables.c b/src/mainboard/asus/a8n_e/irq_tables.c
deleted file mode 100644
index 59d506df01..0000000000
--- a/src/mainboard/asus/a8n_e/irq_tables.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_isa;
-extern unsigned char bus_ck804[6];
-
-
-/**
- * Add one line to IRQ table.
- */
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-/**
- * Create the IRQ routing table.
- * Values are derived from getpir generated code.
- */
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num, sbdn;
- uint8_t *v, sum = 0;
- int i;
-
- /* get_bus_conf() will find out all bus num and APIC that share with
- * mptable.c and mptable.c.
- */
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000. */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *)(addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
- pirq->rtr_bus = bus_ck804[0];
- pirq->rtr_devfn = ((sbdn + 9) << 3) | 0;
- pirq->exclusive_irqs = 0x828;
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x005c;
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* Slot1 PCIE 16x */
- write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4,
- 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot2 PCIE 1x */
- write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot3 PCIE 1x */
- write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2,
- 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot4 PCIE 4x */
- write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2,
- 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot5 - Slot7 PCI */
- for (i = 0; i < 3; i++) {
- write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0,
- ((i + 0) % 4) + 1, 0xdeb8,
- ((i + 1) % 4) + 1, 0xdeb8,
- ((i + 2) % 4) + 1, 0xdeb8,
- ((i + 3) % 4) + 1, 0xdeb8, i, 0);
- pirq_info++;
- slot_num++;
- }
-
- /* PCI bridge */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SMBus */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* USB */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* Audio */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 4) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SATA */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SATA */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* NIC */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 0xa) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-#if 0
- /* Firewire? */
- write_pirq_info(pirq_info, bus_ck804_1, (0x5 << 3) | 0, 0x3, 0xdeb8, 0,
- 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-#endif
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum)
- pirq->checksum = sum;
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c
deleted file mode 100644
index 40a06a4c77..0000000000
--- a/src/mainboard/asus/a8n_e/mptable.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_ck804[6];
-extern unsigned apicid_ck804;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned sbdn;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11,
- res2mmio(res, 0, 0));
- }
-
- /* Initialize interrupt mapping. */
- dword = 0x01200000;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x12008009;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0x0002010d;
- pci_write_config32(dev, 0x84, dword);
-
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
-
- // Onboard ck804 smbus
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
- 0xa);
-
- // Onboard ck804 USB 1.1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
- 0x15);
-
- // Onboard ck804 USB 2
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
- 0x14);
-
- /* Onboard audio */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 4) << 2) | 0, apicid_ck804, 0x3);
-
- // Onboard ck804 SATA 0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
- 0x17);
-
- // Onboard ck804 SATA 1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
- 0x16);
-
- // Onboard ck804 NIC
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804,
- 0x17);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_ck804[0]);
-
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
deleted file mode 100644
index e4ed339924..0000000000
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Used by ite_enable_serial(). */
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
-#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <cpu/x86/lapic.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <console/console.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include <southbridge/nvidia/ck804/early_smbus.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include <southbridge/nvidia/ck804/early_setup_ss.h>
-#include "southbridge/nvidia/ck804/early_setup.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- /* Subject decoding */
- byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
-
- /* LPC Positive Decode 0 */
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
- dword |= (1 << 0) | (1 << 1); /* Serial 0, Serial 1 */
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
-#endif
- };
-
- int needs_reset;
- unsigned nodes, bsp_apicid = 0;
- struct mem_controller ctrl[8];
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx);
-
- ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 0));
-#endif
-
- needs_reset = setup_coherent_ht_domain();
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched. */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- needs_reset |= ht_setup_chains_x();
- needs_reset |= ck804_early_setup_x();
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- nodes = get_nodes();
- /* It's the time to set ctrl now. */
- fill_mem_ctrl(nodes, ctrl, spd_addr);
-
- enable_smbus();
-
-#if 0
- dump_spd_registers(&ctrl[0]);
- dump_smbus_registers();
-#endif
-
- sdram_initialize(nodes, ctrl);
-
-#if 0
- print_pci_devices();
- dump_pci_devices();
-#endif
-}
diff --git a/src/mainboard/asus/a8n_sli/Kconfig b/src/mainboard/asus/a8n_sli/Kconfig
deleted file mode 100644
index e2ac03dea5..0000000000
--- a/src/mainboard/asus/a8n_sli/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if BOARD_ASUS_A8N_SLI
-
-# Dummy for abuild
-
-config MAINBOARD_PART_NUMBER
- string
- default "A8N-SLI"
-
-endif
diff --git a/src/mainboard/asus/a8n_sli/Kconfig.name b/src/mainboard/asus/a8n_sli/Kconfig.name
deleted file mode 100644
index 700bdc291a..0000000000
--- a/src/mainboard/asus/a8n_sli/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_A8N_SLI
- bool "A8N-SLI"
diff --git a/src/mainboard/asus/a8n_sli/board_info.txt b/src/mainboard/asus/a8n_sli/board_info.txt
deleted file mode 100644
index e9b47eb220..0000000000
--- a/src/mainboard/asus/a8n_sli/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Board URL: http://www.asus.com/Motherboards/AMD_Socket_939/A8NSLI/
-Category: desktop
-ROM package: PLCC
-ROM socketed: y
-Flashrom support: y
-Clone of: asus/a8n_e
-Release year: 2005
diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig
deleted file mode 100644
index b067047ae1..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/Kconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-if BOARD_ASUS_A8V_E_DELUXE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_939
- select K8_HT_FREQ_1G_SUPPORT
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_VIA_VT8237R
- select SOUTHBRIDGE_VIA_K8T890
- select SOUTHBRIDGE_VIA_SUBTYPE_K8T890
- select SUPERIO_WINBOND_W83627EHG
- select HAVE_OPTION_TABLE
- select HAVE_ACPI_TABLES
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_512
- select RAMINIT_SYSINFO
- select QRANK_DIMM_SUPPORT
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default asus/a8v-e_deluxe
-
-config DCACHE_RAM_BASE
- hex
- default 0xcc000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x4000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "A8V-E Deluxe"
-
-config HW_MEM_HOLE_SIZEK
- hex
- default 0x0
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-endif # BOARD_ASUS_A8V_E_DELUXE
diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig.name b/src/mainboard/asus/a8v-e_deluxe/Kconfig.name
deleted file mode 100644
index c55a1dd02e..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_A8V_E_DELUXE
- bool "A8V-E Deluxe"
diff --git a/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c b/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c
deleted file mode 100644
index 01382ede39..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-#include <cpu/amd/amdk8_sysconf.h>
-
-void get_bus_conf(void)
-{
- /* FIXME: implement this. */
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, IO_APIC_ADDR, 0);
-
- /* Write NB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/a8v-e_deluxe/board_info.txt b/src/mainboard/asus/a8v-e_deluxe/board_info.txt
deleted file mode 100644
index 497c8e9dfb..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_Socket_939/A8VE_Deluxe/
-ROM package: PLCC
-ROM socketed: y
-Flashrom support: y
-Release year: 2005
diff --git a/src/mainboard/asus/a8v-e_deluxe/cmos.layout b/src/mainboard/asus/a8v-e_deluxe/cmos.layout
deleted file mode 100644
index aae7ceb075..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/a8v-e_deluxe/devicetree.cb b/src/mainboard/asus/a8v-e_deluxe/devicetree.cb
deleted file mode 100644
index 5e56acca0a..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/devicetree.cb
+++ /dev/null
@@ -1,97 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # APIC cluster
- chip cpu/amd/socket_939 # CPU
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- subsystemid 1043 0 inherit
- chip northbridge/amd/amdk8 # mc0
- device pci 18.0 on # Northbridge
- # Devices on link 0, link 0 == LDT 0
- chip southbridge/via/vt8237r # Southbridge
- register "ide0_enable" = "1" # Enable IDE channel 0
- register "ide1_enable" = "1" # Enable IDE channel 1
- register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
- register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
- register "fn_ctrl_lo" = "0" # Enable SB functions
- register "fn_ctrl_hi" = "0xad" # Enable SB functions
- device pci 0.0 on end # HT
- device pci f.1 on end # IDE
- device pci 11.0 on # LPC
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip superio/winbond/w83627ehg # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2 (N/A on this board)
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 off # PS/2 keyboard & mouse (off)
- end
- device pnp 2e.106 off # Serial flash interface (SFI)
- io 0x60 = 0x100
- end
- device pnp 2e.007 off # GPIO 1
- end
- device pnp 2e.107 on # Game port
- io 0x60 = 0x201
- end
- device pnp 2e.207 on # MIDI
- io 0x62 = 0x330
- irq 0x70 = 0xa
- end
- device pnp 2e.307 off # GPIO 6
- end
- device pnp 2e.8 off # WDTO#, PLED
- end
- device pnp 2e.009 on # GPIO 2
- end
- device pnp 2e.109 off # GPIO 3
- end
- device pnp 2e.209 off # GPIO 4
- end
- device pnp 2e.309 on # GPIO 5
- end
- device pnp 2e.a off # ACPI
- end
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 0
- end
- end
- end
- device pci 12.0 off end # VIA LAN (off, other chip used)
- end
- chip southbridge/via/k8t890 # "Southbridge" K8T890
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl
deleted file mode 100644
index 06cc76accd..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
-{
- #include <southbridge/via/k8t890/acpi/sleepstates.asl>
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- /* PCI Routing Table */
- /* aaa */
- Name (_PRT, Package () {
- Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
- Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */
- Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
- Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */
- Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
- Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
- Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
- Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
- Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
- Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
- })
-
- Device (PEGG)
- {
- Name (_ADR, 0x00020000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
- })
- }
-
- Device (PEX0)
- {
- Name (_ADR, 0x00030000)
- Name (_UID, 0x00)
- Name (_BBN, 0x03)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
- })
- }
-
- Device (PEX1)
- {
- Name (_ADR, 0x00030001)
- Name (_UID, 0x00)
- Name (_BBN, 0x04)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
- })
- }
-
- Device (PEX2)
- {
- Name (_ADR, 0x00030002)
- Name (_UID, 0x00)
- Name (_BBN, 0x05)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
- })
- }
-
- Device (PEX3)
- {
- Name (_ADR, 0x00030003)
- Name (_UID, 0x00)
- Name (_BBN, 0x06)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
- })
- }
-
- Device (ISA) {
- Name (_ADR, 0x00110000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
- IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- }
- }
- }
-}
diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c
deleted file mode 100644
index f3d3d06207..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/mptable.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <stdint.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
-
- mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
deleted file mode 100644
index 5ade055bc8..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2006 MSI
- * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <halt.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/early_ht.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627ehg/w83627ehg.h>
-#include <southbridge/via/vt8237r/vt8237r.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <spd.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
-#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <reset.h>
-void do_soft_reset(void)
-{
- uint8_t tmp;
-
- set_bios_reset();
- printk(BIOS_DEBUG, "soft reset\n");
-
- /* PCI reset */
- tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
- tmp |= 0x01;
- pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
-
- halt();
-}
-
-#include "southbridge/via/k8t890/early_car.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
-}
-
-static void sio_init(void)
-{
- u8 reg;
-
- pnp_enter_conf_state(SERIAL_DEV);
- /* We have 24MHz input. */
- reg = pnp_read_config(SERIAL_DEV, 0x24);
- pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
- /* We have GPIO for KB/MS pin. */
- reg = pnp_read_config(SERIAL_DEV, 0x2a);
- pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
- /* We have all RESTOUT and even some reserved bits, too. */
- reg = pnp_read_config(SERIAL_DEV, 0x2c);
- pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
- pnp_exit_conf_state(SERIAL_DEV);
-
- pnp_enter_conf_state(ACPI_DEV);
- pnp_set_logical_device(ACPI_DEV);
- /*
- * Set the delay rising time from PWROK_LP to PWROK_ST to
- * 300 - 600ms, and 0 to vice versa.
- */
- reg = pnp_read_config(ACPI_DEV, 0xe6);
- pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
- /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
- reg = pnp_read_config(ACPI_DEV, 0xe4);
- pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
- pnp_exit_conf_state(ACPI_DEV);
-
- pnp_enter_conf_state(GPIO_DEV);
- pnp_set_logical_device(GPIO_DEV);
- /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
- pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
- pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
- pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
- pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0 = output 1 = input */
- pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */
- pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
- pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
- pnp_exit_conf_state(GPIO_DEV);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
- unsigned bsp_apicid = 0;
- int needs_reset = 0;
- struct sys_info *sysinfo = &sysinfo_car;
-
- sio_init();
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- enable_rom_decode();
-
- printk(BIOS_INFO, "now booting... romstage\n");
-
- /* Is this a CPU only reset? Or is this a secondary CPU? */
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0. */
- /* Allow the HT devices to be found. */
- enumerate_ht_chain();
- }
-
- printk(BIOS_INFO, "now booting... real_main\n");
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- /* Halt if there was a built in self test failure. */
- report_bist_failure(bist);
-
- setup_default_resource_map();
- setup_coherent_ht_domain();
- wait_all_core0_started();
-
- printk(BIOS_INFO, "now booting... Core0 started\n");
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched. */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
- init_timer();
- ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= k8t890_early_setup_ht();
-
- if (needs_reset) {
- printk(BIOS_DEBUG, "ht reset -\n");
- soft_reset();
- }
-
- /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
- enable_fid_change();
- init_fidvid_bsp(bsp_apicid);
-
- /* Stop the APs so we can start them later in init. */
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now. */
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig
deleted file mode 100644
index 0188ff98b5..0000000000
--- a/src/mainboard/asus/a8v-e_se/Kconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-if BOARD_ASUS_A8V_E_SE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_939
- select K8_HT_FREQ_1G_SUPPORT
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_VIA_VT8237R
- select SOUTHBRIDGE_VIA_K8T890
- select SOUTHBRIDGE_VIA_SUBTYPE_K8T890
- select SUPERIO_WINBOND_W83627EHG
- select HAVE_OPTION_TABLE
- select HAVE_ACPI_TABLES
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_512
- select RAMINIT_SYSINFO
- select QRANK_DIMM_SUPPORT
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default asus/a8v-e_se
-
-config DCACHE_RAM_BASE
- hex
- default 0xcc000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x4000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "A8V-E SE"
-
-config HW_MEM_HOLE_SIZEK
- hex
- default 0x0
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-endif # BOARD_ASUS_A8V_E_SE
diff --git a/src/mainboard/asus/a8v-e_se/Kconfig.name b/src/mainboard/asus/a8v-e_se/Kconfig.name
deleted file mode 100644
index 34afcd89c0..0000000000
--- a/src/mainboard/asus/a8v-e_se/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_A8V_E_SE
- bool "A8V-E SE"
diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c
deleted file mode 100644
index ab9811a127..0000000000
--- a/src/mainboard/asus/a8v-e_se/acpi_tables.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-void get_bus_conf(void)
-{
- /* FIXME: implement this. */
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, IO_APIC_ADDR, 0);
-
- /* Write NB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/a8v-e_se/board_info.txt b/src/mainboard/asus/a8v-e_se/board_info.txt
deleted file mode 100644
index c08475a48b..0000000000
--- a/src/mainboard/asus/a8v-e_se/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_Socket_939/A8VE_SE/
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2006
diff --git a/src/mainboard/asus/a8v-e_se/cmos.layout b/src/mainboard/asus/a8v-e_se/cmos.layout
deleted file mode 100644
index aae7ceb075..0000000000
--- a/src/mainboard/asus/a8v-e_se/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/a8v-e_se/devicetree.cb b/src/mainboard/asus/a8v-e_se/devicetree.cb
deleted file mode 100644
index f2d078a74e..0000000000
--- a/src/mainboard/asus/a8v-e_se/devicetree.cb
+++ /dev/null
@@ -1,97 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # APIC cluster
- chip cpu/amd/socket_939 # CPU
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1043 0 inherit
- chip northbridge/amd/amdk8 # mc0
- device pci 18.0 on # Northbridge
- # Devices on link 0, link 0 == LDT 0
- chip southbridge/via/vt8237r # Southbridge
- register "ide0_enable" = "1" # Enable IDE channel 0
- register "ide1_enable" = "1" # Enable IDE channel 1
- register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
- register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
- register "fn_ctrl_lo" = "0" # Enable SB functions
- register "fn_ctrl_hi" = "0xad" # Enable SB functions
- device pci 0.0 on end # HT
- device pci f.1 on end # IDE
- device pci 11.0 on # LPC
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip superio/winbond/w83627ehg # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2 (N/A on this board)
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 off # PS/2 keyboard & mouse (off)
- end
- device pnp 2e.106 off # Serial flash interface (SFI)
- io 0x60 = 0x100
- end
- device pnp 2e.007 off # GPIO 1
- end
- device pnp 2e.107 on # Game port
- io 0x60 = 0x201
- end
- device pnp 2e.207 on # MIDI
- io 0x62 = 0x330
- irq 0x70 = 0xa
- end
- device pnp 2e.307 off # GPIO 6
- end
- device pnp 2e.8 off # WDTO#, PLED
- end
- device pnp 2e.009 on # GPIO 2
- end
- device pnp 2e.109 off # GPIO 3
- end
- device pnp 2e.209 off # GPIO 4
- end
- device pnp 2e.309 on # GPIO 5
- end
- device pnp 2e.a off # ACPI
- end
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 0
- end
- end
- end
- device pci 12.0 off end # VIA LAN (off, other chip used)
- end
- chip southbridge/via/k8t890 # "Southbridge" K8T890
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/a8v-e_se/dsdt.asl b/src/mainboard/asus/a8v-e_se/dsdt.asl
deleted file mode 100644
index 1da24173e3..0000000000
--- a/src/mainboard/asus/a8v-e_se/dsdt.asl
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- #include <southbridge/via/k8t890/acpi/sleepstates.asl>
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
- Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */
- Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
- Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */
- Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
- Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
- Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
- Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
- Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
- Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
- })
-
- Device (PEGG)
- {
- Name (_ADR, 0x00020000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
- })
- }
-
- Device (PEX0)
- {
- Name (_ADR, 0x00030000)
- Name (_UID, 0x00)
- Name (_BBN, 0x03)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
- })
- }
-
- Device (PEX1)
- {
- Name (_ADR, 0x00030001)
- Name (_UID, 0x00)
- Name (_BBN, 0x04)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
- })
- }
-
- Device (PEX2)
- {
- Name (_ADR, 0x00030002)
- Name (_UID, 0x00)
- Name (_BBN, 0x05)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
- })
- }
-
- Device (PEX3)
- {
- Name (_ADR, 0x00030003)
- Name (_UID, 0x00)
- Name (_BBN, 0x06)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
- })
- }
-
- Device (ISA) {
- Name (_ADR, 0x00110000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
- IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- }
- /* Dummy device to hold auto generated reserved resources */
- Device(MBRS) {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- External(_CRS) /* Resource Template in SSDT */
- }
-
- }
- }
-}
diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c
deleted file mode 100644
index f3d3d06207..0000000000
--- a/src/mainboard/asus/a8v-e_se/mptable.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <stdint.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
-
- mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
deleted file mode 100644
index 2df2a48815..0000000000
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2006 MSI
- * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <halt.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/early_ht.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627ehg/w83627ehg.h>
-#include <southbridge/via/vt8237r/vt8237r.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <spd.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
-#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <reset.h>
-void do_soft_reset(void)
-{
- uint8_t tmp;
-
- set_bios_reset();
- printk(BIOS_DEBUG, "soft reset\n");
-
- /* PCI reset */
- tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
- tmp |= 0x01;
- pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
-
- halt();
-}
-
-#include "southbridge/via/k8t890/early_car.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
-}
-
-static void sio_init(void)
-{
- u8 reg;
-
- pnp_enter_conf_state(SERIAL_DEV);
- /* We have 24MHz input. */
- reg = pnp_read_config(SERIAL_DEV, 0x24);
- pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
- /* We have GPIO for KB/MS pin. */
- reg = pnp_read_config(SERIAL_DEV, 0x2a);
- pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
- /* We have all RESTOUT and even some reserved bits, too. */
- reg = pnp_read_config(SERIAL_DEV, 0x2c);
- pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
- pnp_exit_conf_state(SERIAL_DEV);
-
- pnp_enter_conf_state(ACPI_DEV);
- pnp_set_logical_device(ACPI_DEV);
- /*
- * Set the delay rising time from PWROK_LP to PWROK_ST to
- * 300 - 600ms, and 0 to vice versa.
- */
- reg = pnp_read_config(ACPI_DEV, 0xe6);
- pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
- /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
- reg = pnp_read_config(ACPI_DEV, 0xe4);
- pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
- pnp_exit_conf_state(ACPI_DEV);
-
- pnp_enter_conf_state(GPIO_DEV);
- pnp_set_logical_device(GPIO_DEV);
- /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
- pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
- pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
- pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
- pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0 = output 1 = input */
- pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */
- pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
- pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
- pnp_exit_conf_state(GPIO_DEV);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- 0, 0, 0, 0,
- // Node 1
- DIMM1, DIMM3, 0, 0,
- 0, 0, 0, 0,
- };
- unsigned bsp_apicid = 0;
- int needs_reset = 0;
- struct sys_info *sysinfo = &sysinfo_car;
-
- sio_init();
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- enable_rom_decode();
-
- printk(BIOS_INFO, "now booting... fallback\n");
-
- /* Is this a CPU only reset? Or is this a secondary CPU? */
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0. */
- /* Allow the HT devices to be found. */
- enumerate_ht_chain();
- }
-
- printk(BIOS_INFO, "now booting... real_main\n");
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- /* Halt if there was a built in self test failure. */
- report_bist_failure(bist);
-
- setup_default_resource_map();
- setup_coherent_ht_domain();
- wait_all_core0_started();
-
- printk(BIOS_INFO, "now booting... Core0 started\n");
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched. */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
- init_timer();
- ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= k8t890_early_setup_ht();
-
- if (needs_reset) {
- printk(BIOS_DEBUG, "ht reset -\n");
- soft_reset();
- }
-
- /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
- enable_fid_change();
- init_fidvid_bsp(bsp_apicid);
-
- /* Stop the APs so we can start them later in init. */
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now. */
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig
deleted file mode 100644
index 674059b0a5..0000000000
--- a/src/mainboard/asus/k8v-x/Kconfig
+++ /dev/null
@@ -1,69 +0,0 @@
-if BOARD_ASUS_K8V_X
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_754
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_VIA_VT8237R
- select SOUTHBRIDGE_VIA_K8T890
- select SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
- select SUPERIO_WINBOND_W83697HF
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_ACPI_TABLES
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_512
- select RAMINIT_SYSINFO
- select SET_FIDVID
- select K8_FORCE_2T_DRAM_TIMING
- select PIRQ_ROUTE
-
-config MAINBOARD_DIR
- string
- default asus/k8v-x
-
-config DCACHE_RAM_BASE
- hex
- default 0xcc000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x4000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "K8V-X"
-
-config AGP_APERTURE_SIZE
- hex
- default 0x10000000
-
-config HW_MEM_HOLE_SIZEK
- hex
- default 0x0
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_ASUS_K8V_X
diff --git a/src/mainboard/asus/k8v-x/Kconfig.name b/src/mainboard/asus/k8v-x/Kconfig.name
deleted file mode 100644
index 20a46315fa..0000000000
--- a/src/mainboard/asus/k8v-x/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_K8V_X
- bool "K8V-X"
diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c
deleted file mode 100644
index b992d1ad08..0000000000
--- a/src/mainboard/asus/k8v-x/acpi_tables.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8x8xx.h"
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-void get_bus_conf(void)
-{
- /* FIXME: implement this. */
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, IO_APIC_ADDR, 0);
-
- /* Write NB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/k8v-x/board_info.txt b/src/mainboard/asus/k8v-x/board_info.txt
deleted file mode 100644
index 65a26e43fd..0000000000
--- a/src/mainboard/asus/k8v-x/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: desktop
-Release year: 2005
diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout
deleted file mode 100644
index aae7ceb075..0000000000
--- a/src/mainboard/asus/k8v-x/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb
deleted file mode 100644
index 7764413c52..0000000000
--- a/src/mainboard/asus/k8v-x/devicetree.cb
+++ /dev/null
@@ -1,113 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # APIC cluster
- chip cpu/amd/socket_754 # CPU
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1043 0x80ed inherit
- chip northbridge/amd/amdk8 # mc0
- device pci 18.0 on # Northbridge
- # Devices on link 0, link 0 == LDT 0
- chip southbridge/via/vt8237r # Southbridge
- register "ide0_enable" = "1" # Enable IDE channel 0
- register "ide1_enable" = "1" # Enable IDE channel 1
- register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
- register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
- register "fn_ctrl_lo" = "0" # Enable SB functions
- register "fn_ctrl_hi" = "0xad" # Enable SB functions
- register "usb2_termination_set" = "1"
- register "usb2_termination_a" = "8"
- register "usb2_termination_b" = "8"
- register "usb2_termination_c" = "6"
- register "usb2_termination_d" = "6"
- register "usb2_termination_e" = "6"
- register "usb2_termination_f" = "6"
- register "usb2_termination_g" = "6"
- register "usb2_termination_h" = "6"
- register "usb2_dpll_set" = "1"
- register "usb2_dpll_delay" = "3"
- register "int_efgh_as_gpio" = "1"
- register "enable_gpo3" = "1"
- register "disable_gpo26_gpo27" = "1"
- register "enable_aol_2_smb_slave" = "1"
- register "enable_gpo5" = "1"
- register "gpio15_12_dir_output" = "1"
- device pci 0.0 on # HT
- subsystemid 0x1043 0x80a3
- end
- device pci a.0 on # GbE
- subsystemid 0x1043 0x811a
- end
- device pci f.0 on end # SATA
- device pci f.1 on end # IDE
- device pci 10.0 on end # USB1
- device pci 10.1 on end # USB1
- device pci 10.2 on end # USB1
- device pci 10.3 on end # USB1
- device pci 10.4 on end # USB2
- device pci 11.0 on # LPC
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip superio/winbond/w83697hf # Super I/O
- register "hwmon_fan1_divisor" = "128"
- register "hwmon_fan2_divisor" = "4"
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2 (N/A on this board)
- end
- device pnp 2e.6 off # CIR
- end
- device pnp 2e.7 off # Game port/GPIO 1
- end
- device pnp 2e.8 off # MIDI/GPIO 5
- end
- device pnp 2e.009 off # GPIO 2
- end
- device pnp 2e.109 off # GPIO 3
- end
- device pnp 2e.209 off # GPIO 4
- end
- device pnp 2e.a off # ACPI
- end
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 0
- irq 0x24 = 0x28 # Global CR24 change bit3: MEMW# Enable
- end
- end
- end
- device pci 11.5 on # AC97 Audio
- subsystemid 0x1043 0x80b0
- end
- device pci 11.6 on end # AC97 Modem
- device pci 12.0 off end # VIA LAN (off, other chip used)
- end
- chip southbridge/via/k8t890 # "Southbridge" K8T890
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl
deleted file mode 100644
index fc96e7630c..0000000000
--- a/src/mainboard/asus/k8v-x/dsdt.asl
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- #include <southbridge/via/k8t890/acpi/sleepstates.asl>
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
- Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */
- Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
- Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */
- Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
- Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */
- Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 },
- Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 },
- Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */
- Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */
- Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
- Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
- Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
- Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
- Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */
- })
-
- Device (ISA) {
- Name (_ADR, 0x00110000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
- IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- }
- /* Dummy device to hold auto generated reserved resources */
- Device(MBRS) {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- External(_CRS) /* Resource Template in SSDT */
- }
-
- }
- }
-}
diff --git a/src/mainboard/asus/k8v-x/irq_tables.c b/src/mainboard/asus/k8v-x/irq_tables.c
deleted file mode 100644
index 51b7dd1198..0000000000
--- a/src/mainboard/asus/k8v-x/irq_tables.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Urja Rannikko <urjaman@gmail.com>
- *
- * Code based on KFSN4-DRE irq_tables.c:
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint8_t link1, uint8_t link2,
- uint8_t link3, uint8_t slot, uint8_t rfu)
-{
- const uint16_t valid_irqs = 0xccb8;
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = link0 ? valid_irqs : 0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = link1 ? valid_irqs : 0;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = link2 ? valid_irqs : 0;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = link3 ? valid_irqs : 0;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- uint8_t *v, sum = 0;
- unsigned int slot_num = 0;
- int i;
-
- /* Align the table to be 16 byte aligned. */
- addr = ALIGN_UP(addr, 16);
-
- /* This table must be between 0xf0000 & 0x100000. */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *)(addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
- pirq->rtr_bus = 0;
- pirq->rtr_devfn = ((0x11) << 3) | 0;
- pirq->exclusive_irqs = 0;
- pirq->rtr_vendor = PCI_VENDOR_ID_VIA;
- pirq->rtr_device = PCI_DEVICE_ID_VIA_VT8237R_LPC;
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
-
- /* AGP Bridge. */
- write_pirq_info(pirq_info, 0, (0x01 << 3) | 0, 1, 2, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* ISA Bridge + AC97 + MC97 */
- write_pirq_info(pirq_info, 0, (0x11 << 3) | 0, 0, 0, 3, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* PATA and SATA. */
- write_pirq_info(pirq_info, 0, (0x0f << 3) | 0, 1, 2, 3, 5, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* USB (UHCI and EHCI) */
- write_pirq_info(pirq_info, 0, (0x10 << 3) | 0, 1, 2, 3, 5, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* 5 PCI Slots */
- write_pirq_info(pirq_info, 0, (0x0b << 3) | 0, 1, 2, 3, 5, 1, 0);
- pirq_info++;
- slot_num++;
-
- write_pirq_info(pirq_info, 0, (0x0c << 3) | 0, 2, 3, 5, 1, 2, 0);
- pirq_info++;
- slot_num++;
-
- write_pirq_info(pirq_info, 0, (0x0d << 3) | 0, 3, 5, 1, 2, 3, 0);
- pirq_info++;
- slot_num++;
-
- write_pirq_info(pirq_info, 0, (0x0e << 3) | 0, 5, 1, 2, 3, 4, 0);
- pirq_info++;
- slot_num++;
-
- write_pirq_info(pirq_info, 0, (0x09 << 3) | 0, 1, 2, 3, 5, 5, 0);
- pirq_info++;
- slot_num++;
-
- /* Ethernet */
- write_pirq_info(pirq_info, 0, (0x0a << 3) | 0, 2, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* AGP Slot. */
- write_pirq_info(pirq_info, 1, (0x00 << 3) | 0, 1, 2, 0, 0, 6, 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum)
- pirq->checksum = sum;
-
- printk(BIOS_INFO, "done.\n");
-
- /* Call copy for side effects: setting PCI IRQ registers. Hack? */
- return copy_pirq_routing_table(addr, pirq);
-}
diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c
deleted file mode 100644
index 9f35cd389b..0000000000
--- a/src/mainboard/asus/k8v-x/mainboard.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-
-u32 vt8237_ide_80pin_detect(struct device *dev)
-{
- struct device *lpc_dev;
- u16 acpi_io_base;
- u32 gpio_in;
- u32 res;
-
- lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
- if (!lpc_dev)
- return 0;
-
- acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1;
- if (!acpi_io_base)
- return 0;
-
- /* select function GPIO29 for pin AB9 */
- pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08);
-
- gpio_in = inl(acpi_io_base + 0x48);
- /* bit 29 for primary port, clear if unconnected or 80-pin cable */
- res = gpio_in & (1 << 29) ? 0 : VT8237R_IDE0_80PIN_CABLE;
- /* bit 8 for secondary port, clear if unconnected or 80-pin cable */
- res |= gpio_in & (1 << 8) ? 0 : VT8237R_IDE1_80PIN_CABLE;
-
- printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
- res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);
- printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary",
- res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40);
-
- return res;
-}
diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c
deleted file mode 100644
index 8525b029f1..0000000000
--- a/src/mainboard/asus/k8v-x/mptable.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <stdint.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8x8xx.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
-
- mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
deleted file mode 100644
index 053028497a..0000000000
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2006 MSI
- * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <halt.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/early_ht.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83697hf/w83697hf.h>
-#include <southbridge/via/vt8237r/vt8237r.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <spd.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <reset.h>
-void do_soft_reset(void)
-{
- uint8_t tmp;
-
- set_bios_reset();
- printk(BIOS_DEBUG, "soft reset\n");
-
- /* PCI reset */
- tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
- tmp |= 0x01;
- pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
-
- halt();
-}
-
-#include "southbridge/via/k8t890/early_car.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // Node 0
- DIMM0, DIMM1, DIMM2, 0,
- 0, 0, 0, 0,
- // Node 1
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- };
- unsigned bsp_apicid = 0;
- int needs_reset = 0;
- struct sys_info *sysinfo = &sysinfo_car;
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- enable_rom_decode();
-
- printk(BIOS_INFO, "now booting... fallback\n");
-
- /* Is this a CPU only reset? Or is this a secondary CPU? */
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0. */
- /* Allow the HT devices to be found. */
- enumerate_ht_chain();
- }
-
- printk(BIOS_INFO, "now booting... real_main\n");
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- /* Halt if there was a built in self test failure. */
- report_bist_failure(bist);
-
- setup_default_resource_map();
- setup_coherent_ht_domain();
- wait_all_core0_started();
-
- printk(BIOS_INFO, "now booting... Core0 started\n");
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched. */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
- init_timer();
- ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= k8t890_early_setup_ht();
-
- if (needs_reset) {
- printk(BIOS_DEBUG, "ht reset -\n");
- soft_reset();
- }
-
- /* the HT settings needs to be OK, because link freq change may cause HT disconnect */
- vt8237_sb_enable_fid_vid();
- enable_fid_change();
- init_fidvid_bsp(bsp_apicid);
-
- /* Stop the APs so we can start them later in init. */
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now. */
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
- /* this seems to be some GPIO on the SMBus--in any case, setting these
- * two bits reduces the pullup impedance of the bus lines and is required
- * in order to be able to read SPD info */
- smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80);
- smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10);
-
- unsigned char mask;
-
- mask = 0;
-// mask |= 1 /* AGP voltage 1.7 V (not verified, just vendor BIOS value) */
-// mask |= 2 /* V-Link voltage 2.6 V (not verified either) */
- smbus_write_byte(0x4a, 0x00, (smbus_read_byte(0x4a, 0x00) & ~0x0f) | (0x0f ^ (mask << 2)));
- smbus_write_byte(0x4a, 0x01, (smbus_read_byte(0x4a, 0x01) & ~0x03) | (0x03 ^ mask));
-
- mask = 25; /* RAM voltage in decivolts, valid range from 25 to 28 */
- mask = 3 - (mask - 25);
- smbus_write_byte(0x4a, 0x02, 0x4f | (mask << 4));
- smbus_write_byte(0x4a, 0x03, 0x04 | mask);
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/Kconfig b/src/mainboard/asus/kfsn4-dre_k8/Kconfig
deleted file mode 100644
index 0d13a4ece4..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/Kconfig
+++ /dev/null
@@ -1,98 +0,0 @@
-if BOARD_ASUS_KFSN4_DRE_K8
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_F
- select DIMM_DDR2
- select DIMM_REGISTERED
- select QRANK_DIMM_SUPPORT
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_CK804
- select SUPERIO_WINBOND_W83627THG
- select PARALLEL_CPU_INIT
- select HAVE_HARD_RESET
- select HAVE_OPTION_TABLE
- select HAVE_CMOS_DEFAULT
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select HAVE_ACPI_TABLES
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_1024
- select ENABLE_APIC_EXT_ID
- select K8_ALLOCATE_IO_RANGE
- select DRIVERS_I2C_W83793
- select DRIVERS_XGI_Z9S
-
-config MAINBOARD_DIR
- string
- default "asus/kfsn4-dre_k8"
-
-config BOOTBLOCK_MAINBOARD_INIT
- string
- default "mainboard/asus/kfsn4-dre_k8/bootblock.c"
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "KFSN4-DRE_K8"
-
-config HW_MEM_HOLE_SIZEK
- hex
- default 0x100000
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config MEM_TRAIN_SEQ
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 13
-
-config CK804_PCI_E_X
- int
- default 1
-
-config CK804_PCIE_PME_WAKE
- bool
- default y
-
-config ONBOARD_VGA_IS_PRIMARY
- bool
- default y
-
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
- bool
- default y
-
-config MAX_REBOOT_CNT
- int
- default 10
-
-endif # BOARD_ASUS_KFSN4_DRE_K8
diff --git a/src/mainboard/asus/kfsn4-dre_k8/Kconfig.name b/src/mainboard/asus/kfsn4-dre_k8/Kconfig.name
deleted file mode 100644
index 5720f3ef3f..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_KFSN4_DRE_K8
- bool "KFSN4-DRE_K8"
diff --git a/src/mainboard/asus/kfsn4-dre_k8/acpi/pm_ctrl.asl b/src/mainboard/asus/kfsn4-dre_k8/acpi/pm_ctrl.asl
deleted file mode 100644
index 0afb841435..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/acpi/pm_ctrl.asl
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- * Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky!
- */
-
- /* SuperIO control port */
- Name (SPIO, 0x2E)
-
- /* SuperIO control map */
- OperationRegion (SPIM, SystemIO, SPIO, 0x02)
- Field (SPIM, ByteAcc, NoLock, Preserve) {
- INDX, 8,
- DATA, 8
- }
-
- /* SuperIO control registers */
- IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) {
- Offset (0x07),
- CR07, 8, /* Logical device number */
- Offset (0x2C),
- CR2C, 8, /* GPIO3 multiplexed pin selection */
- Offset (0x30),
- CR30, 8, /* Logical device activation control register */
- Offset (0xE0),
- CRE0, 8, /* Wake control register */
- Offset (0xE6),
- CRE6, 8, /* Mouse wake event configuration register */
- Offset (0xF1),
- CRF1, 8, /* GPIO3 data register */
- Offset (0xF3),
- CRF3, 8, /* SUSLED mode register */
- Offset (0xF6),
- CRF6, 8, /* SMI/PME event generation control register */
- Offset (0xF9),
- CRF9, 8, /* ACPI PME configuration register */
- }
-
- /* Southbridge control ports */
- /* Both are offsets from PM base address (0x2000) */
- Name (SBC1, 0x2090) /* Offset 0x90 */
- Name (SBC2, 0x2400) /* Offset 0x400 */
-
- /* Southbridge control maps */
- OperationRegion (SBM1, SystemIO, SBC1, 0x10)
- Field (SBM1, ByteAcc, NoLock, Preserve) {
- S1CT, 2,
- Offset (0x04),
- S3CT, 2,
- Offset (0x08),
- S4CT, 2,
- Offset (0x0C),
- S5CT, 2,
- }
- OperationRegion (SBM2, SystemIO, SBC2, 0x08)
- Field (SBM2, ByteAcc, NoLock, Preserve) {
- , 15,
- PS1S, 1,
- , 31,
- PS1E, 1,
- }
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* Set up LEDs */
- /* Access SuperIO GPIO3/GPIO4 device */
- Store(0x87, INDX)
- Store(0x87, INDX)
- Store(0x09, CR07)
-
- /* Set GPIO3 pin 64 (power LED) to GP37 mode */
- And(CR2C, 0xF3, Local0)
- Or(Local0, 0x04, CR2C)
-
- /* Set power LED to steady on */
- Or(CRF1, 0x80, CRF1)
-
- /* Restore default SuperIO access */
- Store(0xAA, INDX)
-
- /* Configure SuperIO for wake */
- /* Access SuperIO ACPI device */
- Store(0x87, INDX)
- Store(0x87, INDX)
- Store(0x0A, CR07)
-
- if (LEqual(Arg0, One)) /* Resuming from power state S1 */
- {
- /* Set power management to SMI mode and disable SMI events */
- And(CRF9, 0xFA, CRF9)
-
- /* Deactivate the ACPI device */
- Store(Zero, CR30)
-
- /* Disable PS/2 SMI/PME events */
- And(CRF6, 0xCF, CRF6)
- }
- if (Lor(LEqual(Arg0, 0x03), LEqual(Arg0, 0x04))) /* Resuming from power state S3 or S4 */
- {
- /* Disable PS/2 wake */
- And(CRE0, 0x1D, CRE0)
- And(CRE6, 0x7F, CRE6)
- }
-
- /* Restore default SuperIO access */
- Store(0xAA, INDX)
-
- /* Configure southbridge for wake */
- Store(Zero, PS1E)
- Store(0x02, S1CT)
- Store(0x02, S3CT)
- Store(0x02, S4CT)
- Store(0x02, S5CT)
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-
- Return(WKST)
- } /* End Method(\_WAK) */
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* Set up LEDs */
- if (LEqual(Arg0, One)) /* Power state S1 requested */
- {
- /* Access SuperIO GPIO3/GPIO4 device */
- Store(0x87, INDX)
- Store(0x87, INDX)
- Store(0x09, CR07)
-
- /* Set GPIO3 pin 64 (power LED) to SUSLED mode */
- And(CR2C, 0xF3, CR2C)
-
- /* Set suspend LED to 1Hz toggle pulse with 50% duty cycle */
- Or(CRF3, 0x80, CRF3)
-
- /* Restore default SuperIO access */
- Store(0xAA, INDX)
- }
-
- /* Configure SuperIO for sleep */
- /* Access SuperIO ACPI device */
- Store(0x87, INDX)
- Store(0x87, INDX)
- Store(0x0A, CR07)
-
- /* Disable PS/2 wakeup and connect PANSW_IN to PANSW_OUT */
- And(CRE0, 0x1F, CRE0)
-
- if (LEqual(Arg0, One)) /* Power state S1 requested */
- {
- /* Set power management to PME mode and enable PME events */
- Or(CRF9, 0x05, CRF9)
-
- /* Activate the ACPI device */
- Store(One, CR30)
-
- /* Enable PS/2 keyboard SMI/PME events */
- And(CRF6, 0xEF, CRF6)
-
- /* Enable PS/2 keyboard wake */
- Or(CRE0, 0x40, CRE0)
-
- /* Enable PS/2 mouse SMI/PME events */
- And(CRF6, 0xDF, CRF6)
-
- /* Enable PS/2 mouse wake */
- Or(CRE0, 0x20, CRE0)
- }
- else {
- /* Enable PS/2 keyboard wake on any keypress */
- Or(CRE0, 0x41, CRE0)
-
- /* Enable PS/2 mouse wake on any click */
- Or(CRE0, 0x22, CRE0)
- Or(CRE6, 0x80, CRE6)
- }
-
- /* Restore default SuperIO access */
- Store(0xAA, INDX)
-
- /* Configure southbridge for sleep */
- Store(One, PS1S)
- Store(One, PS1E)
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- } /* End Method(\_PTS) */
diff --git a/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c b/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c
deleted file mode 100644
index 6061f89819..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * ACPI support
- * written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
- *
- * Copyright 2005 AMD
- * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <assert.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-/* APIC */
-unsigned long acpi_fill_madt(unsigned long current)
-{
- struct device *dev;
- struct resource *res;
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write NVIDIA CK804 IOAPIC. */
- dev = dev_find_slot(0x0, PCI_DEVFN(sysconf.sbdn + 0x1, 0));
- ASSERT(dev != NULL);
-
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- ASSERT(res != NULL);
-
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
- CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0);
-
- /* Initialize interrupt mapping if mptable.c didn't. */
- if (!IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) {
- /* Copied from mptable.c */
- /* Enable interrupts for commonly used devices (USB, SATA, etc.) */
- pci_write_config32(dev, 0x7c, 0x0d800018);
- pci_write_config32(dev, 0x80, 0xd8002009);
- pci_write_config32(dev, 0x84, 0x00000001);
- }
-
-// /* IRQ of timer (override IRQ0 --> APIC IRQ2) */
-// current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-// current, 0, 0, 2, 0);
- /* IRQ9 */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
- /* IRQ14 */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 14, 14, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH);
- /* IRQ15 */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 15, 15, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH);
-
- /* create all subtables for processors */
- /* acpi_create_madt_lapic_nmis returns current, not size. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/board_info.txt b/src/mainboard/asus/kfsn4-dre_k8/board_info.txt
deleted file mode 100644
index 678373ad2c..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: server
-ROM package: PLCC-32
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2007
diff --git a/src/mainboard/asus/kfsn4-dre_k8/bootblock.c b/src/mainboard/asus/kfsn4-dre_k8/bootblock.c
deleted file mode 100644
index 454443f370..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/bootblock.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <pc80/mc146818rtc.h>
-
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627thg/w83627thg.h>
-
-#define GPIO_DEV PNP_DEV(0x2e, W83627THG_GPIO3)
-
-#define WINBOND_ENTRY_KEY 0x87
-#define WINBOND_EXIT_KEY 0xAA
-
-/* Enable configuration: pass entry key '0x87' into index port dev. */
-static void pnp_enter_conf_state(pnp_devfn_t dev)
-{
- u16 port = dev >> 8;
- outb(WINBOND_ENTRY_KEY, port);
- outb(WINBOND_ENTRY_KEY, port);
-}
-
-/* Disable configuration: pass exit key '0xAA' into index port dev. */
-static void pnp_exit_conf_state(pnp_devfn_t dev)
-{
- u16 port = dev >> 8;
- outb(WINBOND_EXIT_KEY, port);
-}
-
-uint8_t bootblock_read_recovery_jumper(pnp_devfn_t dev)
-{
- uint8_t recovery_enabled = 0;
-
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 1); /* Enable GPIO3 */
- pnp_write_config(dev, 0xf0, 0xff); /* Set GPIO3 to input */
- recovery_enabled = !(pnp_read_config(dev, 0xf1) & 0x08); /* Read GP33 */
- pnp_exit_conf_state(dev);
-
- return recovery_enabled;
-}
-
-void bootblock_mainboard_init(void)
-{
- uint8_t recovery_enabled;
- unsigned char addr;
- unsigned char byte;
-
- recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV);
- if (recovery_enabled) {
-#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
- /* Clear NVRAM checksum */
- for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
- cmos_write(0x0, addr);
- }
-
- /* Set fallback boot */
- byte = cmos_read(RTC_BOOT_BYTE);
- byte &= 0xfc;
- cmos_write(byte, RTC_BOOT_BYTE);
-#else
- /* FIXME
- * Figure out how to recover if the option table is not available
- */
-#endif
- }
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/cmos.default b/src/mainboard/asus/kfsn4-dre_k8/cmos.default
deleted file mode 100644
index d3a8081d95..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/cmos.default
+++ /dev/null
@@ -1,12 +0,0 @@
-debug_level = Spew
-multi_core = Enable
-slow_cpu = off
-hypertransport_speed_limit = Auto
-max_mem_clock = DDR2-800
-ECC_memory = Enable
-hw_scrubber = Enable
-interleave_chip_selects = Enable
-interleave_nodes = Disable
-interleave_memory_channels = Enable
-power_on_after_fail = Enable
-boot_option = Fallback
diff --git a/src/mainboard/asus/kfsn4-dre_k8/cmos.layout b/src/mainboard/asus/kfsn4-dre_k8/cmos.layout
deleted file mode 100644
index 86b95a94e4..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/cmos.layout
+++ /dev/null
@@ -1,117 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-393 3 r 0 unused
-396 1 e 1 hw_scrubber
-397 1 e 1 interleave_chip_selects
-398 1 e 1 interleave_nodes
-399 1 e 1 interleave_memory_channels
-408 2 e 8 max_mem_clock
-410 1 e 2 multi_core
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-446 1 e 1 power_on_after_fail
-456 1 e 1 ECC_memory
-458 4 e 11 hypertransport_speed_limit
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 0 Emergency
-6 1 Alert
-6 2 Critical
-6 3 Error
-6 4 Warning
-6 5 Notice
-6 6 Information
-6 7 Debug
-6 8 Spew
-8 0 DDR2-800
-8 1 DDR2-667
-8 2 DDR2-533
-8 3 DDR2-400
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-10 0 Disabled
-10 1 40ns
-10 2 80ns
-10 3 160ns
-10 4 320ns
-10 5 640ns
-10 6 1.28us
-10 7 2.56us
-10 8 5.12us
-10 9 10.2us
-10 10 20.5us
-10 11 41us
-10 12 81.9us
-10 13 163.8us
-10 14 327.7us
-10 15 655.4us
-10 16 1.31ms
-10 17 2.62ms
-10 18 5.24ms
-10 19 10.49ms
-10 20 20.97ms
-10 21 42ms
-10 22 84ms
-11 0 Auto
-11 1 2.6GHz
-11 2 2.4GHz
-11 3 2.2GHz
-11 4 2.0GHz
-11 5 1.8GHz
-11 6 1.6GHz
-11 7 1.4GHz
-11 8 1.2GHz
-11 9 1.0GHz
-11 10 800MHz
-11 11 600MHz
-11 12 500MHz
-11 13 400MHz
-11 14 300MHz
-11 15 200MHz
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb b/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb
deleted file mode 100644
index a02b234d04..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb
+++ /dev/null
@@ -1,197 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_F # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1043 0x8162 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- register "maximum_memory_capacity" = "0x1000000000" # 64GB
- device pci 18.0 on end # Link 0 == LDT 0
- device pci 18.0 on # Link 1 == LDT 1 [SB on link 1]
- chip southbridge/nvidia/ck804 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627thg # Super I/O
- device pnp 2e.0 on # Floppy
- # Set up interface resources
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off end # Parallel port
- device pnp 2e.2 on # Com1
- # Set up interface resources
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # Com2
- # Set up interface resources
- io 0x60 = 0x2f8
- irq 0x70 = 3
- # Select correct package I/O pins
- io 0xf1 = 0x04
- end
- device pnp 2e.5 on # PS/2 keyboard & mouse
- # Set up interface resources
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.7 off end # Game port, MIDI, GPIO 1 & 5
- device pnp 2e.8 off end # GPIO 2
- device pnp 2e.9 on end # GPIO 3, GPIO 4
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # Hardware monitor
- # Set up interface resources
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM n-0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM n-0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM n-0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM n-0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic # DIMM n-1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic # DIMM n-1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic # DIMM n-1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic # DIMM n-1-1-1
- device i2c 57 on end
- end
- chip drivers/i2c/w83793
- register "mfc" = "0x29" # Enable FANIN1/FANIN12, FANIN9/FANIN10, and FANIN8/FANCTRL8 inputs
- register "fanin" = "0x7f" # Enable monitoring of FANIN6 - FANIN12
- register "fanin_sel" = "0x0f" # Connect FANIN9 - FANIN12 to pins 37 - 40
- register "peci_agent_conf" = "0x33" # Set Intel CPU PECI agent domain (not used by AMD but may affect chip operation)
- register "tcase0" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
- register "tcase1" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
- register "tcase2" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
- register "tcase3" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
- register "tr_enable" = "0x03" # Enable montoring of TR1 and TR2
- register "td_mode_select" = "0x05" # Use internal temperature sensors and disable unconnected TD3/TD4
- register "td1_critical_temperature" = "85" # Set TD1 (CPU0) critical temperature to 85°C
- register "td1_critical_hysteresis" = "80" # Set TD1 (CPU0) critical hysteresis temperature to 80°C
- register "td1_warning_temperature" = "70" # Set TD1 (CPU0) warning temperature to 70°C
- register "td1_warning_hysteresis" = "65" # Set TD1 (CPU0) warning hysteresis temperature to 65°C
- register "td2_critical_temperature" = "85" # Set TD2 (CPU1) critical temperature to 85°C
- register "td2_critical_hysteresis" = "80" # Set TD2 (CPU1) critical hysteresis temperature to 80°C
- register "td2_warning_temperature" = "70" # Set TD2 (CPU1) warning temperature to 70°C
- register "td2_warning_hysteresis" = "65" # Set TD2 (CPU1) warning hysteresis temperature to 65°C
- register "tr1_critical_temperature" = "60" # Set TR1 (mainboard) critical temperature to 60°C
- register "tr1_critical_hysteresis" = "55" # Set TR1 (mainboard) critical hysteresis temperature to 55°C
- register "tr1_warning_temperature" = "50" # Set TR1 (mainboard) warning temperature to 50°C
- register "tr1_warning_hysteresis" = "45" # Set TR1 (mainboard) warning hysteresis temperature to 45°C
- register "critical_temperature" = "80" # Set critical temperature to 80°C
- register "fanctrl1" = "0x48" # Set Fan 4 and Fan 7 to output buffer mode, all others to open drain
- register "fanctrl2" = "0x01" # Set Fan 4 to Fan 7 to output buffer mode, Fan 1 to DC mode
- register "first_valid_fan_number" = "2" # Fan 1/Fan 2 controls and sensors are not connected to anything
- register "td1_fan_select" = "0x00" # All fans to manual mode (no dependence on TD1)
- register "td2_fan_select" = "0x00" # All fans to manual mode (no dependence on TD2)
- register "td3_fan_select" = "0x00" # All fans to manual mode (no dependence on TD3)
- register "td4_fan_select" = "0x00" # All fans to manual mode (no dependence on TD4)
- register "tr1_fan_select" = "0x00" # All fans to manual mode (no dependence on TR1)
- register "tr2_fan_select" = "0x00" # All fans to manual mode (no dependence on TR2)
- register "fan1_nonstop" = "7" # Set Fan 1 minimum speed
- register "fan2_nonstop" = "7" # Set Fan 2 minimum speed
- register "fan3_nonstop" = "7" # Set Fan 3 minimum speed
- register "fan4_nonstop" = "7" # Set Fan 4 minimum speed
- register "fan5_nonstop" = "7" # Set Fan 5 minimum speed
- register "fan6_nonstop" = "7" # Set Fan 6 minimum speed
- register "fan7_nonstop" = "7" # Set Fan 7 minimum speed
- register "fan8_nonstop" = "7" # Set Fan 8 minimum speed
- register "default_speed" = "100" # All fans to full speed on power up
- register "fan1_duty" = "100" # Fan 1 to full speed
- register "fan2_duty" = "100" # Fan 2 to full speed
- register "fan3_duty" = "100" # Fan 3 to full speed
- register "fan4_duty" = "100" # Fan 4 to full speed
- register "fan5_duty" = "100" # Fan 5 to full speed
- register "fan6_duty" = "100" # Fan 6 to full speed
- register "fan7_duty" = "100" # Fan 7 to full speed
- register "fan8_duty" = "100" # Fan 8 to full speed
- register "vcorea_high_limit_mv" = "1500" # VCOREA (Node 0) high limit to 1.5V
- register "vcorea_low_limit_mv" = "900" # VCOREA (Node 0) low limit to 0.9V
- register "vcoreb_high_limit_mv" = "1500" # VCOREB (Node 1) high limit to 1.5V
- register "vcoreb_low_limit_mv" = "900" # VCOREB (Node 1) low limit to 0.9V
- register "vtt_high_limit_mv" = "1250" # VTT (HT link voltage) high limit to 1.25V
- register "vtt_low_limit_mv" = "1150" # VTT (HT link voltage) low limit to 1.15V
- register "vsen1_high_limit_mv" = "1900" # VSEN1 (Node 0 RAM voltage) high limit to 1.9V
- register "vsen1_low_limit_mv" = "1700" # VSEN1 (Node 0 RAM voltage) low limit to 1.7V
- register "vsen2_high_limit_mv" = "1900" # VSEN2 (Node 1 RAM voltage) high limit to 1.9V
- register "vsen2_low_limit_mv" = "1700" # VSEN2 (Node 1 RAM voltage) low limit to 1.7V
- register "vsen3_high_limit_mv" = "3500" # VSEN3 (+3.3V) high limit to 3.5V
- register "vsen3_low_limit_mv" = "3100" # VSEN3 (+3.3V) low limit to 3.1V
- register "vsen4_high_limit_mv" = "1070" # VSEN4 (+12V, scaling factor ~12.15) high limit to 13V
- register "vsen4_low_limit_mv" = "905" # VSEN4 (+12V, scaling factor ~12.15) low limit to 11V
- register "vdd_high_limit_mv" = "5200" # 5VDD high limit to 5.2V
- register "vdd_low_limit_mv" = "4800" # 5VDD low limit to 4.8V
- register "vsb_high_limit_mv" = "5200" # 5VSB high limit to 5.2V
- register "vsb_low_limit_mv" = "4800" # 5VSB low limit to 4.8V
- register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V
- register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V
- device i2c 0x2f on end
- end
- end
- device pci 1.1 on end # SM 1
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 off end # AC'97 Audio (N/A)
- device pci 4.1 off end # AC'97 Modem (N/A)
- device pci 6.0 on end # IDE
- device pci 7.0 on end # SATA 0
- device pci 8.0 on end # SATA 1
- device pci 9.0 on # Bridge
- device pci 4.0 on end # VGA
- end
- device pci a.0 off end
- device pci b.0 on # Bridge
- device pci 0.0 on end # NIC A
- end
- device pci c.0 on # Bridge
- device pci 0.0 on end # LSI SAS
- end
- device pci d.0 on # Bridge
- device pci 0.0 on end # NIC B
- end
- device pci e.0 on # Bridge
- # Slot # PCI E 0
- end
- device pci f.0 off end
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- end
- end
- device pci 18.0 on end # Link 2 == LDT 2
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- device pci 18.4 on end
- device pci 19.0 on end # Link 0 == LDT 0
- device pci 19.0 on end # Link 1 == LDT 1
- device pci 19.0 on end # Link 2 == LDT 2
- device pci 19.1 on end
- device pci 19.2 on end
- device pci 19.3 on end
- device pci 19.4 on end
- end
- end
-end
diff --git a/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl b/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl
deleted file mode 100644
index ce01a49db8..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl
+++ /dev/null
@@ -1,947 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky!
- * Everything else does to the best of my knowledge... (T.P. 01/26/2015)
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-/*
- * PCI link routing templates taken from ck804.asl and modified for this board
- */
-
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "ASUS ", /* OEMID */
- "COREBOOT", /* TABLE ID */
- 0x00000001 /* OEM Revision */
- )
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- /* Some global data */
- Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PICM, One) /* Assume APIC */
-
- /* HPET control */
- Name (SHPB, 0xFED00000)
- Name (SHPL, 0x1000)
-
- /* Define power states */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */
- Name (_S1, Package () { 0x01, 0x00, 0x00, 0x00 }) /* Standby */
- /* Name (_S3, Package () { 0x05, 0x00, 0x00, 0x00 }) */ /* Not supported by hardware */
- /* Name (_S4, Package () { 0x06, 0x00, 0x00, 0x00 }) */
- Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 }) /* Hard power off */
-
- /* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
- Method (_PIC, 1, Serialized) {
- Store (Arg0, PICM)
- }
-
- /* _PR CPU0 is dynamically supplied by SSDT */
- /* CPU objects and _PSS entries are dynamically supplied by SSDT */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* VGA controller PME# */
- Method(_L00) {
- /* Level-Triggered GPE */
- Notify(\_SB.PCI0.VGAC, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* Keyboard controller PME# */
- Method(_L03) {
- /* Level-Triggered GPE */
- Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* USB2 PME# */
- Method(_L05) {
- /* Level-Triggered GPE */
- Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* Slot PME# */
- Method(_L0B) {
- /* Level-Triggered GPE */
- Notify (\_SB.PCI0.PCIE.SLT1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.LSIC.SLT2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* USB0 PME# */
- Method(_L0D) {
- /* Level-Triggered GPE */
- Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* Keyboard controller PME# */
- Method(_L10) {
- /* Level-Triggered GPE */
- Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* PCIe PME# */
- Method(_L11) {
- /* Level-Triggered GPE */
- Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.PCIE, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.LSIC, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- } /* End Scope GPE */
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device (CK804) */
- Device (PCI0)
- {
- /* BUS0 root bus */
-
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00180001)
- Name (_UID, 0x00)
-
- Name (HCIN, 0x00) // HC1
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- /* Operating System Capabilities Method */
- Method(_OSC,4)
- {
- /* Let OS control everything */
- Return (Arg3)
- }
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
- External (CBST)
-
- /* PCI Routing Tables */
- Name (PR00, Package () {
- /* PIC */
- /* ISA Bridge */
- Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 },
-
- /* USB */
- Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 },
-
- /* SATA 0 */
- Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 },
-
- /* SATA 1 */
- Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 },
-
- /* NIC A (Bridge) */
- Package (0x04) { 0x000BFFFF, 0x00, LNKB, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x01, LNKC, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x02, LNKD, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x03, LNKA, 0x00 },
-
- /* NIC B (Bridge) */
- Package (0x04) { 0x000CFFFF, 0x00, LNKA, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x01, LNKB, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x02, LNKC, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x03, LNKD, 0x00 },
-
- /* LSI SAS Controller (Bridge) */
- Package (0x04) { 0x000DFFFF, 0x00, LNKD, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x01, LNKA, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x02, LNKB, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x03, LNKC, 0x00 },
-
- /* PCI-E Slot (Bridge) */
- Package (0x04) { 0x000EFFFF, 0x00, LNKC, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x01, LNKD, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x02, LNKA, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x03, LNKB, 0x00 },
- })
-
- Name (AR00, Package () {
- /* APIC */
- /* ISA Bridge */
- Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 },
-
- /* USB */
- Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 },
-
- /* SATA 0 */
- Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 },
-
- /* SATA 1 */
- Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 },
-
- /* NIC A (Bridge) */
- Package (0x04) { 0x000BFFFF, 0x00, LNIB, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x01, LNIC, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x02, LNND, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x03, LNIA, 0x00 },
-
- /* NIC B (Bridge) */
- Package (0x04) { 0x000CFFFF, 0x00, LNIA, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x01, LNIB, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x02, LNIC, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x03, LNND, 0x00 },
-
- /* LSI SAS Controller (Bridge) */
- Package (0x04) { 0x000DFFFF, 0x00, LNND, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x01, LNIA, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x02, LNIB, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x03, LNIC, 0x00 },
-
- /* PCI-E Slot (Bridge) */
- Package (0x04) { 0x000EFFFF, 0x00, LNIC, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x01, LNND, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x02, LNIA, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x03, LNIB, 0x00 },
- })
-
- Name (PR01, Package () {
- /* PIC */
- Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 },
- })
-
- Name (AR01, Package () {
- /* APIC */
- Package (0x04) { 0x0004FFFF, 0x00, LNIA, 0x00 },
- })
-
- Name (PR02, Package () {
- /* PIC */
- Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNKC, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNKD, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNKA, 0x00 },
- })
-
- Name (AR02, Package () {
- /* APIC */
- Package (0x04) { 0xFFFF, 0x00, LNIB, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNIC, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNND, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNIA, 0x00 },
- })
-
- Name (PR03, Package () {
- /* PIC */
- Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
- })
-
- Name (AR03, Package () {
- /* APIC */
- Package (0x04) { 0xFFFF, 0x00, LNIA, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNIB, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNIC, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNND, 0x00 },
- })
-
- Name (PR04, Package () {
- /* PIC */
- Package (0x04) { 0xFFFF, 0x00, LNKD, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNKA, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNKB, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNKC, 0x00 },
- })
-
- Name (AR04, Package () {
- /* APIC */
- Package (0x04) { 0xFFFF, 0x00, LNND, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNIA, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNIB, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNIC, 0x00 },
- })
-
- Name (PR05, Package () {
- /* PIC */
- Package (0x04) { 0xFFFF, 0x00, LNKC, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNKD, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNKA, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNKB, 0x00 },
- })
-
- Name (AR05, Package () {
- /* APIC */
- Package (0x04) { 0xFFFF, 0x00, LNIC, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNND, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNIA, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNIB, 0x00 },
- })
-
- /* PCI Resource Tables */
-
- Name (RSIA, ResourceTemplate () {
- /* PIC */
- IRQ (Level, ActiveLow, Shared, ) {8}
- })
-
- Name (RSMA, ResourceTemplate () {
- /* APIC */
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {16}
- })
-
- Name (RSIB, ResourceTemplate () {
- /* PIC */
- IRQ (Level, ActiveLow, Shared, ) {1}
- })
-
- Name (RSMB, ResourceTemplate () {
- /* APIC */
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {17}
- })
-
- Name (RSIC, ResourceTemplate () {
- /* PIC */
- IRQ (Level, ActiveLow, Shared, ) {2}
- })
-
- Name (RSMC, ResourceTemplate () {
- /* APIC */
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {18}
- })
-
- Name (RSND, ResourceTemplate () {
- /* PIC */
- IRQ (Level, ActiveLow, Shared, ) {13}
- })
-
- Name (RSMD, ResourceTemplate () {
- /* APIC */
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {19}
- })
-
- Name (RSS2, ResourceTemplate ()
- {
- /* PIC */
- IRQ (Level, ActiveLow, Shared, )
- {3, 4, 5, 7, 9, 10, 11, 12, 14, 15}
- })
-
- Name (RSA1, ResourceTemplate ()
- {
- /* APIC */
- IRQ (Level, ActiveLow, Shared, )
- {3, 4, 5, 6, 7, 10, 11, 12, 14, 15}
- })
-
- Method (_CRS, 0, Serialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods below use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
-#include "southbridge/nvidia/ck804/acpi/ck804.asl"
-
- /* PCI Routing Table Access */
- Method (_PRT, 0, NotSerialized) {
- If (PICM) {
- Return (AR00)
- } Else {
- Return (PR00)
- }
- }
-
- /* USB0 */
- Device (LUB0)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x05) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTQ) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTQ)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (PRSC)
- } Else {
- Return (RSA1)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSC(\_SB.PCI0.LPCB.INTQ))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTQ))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTQ)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTQ)
- }
- }
- }
-
- /* USB2 */
- Device (LUB2)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x07) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTL) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTL)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (PRSC)
- } Else {
- Return (RSA1)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSC(\_SB.PCI0.LPCB.INTL))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTL))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTL)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTL)
- }
- }
- }
-
- /* ISA Bridge */
- Device (LKSM)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x0C) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTK) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTK)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (RSA1)
- } Else {
- Return (RSS2)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSB(\_SB.PCI0.LPCB.INTK))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTK))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTK)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTK)
- }
- }
- }
-
- /* Bridge device link (NIC A) */
- Device (LNIA)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x10) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTA) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTA)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (RSMA)
- } Else {
- Return (RSIA)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSB(\_SB.PCI0.LPCB.INTA))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTA))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTA)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTA)
- }
- }
- }
-
- /* Bridge device link (NIC B) */
- Device (LNIB)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x11) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTB) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTB)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (RSMB)
- } Else {
- Return (RSIB)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSB(\_SB.PCI0.LPCB.INTB))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTB))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTB)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTB)
- }
- }
- }
-
- /* Bridge device link */
- Device (LNIC)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x12) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTC) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTC)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (RSMC)
- } Else {
- Return (RSIC)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSB(\_SB.PCI0.LPCB.INTC))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTC))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTC)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTC)
- }
- }
- }
-
- /* Bridge device link */
- Device (LNND)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x13) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTD) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTD)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (RSMD)
- } Else {
- Return (RSND)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSB(\_SB.PCI0.LPCB.INTD))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTD))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTD)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTD)
- }
- }
- }
-
- /* 0:02.0 CK804 USB 0 */
- Device (USB0)
- {
- Name (_ADR, 0x00020000) // _ADR: Address
- Name(_PRW, Package () {0x0D, 0x04}) // Wake from S1-S4
- }
-
- /* 0:02.0 CK804 USB 2 */
- Device (USB2)
- {
- Name (_ADR, 0x00020001) // _ADR: Address
- Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
- }
-
- /* 1:04.0 VGA Controller */
- Device (VGAC)
- {
- Name (_ADR, 0x00090000) // _ADR: Address
- Name(_PRW, Package () {0x00, 0x04}) // Wake from S1-S4
- Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
- {
- If (PICM) {
- Return (AR01)
- } Else {
- Return (PR01)
- }
- }
- }
-
- /* 2:00.0 PCIe NIC A */
- Device (NICA)
- {
- Name (_ADR, 0x000B0000) // _ADR: Address
- Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
- Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
- {
- If (PICM) {
- Return (AR02)
- } Else {
- Return (PR02)
- }
- }
- Device (BDC1)
- {
- Name (_ADR, Zero) // _ADR: Address
- }
- }
-
- /* 3:00.0 PCIe NIC B */
- Device (NICB)
- {
- Name (_ADR, 0x000C0000) // _ADR: Address
- Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
- Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
- {
- If (PICM) {
- Return (AR03)
- } Else {
- Return (PR03)
- }
- }
- Device (BDC2)
- {
- Name (_ADR, Zero) // _ADR: Address
- }
- }
-
- /* 4:00.0 PCIe LSI SAS Controller */
- Device (LSIC)
- {
- Name (_ADR, 0x000D0000) // _ADR: Address
- Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
- Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
- {
- If (PICM) {
- Return (AR04)
- } Else {
- Return (PR04)
- }
- }
-
- Device (SLT2)
- {
- Name (_ADR, 0xFFFF) // _ADR: Address
- Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
- }
- }
-
- /* 5:00.0 PCIe x16 */
- Device (PCIE)
- {
- Name (_ADR, 0x000E0000) // _ADR: Address
- Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
- Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
- {
- If (PICM) {
- Return (AR05)
- } Else {
- Return (PR05)
- }
- }
- Device (SLT1)
- {
- Name (_ADR, 0xFFFF) // _ADR: Address
- Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
- }
- }
-
- Device (LPC) {
- Name (_HID, EisaId ("PNP0A05"))
- Name (_ADR, 0x00010000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Name (_CID, EisaId ("PNP030B"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, Serialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F03"))
- Name (_CID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, Serialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
-
- /* UART 1 */
- Device (URT1)
- {
- Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART
- Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f) // Always enable
- }
- Name (_PRS, ResourceTemplate() {
- StartDependentFn(0, 1) {
- IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
- IRQNoFlags() { 4 }
- } EndDependentFn()
- })
- Method (_CRS, 0)
- {
- Return(ResourceTemplate() {
- IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
- IRQNoFlags() { 4 }
- })
- }
- }
-
- /* UART 2 */
- Device (URT2)
- {
- Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART
- Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f) // Always enable
- }
- Name (_PRS, ResourceTemplate() {
- StartDependentFn(0, 1) {
- IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
- IRQNoFlags() { 3 }
- } EndDependentFn()
- })
- Method (_CRS, 0)
- {
- Return(ResourceTemplate() {
- IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
- IRQNoFlags() { 3 }
- })
- }
- }
-
- /* Floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, Serialized)
- {
- Name (BUF0, ResourceTemplate () {
- FixedIO (0x03F0, 0x08)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- Device (HPET)
- {
- Name (_HID, EisaId ("PNP0103"))
- Name (CRS, ResourceTemplate ()
- {
- Memory32Fixed (ReadOnly,
- 0x00000000,
- 0x00001000,
- _Y02)
- IRQNoFlags () {0}
- IRQNoFlags () {8}
- })
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
- Method (_CRS, 0, NotSerialized)
- {
- CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT1)
- CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._LEN, HPT2)
- Store (SHPB, HPT1)
- Store (SHPL, HPT2)
- Return (CRS)
- }
-
- }
- }
- }
-
- Device (PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
- }
-
-#include "acpi/pm_ctrl.asl"
-
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c
deleted file mode 100644
index d527751eeb..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-#include <cpu/amd/multicore.h>
-#endif
-#include <stdlib.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-/*
- * Global variables for MB layouts and these will be shared by irqtable,
- * mptable and acpi_tables.
- */
-/* busnum is default */
-unsigned char bus_ck804[6];
-unsigned apicid_ck804;
-
-/* Here you only need to set value in pci1234 for HT-IO that could be
-installed or not You may need to preset pci1234 for HTIO board, please
-refer to src/northbridge/amd/amdk8/get_pci1234.c for detail */
-static u32 pci1234x[] = {
- 0x0000ff0, 0x0000ff0, 0x0000ff0,
-};
-
-
-/* HT Chain device num, actually it is unit id base of every ht device
-in chain, assume every chain only have 4 ht device at most */
-
-static unsigned hcdnx[] = {
- 0x20202020, 0x20202020, 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- unsigned apicid_base, sbdn;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* Do it only once. */
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- sbdn = sysconf.sbdn;
-
- for (i = 0; i < 6; i++)
- bus_ck804[i] = 0;
-
- /* CK804 */
- dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0));
- if (dev) {
- bus_ck804[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804[2]++;
- } else {
- printk
- (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x09);
- bus_ck804[1] = 2;
- bus_ck804[2] = 3;
- }
-
- for (i = 2; i < 6; i++) {
- dev = dev_find_slot(bus_ck804[0],
- PCI_DEVFN(sbdn + 0x0b + i - 2, 0));
- if (dev) {
- bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804[0], sbdn + 0x0b + i - 2);
- }
- }
-
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
- apicid_base = get_apicid_base(1);
- printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base);
- } else {
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 0: apicid_base: %08x\n", apicid_base);
- }
- apicid_ck804 = apicid_base + 0;
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/irq_tables.c b/src/mainboard/asus/kfsn4-dre_k8/irq_tables.c
deleted file mode 100644
index d06980c773..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/irq_tables.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// WARNING
-// These tables are INVALID for this mainboard!
-// The ACPI tables are correct; a backport to these PIR tables is needed...
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_isa;
-extern unsigned char bus_ck804[6];
-
-
-/**
- * Add one line to IRQ table.
- */
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-/**
- * Create the IRQ routing table.
- * Values are derived from getpir generated code.
- */
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num, sbdn;
- uint8_t *v, sum = 0;
- int i;
-
- /* get_bus_conf() will find out all bus num and APIC that share with
- * mptable.c and mptable.c.
- */
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000. */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *)(addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
- pirq->rtr_bus = bus_ck804[0];
- pirq->rtr_devfn = ((sbdn + 9) << 3) | 0;
- pirq->exclusive_irqs = 0x828;
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x005c;
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* Slot1 PCIE 16x */
- write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4,
- 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0);
- pirq_info++;
- slot_num++;
-
-
- /* Slot2 PCIE 1x */
- write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot3 PCIE 1x */
- write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2,
- 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot4 PCIE 4x */
- write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2,
- 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot5 - Slot7 PCI */
- for (i = 0; i < 3; i++) {
- write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0,
- ((i + 0) % 4) + 1, 0xdeb8,
- ((i + 1) % 4) + 1, 0xdeb8,
- ((i + 2) % 4) + 1, 0xdeb8,
- ((i + 3) % 4) + 1, 0xdeb8, i, 0);
- pirq_info++;
- slot_num++;
- }
-
- /* PCI bridge */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SMBus */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* USB */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SATA */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SATA */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum)
- pirq->checksum = sum;
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/mptable.c b/src/mainboard/asus/kfsn4-dre_k8/mptable.c
deleted file mode 100644
index efa583c47f..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/mptable.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// WARNING
-// These tables are INCOMPLETE for this mainboard!
-// The ACPI tables are correct; a backport to these MP tables is needed...
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_ck804[6];
-extern unsigned apicid_ck804;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned sbdn;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- struct resource *res;
-
- dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11,
- res2mmio(res, 0, 0));
- }
-
- /* Initialize interrupt mapping. */
-
- /*
- LPC bridge PCI config registers:
-
- 0x7c:0x0000ffff
- - bitmap of masked pci irqs?
- - PIRQ[ABCD] possibly?
-
- 0x7c:0x00f00000
- - sata at f8 - port 1
-
- 0x7c:0x0f000000
- - sata at f7 - port 1
-
- 0x80:0xf0000000
- - sata at f7 - port 0
-
- 0x80:0x0f000000
- - sata at f8 - port 0
-
- 0x80:0x0000f000
- - EHCI
-
- 0x84:0x00000f00
- - NIC
-
- 0x84:0x0000000f
- - OHCI
-
- known values of nibbles:
-
- 0 - unrouted?
- 1 - irq 23
- 8 - irq 20
- c - irq 12
- d - irq 21
- e - irq 14
- f - irq 15
- */
-
- // Enable interrupts for commonly used devices (USB, SATA, etc.)
- pci_write_config32(dev, 0x7c, 0x0d800018);
- pci_write_config32(dev, 0x80, 0xd8002009);
- pci_write_config32(dev, 0x84, 0x00000001);
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
-
- // Onboard ck804 smbus
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
- 0xa);
-
- // Onboard ck804 USB 1.1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
- 0x15);
-
- // Onboard ck804 USB 2
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
- 0x14);
-
- // Onboard ck804 SATA 0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
- 0x17);
-
- // Onboard ck804 SATA 1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
- 0x16);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_ck804[0]);
-
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c b/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
deleted file mode 100644
index cfbade68f2..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [31:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independent of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c
deleted file mode 100644
index a404b06ad3..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <timestamp.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/ck804/early_smbus.h"
-#include <reset.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include <cbmem.h>
-#include <delay.h>
-
-#include <cpu/amd/mtrr.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627thg/w83627thg.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <northbridge/amd/amdk8/f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-#define CK804_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/
-
-#include <southbridge/nvidia/ck804/early_setup_ss.h>
-#include "southbridge/nvidia/ck804/early_setup_car.c"
-#include <cpu/amd/microcode.h>
-
-#define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3)
-
-/**
- * @brief Get SouthBridge device number
- * @param[in] bus target bus number
- * @return southbridge device number
- */
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus);
- return (dev >> 15) & 0x1f;
-}
-
-/*
- * ASUS KFSN4-DRE specific SPD enable/disable magic.
- *
- * Setting CK804 GPIO43 and GPIO44 to 0 and 0 respectively will make the
- * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD
- * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which
- * will make RAM init fail.
- *
- * Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets
- * which is required e.g. by lm-sensors.
- */
-
-#define CK804_BOARD_BOOT_BASE_UNIT_UID 1
-
-static const unsigned int ctrl_conf_enable_spd_node0[] = {
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/
-};
-
-static const unsigned int ctrl_conf_enable_spd_node1[] = {
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x01),/* W3,GPIO44, U6 input S1*/
-};
-
-static const unsigned int ctrl_conf_disable_spd[] = {
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x01),/* W2,GPIO43, U6 input S0*/
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/
-};
-
-static const unsigned int ctrl_conf_fix_pci_numbering[] = {
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x44), ~(0x00010000), 0x00000000, /* Force CK804 to start its internal device numbering (Base Unit ID) at 0 instead of the power-on default of 1 */
-};
-
-static const unsigned int ctrl_conf_enable_msi_mapping[] = {
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */
-};
-
-static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id)
-{
- unsigned busn[4], io_base[4];
- int i, ck804_num = 0;
-
- for (i = 0; i < 4; i++) {
- u32 id;
- pci_devfn_t dev;
- if (i == 0) /* SB chain */
- dev = PCI_DEV(i * 0x40, bus_unit_id, 0);
- else
- dev = 0;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (id == 0x005e10de) {
- busn[ck804_num] = i * 0x40;
- io_base[ck804_num] = i * 0x4000;
- ck804_num++;
- }
- }
-
- if (ck804_num < 1)
- printk(BIOS_WARNING, "CK804 not found at device base unit id %02x!\n", bus_unit_id);
-
- ck804_early_set_port(ck804_num, busn, io_base);
-
- setup_resource_map_x_offset(values,
- size,
- PCI_DEV(0, bus_unit_id, 0), io_base[0]);
-
- ck804_early_clear_port(ck804_num, busn, io_base);
-}
-
-static void sio_setup(void)
-{
- u32 dword;
- u8 byte;
-
- /* Subject decoding */
- byte = pci_read_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b, byte);
-
- /* LPC Positive Decode 0 */
- dword = pci_read_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0);
- /* Serial 0, Serial 1 */
- dword |= (1 << 0) | (1 << 1);
- pci_write_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0, dword);
-}
-
-static const uint16_t spd_addr[] = {
- // Node 0
- RC00 | DIMM0, RC00 | DIMM2, RC00 | DIMM4, RC00 | DIMM6, RC00 | DIMM1, RC00 | DIMM3, RC00 | DIMM5, RC00 | DIMM7,
- // Node 1
- RC01 | DIMM0, RC01 | DIMM2, RC01 | DIMM4, RC01 | DIMM6, RC01 | DIMM1, RC01 | DIMM3, RC01 | DIMM5, RC01 | DIMM7,
-};
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
- printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id);
- if (ctrl->node_id == 0) {
- printk(BIOS_DEBUG, "enable_spd_node0()\n");
- ck804_control(ctrl_conf_enable_spd_node0, ARRAY_SIZE(ctrl_conf_enable_spd_node0), CK804_DEVN_BASE);
- }
- else if (ctrl->node_id == 1) {
- printk(BIOS_DEBUG, "enable_spd_node1()\n");
- ck804_control(ctrl_conf_enable_spd_node1, ARRAY_SIZE(ctrl_conf_enable_spd_node1), CK804_DEVN_BASE);
- }
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- struct sys_info *sysinfo = &sysinfo_car;
-
- uint32_t bsp_apicid = 0;
- uint32_t dword;
- uint8_t needs_reset = 0;
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- struct cpuid_result cpuid1;
-#endif
-
- timestamp_init(timestamp_get());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- post_code(0x30);
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- post_code(0x32);
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- if (CONFIG_MAX_PHYSICAL_CPUS != 2)
- printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!\n", CONFIG_MAX_PHYSICAL_CPUS);
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- dword = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", dword);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- /* Setup sysinfo defaults */
- set_sysinfo_in_ram(0);
-
- post_code(0x33);
-
- setup_coherent_ht_domain();
- post_code(0x35);
-
- /* Wait for all base cores to start */
- wait_all_core0_started();
- post_code(0x36);
-
- /* Setup any mainboard PCI settings etc. */
- setup_mb_resource_map();
- post_code(0x37);
-
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
- /* Core0 on each node is configured. Now setup any additional cores. */
- printk(BIOS_DEBUG, "start_other_cores()\n");
- start_other_cores();
- post_code(0x38);
- wait_all_other_cores_started(bsp_apicid);
- post_code(0x39);
- }
-
- ht_setup_chains_x(sysinfo);
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- cpuid1 = cpuid(0x80000007);
- if ((cpuid1.edx & 0x6) == 0x6) {
- msr_t msr;
-
- /* Read FIDVID_STATUS */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
-
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
-
- /* Show final FID and VID */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- } else {
- printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
- }
-#endif
-
- init_timer(); /* Need to use TMICT to synchronize FID/VID. */
-
- printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n");
- ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID);
-
- post_code(0x3a);
-
- printk(BIOS_DEBUG, "optimize_link_coherent_ht()\n");
- needs_reset = optimize_link_coherent_ht();
- printk(BIOS_DEBUG, "optimize_link_incoherent_ht()\n");
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- printk(BIOS_DEBUG, "ck804_early_setup_x()\n");
- needs_reset |= ck804_early_setup_x();
-
- /* FIDVID change will issue one LDTSTOP and the HT change will be effective too */
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- post_code(0x3b);
-
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl in sysinfo now; */
- printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- post_code(0x3d);
-
- printk(BIOS_DEBUG, "enable_smbus()\n");
- enable_smbus();
-
-#if 0
- /* FIXME
- * After the AMD K10 code has been converted to use
- * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
- */
- if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
- dump_spd_registers(&cpu[0]);
- dump_smbus_registers();
- }
-#endif
-
- post_code(0x40);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
- printk(BIOS_DEBUG, "sdram_initialize()\n");
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- cbmem_initialize_empty();
- post_code(0x41);
-
- printk(BIOS_DEBUG, "disable_spd()\n");
- ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE);
-
- printk(BIOS_DEBUG, "enable_msi_mapping()\n");
- ck804_control(ctrl_conf_enable_msi_mapping, ARRAY_SIZE(ctrl_conf_enable_msi_mapping), CK804_DEVN_BASE);
-
- /* Initialize GPIO */
- /* Access SuperIO GPI03 logical device */
- uint16_t port = GPIO3_DEV >> 8;
- outb(0x87, port);
- outb(0x87, port);
- pnp_set_logical_device(GPIO3_DEV);
- /* Set GP37 (power LED) to output */
- pnp_write_config(GPIO3_DEV, 0xf0, 0x7f);
- /* Set GP37 (power LED) on */
- pnp_write_config(GPIO3_DEV, 0xf1, 0x80);
- /* Set pin 64 multiplex to GP37 */
- uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c);
- pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04);
- /* Restore default SuperIO access */
- outb(0xaa, port);
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/spd_notes.txt b/src/mainboard/asus/kfsn4-dre_k8/spd_notes.txt
deleted file mode 100644
index 9287a5f75a..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/spd_notes.txt
+++ /dev/null
@@ -1,69 +0,0 @@
-====================================================================================================
-SPD mux
-====================================================================================================
-
-DIMM_A1 SDA signal traced to U6 pin 1
-Destructive testing of failed board (removal of U7 northbridge!) yielded the following information:
-U6 S0 <--> U7 W2
-U6 S1 <--> U7 W3
-
-Proprietary BIOS enables the SPD during POST with:
-S0: LOW
-S1: LOW
-
-then temporarily switches to:
-S0: LOW
-S1: HIGH
-
-then switches to runtime mode with:
-S0: HIGH
-S1: LOW
-
-After probing with a custom GPIO-flipping tool under Linux the following GPIO mappings were found:
-CK804 pin W2 <--> GPIO43
-CK804 pin W3 <--> GPIO44
-
-====================================================================================================
-W83793 (U46)
-====================================================================================================
-
-Sensor mappings:
-FRNT_FAN1: FAN3
-FRNT_FAN2: FAN4
-FRNT_FAN3: FAN5
-FRNT_FAN4: FAN6
-FRNT_FAN5: FAN9
-FRNT_FAN6: FAN10
-REAR_FAN1: FAN7
-REAR_FAN2: FAN8
-REAR_FAN3: FAN11
-REAR_FAN4: FAN12
-
-====================================================================================================
-Other hardware
-====================================================================================================
-
-Power LED (-) is connected to U15 (SuperIO) pin 64 via U4 pins 5,6 and a small MOSFET
-ID LED (-) is connected to a ??? via U4 pins 1,2,3,4 and U77 pins 5,6
-It appears that setting U15 (SuperIO) pin 88 LOW will override the ID LED and force it ON
-
-RECOVERY2 middle pin is connected to U15 (SuperIO) pin 89
-Normal is HIGH, recovery is LOW.
-
-PCIe slot WAKE# connects to U7 pin E23 (PCIE_WAKE#)
-
-CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10)
-MEM_WARN1 is driven by U7 pin AD3 (CPUVDD_EN) via a simple buffer (U101 pin 3)
-
-U7 pin AK3 is disconnected (routed to unpopulated capacitor/resistor)
-PU1 pin 37 (VDDPWRGD) drives U7 pin AJ4 (CPU_VLD)
-A small MOSFET directly above another small MOSFET directly above the right-hand edge of the PCIe slot drives U7 pin AK5 (HT_VLD)
-
-When > Barcelona CPU installed on PCB rev 1.04G:
-U7 pin AK4 (MEM_VLD): HIGH
-PU1 pin 37: LOW
-U7 pin AK5: LOW
-
-HyperTransport 1.2V supply appears to be generated by a linear regulator containing Q191 and downconverting the CK804 1.5V supply
-The enable pin appears to be tied to AUX_PANEL pin 1 (+5VSB) via a resistor
-Through two MOSFETs the HT supply enable pin is tied to U7 pin AE3 (HTVDD_EN)
diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig
deleted file mode 100644
index 7cb903bb93..0000000000
--- a/src/mainboard/asus/m2n-e/Kconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-if BOARD_ASUS_M2N_E
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_AM2
- select DIMM_DDR2
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_MCP55
- select HT_CHAIN_DISTRIBUTE
- select MCP55_USE_NIC
- select MCP55_USE_AZA
- select SUPERIO_ITE_IT8716F
- select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_512
- select K8_ALLOCATE_IO_RANGE
-
-config MAINBOARD_DIR
- string
- default asus/m2n-e
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MEM_TRAIN_SEQ
- int
- default 2
-
-config MAINBOARD_PART_NUMBER
- string
- default "M2N-E"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-endif # BOARD_ASUS_M2N_E
diff --git a/src/mainboard/asus/m2n-e/Kconfig.name b/src/mainboard/asus/m2n-e/Kconfig.name
deleted file mode 100644
index e3cbc5da00..0000000000
--- a/src/mainboard/asus/m2n-e/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_M2N_E
- bool "M2N-E"
diff --git a/src/mainboard/asus/m2n-e/Makefile.inc b/src/mainboard/asus/m2n-e/Makefile.inc
deleted file mode 100644
index 94559573a7..0000000000
--- a/src/mainboard/asus/m2n-e/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) += fanctl.c
diff --git a/src/mainboard/asus/m2n-e/board_info.txt b/src/mainboard/asus/m2n-e/board_info.txt
deleted file mode 100644
index d7b04de6d1..0000000000
--- a/src/mainboard/asus/m2n-e/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_AM2/M2NE/
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2006
diff --git a/src/mainboard/asus/m2n-e/cmos.layout b/src/mainboard/asus/m2n-e/cmos.layout
deleted file mode 100644
index 95b7de3a6e..0000000000
--- a/src/mainboard/asus/m2n-e/cmos.layout
+++ /dev/null
@@ -1,68 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 200Mhz
-8 1 166Mhz
-8 2 133Mhz
-8 3 100Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/m2n-e/devicetree.cb b/src/mainboard/asus/m2n-e/devicetree.cb
deleted file mode 100644
index 5938684899..0000000000
--- a/src/mainboard/asus/m2n-e/devicetree.cb
+++ /dev/null
@@ -1,117 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_AM2 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1043 0x8239 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/ite/it8716f # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2 (N/A)
- end
- device pnp 2e.3 on # Parallel port
- io 0x60 = 0x378
- io 0x62 = 0x000
- irq 0x70 = 7
- drq 0x74 = 4
- end
- device pnp 2e.4 on # Environment controller
- io 0x60 = 0x290
- io 0x62 = 0x000
- irq 0x70 = 0
- end
- device pnp 2e.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # PS/2 keyboard IRQ
- end
- device pnp 2e.6 on # PS/2 mouse
- irq 0x70 = 12 # PS/2 mouse IRQ
- end
- device pnp 2e.7 off # GPIO
- io 0x60 = 0x0000 # SMI# Normal Run Access
- io 0x62 = 0x800 # Simple I/O
- io 0x64 = 0x0000 # Serial Flash I/F
- end
- device pnp 2e.8 off # MIDI (N/A)
- end
- device pnp 2e.9 off # Game port (N/A)
- end
- device pnp 2e.a off # Consumer IR (N/A)
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
- device pci 6.0 on end # PCI
- device pci 6.1 on end # Azalia (HD Audio)
- device pci 8.0 on end # NIC
- device pci 9.0 off end # NIC (N/A)
- device pci a.0 on end # PCI E 5 (PCIEX4)
- device pci b.0 off end # PCI E 4
- device pci c.0 on end # PCI E 3 (PCIEX1_2)
- device pci d.0 on end # PCI E 2 (PCIEX1_1)
- device pci e.0 off end # PCI E 1
- device pci f.0 on end # PCI E 0 (PCIEX16_1)
- register "ide0_enable" = "1" # Primary IDE
- register "ide1_enable" = "0" # Secondary IDE (N/A)
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- end
- end
- device pci 18.0 on end # Link 1
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/m2n-e/fanctl.c b/src/mainboard/asus/m2n-e/fanctl.c
deleted file mode 100644
index 8fa7d82578..0000000000
--- a/src/mainboard/asus/m2n-e/fanctl.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * The ASUS M2N-E has 6 different fans, connected to two different chips:
- * - ITE IT8716F: fan1 = CPU_FAN, fan2 = CHA_FAN1, fan3 = PWR_FAN1
- * - Analog Devices ADT7475: fan1 = CHA_FAN4, fan2 = CHA_FAN2, fan3 = CHA_FAN3
- */
-
-#include <arch/io.h>
-#include <stdlib.h>
-#include <superio/ite/it8716f/it8716f.h>
-
-static void write_index(u16 port, u8 reg, u8 value)
-{
- outb(reg, port);
- outb(value, port + 1);
-}
-
-static const struct {
- u8 index;
- u8 value;
-} sequence[] = {
- /* Enable startup of monitoring operations. */
- { 0x00, 0x11},
- /* Polarity active-high, PWM frequency 23.43KHz, activate fans 1-3. */
- { 0x14, 0xd7},
- /* Set the correct sensor types. TMPIN1: diode, TMPIN2/3: resistor. */
- { 0x51, 0x31},
- /* Fan1 (CPU_FAN) is software-controlled. */
- { 0x15, 0x7f},
- /* Fan2 (CHA_FAN1) is software-controlled. */
- { 0x16, 0x7f},
- /* Fan3 (PWR_FAN1) is software-controlled. */
- { 0x17, 0x7f},
- /* Enable fan1/2/3, select "on/off mode" for all of them. */
- { 0x13, 0x70},
-};
-
-/* Called from src/ite/it8716f/superio.c. */
-void init_ec(u16 base)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(sequence); i++)
- write_index(base, sequence[i].index, sequence[i].value);
-}
diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c
deleted file mode 100644
index 6809eda4a9..0000000000
--- a/src/mainboard/asus/m2n-e/get_bus_conf.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-/* Global variables for MB layouts (shared by irqtable/mptable/acpi_table). */
-// busnum is default.
-unsigned char bus_mcp55[8]; // 1
-unsigned apicid_mcp55;
-
-unsigned pci1234x[] = {
- /* Here you only need to set value in pci1234 for HT-IO that could
- * be installed or not. You may need to preset pci1234 for HTIO board,
- * please refer to * src/northbridge/amd/amdk8/get_sblk_pci1234.c.
- */
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-unsigned hcdnx[] = {
- /* HT Chain device num, actually it is unit id base of every ht
- * device in chain, assume every chain only have 4 ht device at most.
- */
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- unsigned int apicid_base, sbdn;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* Do it only once. */
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* First byte of first chain */
- sbdn = sysconf.sbdn;
-
- for (i = 0; i < 8; i++)
- bus_mcp55[i] = 0;
-
- bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0));
- if (dev) {
- bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_mcp55[2]++;
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, "
- "using defaults\n", sbdn + 0x06);
- bus_mcp55[1] = 2;
- bus_mcp55[2] = 3;
- }
-
- for (i = 2; i < 8; i++) {
- dev = dev_find_slot(bus_mcp55[0],
- PCI_DEVFN(sbdn + 0x0a + i - 2, 0));
- if (dev)
- bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_mcp55 = apicid_base + 0;
-}
diff --git a/src/mainboard/asus/m2n-e/hda_verb.c b/src/mainboard/asus/m2n-e/hda_verb.c
deleted file mode 100644
index 3c82ba84e0..0000000000
--- a/src/mainboard/asus/m2n-e/hda_verb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * HDA codec soldered onto the ASUS M2N-E:
- * Analog Devices AD1988B (High Definition Audio SoundMAX Codec), rev. 0x100200
- * http://www.analog.com/static/imported-files/data_sheets/AD1988A_1988B.pdf
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
- /* coreboot specific header */
- 0x11d4198b, /* Codec Vendor / Device ID: Analog Devices AD1988B */
- 0x104381f6, /* Subsystem ID (0x1043 == ASUS) */
- 0x0000000d, /* Number of "pin complex" entries in the table */
-
- /* NID 0x01, FUNCTION, Designates this device as an audio codec */
- /* Set the Implementation ID (IID), here: 0x104381f6. */
- AZALIA_SUBVENDOR(0x0, 0x104381f6),
-
- /* "Pin complex" HDA widgets. Comments: Node ID, Name, Description. */
-
- /* NID 0x11, Port A, Front panel headphone jack */
- AZALIA_PIN_CFG(0x0, 0x11, 0x02214130),
-
- /* NID 0x12, Port D, Rear panel front speaker jack */
- AZALIA_PIN_CFG(0x0, 0x12, 0x01014010),
-
- /* NID 0x13, MONO_OUT, Monaural output pin */
- AZALIA_PIN_CFG(0x0, 0x13, 0x511711f0),
-
- /* NID 0x14, Port B, Front panel microphone jack */
- AZALIA_PIN_CFG(0x0, 0x14, 0x02a19122),
-
- /* NID 0x15, Port C, Rear panel line-in jack */
- AZALIA_PIN_CFG(0x0, 0x15, 0x01813021),
-
- /* NID 0x16, Port F, Rear panel surround-back (5.1) jack */
- AZALIA_PIN_CFG(0x0, 0x16, 0x01011012),
-
- /* NID 0x17, Port E, Rear panel microphone jack */
- AZALIA_PIN_CFG(0x0, 0x17, 0x01a19020),
-
- /* NID 0x18, CD IN, Analog CD input */
- AZALIA_PIN_CFG(0x0, 0x18, 0x9933112e),
-
- /* NID 0x1a, Analog PCBEEP, External analog PCBEEP signal input */
- AZALIA_PIN_CFG(0x0, 0x1a, 0x99f301f0),
-
- /* NID 0x1b, S/PDIF Out, S/PDIF output pin */
- AZALIA_PIN_CFG(0x0, 0x1b, 0x0145f1f0),
-
- /* NID 0x1c, S/PDIF In, S/PDIF input pin */
- AZALIA_PIN_CFG(0x0, 0x1c, 0x41c5f1f0),
-
- /* NID 0x24, Port G, Rear panel C/LFE jack */
- AZALIA_PIN_CFG(0x0, 0x24, 0x01016011),
-
- /* NID 0x25, Port H, Rear panel surround-side (7.1) jack */
- AZALIA_PIN_CFG(0x0, 0x25, 0x01012014),
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c
deleted file mode 100644
index 5d9f0fc400..0000000000
--- a/src/mainboard/asus/m2n-e/mptable.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, \
- MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, \
- bus_mcp55[bus], (((dev) << 2) | (fn)), apicid_mcp55, (pin))
-
-extern unsigned char bus_mcp55[8];
-extern unsigned apicid_mcp55;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned int sbdn;
- int i, j, bus_isa;
- struct device *dev;
- struct resource *res;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x1, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res)
- smp_write_ioapic(mc, apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
-
- pci_write_config32(dev, 0x7c, 0x00000000);
- pci_write_config32(dev, 0x80, 0x11002009);
- pci_write_config32(dev, 0x84, 0x2000dd08);
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
-
- /* I/O Ints */
- PCI_INT(0, sbdn + 1, 1, 10); /* SMBus */
- PCI_INT(0, sbdn + 2, 0, 20); /* USB 1.1 */
- PCI_INT(0, sbdn + 2, 1, 22); /* USB 2.0 */
- PCI_INT(0, sbdn + 4, 0, 14); /* IDE */
- PCI_INT(0, sbdn + 5, 0, 23); /* SATA 0 */
- PCI_INT(0, sbdn + 5, 1, 23); /* SATA 1 */
- PCI_INT(0, sbdn + 5, 2, 22); /* SATA 2 */
- PCI_INT(0, sbdn + 6, 1, 21); /* HD audio */
- PCI_INT(0, sbdn + 8, 0, 24); /* NIC */
-
- /* PCI-E slots (two x1, one x4, one x16) */
- for (j = 7; j >= 2; j--) {
- if (!bus_mcp55[j])
- continue;
- for (i = 0; i < 4; i++)
- PCI_INT(j, 0, i, 0x10 + (2 + j + i + 4 - sbdn % 4) % 4);
- }
-
- /* PCI slots (three on this board) */
- for (j = 0; j < 3; j++) {
- for (i = 0; i < 4; i++)
- PCI_INT(1, 0x06 + j, i, 0x10 + (2 + i + j) % 4);
- }
-
- /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_isa);
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/m2n-e/resourcemap.c b/src/mainboard/asus/m2n-e/resourcemap.c
deleted file mode 100644
index 57e7389490..0000000000
--- a/src/mainboard/asus/m2n-e/resourcemap.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
deleted file mode 100644
index 329a95e4d7..0000000000
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <southbridge/nvidia/mcp55/mcp55.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/x86/lapic.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8716f/it8716f.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
-#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
-
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl) {}
-void activate_spd_rom(const struct mem_controller *ctrl) {}
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-/* FIXME
- * Dummy method to allow build
- * Determine if this board / CPU should support
- * FID/VID and implement proper support if so
- */
-#if IS_ENABLED(CONFIG_SET_FIDVID)
-void init_fidvid_ap(u32 bsp_apicid, u32 apicid) { }
-#endif
-
-static void sio_setup(void)
-{
- u8 byte;
- u32 dword;
- pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */
-
- /* Subject decoding */
- byte = pci_read_config8(dev, 0x7b);
- byte |= (1 << 5);
- pci_write_config8(dev, 0x7b, byte);
-
- /* LPC Positive Decode 0 */
- dword = pci_read_config32(dev, 0xa0);
- dword |= (1 << 0); /* COM1 */
- pci_write_config32(dev, 0xa0, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const u16 spd_addr[] = {
- DIMM0, DIMM2, 0, 0, /* Channel A (DIMM_A1, DIMM_A2) */
- DIMM1, DIMM3, 0, 0, /* Channel B (DIMM_B1, DIMM_B2) */
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset = 0;
- unsigned bsp_apicid = 0;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Allow the HT devices to be found. */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- setup_mb_resource_map();
- report_bist_failure(bist);
- console_init();
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);
- printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid);
-
- /* In BSP so could hold all AP until sysinfo is in RAM. */
- set_sysinfo_in_ram(0);
-
- setup_coherent_ht_domain(); /* Routing table and start other core0. */
- wait_all_core0_started();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /*
- * It is said that we should start core1 after all core0 launched
- * becase optimize_link_coherent_ht is moved out from
- * setup_coherent_ht_domain, so here need to make sure last core0 is
- * started, esp for two way system (there may be APIC ID conflicts in
- * that case).
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* Set up chains and store link pair for optimization later. */
- ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
- /* TODO: FIDVID */
-
- init_timer(); /* Need to use TMICT to synchronize FID/VID. */
-
- needs_reset |= optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= mcp55_early_setup_x();
-
- /*
- * FIDVID change will issue one LDTSTOP and the HT change will be
- * effective too.
- */
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
- allow_all_aps_stop(bsp_apicid);
-
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
-}
diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig
deleted file mode 100644
index 60ed865fad..0000000000
--- a/src/mainboard/asus/m2v-mx_se/Kconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Cristi Măgherușan <cristi.magherusan@net.utcluj.ro>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-if BOARD_ASUS_M2V_MX_SE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_AM2
- select DIMM_DDR2
- select QRANK_DIMM_SUPPORT
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_VIA_VT8237R
- select SOUTHBRIDGE_VIA_K8T890
- select SOUTHBRIDGE_VIA_SUBTYPE_K8M890
- select SUPERIO_ITE_IT8712F
- select HAVE_OPTION_TABLE
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_512
- select VGA
- select HAVE_ACPI_RESUME
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default asus/m2v-mx_se
-
-config DCACHE_RAM_BASE
- hex
- default 0xcc000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x4000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "M2V-MX SE"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-endif # BOARD_ASUS_M2V_MX_SE
diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig.name b/src/mainboard/asus/m2v-mx_se/Kconfig.name
deleted file mode 100644
index f15d444131..0000000000
--- a/src/mainboard/asus/m2v-mx_se/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_M2V_MX_SE
- bool "M2V-MX SE"
diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c
deleted file mode 100644
index 397d310a99..0000000000
--- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-void get_bus_conf(void)
-{
- /* FIXME: implement this. */
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, IO_APIC_ADDR, 0);
-
- /* Write NB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/m2v-mx_se/board_info.txt b/src/mainboard/asus/m2v-mx_se/board_info.txt
deleted file mode 100644
index 00139ad873..0000000000
--- a/src/mainboard/asus/m2v-mx_se/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_AM2/M2VMX_SE/
-ROM package: DIP8
-ROM protocol: SPI
-ROM socketed: y
-Flashrom support: y
-Release year: 2007
diff --git a/src/mainboard/asus/m2v-mx_se/cmos.default b/src/mainboard/asus/m2v-mx_se/cmos.default
deleted file mode 100644
index fae766bc88..0000000000
--- a/src/mainboard/asus/m2v-mx_se/cmos.default
+++ /dev/null
@@ -1,11 +0,0 @@
-boot_option = Fallback
-hw_scrubber = Enable
-interleave_chip_selects = Enable
-max_mem_clock = DDR2-400
-multi_core = Enable
-power_on_after_fail = On
-debug_level = Spew
-slow_cpu = off
-nmi = Disable
-videoram_size = 8MB
-iommu = Enable
diff --git a/src/mainboard/asus/m2v-mx_se/cmos.layout b/src/mainboard/asus/m2v-mx_se/cmos.layout
deleted file mode 100644
index 29476ecc33..0000000000
--- a/src/mainboard/asus/m2v-mx_se/cmos.layout
+++ /dev/null
@@ -1,60 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-448 3 e 10 videoram_size
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-# videoram_size: mimics the bits in the ramcontroller.
-10 1 8MB
-10 2 16MB
-10 3 32MB
-10 4 64MB
-10 5 128MB
-10 6 256MB
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/m2v-mx_se/devicetree.cb b/src/mainboard/asus/m2v-mx_se/devicetree.cb
deleted file mode 100644
index 213e3ea9c0..0000000000
--- a/src/mainboard/asus/m2v-mx_se/devicetree.cb
+++ /dev/null
@@ -1,77 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # APIC cluster
- chip cpu/amd/socket_AM2 # CPU
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1043 0 inherit
- chip northbridge/amd/amdk8 # mc0
- device pci 18.0 on # Northbridge
- # Devices on link 0, link 0 == LDT 0
- chip southbridge/via/vt8237r # Southbridge
- register "ide0_enable" = "1" # Enable IDE channel 0
- register "ide1_enable" = "1" # Enable IDE channel 1
- register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
- register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
- register "fn_ctrl_lo" = "0xc0" # Enable SB functions
- register "fn_ctrl_hi" = "0x1d" # Enable SB functions
- device pci 0.0 on end # HT
- device pci f.1 on end # IDE
- device pci 11.0 on # LPC
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip superio/ite/it8712f # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 on # Environment controller
- io 0x60 = 0x290
- io 0x62 = 0x230
- irq 0x70 = 0x00
- end
- device pnp 2e.5 off end # PS/2 keyboard
- device pnp 2e.6 off end # PS/2 mouse
- device pnp 2e.7 off end # GPIO config
- device pnp 2e.8 off end # Midi port
- device pnp 2e.9 off end # Game port
- device pnp 2e.a off end # IR
- end
- end
- device pci 12.0 on end # VIA LAN
- device pci 13.0 on end # br
- device pci 13.1 on end # br2 need to have it here to discover it
- end
- chip southbridge/via/k8t890 # "Southbridge" K8M890
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/m2v-mx_se/dsdt.asl b/src/mainboard/asus/m2v-mx_se/dsdt.asl
deleted file mode 100644
index 30ce550996..0000000000
--- a/src/mainboard/asus/m2v-mx_se/dsdt.asl
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- #include <southbridge/via/k8t890/acpi/sleepstates.asl>
-
- /* blink a LED when entering the sleep (any type) */
- Method (_PTS, 1, NotSerialized)
- {
- Store (0x1, \_SB.PCI0.ISA.LEDR)
- }
-
- /* cancel a LED blinking when waking from sleep (any type) */
- Method (_WAK, 1, NotSerialized)
- {
- Store (0x0, \_SB.PCI0.ISA.LEDR)
- /* wake OK */
- Return(Package(0x02){0x00, 0x00})
- }
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 }, /* 0xf SATA IRQ 21 */
- Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
- Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x14 }, /* USB routing */
- Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x16 },
- Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x17 },
- Package (0x04) { 0x0012FFFF, 0x00, 0x00, 0x17 }, /* LAN */
- Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 }, /* PCIe bridge SB */
- Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x16 }, /* PCIe bridge SB */
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP pridge */
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, /* FIXME FIXME */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
- })
-
- Device (PEGG)
- {
- Name (_ADR, 0x00020000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
- })
- }
-
- Device (PEX0)
- {
- Name (_ADR, 0x00030000)
- Name (_UID, 0x00)
- Name (_BBN, 0x03)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
- })
- }
-
- Device (PEX1)
- {
- Name (_ADR, 0x00130000)
- Name (_UID, 0x00)
- Name (_BBN, 0x4)
- Name (_PRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* PCIE audio */
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x11 },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x11 },
- })
- }
-
- Device (TBRG)
- {
- Name (_ADR, 0x00130001)
- Name (_UID, 0x00)
- Name (_BBN, 0x5)
- Name (_PRT, Package () {
- Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 }, /* PCI slot */
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 }, /* PCI slot */
- Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
- })
- }
- Device (ISA) {
- Name (_ADR, 0x00110000)
- OperationRegion (PCIC, PCI_Config, 0x0, 0xff)
- Field (PCIC, ByteAcc, NoLock, Preserve)
- {
- Offset (0x94),
- /* two LSB bits are blink rate */
- LEDR, 2,
- }
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
- IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- }
- /* Dummy device to hold auto generated reserved resources */
- Device(MBRS) {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- External(_CRS) /* Resource Template in SSDT */
- }
- }
- }
-}
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
deleted file mode 100644
index 322f76302f..0000000000
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2006 MSI
- * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <halt.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include <southbridge/via/vt8237r/vt8237r.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <spd.h>
-#include <northbridge/amd/amdk8/f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "southbridge/via/k8t890/early_car.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-#define SB_VFSMAF 0
-
-static void ldtstop_sb(void)
-{
- printk(BIOS_DEBUG, "toggle LDTSTP#\n");
-
- /* fix errata #181, disable DRAM controller it will get enabled later */
- u8 tmp = pci_read_config8(PCI_DEV(0, 0x18, 2), 0x94);
- tmp |= (( 1 << 14) | (1 << 3));
- pci_write_config8(PCI_DEV(0, 0x18, 2), 0x94, tmp);
-
- u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
- reg = reg ^ (1 << 0);
- outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
- reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
- printk(BIOS_DEBUG, "done\n");
-}
-
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-void do_soft_reset(void)
-{
- uint8_t tmp;
-
- set_bios_reset();
- printk(BIOS_DEBUG, "soft reset\n");
-
- /* PCI reset */
- tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
- tmp |= 0x01;
- /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
- pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
-
- halt();
-}
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
- unsigned bsp_apicid = 0;
- int needs_reset = 0;
- struct sys_info *sysinfo = &sysinfo_car;
-
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- ite_kill_watchdog(GPIO_DEV);
- ite_enable_3vsbsw(GPIO_DEV);
- console_init();
- enable_rom_decode();
-
- printk(BIOS_INFO, "now booting...\n");
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- /* Halt if there was a built in self test failure. */
- report_bist_failure(bist);
- setup_default_resource_map();
- setup_coherent_ht_domain();
- wait_all_core0_started();
-
- printk(BIOS_INFO, "now booting... All core 0 started\n");
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched. */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
- init_timer();
- ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
- needs_reset = optimize_link_coherent_ht();
- printk(BIOS_DEBUG, "%02x", needs_reset);
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- printk(BIOS_DEBUG, "%02x", needs_reset);
- needs_reset |= k8t890_early_setup_ht();
- printk(BIOS_DEBUG, "%02x", needs_reset);
-
- vt8237_early_network_init(NULL);
- vt8237_early_spi_init();
-
- if (needs_reset) {
- printk(BIOS_DEBUG, "ht reset -\n");
- soft_reset();
- printk(BIOS_DEBUG, "FAILED!\n");
- }
-
- /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
- /* allow LDT STOP asserts */
- vt8237_sb_enable_fid_vid();
-
- enable_fid_change();
- printk(BIOS_DEBUG, "after enable_fid_change\n");
-
- init_fidvid_bsp(bsp_apicid);
-
- /* Stop the APs so we can start them later in init. */
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now. */
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- enable_smbus();
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig
deleted file mode 100644
index 26bfeef26f..0000000000
--- a/src/mainboard/asus/m2v/Kconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-if BOARD_ASUS_M2V
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_AM2
- select DIMM_DDR2
- select QRANK_DIMM_SUPPORT
- select K8_HT_FREQ_1G_SUPPORT
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_VIA_VT8237R
- select SOUTHBRIDGE_VIA_K8T890
- select SOUTHBRIDGE_VIA_SUBTYPE_K8T890
- select SUPERIO_ITE_IT8712F
- select HAVE_OPTION_TABLE
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_512
- select HAVE_ACPI_RESUME
- select HAVE_PIRQ_TABLE
- select PIRQ_ROUTE
- select HAVE_MP_TABLE
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default asus/m2v
-
-config DCACHE_RAM_BASE
- hex
- default 0xcc000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x4000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "M2V"
-
-config HW_MEM_HOLE_SIZEK
- hex
- default 0x0
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 14
-
-endif # BOARD_ASUS_M2V
diff --git a/src/mainboard/asus/m2v/Kconfig.name b/src/mainboard/asus/m2v/Kconfig.name
deleted file mode 100644
index c0fc2f31a3..0000000000
--- a/src/mainboard/asus/m2v/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_M2V
- bool "M2V"
diff --git a/src/mainboard/asus/m2v/acpi_tables.c b/src/mainboard/asus/m2v/acpi_tables.c
deleted file mode 100644
index fce0fb6db2..0000000000
--- a/src/mainboard/asus/m2v/acpi_tables.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-void get_bus_conf(void)
-{
- /* FIXME: implement this. */
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, IO_APIC_ADDR, 0);
-
- /* Write NB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/m2v/board_info.txt b/src/mainboard/asus/m2v/board_info.txt
deleted file mode 100644
index 1abcb5b361..0000000000
--- a/src/mainboard/asus/m2v/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_AM2/M2V/
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2007
diff --git a/src/mainboard/asus/m2v/cmos.layout b/src/mainboard/asus/m2v/cmos.layout
deleted file mode 100644
index aae7ceb075..0000000000
--- a/src/mainboard/asus/m2v/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/m2v/devicetree.cb b/src/mainboard/asus/m2v/devicetree.cb
deleted file mode 100644
index 61d94bad3f..0000000000
--- a/src/mainboard/asus/m2v/devicetree.cb
+++ /dev/null
@@ -1,75 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # APIC cluster
- chip cpu/amd/socket_AM2 # CPU
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1043 0 inherit
- chip northbridge/amd/amdk8 # mc0
- device pci 18.0 on # Northbridge
- # Devices on link 0, link 0 == LDT 0
- chip southbridge/via/vt8237r # Southbridge
- register "ide0_enable" = "1" # Enable IDE channel 0
- register "ide1_enable" = "1" # Enable IDE channel 1
- register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
- register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
- register "fn_ctrl_lo" = "0xc0" # Enable SB functions
- register "fn_ctrl_hi" = "0x0d" # Enable SB functions
- device pci 0.0 on end # HT
- device pci f.1 on end # IDE
- device pci 11.0 on # LPC
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip superio/ite/it8712f # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off end # Com2 (N/A on this board)
- device pnp 2e.3 on # Lpt1
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.4 on # Environment controller
- io 0x60 = 0xd00
- io 0x62 = 0xc00
- irq 0x70 = 0x00
- end
- device pnp 2e.5 off end # PS/2 keyboard
- device pnp 2e.6 off end # PS/2 mouse
- device pnp 2e.7 off end # GPIO config
- device pnp 2e.8 off end # Midi port
- device pnp 2e.9 off end # Game port
- device pnp 2e.a off end # IR
- end
- end
- device pci 12.0 off end # VIA LAN (off, other chip used)
- device pci 13.0 on end # br
- device pci 13.1 on end # br2, need to have it here to discover it
- end
- chip southbridge/via/k8t890 # "Southbridge" K8T890
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/m2v/dsdt.asl b/src/mainboard/asus/m2v/dsdt.asl
deleted file mode 100644
index 760d5e214c..0000000000
--- a/src/mainboard/asus/m2v/dsdt.asl
+++ /dev/null
@@ -1,545 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-#define LNKA INTA
-#define LNKB INTB
-#define LNKC INTC
-#define LNKD INTD
-
-/*
- * For simplicity map LNK[E-H] to LNK[A-D].
- * This also means we are 82C596 compatible.
- * Needs 0:11.0 0x46[4] set to 0.
- */
-#define LNKE INTA
-#define LNKF INTB
-#define LNKG INTC
-#define LNKH INTD
-
-DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
-{
- Name(APIC, 0) // 0=>8259, 1=>IOAPIC
-
- /* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
-
- Method(_PIC, 1)
- {
- // Remember the OS' IRQ routing choice.
- Store(Arg0, APIC)
- }
-
- /* _PR CPU0 is dynamically supplied by SSDT */
-
- #include <southbridge/via/k8t890/acpi/sleepstates.asl>
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00180000)
- Name (_BBN, 0x00)
-
- Name (APRT, Package() {
- /* AGP? */
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x13 },
- /* PCIe graphics bridge */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
- /* PCIe bridge */
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B },
- /* SATA */
- Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 },
- /* IDE */
- Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x15 },
- /* USB */
- Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x14 },
- Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x16 },
- Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x17 },
- /* PCI bridge */
- Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 },
- Package (0x04) { 0x0013FFFF, 0x01, 0x00, 0x14 },
- Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x14 },
- Package (0x04) { 0x0013FFFF, 0x03, 0x00, 0x14 },
- })
- Name (PPRT, Package() {
- /* ?? */
- Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, LNKD, 0x00 },
- /* PCIe graphics bridge */
- Package (0x04) { 0x0002FFFF, 0x00, LNKH, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x01, LNKH, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x02, LNKH, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x03, LNKH, 0x00 },
- /* PCIe bridge */
- Package (0x04) { 0x0003FFFF, 0x00, LNKH, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x01, LNKH, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x02, LNKH, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x03, LNKH, 0x00 },
- /* SATA */
- Package (0x04) { 0x000FFFFF, 0x01, LNKB, 0x00 },
- /* USB */
- Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 },
- Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 },
- Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 },
- Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 },
- /* PCI bridge */
- Package (0x04) { 0x0013FFFF, 0x00, LNKD, 0x00 },
- Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 },
- Package (0x04) { 0x0013FFFF, 0x02, LNKD, 0x00 },
- Package (0x04) { 0x0013FFFF, 0x03, LNKD, 0x00 },
- })
-
- /* PCI Routing Table */
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
-
- Device (PEGG)
- {
- Name (_ADR, 0x00020000)
- Name (APRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
- })
- Name (PPRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
- }
-
- Device (PEX0)
- {
- Name (_ADR, 0x00030000)
- Name (APRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
- })
- Name (PPRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
- }
-
- Device (PEX1)
- {
- Name (_ADR, 0x00030001)
- Name (APRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
- })
- Name (PPRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
- }
-
- Device (PEX2)
- {
- Name (_ADR, 0x00030002)
- Name (APRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
- })
- Name (PPRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
- }
-
- Device (PCI6)
- {
- Name (_ADR, 0x00130000)
- Name (APRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* IRQ17 */
- })
- Name (PPRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, LNKB, 0x00 },
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
- }
-
- Device (PCI7)
- {
- Name (_ADR, 0x00130001)
- Name (APRT, Package () {
- /* PCI slot 1 */
- Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
-
- /* PCI slot 2 */
- Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 },
- Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
-
- /* PCI slot 3 */
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 },
- Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x11 },
-
- /* PCI slot 4 */
- Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x13 },
- Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x11 },
- Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x12 },
- })
- Name (PPRT, Package () {
- /* PCI slot 1 */
- Package (0x04) { 0x0006FFFF, 0x00, LNKA, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x01, LNKB, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x02, LNKC, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x03, LNKD, 0x00 },
-
- /* PCI slot 2 */
- Package (0x04) { 0x0007FFFF, 0x00, LNKB, 0x00 },
- Package (0x04) { 0x0007FFFF, 0x01, LNKC, 0x00 },
- Package (0x04) { 0x0007FFFF, 0x02, LNKD, 0x00 },
- Package (0x04) { 0x0007FFFF, 0x03, LNKA, 0x00 },
-
- /* PCI slot 3 */
- Package (0x04) { 0x0008FFFF, 0x00, LNKC, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x01, LNKD, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x02, LNKA, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x03, LNKB, 0x00 },
-
- /* PCI slot 4 */
- Package (0x04) { 0x0009FFFF, 0x00, LNKD, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x01, LNKA, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x02, LNKB, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x03, LNKC, 0x00 },
- })
-
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
- }
-
- Device (SBRG) { /* southbridge */
- Name (_ADR, 0x00110000)
- OperationRegion (PCIC, PCI_Config, 0x0, 0x100)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, Serialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, Serialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* Parallel port */
- Device (LPT0)
- {
- Name (_HID, EisaId ("PNP0401"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, Serialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0378, 0x0378, 0x01, 0x08)
- IO (Decode16, 0x0778, 0x0778, 0x01, 0x08)
- IRQNoFlags () {7}
- DMA (Compatibility, NotBusMaster, Transfer8) {3}
- })
- Return (TMP)
- }
- }
- }
-
- Device(MBRS) {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
-
- External(_CRS) /* Resource Template in SSDT */
- }
-
- External(TOM1) /* top of memory below 4GB */
-
- Method(_CRS, 0, Serialized) {
- Name(TMP, ResourceTemplate() {
- WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, // Granularity
- 0x0000, // Range Minimum
- 0x00FF, // Range Maximum
- 0x0000, // Translation Offset
- 0x0100, // Length
- ,,
- )
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- /* memory space for PCI BARs below 4GB */
- Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
- })
- CreateDWordField(TMP, MMIO._BAS, MM1B)
- CreateDWordField(TMP, MMIO._LEN, MM1L)
- /*
- * Declare memory between TOM1 and 4GB as available
- * for PCI MMIO.
- *
- * Use ShiftLeft to avoid 64bit constant (for XP).
- * This will work even if the OS does 32bit arithmetic, as
- * 32bit (0x00000000 - TOM1) will wrap and give the same
- * result as 64bit (0x100000000 - TOM1).
- */
- Store(TOM1, MM1B)
- ShiftLeft(0x10000000, 4, Local0)
- Subtract(Local0, TOM1, Local0)
- Store(Local0, MM1L)
-
- Return(TMP)
- }
- }
-
- Field (PCI0.SBRG.PCIC, ByteAcc, NoLock, Preserve)
- {
- Offset (0x55),
- /*
- * Offset 0x55:
- * 3-0: reserved
- * 7-4: PCI INTA# routing
- * Offset 0x56:
- * 3-0: PCI INTB# routing
- * 7-4: PCI INTC# routing
- * Offset 0x57:
- * 3-0: reserved
- * 7-4: PCI INTD# routing
- *
- * Valid values for routing link:
- * 0: disabled
- * 2,8,13: reserved
- * 1,3-7,9-12,14,15: corresponding irq
- */
- , 4,
- PINA, 4,
- PINB, 4,
- PINC, 4,
- , 4,
- PIND, 4,
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 6, 7, 10, 11, 12}
- })
-
- /* adapted from ma78gm/dsdt.asl */
-#define PCI_INTX_DEV(intx, pinx, uid) \
- Device(intx) { \
- Name(_HID, EISAID("PNP0C0F")) \
- Name(_UID, uid) \
- \
- Method(_STA, 0) { \
- if (pinx) { \
- Return(0x0B) \
- } \
- Return(0x09) \
- } \
- \
- Method(_DIS ,0) { \
- Store(0, pinx) \
- } \
- \
- Method(_PRS ,0) { \
- Return(IRQP) \
- } \
- \
- Method(_CRS ,0) { \
- CreateWordField(IRQB, 1, IRQN) \
- ShiftLeft(1, pinx, IRQN) \
- Return(IRQB) \
- } \
- \
- Method(_SRS, 1) { \
- CreateWordField(ARG0, 1, IRQM) \
- \
- /* Use lowest available IRQ */ \
- FindSetRightBit(IRQM, Local0) \
- if (Local0) { \
- Decrement(Local0) \
- } \
- Store(Local0, pinx) \
- } \
- } \
-
-PCI_INTX_DEV(INTA, PINA, 1)
-PCI_INTX_DEV(INTB, PINB, 2)
-PCI_INTX_DEV(INTC, PINC, 3)
-PCI_INTX_DEV(INTD, PIND, 4)
- }
-
- Field (_SB.PCI0.SBRG.PCIC, ByteAcc, NoLock, Preserve)
- {
- Offset (0x94),
- /* two LSB bits are blink rate */
- LEDR, 2,
- }
-
- Method (_PTS, 1, NotSerialized)
- {
- /* blink power led while suspended */
- Store (0x1, LEDR)
- }
-
- Method (_WAK, 1, NotSerialized)
- {
- /* stop power led blinking */
- Store (0x0, LEDR)
- /* wake OK */
- Return(Package(0x02){0x00, 0x00})
- }
-}
diff --git a/src/mainboard/asus/m2v/irq_tables.c b/src/mainboard/asus/m2v/irq_tables.c
deleted file mode 100644
index 18bebf545e..0000000000
--- a/src/mainboard/asus/m2v/irq_tables.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * IRQ Routing Table
- *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
- */
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <device/pci_ids.h>
-
-/* Free irqs are 3, 5, 10 and 11 */
-#define IRQBM ((1 << 3)|(1 << 5)|(1 << 10)|(1 << 11))
-
-#define LNKA 1
-#define LNKB 2
-#define LNKC 3
-#define LNKD 4
-
-/*
- * For simplicity map LNK[E-H] to LNK[A-D].
- * This also means we are 82C596 compatible.
- * Needs 0:11.0 0x46[4] set to 0.
- */
-#define LNKE 1
-#define LNKF 2
-#define LNKG 3
-#define LNKH 4
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0, /* Where the interrupt router lies (bus) */
- (0x11 << 3)|0, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- PCI_VENDOR_ID_VIA, /* Compatible Vendor (VIA) */
- PCI_DEVICE_ID_VIA_82C596, /* Compatible Device (82C596) */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x5f, /* u8 checksum, this has to be set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- /* peg bridge */
- {0x00, (0x02 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
- /* pcie bridge */
- {0x00, (0x03 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
- /* sata/ide */
- {0x00, (0x0f << 3) | 0x0, {{0x00, 0x0000}, {LNKB, IRQBM}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
- /* usb */
- {0x00, (0x10 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x0, 0x0},
- /* agp bus? */
- {0x01, (0x00 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x0, 0x0},
- /* pcie graphics */
- {0x02, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x6, 0x0},
- /* onboard pcie atl1 ethernet */
- {0x03, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
- /* pcie slot */
- {0x04, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x5, 0x0},
- /* onboard marvell mv6121 sata */
- {0x05, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
- /* Azalia HDAC */
- {0x06, (0x01 << 3) | 0x0, {{LNKB, IRQBM}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
- /* PCI slots */
- {0x07, (0x06 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x1, 0x0},
- {0x07, (0x07 << 3) | 0x0, {{LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}, {LNKA, IRQBM}}, 0x2, 0x0},
- {0x07, (0x08 << 3) | 0x0, {{LNKC, IRQBM}, {LNKD, IRQBM}, {LNKA, IRQBM}, {LNKB, IRQBM}}, 0x3, 0x0},
- {0x07, (0x09 << 3) | 0x0, {{LNKD, IRQBM}, {LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}}, 0x4, 0x0},
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c
deleted file mode 100644
index e16faebfae..0000000000
--- a/src/mainboard/asus/m2v/mainboard.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-
-u32 vt8237_ide_80pin_detect(struct device *dev)
-{
- struct device *lpc_dev;
- u16 acpi_io_base;
- u32 gpio_in;
- u32 res;
-
- lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);
- if (!lpc_dev)
- return 0;
-
- acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1;
- if (!acpi_io_base)
- return 0;
-
- gpio_in = inl(acpi_io_base + 0x48);
- /* bit 9 for primary port, clear if unconnected or 80-pin cable */
- res = gpio_in & (1 << 9) ? 0 : VT8237R_IDE0_80PIN_CABLE;
- /* bit 4 for secondary port, clear if unconnected or 80-pin cable */
- res |= gpio_in & (1 << 4) ? 0 : VT8237R_IDE1_80PIN_CABLE;
-
- printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
- res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);
- printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary",
- res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40);
-
- return res;
-}
diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c
deleted file mode 100644
index 8de77ccdb5..0000000000
--- a/src/mainboard/asus/m2v/mptable.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <stdint.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-
-static void smp_write_intsrc_pci(struct mp_config_table *mc,
- unsigned char srcbus, unsigned char srcbusirq,
- unsigned char dstapic, unsigned char dstirq)
-{
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- srcbus, srcbusirq, dstapic, dstirq);
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void*)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, VIO_APIC_VADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, (void*)K8T890_APIC_BASE);
-
- mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
-
- /* agp? bridge */
- smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 0, VT8237R_APIC_ID, 0x10);
- smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 1, VT8237R_APIC_ID, 0x11);
- smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 2, VT8237R_APIC_ID, 0x12);
- smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 3, VT8237R_APIC_ID, 0x13);
-
- /* peg bridge */
- smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
- smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
- smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
- smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- /* pex bridge */
- smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
- smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
- smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
- smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- /* SATA / IDE */
- smp_write_intsrc_pci(mc, 0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x15);
-
- /* USB */
- smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x16);
- smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 3, VT8237R_APIC_ID, 0x17);
-
- /* PCIE graphics */
- smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
- smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
- smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
- smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- /* onboard PCIE atl1 ethernet */
- smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
- smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
- smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
- smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
-
- /* PCIE slot */
- smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
- smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
- smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
- smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
-
- /* onboard marvell mv6121 sata */
- smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
- smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
- smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
- smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
-
- /* azalia HDCA */
- smp_write_intsrc_pci(mc, 6, (0x01 << 2) | 0, VT8237R_APIC_ID, 0x11);
-
- /* pci slot 1 */
- smp_write_intsrc_pci(mc, 7, (6 << 2) | 0, VT8237R_APIC_ID, 0x10);
- smp_write_intsrc_pci(mc, 7, (6 << 2) | 1, VT8237R_APIC_ID, 0x11);
- smp_write_intsrc_pci(mc, 7, (6 << 2) | 2, VT8237R_APIC_ID, 0x12);
- smp_write_intsrc_pci(mc, 7, (6 << 2) | 3, VT8237R_APIC_ID, 0x13);
-
- /* pci slot 2 */
- smp_write_intsrc_pci(mc, 7, (7 << 2) | 0, VT8237R_APIC_ID, 0x11);
- smp_write_intsrc_pci(mc, 7, (7 << 2) | 1, VT8237R_APIC_ID, 0x12);
- smp_write_intsrc_pci(mc, 7, (7 << 2) | 2, VT8237R_APIC_ID, 0x13);
- smp_write_intsrc_pci(mc, 7, (7 << 2) | 3, VT8237R_APIC_ID, 0x10);
-
- /* pci slot 3 */
- smp_write_intsrc_pci(mc, 7, (8 << 2) | 0, VT8237R_APIC_ID, 0x12);
- smp_write_intsrc_pci(mc, 7, (8 << 2) | 1, VT8237R_APIC_ID, 0x13);
- smp_write_intsrc_pci(mc, 7, (8 << 2) | 2, VT8237R_APIC_ID, 0x10);
- smp_write_intsrc_pci(mc, 7, (8 << 2) | 3, VT8237R_APIC_ID, 0x11);
-
- /* pci slot 4 */
- smp_write_intsrc_pci(mc, 7, (9 << 2) | 0, VT8237R_APIC_ID, 0x13);
- smp_write_intsrc_pci(mc, 7, (9 << 2) | 1, VT8237R_APIC_ID, 0x10);
- smp_write_intsrc_pci(mc, 7, (9 << 2) | 2, VT8237R_APIC_ID, 0x11);
- smp_write_intsrc_pci(mc, 7, (9 << 2) | 3, VT8237R_APIC_ID, 0x12);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, 0);
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
deleted file mode 100644
index d49f231f75..0000000000
--- a/src/mainboard/asus/m2v/romstage.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2006 MSI
- * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <halt.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include <southbridge/via/vt8237r/vt8237r.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-
-#define IT8712F_GPIO_BASE 0x0a20
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "southbridge/via/k8t890/early_car.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-void do_soft_reset(void)
-{
- uint8_t tmp;
-
- set_bios_reset();
- printk(BIOS_DEBUG, "soft reset\n");
-
- /* PCI reset */
- tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
- tmp |= 0x01;
- /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
- pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
-
- halt();
-}
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
-}
-
-struct gpio_init_val {
- u8 addr;
- u8 val;
-};
-
-static const struct gpio_init_val gpio_init_data[] = {
- /* multi-function pin selection */
- { 0x25, 0x00 },
- { 0x28, 0x00 }, /* gp46 is infrared receive input */
- { 0x29, 0x40 }, /* reserved value?!? */
- { 0x2a, 0x00 },
- { 0x2c, 0x1d }, /* pin91 is VIN7 instead of PCIRSTIN# */
- /* gpio i/o port base */
- { 0x62, IT8712F_GPIO_BASE >> 8 },
- { 0x63, IT8712F_GPIO_BASE & 0xff },
- /* 0xb8 - 0xbc: gpio pull-up enable */
- { 0xb8, 0x00 },
- /* 0xc0 - 0xc4: gpio alternate function select */
- { 0xc0, 0x00 },
- { 0xc3, 0x00 },
- { 0xc4, 0xc0 },
- /* 0xc8 - 0xcc: gpio output enable */
- { 0xc8, 0x00 },
- { 0xcb, 0x00 },
- { 0xcc, 0xc0 },
- /* end of list */
- { 0, 0 },
-};
-
-static void m2v_it8712f_gpio_init(void)
-{
- const struct gpio_init_val *giv;
-
- printk(BIOS_SPEW, "it8712f gpio init...\n");
-
- /*
- * it8712f gpio config
- *
- * Most importantly this switches pin 91 from
- * PCIRSTIN# to VIN7.
- * Note that only PCIRST3# and PCIRST5# are affected
- * by PCIRSTIN#, the PCIRST1#, PCIRST2#, PCIRST4# are always
- * direct buffers of #LRESET (low pin count bus reset).
- * If this is not done All PCIRST are in reset state and the
- * pcie slots don't initialize.
- *
- * pci reset handling:
- * pin 91: VIN7 (alternate PCIRSTIN#)
- * pin 48: PCIRST5# / gpio port 5 bit 0
- * pin 84: PCIRST4# / gpio port 1 bit 0
- * pin 31: PCIRST1# / gpio port 1 bit 4
- * pin 33: PCIRST2# / gpio port 1 bit 2
- * pin 34: PCIRST3# / gpio port 1 bit 1
- *
- * PCIRST[0-5]# are connected as follows:
- * pcirst1# -> pci bus
- * pcirst2# -> ide bus
- * pcirst3# -> pcie devices
- * pcirst4# -> pcie graphics
- * pcirst5# -> maybe n/c (untested)
- *
- * For software control of PCIRST[1-5]#:
- * 0x2a = 0x17 (deselect pcirst# hardwiring, enable 0x25 control)
- * 0x25 = 0x17 (select gpio function)
- * 0xc0 = 0x17, 0xc8 = 0x17 gpio port 1 select & output enable
- * 0xc4 = 0xc1, 0xcc = 0xc1 gpio port 5 select & output enable
- */
- giv = gpio_init_data;
- while (giv->addr) {
- printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n",
- giv->addr, giv->val);
- ite_reg_write(IT8712F_GPIO, giv->addr, giv->val);
- giv++;
- }
-
- printk(BIOS_INFO, "it8712f gpio: Setting DDR2 voltage to 1.80V\n");
- /*
- * upper two bits of gpio_base+4 control ddr2 voltage:
- * 11: 1.80V
- * 01: 1.85V
- * 10: 1.90V
- * 00: 1.95V
- *
- * The lower six bits are inputs and normally read back as 1
- * (except bit 2, which seems rather random).
- */
- outb(0xff, IT8712F_GPIO_BASE+4);
-}
-
-static void m2v_bus_init(void)
-{
- pci_devfn_t dev;
-
- printk(BIOS_SPEW, "m2v_bus_init\n");
-
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8T890CF_0), 0);
- pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
-
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8T890CF_5), 0);
- /*
- * bit | meaning
- * 6 | 0: hide scratch register function 0:0.6 (we don't use it)
- * 5 | 1: enable pcie bridge 0:2.0
- * 4 | 0: hide pcie bridge 0:3.3 (not connected)
- * 3 | 1: enable pcie bridge 0:3.2
- * 2 | 1: enable pcie bridge 0:3.1
- * 1 | 1: enable pcie bridge 0:3.0
- */
- pci_write_config8(dev, 0xf0, 0x2e);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
- unsigned bsp_apicid = 0;
- int needs_reset = 0;
- struct sys_info *sysinfo = &sysinfo_car;
-
- ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- ite_kill_watchdog(GPIO_DEV);
- console_init();
- enable_rom_decode();
- m2v_bus_init();
- m2v_it8712f_gpio_init();
- ite_enable_3vsbsw(GPIO_DEV);
-
- printk(BIOS_INFO, "now booting...\n");
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- /* Halt if there was a built in self test failure. */
- report_bist_failure(bist);
- setup_default_resource_map();
- setup_coherent_ht_domain();
- wait_all_core0_started();
-
- printk(BIOS_INFO, "now booting... All core 0 started\n");
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched. */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
- init_timer();
- ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
- needs_reset = optimize_link_coherent_ht();
- printk(BIOS_DEBUG, "%02x", needs_reset);
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- printk(BIOS_DEBUG, "%02x", needs_reset);
- needs_reset |= k8t890_early_setup_ht();
- printk(BIOS_DEBUG, "%02x", needs_reset);
-
- if (needs_reset) {
- printk(BIOS_DEBUG, "ht reset -\n");
- soft_reset();
- printk(BIOS_DEBUG, "FAILED!\n");
- }
-
- /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
- /* allow LDT STOP asserts */
- vt8237_sb_enable_fid_vid();
-
- enable_fid_change();
- printk(BIOS_DEBUG, "after enable_fid_change\n");
-
- init_fidvid_bsp(bsp_apicid);
-
- /* Stop the APs so we can start them later in init. */
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now. */
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- enable_smbus();
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/broadcom/Kconfig b/src/mainboard/broadcom/Kconfig
deleted file mode 100644
index da78266114..0000000000
--- a/src/mainboard/broadcom/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_BROADCOM
-
-choice
- prompt "Mainboard model"
-
-source "src/mainboard/broadcom/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/broadcom/*/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "Broadcom"
-
-endif # VENDOR_BROADCOM
diff --git a/src/mainboard/broadcom/Kconfig.name b/src/mainboard/broadcom/Kconfig.name
deleted file mode 100644
index 434694fa99..0000000000
--- a/src/mainboard/broadcom/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_BROADCOM
- bool "Broadcom"
diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig
deleted file mode 100644
index ddd2acad36..0000000000
--- a/src/mainboard/broadcom/blast/Kconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-if BOARD_BROADCOM_BLAST
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_940
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_BROADCOM_BCM5780
- select SOUTHBRIDGE_BROADCOM_BCM5785
- select SUPERIO_NSC_PC87417
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_512
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select QRANK_DIMM_SUPPORT
- select DRIVERS_I2C_I2CMUX2
-
-config MAINBOARD_DIR
- string
- default broadcom/blast
-
-config DCACHE_RAM_BASE
- hex
- default 0xcf000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x01000
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "Blast"
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x6
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_BROADCOM_BLAST
diff --git a/src/mainboard/broadcom/blast/Kconfig.name b/src/mainboard/broadcom/blast/Kconfig.name
deleted file mode 100644
index 04e4966200..0000000000
--- a/src/mainboard/broadcom/blast/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_BROADCOM_BLAST
- bool "Blast"
diff --git a/src/mainboard/broadcom/blast/board_info.txt b/src/mainboard/broadcom/blast/board_info.txt
deleted file mode 100644
index b351b8e696..0000000000
--- a/src/mainboard/broadcom/blast/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: eval
diff --git a/src/mainboard/broadcom/blast/cmos.layout b/src/mainboard/broadcom/blast/cmos.layout
deleted file mode 100644
index c4c90f697f..0000000000
--- a/src/mainboard/broadcom/blast/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb
deleted file mode 100644
index 3e02a19a8f..0000000000
--- a/src/mainboard/broadcom/blast/devicetree.cb
+++ /dev/null
@@ -1,122 +0,0 @@
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_940
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x161f 0x3050 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on # northbridge
- # devices on link 0
- chip southbridge/broadcom/bcm5780 # HT2000
- device pci 0.0 on end # PXB 1 0x0130
- device pci 1.0 on # PXB 2 0x0130
- device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
- device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
- end
- device pci 2.0 on end # PCI E 1 #0x0132
- device pci 3.0 on end # PCI E 2
- device pci 4.0 on end # PCI E 3
- device pci 5.0 on end # PCI E 4
- end
- chip southbridge/broadcom/bcm5785 # HT1000
- device pci 0.0 on # HT PXB 0x0036
- device pci d.0 on end # PPBX 0x0104
- device pci e.0 on end # SATA 0x024a
- end
- device pci 1.0 on # Legacy pci main 0x0205
- chip drivers/i2c/i2cmux2 # pca9554 smbus mux
- device i2c 71 on end #0 pca9554 0
- device i2c 71 on end #0 pca9554 1
- device i2c 71 on end #0 pca9554 2
- device i2c 71 on end #0 pca9554 3
- device i2c 71 on end #0 pca9554 4
- device i2c 71 on end #0 pca9554 5
- device i2c 71 on #0 pca9554 6
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 0-1-1
- device i2c 53 on end
- end
- end
- device i2c 71 on #1 pca9554 7
- chip drivers/generic/generic #dimm 1-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 1-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 1-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 1-1-1
- device i2c 53 on end
- end
- end
- end
-
- end
- device pci 1.1 on end # IDE 0x0214
- device pci 1.2 on # LPC 0x0234
- chip superio/nsc/pc87417
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 off # Com 2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Com 1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.4 off end # SWC
- device pnp 2e.5 off end # Mouse
- device pnp 2e.6 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.7 off end # GPIO
- device pnp 2e.f off end # XBUS
- device pnp 2e.10 on #RTC
- io 0x60 = 0x70
- io 0x62 = 0x72
- end
- end
- end
- device pci 1.3 on end # WDTimer 0x0238
- device pci 1.4 on end # XIOAPIC0 0x0235
- device pci 1.5 on end # XIOAPIC1
- device pci 1.6 on end # XIOAPIC2
- device pci 2.0 on end # USB 0x0223
- device pci 2.1 on end # USB
- device pci 2.2 on end # USB
- device pci 4.0 on end # it is in bcm5785_0 bus
- end
- end # device pci 18.0
-
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
-
-
- end #domain
-end
diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c
deleted file mode 100644
index 879178a0d6..0000000000
--- a/src/mainboard/broadcom/blast/get_bus_conf.c
+++ /dev/null
@@ -1,109 +0,0 @@
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_bcm5780[7];
-unsigned char bus_bcm5785_0 = 1;
-unsigned char bus_bcm5785_1 = 8;
-unsigned char bus_bcm5785_1_1 = 9;
-unsigned apicid_bcm5785[3];
-
-unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-unsigned sbdn2;
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
-
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
- sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780
-
- bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_bcm5780[0] = bus_bcm5785_0;
-
- /* bcm5785 */
- dev = dev_find_slot(bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn, 0));
- if (dev) {
- bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- dev = dev_find_slot(bus_bcm5785_1, PCI_DEVFN(0x0d, 0));
- if (dev) {
- bus_bcm5785_1_1 =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:07.0, using defaults\n",
- bus_bcm5785_0);
- }
-
- /* bcm5780 */
- for (i = 1; i < 7; i++) {
- dev =
- dev_find_slot(bus_bcm5780[0], PCI_DEVFN(sbdn2 + i - 1, 0));
- if (dev) {
- bus_bcm5780[i] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:01.0, using defaults\n",
- bus_bcm5780[i]);
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(3);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- for (i = 0; i < 3; i++)
- apicid_bcm5785[i] = apicid_base + i;
-}
diff --git a/src/mainboard/broadcom/blast/irq_tables.c b/src/mainboard/broadcom/blast/irq_tables.c
deleted file mode 100644
index 003a36b384..0000000000
--- a/src/mainboard/broadcom/blast/irq_tables.c
+++ /dev/null
@@ -1,101 +0,0 @@
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
-
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
-
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern unsigned char bus_bcm5780[7];
-extern unsigned char bus_bcm5785_0;
-extern unsigned char bus_bcm5785_1;
-extern unsigned apicid_bcm5785[3];
-
-extern unsigned sbdn2;
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
-
- uint8_t sum = 0;
- int i;
-
- get_bus_conf();
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_bcm5785_0;
- pirq->rtr_devfn = (sysconf.sbdn << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1166;
- pirq->rtr_device = 0x0036;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, bus_bcm5785_0, (sysconf.sbdn << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
deleted file mode 100644
index 98aa2c1f55..0000000000
--- a/src/mainboard/broadcom/blast/mptable.c
+++ /dev/null
@@ -1,138 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-#include <cpu/amd/multicore.h>
-#endif
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_bcm5780[7];
-extern unsigned char bus_bcm5785_0;
-extern unsigned char bus_bcm5785_1;
-extern unsigned char bus_bcm5785_1_1;
-extern unsigned apicid_bcm5785[3];
-
-extern unsigned sbdn2;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int i, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev = NULL;
- struct resource *res;
- for (i = 0; i < 3; i++) {
- dev = dev_find_device(0x1166, 0x0235, dev);
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, apicid_bcm5785[i],
- 0x11,
- res2mmio(res, 0, 0));
- }
- }
- }
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_bcm5785[0], 0);
-
-//IDE
- outb(0x02, 0xc00); outb(0x0e, 0xc01);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE
-
-//SATA
- outb(0x07, 0xc00); outb(0x0f, 0xc01);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e << 2)|0, apicid_bcm5785[0], 0xf);
-
-//USB
- outb(0x01, 0xc00); outb(0x0a, 0xc01);
- for (i = 0; i < 3; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
-
-
-
- /* enable int */
- /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
- {
- struct device *dev;
- dev = dev_find_device(0x1166, 0x0205, 0);
- if(dev) {
- uint32_t dword;
- dword = pci_read_config32(dev, 0x6c);
- dword |= (1 << 4); // enable interrupts
- pci_write_config32(dev, 0x6c, dword);
-
- }
-
- }
-
-//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4 << 2)|i, apicid_bcm5785[1], 2 + (0+i)%4); //
-
-
-//pci slot (on bcm5785)
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4 << 2)|i, apicid_bcm5785[1], i%2); //
-
-
-//onboard ati
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5 << 2)|0, apicid_bcm5785[1], 0x1);
-
-//PCI-X on bcm5780
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4 << 2)|i, apicid_bcm5785[1], 6 + (0+i)%4); //
-
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5 << 2)|i, apicid_bcm5785[1], 6 + (1+i)%4); //
-
-//onboard Broadcom
- for (i = 0; i < 2; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4 << 2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); //
-
-
-// First PCI-E x8
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0 << 2)|i, apicid_bcm5785[1], 0xe); //
-
-
-// Second PCI-E x8
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0 << 2)|i, apicid_bcm5785[1], 0xc); //
-
-
-// Third PCI-E x1
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0 << 2)|i, apicid_bcm5785[1], 0xd); //
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/broadcom/blast/resourcemap.c b/src/mainboard/broadcom/blast/resourcemap.c
deleted file mode 100644
index 43a4904978..0000000000
--- a/src/mainboard/broadcom/blast/resourcemap.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * broadcom blast needs a different resource map
- *
- */
-
-static void setup_blast_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
deleted file mode 100644
index 3743abe1d9..0000000000
--- a/src/mainboard/broadcom/blast/romstage.c
+++ /dev/null
@@ -1,128 +0,0 @@
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/broadcom/bcm5785/early_smbus.c"
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-
-#include <superio/nsc/pc87417/pc87417.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
-#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-
-unsigned get_sbdn(unsigned bus);
-static void memreset_setup(void) { }
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#define SMBUS_HUB 0x71
- unsigned device=(ctrl->channel0[0])>>8;
- smbus_send_byte(SMBUS_HUB, device);
-}
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "southbridge/broadcom/bcm5785/early_setup.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-#define RC0 (6 << 8)
-#define RC1 (7 << 8)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- RC0|DIMM0, RC0|DIMM2, 0, 0,
- RC0|DIMM1, RC0|DIMM3, 0, 0,
- RC1|DIMM0, RC1|DIMM2, 0, 0,
- RC1|DIMM1, RC1|DIMM3, 0, 0,
- };
-
- int needs_reset;
- unsigned bsp_apicid = 0, nodes;
- struct mem_controller ctrl[8];
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- bcm5785_enable_lpc();
- pc87417_enable_dev(RTC_DEV); /* Enable RTC */
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx);
-
- pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- setup_blast_resource_map();
-
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 0));
- dump_pci_device(PCI_DEV(0, 0x19, 0));
-#endif
-
- needs_reset = setup_coherent_ht_domain();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- wait_all_core0_started();
- start_other_cores();
-#endif
- wait_all_aps_started(bsp_apicid);
-
- needs_reset |= ht_setup_chains_x();
-
- bcm5785_early_setup();
-
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- nodes = get_nodes();
- //It's the time to set ctrl now;
- fill_mem_ctrl(nodes, ctrl, spd_addr);
-
- enable_smbus();
-
- memreset_setup();
-
-// init_timer();
-
- sdram_initialize(nodes, ctrl);
-
-#if 0
- print_pci_devices();
- dump_pci_devices();
-#endif
-}
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
deleted file mode 100644
index d6eddff719..0000000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-if BOARD_GIGABYTE_GA_2761GXDK
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_AM2
- select DIMM_DDR2
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_SIS_SIS966
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_ITE_IT8716F
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_512
- select QRANK_DIMM_SUPPORT
- select K8_ALLOCATE_IO_RANGE
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default gigabyte/ga_2761gxdk
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MEM_TRAIN_SEQ
- int
- default 2
-
-config MAINBOARD_PART_NUMBER
- string
- default "GA-2761GXDK"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_GIGABYTE_GA_2761GXDK
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig.name b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig.name
deleted file mode 100644
index 435f1a6afe..0000000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GIGABYTE_GA_2761GXDK
- bool "GA-2761GXDK"
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/board_info.txt b/src/mainboard/gigabyte/ga_2761gxdk/board_info.txt
deleted file mode 100644
index f861f6065a..0000000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Board name: GA-2761GXDK (Churchill)
-Category: desktop
-Board URL: http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gigabyte_dtx-mainboard/
-Release year: 2007
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout b/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout
deleted file mode 100644
index 9e6a9e56f2..0000000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 200Mhz
-8 1 166Mhz
-8 2 133Mhz
-8 3 100Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
deleted file mode 100644
index 6c99032535..0000000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
+++ /dev/null
@@ -1,92 +0,0 @@
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_AM2
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1039 0x1234 inherit
- chip northbridge/amd/amdk8 #mc0
- device pci 18.0 on
- # devices on link 0, link 0 == LDT 0
- chip southbridge/sis/sis966
- device pci 0.0 on end # Northbridge
- device pci 1.0 on # AGP bridge
- device pci 0.0 on end
- end
- device pci 2.0 on # LPC
- chip superio/ite/it8716f
- device pnp 2e.0 off # Floppy (N/A)
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2 (N/A)
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 off # Parallel port (N/A)
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 on # EC
- io 0x60 = 0x290
- io 0x62 = 0x230
- irq 0x70 = 9
- end
- device pnp 2e.5 off # PS/2 keyboard (N/A)
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.6 off # Mouse (N/A)
- irq 0x70 = 12
- end
- device pnp 2e.8 off # MIDI (N/A)
- io 0x60 = 0x300
- irq 0x70 = 10
- end
- device pnp 2e.9 off # GAME (N/A)
- io 0x60 = 0x220
- end
- device pnp 2e.a off end # CIR (N/A)
- end
- end
-
- device pci 2.5 off end # IDE (SiS5513)
- device pci 2.6 off end # Modem (SiS7013)
- device pci 2.7 off end # Audio (SiS7012)
- device pci 3.0 on end # USB (SiS7001,USB1.1)
- device pci 3.1 on end # USB (SiS7001,USB1.1)
- device pci 3.3 on end # USB (SiS7002,USB2.0)
- device pci 4.0 on end # NIC (SiS191)
- device pci 5.0 on end # SATA (SiS1183,Native Mode)
- device pci 6.0 on end # PCI-e x1
- device pci 7.0 on end # PCI-e x1
- device pci a.0 off end
- device pci b.0 off end
- device pci c.0 off end
- device pci d.0 off end
- device pci e.0 off end
- device pci f.0 off end # HD Audio (SiS7502)
-
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- end
- end # device pci 18.0
- device pci 18.0 on end # Link 1
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end # mc0
-
- end # PCI domain
-
-end #root_complex
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
deleted file mode 100644
index 75f6b9ffc0..0000000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
- * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_sis966[8]; //1
-unsigned apicid_sis966;
-
-unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
- unsigned sbdn;
-
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- sbdn = sysconf.sbdn;
-
- for (i = 0; i < 8; i++) {
- bus_sis966[i] = 0;
- }
-
- bus_sis966[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* SIS966 */
- dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn + 0x06, 0));
- if (dev) {
- bus_sis966[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_sis966[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_sis966[2]++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x06);
-
- bus_sis966[1] = 2;
- bus_sis966[2] = 3;
- }
-
- for (i = 2; i < 8; i++) {
- dev =
- dev_find_slot(bus_sis966[0],
- PCI_DEVFN(sbdn + 0x0a + i - 2, 0));
- if (dev) {
- bus_sis966[i] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_sis966 = apicid_base + 0;
-
-}
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
deleted file mode 100644
index d2bc1824be..0000000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
- * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern unsigned char bus_sis966[8]; //1
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
- unsigned sbdn;
-
- uint8_t sum = 0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = 0;
- pirq->rtr_devfn = PCI_DEVFN(2, 0);
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = PCI_VENDOR_ID_SIS;
- pirq->rtr_device = PCI_DEVICE_ID_SIS_SIS966_LPC;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- write_pirq_info(pirq_info, 0, PCI_DEVFN(2, 0), 0x1, 0xdef8, 0x2, 0xdef8,
- 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- {
- struct device *dev;
- dev = dev_find_slot(0, PCI_DEVFN(2, 0));
- if (dev) {
- /* initialize PCI interupts - these assignments depend
- on the PCB routing of PINTA-D
-
- PINTA = IRQ10
- PINTB = IRQ11
- PINTC = NA
- PINTD = IRQ10
- PINTE = IRQ11
- PINTF = IRQ5
- PINTG = NA
- PINTH = IRQ7
-
- */
- uint8_t reg[8] = {
- 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63
- };
- uint8_t irq[8] = {
- 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07
- };
-
- for (i = 0; i < 8; i++)
- pci_write_config8(dev, reg[i], irq[i]);
- }
-
- printk(BIOS_DEBUG, "Setting Onboard SiS Southbridge\n");
-
- dev = dev_find_slot(0, PCI_DEVFN(2, 5)); // 5513 (IDE)
- pci_write_config8(dev, 0x3C, 0x0A);
- dev = dev_find_slot(0, PCI_DEVFN(3, 0)); // USB 1.1
- pci_write_config8(dev, 0x3C, 0x0B);
- dev = dev_find_slot(0, PCI_DEVFN(3, 1)); // USB 1.1
- pci_write_config8(dev, 0x3C, 0x05);
- dev = dev_find_slot(0, PCI_DEVFN(3, 3)); // USB 2.0
- pci_write_config8(dev, 0x3C, 0x07);
- dev = dev_find_slot(0, PCI_DEVFN(4, 0)); // 191 (LAN)
- pci_write_config8(dev, 0x3C, 0x0A);
- dev = dev_find_slot(0, PCI_DEVFN(5, 0)); // 1183 (SATA)
- pci_write_config8(dev, 0x3C, 0x0B);
- dev = dev_find_slot(0, PCI_DEVFN(6, 0)); // PCI-E
- pci_write_config8(dev, 0x3C, 0x0A);
- dev = dev_find_slot(0, PCI_DEVFN(7, 0)); // PCI-E
- pci_write_config8(dev, 0x3C, 0x0A);
- dev = dev_find_slot(0, PCI_DEVFN(15, 0)); // Azalia
- pci_write_config8(dev, 0x3C, 0x05);
- }
-
- printk(BIOS_DEBUG, "pirq routing table, size=%d\n", pirq->size);
- for (i = 0; i < pirq->size; i += 4)
- printk(BIOS_DEBUG, "%.2x%.2x%.2x%.2x\n", v[i + 3], v[i + 2],
- v[i + 1], v[i]);
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
deleted file mode 100644
index ae59264cba..0000000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
- * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_sis966[8]; //1
-
-extern unsigned apicid_sis966;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned sbdn;
- int i, j, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_sis966, 0x11,
- res2mmio(res, 0, 0));
- }
-
- dword = 0x43c6c643;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x81001a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0xd0001202;
- pci_write_config32(dev, 0x84, dword);
-
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sis966, 0);
-
-/* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin))
-
- PCI_INT(0, sbdn+1, 1, 0xa);
- PCI_INT(0, sbdn+2, 0, 0x16); // 22
- PCI_INT(0, sbdn+2, 1, 0x17); // 23
- PCI_INT(0, sbdn+6, 1, 0x17); // 23
- PCI_INT(0, sbdn+5, 0, 0x14); // 20
- PCI_INT(0, sbdn+5, 1, 0x17); // 23
- PCI_INT(0, sbdn+5, 2, 0x15); // 21
- PCI_INT(0, sbdn+8, 0, 0x16); // 22
-
- for (j = 7; j >= 2; j--) {
- if (!bus_sis966[j])
- continue;
- for (i = 0; i < 4; i++)
- PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4);
- }
-
- for (j = 0; j < 2; j++)
- for (i = 0; i < 4; i++)
- PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4);
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
deleted file mode 100644
index 35c54c8344..0000000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
deleted file mode 100644
index b014a9fa88..0000000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
- * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <southbridge/sis/sis966/sis966.h>
-#include "southbridge/sis/sis966/early_smbus.c"
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8716f/it8716f.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/sis/sis966/early_ctrl.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
-#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SIS966_NUM 1
-#define SIS966_USE_NIC 1
-#define SIS966_USE_AZA 1
-
-#define SIS966_PCI_E_X_0 0
-
-#define SIS966_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
-
-#include <southbridge/sis/sis966/early_setup_ss.h>
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset = 0;
- unsigned bsp_apicid = 0;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- setup_mb_resource_map();
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
- setup_coherent_ht_domain(); // routing table and start other core0
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-#endif
-
- needs_reset |= optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
-
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- sis_init_stage1();
- enable_smbus();
-
- //do we need apci timer, tsc...., only debug need it for better output
- /* all ap stopped? */
-// init_timer(); // Need to use TMICT to synchronize FID/VID
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
- sis_init_stage2();
-}
diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig
deleted file mode 100644
index 28473776bb..0000000000
--- a/src/mainboard/gigabyte/m57sli/Kconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-if BOARD_GIGABYTE_M57SLI
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_AM2
- select DIMM_DDR2
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_MCP55
- select HT_CHAIN_DISTRIBUTE
- select MCP55_USE_NIC
- select MCP55_USE_AZA
- select SUPERIO_ITE_IT8716F
- select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_CMOS_DEFAULT
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_512
- select QRANK_DIMM_SUPPORT
- select K8_ALLOCATE_IO_RANGE
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default gigabyte/m57sli
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MEM_TRAIN_SEQ
- int
- default 2
-
-config MAINBOARD_PART_NUMBER
- string
- default "GA-M57SLI-S4"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-config MCP55_PCI_E_X_0
- int
- default 0
-
-endif # BOARD_GIGABYTE_M57SLI
diff --git a/src/mainboard/gigabyte/m57sli/Kconfig.name b/src/mainboard/gigabyte/m57sli/Kconfig.name
deleted file mode 100644
index 32a5470fb8..0000000000
--- a/src/mainboard/gigabyte/m57sli/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GIGABYTE_M57SLI
- bool "GA-M57SLI-S4"
diff --git a/src/mainboard/gigabyte/m57sli/Makefile.inc b/src/mainboard/gigabyte/m57sli/Makefile.inc
deleted file mode 100644
index c18f22441a..0000000000
--- a/src/mainboard/gigabyte/m57sli/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) += fanctl.c
diff --git a/src/mainboard/gigabyte/m57sli/acpi_tables.c b/src/mainboard/gigabyte/m57sli/acpi_tables.c
deleted file mode 100644
index 72b82f5f4d..0000000000
--- a/src/mainboard/gigabyte/m57sli/acpi_tables.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci_ids.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-#include <device/pci.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
- extern unsigned char bus_mcp55[8];
- extern unsigned apicid_mcp55;
-
- unsigned sbdn;
- struct resource *res;
- struct device *dev;
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- apicid_mcp55, res->base, 0);
- }
- }
-
- /* Write NB IOAPIC. */
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x12,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- apicid_mcp55++, res->base, gsi_base);
- }
- }
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/gigabyte/m57sli/board_info.txt b/src/mainboard/gigabyte/m57sli/board_info.txt
deleted file mode 100644
index 33c36557c2..0000000000
--- a/src/mainboard/gigabyte/m57sli/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=2287#ov
-ROM socketed: n
-Flashrom support: y
-Vendor cooperation score: 3
-Vendor cooperation page: Gigabyte m57sli Vendor Cooperation Score
-Release year: 2006
diff --git a/src/mainboard/gigabyte/m57sli/cmos.default b/src/mainboard/gigabyte/m57sli/cmos.default
deleted file mode 100644
index 62068cf4a7..0000000000
--- a/src/mainboard/gigabyte/m57sli/cmos.default
+++ /dev/null
@@ -1,9 +0,0 @@
-debug_level = Spew
-multi_core = Enable
-slow_cpu = off
-max_mem_clock = 200Mhz
-ECC_memory = Enable
-hw_scrubber = Enable
-interleave_chip_selects = Enable
-power_on_after_fail = Disable
-boot_option = Fallback
diff --git a/src/mainboard/gigabyte/m57sli/cmos.layout b/src/mainboard/gigabyte/m57sli/cmos.layout
deleted file mode 100644
index 9e6a9e56f2..0000000000
--- a/src/mainboard/gigabyte/m57sli/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 200Mhz
-8 1 166Mhz
-8 2 133Mhz
-8 3 100Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/gigabyte/m57sli/devicetree.cb b/src/mainboard/gigabyte/m57sli/devicetree.cb
deleted file mode 100644
index efbf76e896..0000000000
--- a/src/mainboard/gigabyte/m57sli/devicetree.cb
+++ /dev/null
@@ -1,154 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_AM2 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
-end
-device domain 0 on # PCI domain
- subsystemid 0x1022 0x2b80 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/ite/it8716f # Super I/O
- device pnp 2e.0 on # Floppy and any LDN
- # Watchdog from CLKIN (24 MHz)
- irq 0x23 = 0x11
- # Serial Flash (SPI only)
- # 0x24 = 0x1a
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 on # Embedded controller
- io 0x60 = 0x290
- io 0x62 = 0x230
- irq 0x70 = 9
- end
- device pnp 2e.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.6 on # PS/2 mouse
- irq 0x70 = 12
- end
- device pnp 2e.7 on # GPIO, SPI flash
- # Pin 84 is not GP10
- irq 0x25 = 0x0
- # Pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
- irq 0x26 = 0x43
- # Pin 13 is GP35
- irq 0x27 = 0x20
- # Pin 70 is not GP46
- # irq 0x28 = 0x0
- # Pin 6,3,128,127,126 is GP63,64,65,66,67
- irq 0x29 = 0x81
- # Enable FAN_CTL/FAN_TAC set to 5 (pin 21, 23),
- # enable FAN_CTL/FAN_TAC set to 4 (pin 20, 22),
- # pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal
- # voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal
- # voltage divider for VCC5V
- # irq 0x2c = 0x1f
- # Simple I/O base
- io 0x62 = 0x800
- # Serial Flash I/O (SPI only)
- io 0x64 = 0x820
- # Watchdog force timeout (parallel flash only)
- # irq 0x71 = 0x1
- # No WDT interrupt
- irq 0x72 = 0x0
- # GPIO pin set 1 disable internal pullup
- irq 0xb8 = 0x0
- # GPIO pin set 5 enable internal pullup
- irq 0xbc = 0x01
- # SIO pin set 1 alternate function
- # irq 0xc0 = 0x0
- # SIO pin set 2 mixed function
- irq 0xc1 = 0x43
- # SIO pin set 3 mixed function
- irq 0xc2 = 0x20
- # SIO pin set 4 alternate function
- # irq 0xc3 = 0x0
- # SIO pin set 1 input mode
- # irq 0xc8 = 0x0
- # SIO pin set 2 input mode
- irq 0xc9 = 0x0
- # SIO pin set 4 input mode
- # irq 0xcb = 0x0
- # Generate SMI# on EC IRQ
- # irq 0xf0 = 0x10
- # SMI# level trigger
- # irq 0xf1 = 0x40
- # HWMON alert beep pin location
- irq 0xf6 = 0x28
- end
- device pnp 2e.8 off # MIDI
- io 0x60 = 0x300
- irq 0x70 = 10
- end
- device pnp 2e.9 off # Game port
- io 0x60 = 0x220
- end
- device pnp 2e.a off end # Consumer IR
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
- device pci 6.0 on end # PCI
- device pci 6.1 on end # AUDIO
- device pci 8.0 on end # NIC
- device pci 9.0 off end # N/A
- device pci a.0 on end # PCI E 5
- device pci b.0 on end # PCI E 4
- device pci c.0 on end # PCI E 3
- device pci d.0 on end # PCI E 2
- device pci e.0 on end # PCI E 1
- device pci f.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.0 on end # Link 1
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/gigabyte/m57sli/dsdt.asl b/src/mainboard/gigabyte/m57sli/dsdt.asl
deleted file mode 100644
index c53f36a47e..0000000000
--- a/src/mainboard/gigabyte/m57sli/dsdt.asl
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0A }, /* 0x1 - 00:01.1 - IRQ 10 - SMBus */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x16 }, /* 0x2 - 00:02.0 - IRQ 22 - USB */
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x17 }, /* 0x2 - 00:01.1 - IRQ 23 - USB */
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x15 }, /* 0x4 - 00:04.0 - IRQ 21 - IDE */
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x14 }, /* 0x5 - 00:05.0 - IRQ 20 - SATA */
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x15 }, /* 0x5 - 00:05.1 - IRQ 21 - SATA */
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, /* 0x5 - 00:05.2 - IRQ 22 - SATA */
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x17 }, /* 0x6 - 00:06.1 - IRQ 23 - HD Audio */
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }, /* 0x8 - 00:08.0 - IRQ 20 - GBit Ethernet */
- })
-
- Device (PEBF) /* PCI-E Bridge F */
- {
- Name (_ADR, 0x000F0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x07)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
- })
- }
-
- Device (PEBE) /* PCI-E Bridge E */
- {
- Name (_ADR, 0x000E0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x06)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
- })
- }
-
- Device (PEBD) /* PCI-E Bridge D */
- {
- Name (_ADR, 0x000D0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x05)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x12 },
- })
- }
-
- Device (PEBC) /* PCI-E Bridge C */
- {
- Name (_ADR, 0x000C0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x04)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
- })
- }
-
- Device (PEBB) /* PCI-E Bridge B */
- {
- Name (_ADR, 0x000B0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x03)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
- })
- }
-
- Device (PEBA) /* PCI-E Bridge A */
- {
- Name (_ADR, 0x000A0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
- })
- }
-
- Device (PCID) /* PCI Device */
- {
- Name (_ADR, 0x00060000)
- Name (_UID, 0x00)
- Name (_BBN, 0x01)
- Name (_PRT, Package () {
- Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 },
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x11 },
- Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x13 }, /* PCI slot 1 */
- Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x11 },
- Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x12 },
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x10 }, /* PCI slot 2 */
- Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x11 },
- Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x10 },
- Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x12 }, /* FireWire */
- Package (0x04) { 0x000AFFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x000AFFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x000AFFFF, 0x03, 0x00, 0x11 },
- })
- }
- }
-
- Device (ISA) {
- Name (_ADR, 0x000010000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP0, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP0)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP1, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {12}
- })
- Return (TMP1)
- }
- }
-
- /* PS/2 floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
- IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- /* Parallel Port */
- Device (LPT1)
- {
- Name (_HID, EisaId ("PNP0400"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF1, ResourceTemplate () {
- IO (Decode16, 0x0378, 0x0378, 0x01, 0x08)
- IRQNoFlags () {7}
- })
- Return (BUF1)
- }
- }
- /* Parallel Port ECP */
- Device (ECP1)
- {
- Name (_HID, EisaId ("PNP0401"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF1, ResourceTemplate () {
- IO (Decode16, 0x0378, 0x0378, 0x01, 0x04)
- IO (Decode16, 0x0778, 0x0778, 0x01, 0x04)
- IRQNoFlags() {7}
- DMA (Compatibility, NotBusMaster, Transfer8) {0,1,3}
- })
- Return (BUF1)
- }
- }
- }
- }
-}
diff --git a/src/mainboard/gigabyte/m57sli/fanctl.c b/src/mainboard/gigabyte/m57sli/fanctl.c
deleted file mode 100644
index cc0cdcac23..0000000000
--- a/src/mainboard/gigabyte/m57sli/fanctl.c
+++ /dev/null
@@ -1,81 +0,0 @@
-#include <arch/io.h>
-#include <stdlib.h>
-#include <superio/ite/it8716f/it8716f.h>
-
-static void write_index(uint16_t port_base, uint8_t reg, uint8_t value)
-{
- outb(reg, port_base);
- outb(value, port_base + 1);
-}
-
-static const struct {
- uint8_t index, value;
-} sequence[]= {
- /* Make sure we can monitor, and enable SMI# interrupt output */
- { 0x00, 0x13},
- /* Disable fan interrupt status bits for SMI# */
- { 0x04, 0x37},
- /* Disable VIN interrupt status bits for SMI# */
- { 0x05, 0xff},
- /* Disable fan interrupt status bits for IRQ */
- { 0x07, 0x37},
- /* Disable VIN interrupt status bits for IRQ */
- { 0x08, 0xff},
- /* Disable external sensor interrupt */
- { 0x09, 0x87},
- /* Enable 16 bit counter divisors */
- { 0x0c, 0x07},
- /* Set FAN_CTL control register (0x14) polarity to high, and
- activate fans 1, 2 and 3. */
- { 0x14, 0xd7},
- /* set the correct sensor types 1,2 thermistor; 3 diode */
- { 0x51, 0x1c},
- /* set the 'zero' voltage for diode type sensor 3 */
- { 0x5c, 0x80},
-// { 0x56, 0xe5},
-// { 0x57, 0xe5},
- { 0x59, 0xec},
- { 0x5c, 0x00},
- /* fan1 (controlled by temp3) control parameters */
- /* fan off limit */
- { 0x60, 0xff},
- /* fan start limit */
- { 0x61, 0x14},
- /* ???? */
-// { 0x62, 0x00},
- /* start PWM */
- { 0x63, 0x27},
- /* smooth and slope PWM */
- { 0x64, 0x90},
- /* direct-down and interval */
- { 0x65, 0x03},
- /* temperature limit of fan stop for fan3 (automatic) */
- { 0x70, 0xff},
- /* temperature limit of fan start for fan3 (automatic) */
- { 0x71, 0x14},
- /* Set PWM start & slope for fan3 */
- { 0x73, 0x20},
- /* Initialize PWM automatic mode slope values for fan3 */
- { 0x74, 0x90},
- /* set smartguardian temperature interval for fan3 */
- { 0x75, 0x03},
- /* fan1 auto controlled by temp3 */
- { 0x15, 0x82},
- /* fan2 auto controlled by temp3 */
- { 0x16, 0x82},
- /* fan3 auto controlled by temp3 */
- { 0x17, 0x82},
- /* all fans enable, fan1 ctl smart */
- { 0x13, 0x77}
-};
-
-/*
- * Called from superio.c
- */
-void init_ec(uint16_t base)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(sequence); i++) {
- write_index(base, sequence[i].index, sequence[i].value);
- }
-}
diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c
deleted file mode 100644
index 5ef79627b4..0000000000
--- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_mcp55[8]; //1
-unsigned apicid_mcp55;
-
-unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
- unsigned sbdn;
-
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- sbdn = sysconf.sbdn;
-
- for (i = 0; i < 8; i++) {
- bus_mcp55[i] = 0;
- }
-
- bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* MCP55 */
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0));
- if (dev) {
- bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_mcp55[2]++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x06);
-
- bus_mcp55[1] = 2;
- bus_mcp55[2] = 3;
- }
-
- for (i = 2; i < 8; i++) {
- dev =
- dev_find_slot(bus_mcp55[0],
- PCI_DEVFN(sbdn + 0x0a + i - 2, 0));
- if (dev) {
- bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_mcp55 = apicid_base + 0;
-
-}
diff --git a/src/mainboard/gigabyte/m57sli/hda_verb.c b/src/mainboard/gigabyte/m57sli/hda_verb.c
deleted file mode 100644
index 072a306131..0000000000
--- a/src/mainboard/gigabyte/m57sli/hda_verb.c
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[0] = {};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/m57sli/irq_tables.c b/src/mainboard/gigabyte/m57sli/irq_tables.c
deleted file mode 100644
index 4d42d7495c..0000000000
--- a/src/mainboard/gigabyte/m57sli/irq_tables.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern unsigned char bus_mcp55[8]; //1
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
- unsigned sbdn;
-
- uint8_t sum = 0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_mcp55[0];
- pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x0370;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
deleted file mode 100644
index e9ffe52b73..0000000000
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_mcp55[8]; //1
-
-extern unsigned apicid_mcp55;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned sbdn;
- int i, j, k, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev;
- struct resource *res;
-
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
- }
- /* set up the interrupt registers of mcp55 */
- pci_write_config32(dev, 0x7c, 0xc643c643);
- pci_write_config32(dev, 0x80, 0x8da01009);
- pci_write_config32(dev, 0x84, 0x200018d2);
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
-
-/* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
- bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))
-
- PCI_INT(0,sbdn+1,1, 10); /* SMBus */
- PCI_INT(0,sbdn+2,0, 22); /* USB */
- PCI_INT(0,sbdn+2,1, 23); /* USB */
- PCI_INT(0,sbdn+4,0, 21); /* IDE */
- PCI_INT(0,sbdn+5,0, 20); /* SATA */
- PCI_INT(0,sbdn+5,1, 21); /* SATA */
- PCI_INT(0,sbdn+5,2, 22); /* SATA */
- PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
- PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */
-
- /* The PCIe slots, each on its own bus */
- k = 1;
- for(i = 0; i < 4; i++){
- for(j = 7; j > 1; j--){
- if(k > 3) k = 0;
- PCI_INT(j,0,i, 16+k);
- k++;
- }
- k--;
- }
-
- /* On bus 1: the PCI bus slots...
- * physical PCI slots are j = 7,8
- * FireWire is j = 10
- */
- k = 2;
- for(i = 0; i < 4; i++){
- for(j = 6; j < 11; j++){
- if(k > 3) k = 0;
- PCI_INT(1,j,i, 16+k);
- k++;
- }
- }
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/gigabyte/m57sli/resourcemap.c b/src/mainboard/gigabyte/m57sli/resourcemap.c
deleted file mode 100644
index 35c54c8344..0000000000
--- a/src/mainboard/gigabyte/m57sli/resourcemap.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
deleted file mode 100644
index 3261c5dcb8..0000000000
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <southbridge/nvidia/mcp55/mcp55.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8716f/it8716f.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
-#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
-
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#define MCP55_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
-
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset = 0;
- unsigned bsp_apicid = 0;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
-#if 0
- uint8_t tmp = 0;
- pnp_enter_ext_func_mode(SERIAL_DEV);
- /* The following line will set CLKIN to 24 MHz, external */
- pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
- tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
- /* Is serial flash enabled? Then enable writing to serial flash. */
- if (tmp & 0x0e) {
- pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
- pnp_set_logical_device(GPIO_DEV);
- /* Set Serial Flash interface to 0x0820 */
- pnp_write_config(GPIO_DEV, 0x64, 0x08);
- pnp_write_config(GPIO_DEV, 0x65, 0x20);
- }
- it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
- pnp_exit_ext_func_mode(SERIAL_DEV);
-#endif
- ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- setup_mb_resource_map();
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
- setup_coherent_ht_domain(); // routing table and start other core0
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-#endif
-
- init_timer(); // Need to use TMICT to synchronize FID/VID
-
- needs_reset |= optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= mcp55_early_setup_x();
-
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
- /* all ap stopped? */
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig
deleted file mode 100644
index 74ce0e726c..0000000000
--- a/src/mainboard/hp/dl145_g1/Kconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-if BOARD_HP_DL145_G1
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_940
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_AMD8131
- select SOUTHBRIDGE_AMD_AMD8111
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_WINBOND_W83627HF
- select HAVE_HARD_RESET
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_512
- select SET_FIDVID
- select SET_FIDVID_DEBUG
- select RAMINIT_SYSINFO
-# select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select QRANK_DIMM_SUPPORT
- select DRIVERS_I2C_I2CMUX
- select HAVE_ACPI_TABLES
-
-config MAINBOARD_DIR
- string
- default hp/dl145_g1
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "ProLiant DL145 G1"
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x6
-
-config IRQ_SLOT_COUNT
- int
- default 9
-
-endif # BOARD_HP_DL145_G1
diff --git a/src/mainboard/hp/dl145_g1/Kconfig.name b/src/mainboard/hp/dl145_g1/Kconfig.name
deleted file mode 100644
index 2840287608..0000000000
--- a/src/mainboard/hp/dl145_g1/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_HP_DL145_G1
- bool "ProLiant DL145 G1"
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
deleted file mode 100644
index 8de268bd15..0000000000
--- a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
+++ /dev/null
@@ -1,617 +0,0 @@
-/*
- * Copyright 2005 AMD
- * Copyright (C) 2011, 2014 Oskar Enoksson <enok@lysator.liu.se>
- */
-//AMD8111
-// APIC version of the interrupt routing table
-Name (APIC, Package (0x04) {
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
-})
-// PIC version of the interrupt routing table
-Name (PICM, Package (0x04) {
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
-})
-Name (DNCG, Ones)
-Method (_PRT, 0, NotSerialized) {
- If (LEqual (^DNCG, Ones)) {
- Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
- // Update the Device Number according to SBDN
- Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
-
- Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
-
- Store (0x00, ^DNCG)
- }
-
- If (LNot (PICF)) {
- Return (PICM)
- } Else {
- Return (APIC)
- }
-}
-
-// AMD8111 System Management I/O Mapped Registers (PMxx)
-OperationRegion (PMIO, SystemIO, PMBS, 0xDF)
-Field (PMIO, ByteAcc, NoLock, Preserve) {
- Offset (0x1E),
- SWSM, 8, // Software SMI Trigger (sets GSTS)
- Offset (0x28),
- GSTS, 16, // Global STatuS
- GNBL, 16, // Global SMI enable
- Offset (0x30),
- STMC, 5, // Miscellaneous SMI Status
- Offset (0x32),
- ENMC, 5, // Miscellaneous SMI Enable
- Offset (0x44),
- STC0, 9, // TCO Status 1
- Offset (0x46),
- STC1, 4, // TCO Status 2
- Offset (0xA8),
- STHW, 20 // Device monitor SMI Interrupt Enable
-}
-Device (HPET) {
- Name (HPT, 0x00)
- Name (_HID, EisaId ("PNP0103"))
- Name (_UID, 0x00)
- Method (_STA, 0, NotSerialized) {
- Return (0x0F)
- }
- Method (_CRS, 0, Serialized) {
- Name (BUF0, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
- })
- Return (BUF0)
- }
-}
-#include "amd8111_pic.asl"
-#include "amd8111_isa.asl"
-
-Device (TP2P) {
- // 8111 P2P and it should 0x00030000 when 8131 present
- Method (_ADR, 0, NotSerialized) {
- Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
- }
- Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
- // result :
- // [0] Bit index into GPEx_EN in the GPE block described by FADT.
- // [1] The lowest power state from which the system can be awakened.
- //If (CondRefOf (\_S3)) {
- // Return (Package (0x02) { 0x08, 0x03 })
- //} Else {
- Return (Package (0x02) { 0x08, 0x01 })
- //}
- }
- Device (ETHR) {
- Name (_ADR, 0x00010000)
- Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
- //If (CondRefOf (\_S3)) {
- // Return (Package (0x02) { 0x08, 0x03 })
- //} Else {
- Return (Package (0x02) { 0x08, 0x01 })
- //}
- }
- }
- Device (USB0) {
- Name (_ADR, 0x00000000)
- Method (_PSW, 1, NotSerialized) { // Power State Wake
- And (GNBL, 0x7FFF, GNBL)
- }
- Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
- //If (CondRefOf (\_S3)) {
- // Return (Package (0x02) { 0x0F, 0x03 })
- //} Else {
- Return (Package (0x02) { 0x0F, 0x01 })
- //}
- }
- }
- Device (USB1) {
- Name (_ADR, 0x00000001)
- Method (_PSW, 1, NotSerialized) { // Power State Wake
- And (GNBL, 0x7FFF, GNBL)
- }
- Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
- //If (CondRefOf (\_S3)) {
- // Return (Package (0x02) { 0x0F, 0x03 })
- //} Else {
- Return (Package (0x02) { 0x0F, 0x01 })
- //}
- }
- }
- Name (APIC, Package (0x0C) {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
- })
- Name (PICM, Package (0x0C) {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 6
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 5
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
- })
- Method (_PRT, 0, NotSerialized) {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
-}
-Device (IDE0) {
- Method (_ADR, 0, NotSerialized) {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010001))
- }
- Name (REGF, 0x01)
- Method (_REG, 2, NotSerialized) {
- If (LEqual (Arg0, 0x02)) {
- Store (Arg1, REGF)
- }
- }
- OperationRegion (BAR0, PCI_Config, 0x00, 0x60)
- Field (BAR0, ByteAcc, NoLock, Preserve) {
- Offset (0x40), // EIDE Controller Configuration Register
- SCEN, 1, // Secondary Channel Enable
- PCEN, 1, // Primary Channel Enable
- , 10,
- SPWB, 1, // Secondary Port posted-write buffer for PIO modes enable
- SRPB, 1, // RW (controls nothing)
- PPWB, 1, // Primary Port posted-write buffer for PIO modes enable
- PRPB, 1, // RW (controls nothing)
- PM80, 1, // High-speed 80-pin cable enable Primary Master
- PS80, 1, // High-speed 80-pin cable enable Primary Slave
- SM80, 1, // High-speed 80-pin cable enable Secondary Master
- SS80, 1, // High-speed 80-pin cable enable Secondary Slave
- , 4, // RW (controls nothing)
- Offset (0x48),
- SSRT, 4, //
- SSPW, 4, //
- SMRT, 4, //
- SMPW, 4,
- PSRT, 4,
- PSPW, 4,
- PMRT, 4,
- PMPW, 4,
- SSAD, 2,
- SMAD, 2,
- PSAD, 2,
- PMAD, 2,
- Offset (0x4E),
- SXRT, 4,
- SXPW, 4,
- PXRT, 4,
- PXPW, 4,
- SSUD, 8,
- SMUD, 8,
- PSUD, 8,
- PMUD, 8,
- PPDN, 1,
- PPDS, 1,
- , 2,
- SPDN, 1,
- SPDS, 1
- }
- Name (TIM0, Package (0x06) {
- Package (0x05) {
- 0x78,
- 0xB4,
- 0xF0,
- 0x0186,
- 0x0258
- },
- Package (0x07) {
- 0x78,
- 0x5A,
- 0x3C,
- 0x2D,
- 0x1E,
- 0x14,
- 0x0F
- },
- Package (0x08) {
- 0x04,
- 0x03,
- 0x02,
- 0x01,
- 0x00,
- 0x00,
- 0x00,
- 0x00
- },
- Package (0x03) {
- 0x02,
- 0x01,
- 0x00
- },
- Package (0x05) {
- 0x20,
- 0x22,
- 0x42,
- 0x65,
- 0xA8
- },
- Package (0x07) {
- 0xC2,
- 0xC1,
- 0xC0,
- 0xC4,
- 0xC5,
- 0xC6,
- 0xC7
- }
- })
- Name (TMD0, Buffer (0x14) {})
- CreateDWordField (TMD0, 0x00, PIO0)
- CreateDWordField (TMD0, 0x04, DMA0)
- CreateDWordField (TMD0, 0x08, PIO1)
- CreateDWordField (TMD0, 0x0C, DMA1)
- CreateDWordField (TMD0, 0x10, CHNF)
- Device (CHN0) {
- Name (_ADR, 0x00)
- Method (_STA, 0, NotSerialized) {
- If (PCEN) { Return (0x0F) }
- Else { Return (0x09) }
- }
- Method (_GTM, 0, NotSerialized) {
- Return (GTM (PMPW, PMRT, PSPW, PSRT, PMUD, PSUD))
- }
- Method (_STM, 3, NotSerialized) {
- Store (Arg0, TMD0)
- Store (STM (), Local0)
- And (Local0, 0xFF, PSUD)
- ShiftRight (Local0, 0x08, Local0)
- And (Local0, 0xFF, PMUD)
- ShiftRight (Local0, 0x08, Local0)
- And (Local0, 0x0F, PSRT)
- ShiftRight (Local0, 0x04, Local0)
- And (Local0, 0x0F, PSPW)
- ShiftRight (Local0, 0x04, Local0)
- And (Local0, 0x0F, PMRT)
- ShiftRight (Local0, 0x04, Local0)
- And (Local0, 0x0F, PMPW)
- Store (GTF (0x00, Arg1), ATA0)
- Store (GTF (0x01, Arg2), ATA1)
- }
- Device (DRV0) {
- Name (_ADR, 0x00)
- Method (_GTF, 0, NotSerialized) {
- Return (RATA (ATA0))
- }
- }
- Device (DRV1) {
- Name (_ADR, 0x01)
- Method (_GTF, 0, NotSerialized) {
- Return (RATA (ATA1))
- }
- }
- }
- Device (CHN1) {
- Name (_ADR, 0x01)
- Method (_STA, 0, NotSerialized) {
- If (SCEN) { Return (0x0F) }
- Else { Return (0x09) }
- }
- Method (_GTM, 0, NotSerialized) {
- Return (GTM (SMPW, SMRT, SSPW, SSRT, SMUD, SSUD))
- }
- Method (_STM, 3, NotSerialized) {
- Store (Arg0, TMD0)
- Store (STM (), Local0)
- And (Local0, 0xFF, SSUD)
- ShiftRight (Local0, 0x08, Local0)
- And (Local0, 0xFF, SMUD)
- ShiftRight (Local0, 0x08, Local0)
- And (Local0, 0x0F, SSRT)
- ShiftRight (Local0, 0x04, Local0)
- And (Local0, 0x0F, SSPW)
- ShiftRight (Local0, 0x04, Local0)
- And (Local0, 0x0F, SMRT)
- ShiftRight (Local0, 0x04, Local0)
- And (Local0, 0x0F, SMPW)
- Store (GTF (0x00, Arg1), ATA2)
- Store (GTF (0x01, Arg2), ATA3)
- }
- Device (DRV0) {
- Name (_ADR, 0x00)
- Method (_GTF, 0, NotSerialized) {
- Return (RATA (ATA2))
- }
- }
- Device (DRV1) {
- Name (_ADR, 0x01)
- Method (_GTF, 0, NotSerialized) {
- Return (RATA (ATA3))
- }
- }
- }
- Method (GTM, 6, Serialized) {
- Store (Ones, PIO0)
- Store (Ones, PIO1)
- Store (Ones, DMA0)
- Store (Ones, DMA1)
- Store (0x1A, CHNF)
- If (REGF) {}
- Else { Return (TMD0) }
- Add (Arg0, Arg1, Local0)
- Add (Local0, 0x02, Local0)
- Multiply (Local0, 0x1E, PIO0)
- Add (Arg2, Arg3, Local0)
- Add (Local0, 0x02, Local0)
- Multiply (Local0, 0x1E, PIO1)
- If (And (Arg4, 0x40)) {
- Or (CHNF, 0x01, CHNF)
- And (Arg4, 0x07, Local0)
- If (LLess (Local0, 0x04)) {
- Add (Local0, 0x02, Local0)
- Multiply (Local0, 0x1E, DMA0)
- } Else {
- If (LEqual (Local0, 0x04)) {
- Store (0x2D, DMA0)
- } Else {
- If (LEqual (Local0, 0x05)) {
- Store (0x1E, DMA0)
- } Else {
- If (LEqual (Local0, 0x06)) {
- Store (0x14, DMA0)
- } Else {
- If (LEqual (Local0, 0x07)) {
- Store (0x0F, DMA0)
- } Else {
- Store (PIO0, DMA0)
- }
- }
- }
- }
- }
- } Else {
- Store (PIO0, DMA0)
- }
- If (And (Arg5, 0x40)) {
- Or (CHNF, 0x04, CHNF)
- And (Arg5, 0x07, Local0)
- If (LLess (Local0, 0x04)) {
- Add (Local0, 0x02, Local0)
- Multiply (Local0, 0x1E, DMA1)
- } Else {
- If (LEqual (Local0, 0x04)) {
- Store (0x2D, DMA1)
- } Else {
- If (LEqual (Local0, 0x05)) {
- Store (0x1E, DMA1)
- } Else {
- If (LEqual (Local0, 0x06)) {
- Store (0x14, DMA1)
- } Else {
- If (LEqual (Local0, 0x07)) {
- Store (0x0F, DMA0)
- } Else {
- Store (PIO1, DMA1)
- }
- }
- }
- }
- }
- } Else {
- Store (PIO1, DMA1)
- }
- Return (TMD0)
- }
- Method (STM, 0, Serialized) {
- If (REGF) {}
- Else { Return (0xFFFFFFFF) }
- If (LEqual (PIO0, 0xFFFFFFFF)) {
- Store (0xA8, Local1)
- } Else {
- And (Match (DerefOf (Index (TIM0, 0x00)),
- MGE, PIO0, MTR,
- 0x00, 0x00),
- 0x07, Local0)
- Store (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
- Local1)
- }
- ShiftLeft (Local1, 0x08, Local1)
- If (LEqual (PIO1, 0xFFFFFFFF)) {
- Or (Local1, 0xA8, Local1)
- } Else {
- And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIO1, MTR,
- 0x00, 0x00), 0x07, Local0)
- Or (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
- Local1, Local1)
- }
- ShiftLeft (Local1, 0x08, Local1)
- If (LEqual (DMA0, 0xFFFFFFFF)) {
- Or (Local1, 0x03, Local1)
- } Else {
- If (And (CHNF, 0x01)) {
- And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA0, MTR,
- 0x00, 0x00), 0x07, Local0)
- Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)),
- Local1, Local1)
- } Else {
- Or (Local1, 0x03, Local1)
- }
- }
- ShiftLeft (Local1, 0x08, Local1)
- If (LEqual (DMA1, 0xFFFFFFFF)) {
- Or (Local1, 0x03, Local1)
- } Else {
- If (And (CHNF, 0x04)) {
- And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA1, MTR,
- 0x00, 0x00), 0x07, Local0)
- Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)),
- Local1, Local1)
- } Else {
- Or (Local1, 0x03, Local1)
- }
- }
- Return (Local1)
- }
- Name (AT01, Buffer (0x07) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF
- })
- Name (AT02, Buffer (0x07) {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90
- })
- Name (AT03, Buffer (0x07) {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6
- })
- Name (AT04, Buffer (0x07) {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91
- })
- Name (ATA0, Buffer (0x1D) {})
- Name (ATA1, Buffer (0x1D) {})
- Name (ATA2, Buffer (0x1D) {})
- Name (ATA3, Buffer (0x1D) {})
- Name (ATAB, Buffer (0x1D) {})
- CreateByteField (ATAB, 0x00, CMDC)
- Method (GTFB, 3, Serialized) {
- Multiply (CMDC, 0x38, Local0)
- Add (Local0, 0x08, Local1)
- CreateField (ATAB, Local1, 0x38, CMDX)
- Multiply (CMDC, 0x07, Local0)
- CreateByteField (ATAB, Add (Local0, 0x02), A001)
- CreateByteField (ATAB, Add (Local0, 0x06), A005)
- Store (Arg0, CMDX)
- Store (Arg1, A001)
- Store (Arg2, A005)
- Increment (CMDC)
- }
- Method (GTF, 2, Serialized) {
- Store (Arg1, Debug)
- Store (0x00, CMDC)
- Name (ID49, 0x0C00)
- Name (ID59, 0x00)
- Name (ID53, 0x04)
- Name (ID63, 0x0F00)
- Name (ID88, 0x0F00)
- Name (IRDY, 0x01)
- Name (PIOT, 0x00)
- Name (DMAT, 0x00)
- If (LEqual (SizeOf (Arg1), 0x0200)) {
- CreateWordField (Arg1, 0x62, IW49)
- Store (IW49, ID49)
- CreateWordField (Arg1, 0x6A, IW53)
- Store (IW53, ID53)
- CreateWordField (Arg1, 0x7E, IW63)
- Store (IW63, ID63)
- CreateWordField (Arg1, 0x76, IW59)
- Store (IW59, ID59)
- CreateWordField (Arg1, 0xB0, IW88)
- Store (IW88, ID88)
- }
- Store (0xA0, Local7)
- If (Arg0) {
- Store (0xB0, Local7)
- And (CHNF, 0x08, IRDY)
- If (And (CHNF, 0x10)) {
- Store (PIO1, PIOT)
- } Else {
- Store (PIO0, PIOT)
- }
- If (And (CHNF, 0x04)) {
- If (And (CHNF, 0x10)) {
- Store (DMA1, DMAT)
- } Else {
- Store (DMA0, DMAT)
- }
- } Else {
- Store (PIO1, DMAT)
- }
- } Else {
- And (CHNF, 0x02, IRDY)
- Store (PIO0, PIOT)
- If (And (CHNF, 0x01)) {
- Store (DMA0, DMAT)
- }
- }
- If (LAnd (LAnd (And (ID53, 0x04), And (ID88, 0xFF00)), DMAT)) {
- Store (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMAT, MTR,
- 0x00, 0x00), Local1)
- If (LGreater (Local1, 0x06)) {
- Store (0x06, Local1)
- }
- GTFB (AT01, Or (0x40, Local1), Local7)
- } Else {
- If (LAnd (And (ID63, 0xFF00), PIOT)) {
- And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR,
- 0x00, 0x00), 0x07, Local0)
- If (Local0) {
- If (And (Local0, 0x04)) {
- Store (0x02, Local0)
- } Else {
- Store (0x01, Local0)
- }
- }
- Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local0
- )), Local1)
- GTFB (AT01, Local1, Local7)
- }
- }
- If (IRDY) {
- And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR,
- 0x00, 0x00), 0x07, Local0)
- Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0
- )), Local1)
- GTFB (AT01, Local1, Local7)
- } Else {
- If (And (ID49, 0x0400)) {
- GTFB (AT01, 0x01, Local7)
- }
- }
- If (LAnd (And (ID59, 0x0100), And (ID59, 0xFF))) {
- GTFB (AT03, And (ID59, 0xFF), Local7)
- }
- Store (ATAB, Debug)
- Return (ATAB)
- }
- Method (RATA, 1, NotSerialized) {
- CreateByteField (Arg0, 0x00, CMDN)
- Multiply (CMDN, 0x38, Local0)
- CreateField (Arg0, 0x08, Local0, RETB)
- Store (RETB, Debug)
- Return (RETB)
- }
-}
-Device (PMF) {
- // ACPI smbus it should be 0x00040003 if 8131 present
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
- }
- OperationRegion (BAR0, PCI_Config, 0x00, 0xff)
- Field (BAR0, ByteAcc, NoLock, Preserve) {
- Offset (0x56),
- PIRA, 4,
- PIRB, 4,
- PIRC, 4,
- PIRD, 4
- }
- //OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
- //Field (TS3_, DWordAcc, NoLock, Preserve) {
- // PTS3, 16
- //}
-}
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl
deleted file mode 100644
index be2a1ffdb4..0000000000
--- a/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Copyright 2005 AMD
- * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
- */
-//AMD8111 isa
-
-Device (ISA) {
- // lpc 0x00040000
- Method (_ADR, 0, NotSerialized) {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
- }
- /*
- OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
- Field (PIRY, ByteAcc, NoLock, Preserve) {
- Z000, 2, // Parallel Port Range
- , 1,
- ECP , 1, // ECP Enable
- FDC1, 1, // Floppy Drive Controller 1
- FDC2, 1, // Floppy Drive Controller 2
- Offset (0x01),
- Z001, 3, // Serial Port A Range
- SAEN, 1, // Serial Post A Enabled
- Z002, 3, // Serial Port B Range
- SBEN, 1 // Serial Post B Enabled
- }
- */
- Device (PIC) {
- Name (_HID, EisaId ("PNP0000"))
- Name (_CRS, ResourceTemplate () {
- IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) // Master Interrupt controller
- IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) // Slave Interrupt controller
- IRQ (Edge, ActiveHigh, Exclusive) {2}
- })
- }
- Device (DMA1) {
- Name (_HID, EisaId ("PNP0200"))
- Name (_CRS, ResourceTemplate () {
- IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) // Slave DMA controller
- IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) // DMA page registers
- IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) // Master DMA controller
- DMA (Compatibility, NotBusMaster, Transfer16) {4}
- })
- }
- Device (TMR) {
- Name (_HID, EisaId ("PNP0100"))
- Name (_CRS, ResourceTemplate () {
- IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) // Programmable Interval timer
- IRQ (Edge, ActiveHigh, Exclusive) {0}
- })
- }
- Device (RTC) {
- Name (_HID, EisaId ("PNP0B00"))
- Name (_CRS, ResourceTemplate () {
- IO (Decode16, 0x0070, 0x0070, 0x01, 0x04) // Realtime Clock and CMOS ram
- IRQ (Edge, ActiveHigh, Exclusive) {8}
- })
- }
- Device (SPKR) {
- Name (_HID, EisaId ("PNP0800"))
- Name (_CRS, ResourceTemplate () {
- IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) // PC speaker
- })
- }
- Device (COPR) { // Co-processor
- Name (_HID, EisaId ("PNP0C04"))
- Name (_CRS, ResourceTemplate () {
- IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) // Floating point Error control
- IRQ (Edge, ActiveHigh, Exclusive) {13}
- })
- }
- Device (SYSR) { // System control registers (?)
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x00)
- Name (CRS, ResourceTemplate () {
- IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
- IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
- IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
- IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
- IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
- IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C)
- IO (Decode16, 0x0080, 0x0080, 0x01, 0x01)
- IO (Decode16, 0x0084, 0x0084, 0x01, 0x03)
- IO (Decode16, 0x0088, 0x0088, 0x01, 0x01)
- IO (Decode16, 0x008C, 0x008C, 0x01, 0x03)
- IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
- IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
- IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
- // IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- // EISA defined level triggered interrupt control registers
- IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02)
- // IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- // IO (Decode16, 0xDE00, 0xDE00, 0x00, 0x80)
- // IO (Decode16, 0xDE80, 0xDE80, 0x00, 0x80)
- IO (Decode16,0xDE00,0xDE00,0x00,0x80)
- IO (Decode16,0xDE80,0xDE80,0x00,0x80)
- // IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
- // IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
- IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0D) // PMBS block
- IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0E) // SMBS block
- IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0F) // GPBS block
- })
- Method (_CRS, 0, NotSerialized) {
- CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MIN, GP00)
- CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MAX, GP01)
- CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._LEN, GP0L)
- Store (PMBS, GP00)
- Store (PMBS, GP01)
- Store (PMLN, GP0L)
- If (SMBS) {
- CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MIN, GP10)
- CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MAX, GP11)
- CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._LEN, GP1L)
- Store (SMBS, GP10)
- Store (SMBS, GP11)
- Store (SMBL, GP1L)
- }
- If (GPBS) {
- CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MIN, GP20)
- CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MAX, GP21)
- CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._LEN, GP2L)
- Store (GPBS, GP20)
- Store (GPBS, GP21)
- Store (GPLN, GP2L)
- }
- Return (CRS)
- }
- }
- Device (MEM) {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- Method (_CRS, 0, Serialized) {
- Name (BUF0, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
- Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404
- Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
- Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
- Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
- Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- })
-// Read the Video Memory length
- CreateDWordField (BUF0, 0x14, CLEN)
- CreateDWordField (BUF0, 0x10, CBAS)
-
- ShiftLeft (VGA1, 0x09, Local0)
- Store (Local0, CLEN)
-
- Return (BUF0)
- }
- }
-#include "superio/winbond/w83627hf/acpi/superio.asl"
-}
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl
deleted file mode 100644
index a09c576102..0000000000
--- a/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright 2005 AMD
- * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
- */
-//AMD8111 pic LNKA B C D
-
-Device (LNKA) {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x01)
- Method (_STA, 0, NotSerialized) {
- If (LEqual (\_SB.PCI0.PMF.PIRA, 0x00) ) { Return (0x09) } //Disabled
- Else { Return (0x0B) } //Enabled
- }
- Method (_PRS, 0, Serialized) {
- Name (BUFA, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
- Method (_DIS, 0, NotSerialized) {
- Store (0x00, \_SB.PCI0.PMF.PIRA )
- }
-
- Method (_CRS, 0, Serialized) {
- Name (BUFA, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local2)
- Store (0x00, Local3)
- Store (\_SB.PCI0.PMF.PIRA, Local1)
- If (LNot (LEqual (Local1, 0x00))) { // Routing enable
- If (LGreater (Local1, 0x07)) {
- Subtract (Local1, 0x08, Local1)
- ShiftLeft (One, Local1, Local3)
- } Else {
- If (LGreater (Local1, 0x00)) {
- ShiftLeft (One, Local1, Local2)
- }
- }
- Store (Local2, IRA1)
- Store (Local3, IRA2)
- }
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized) {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00)) {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
- Store(Local1,\_SB.PCI0.PMF.PIRA)
- }
-}
-
-Device (LNKB) {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized) {
- If (LEqual (\_SB.PCI0.PMF.PIRB, 0x00) ) { Return (0x09) } //Disabled
- Else { Return (0x0B) } //Enabled
- }
-
- Method (_PRS, 0, Serialized) {
- Name (BUFB, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized) {
- Store (0x00, \_SB.PCI0.PMF.PIRB )
- }
-
- Method (_CRS, 0, Serialized) {
- Name (BUFB, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRA1)
- CreateByteField (BUFB, 0x02, IRA2)
- Store (0x00, Local2)
- Store (0x00, Local3)
- Store (\_SB.PCI0.PMF.PIRB, Local1)
- If (LNot (LEqual (Local1, 0x00))) { // Routing enable
- If (LGreater (Local1, 0x07)) {
- Subtract (Local1, 0x08, Local1)
- ShiftLeft (One, Local1, Local3)
- } Else {
- If (LGreater (Local1, 0x00)) {
- ShiftLeft (One, Local1, Local2)
- }
- }
- Store (Local2, IRA1)
- Store (Local3, IRA2)
- }
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized) {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00)) {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
- Store(Local1,\_SB.PCI0.PMF.PIRB)
- }
-}
-
-Device (LNKC) {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x03)
- Method (_STA, 0, NotSerialized) {
- If (LEqual (\_SB.PCI0.PMF.PIRC, 0x00) ) { Return (0x09) } //Disabled
- Else { Return (0x0B) } //Enabled
- }
-
- Method (_PRS, 0, Serialized) {
- Name (BUFA, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized) {
- Store (0x00, \_SB.PCI0.PMF.PIRC )
- }
-
- Method (_CRS, 0, Serialized) {
- Name (BUFA, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local2)
- Store (0x00, Local3)
- Store (\_SB.PCI0.PMF.PIRC, Local1)
- If (LNot (LEqual (Local1, 0x00))) { // Routing enable
- If (LGreater (Local1, 0x07)) {
- Subtract (Local1, 0x08, Local1)
- ShiftLeft (One, Local1, Local3)
- } Else {
- If (LGreater (Local1, 0x00)) {
- ShiftLeft (One, Local1, Local2)
- }
- }
- Store (Local2, IRA1)
- Store (Local3, IRA2)
- }
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized) {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00)) {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
- Store(Local1,\_SB.PCI0.PMF.PIRC)
- }
-}
-
-Device (LNKD) {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x04)
- Method (_STA, 0, NotSerialized) {
- If (LEqual (\_SB.PCI0.PMF.PIRD, 0x00) ) { Return (0x09) } //Disabled
- Else { Return (0x0B) } //Enabled
- }
- Method (_PRS, 0, Serialized) {
- Name (BUFB, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
- Method (_DIS, 0, NotSerialized) {
- Store (0x00, \_SB.PCI0.PMF.PIRD )
- }
- Method (_CRS, 0, Serialized) {
- Name (BUFB, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRA1)
- CreateByteField (BUFB, 0x02, IRA2)
- Store (0x00, Local2)
- Store (0x00, Local3)
- Store (\_SB.PCI0.PMF.PIRD, Local1)
- If (LNot (LEqual (Local1, 0x00))) { // Routing enable
- If (LGreater (Local1, 0x07)) {
- Subtract (Local1, 0x08, Local1)
- ShiftLeft (One, Local1, Local3)
- } Else {
- If (LGreater (Local1, 0x00)) {
- ShiftLeft (One, Local1, Local2)
- }
- }
- Store (Local2, IRA1)
- Store (Local3, IRA2)
- }
- Return (BUFB)
- }
- Method (_SRS, 1, NotSerialized) {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00)) {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
- Store(Local1,\_SB.PCI0.PMF.PIRD)
- }
-}
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8131.asl b/src/mainboard/hp/dl145_g1/acpi/amd8131.asl
deleted file mode 100644
index 29808aabd9..0000000000
--- a/src/mainboard/hp/dl145_g1/acpi/amd8131.asl
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright 2005 AMD
- * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
- */
-
-Device (PG0A) {
-/* 8131 pcix bridge 1 */
- Method (_ADR, 0, NotSerialized) {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
- Method (_PRW, 0, NotSerialized) {
- //If (CondRefOf (\_S3)) {
- // Return (Package (0x02) { 0x29, 0x03 })
- //} Else {
- Return (Package (0x02) { 0x29, 0x01 })
- //}
- }
- Name (APIC, Package (0x0c) {
- // Slot 3 - PIRQ BCDA ---- verified
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
- // Slot 4 - PIRQ CDAB ---- verified
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //?
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
- // Onboard NIC 1 - PIRQ DABC
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //?
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A },
- // NIC 2 - PIRQ ABCD -- verified
- // Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //?
- // Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 },
- // Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A },
- // Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B },
- // SERIAL ATA - PIRQ BCDA
- // Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //?
- // Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A },
- // Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B },
- // Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 }
- })
- Name (PICM, Package (0x0c) {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
- // Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- // Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- // Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- // Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- // Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
- // Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- // Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- // Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
- })
- Method (_PRT, 0, NotSerialized) {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
-}
-Device (PG0B) {
-/* 8131 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized) {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
- Method (_PRW, 0, NotSerialized) {
- //If (CondRefOf (\_S3)) {
- // Return (Package (0x02) { 0x22, 0x03 })
- //} Else {
- Return (Package (0x02) { 0x22, 0x01 })
- //}
- }
- Name (APIC, Package (0x04) {
- // Slot A - PIRQ CDAB -- verfied
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },// Slot 2
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1C },
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1D },
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1E }
- })
- Name (PICM, Package (0x04) {
- Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 2
- Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }
- })
- Method (_PRT, 0, NotSerialized) {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
-}
diff --git a/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl b/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl
deleted file mode 100644
index 021ee1f279..0000000000
--- a/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl
+++ /dev/null
@@ -1,6 +0,0 @@
-/*
- * Copyright (c) 2011, 2014 Oskar Enoksson <enok@lysator.liu.se>
- * Subject to the GNU GPL v2, or (at your option) any later version.
- */
-#include "amd8111.asl" //real SB at first
-#include "amd8131.asl"
diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c
deleted file mode 100644
index a464678036..0000000000
--- a/src/mainboard/hp/dl145_g1/acpi_tables.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Island Aruma ACPI support
- * written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
- *
- * Copyright 2005 AMD
- * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
- *
- * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
- * Modified to work with hp/dl145_g1
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include "mb_sysconf.h"
-#include <cpu/amd/powernow.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
-
- struct mb_sysconf_t *m;
-
- get_bus_conf();
-
- m = sysconf.mb;
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write 8111 IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111,
- IO_APIC_ADDR, 0);
-
- /* Write all 8131 IOAPICs */
- {
- struct device *dev;
- struct resource *res;
- dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8131_1,
- res->base, gsi_base );
- gsi_base+=4;
-
- }
- }
- dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8131_2,
- res->base, gsi_base );
- gsi_base+=4;
- }
- }
-
-
- }
-
- current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 5 );
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high*/
-
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapic_nmis(current, 5, 1);
- /* 1: LINT1 connect to NMI */
-
-
- return current;
-}
diff --git a/src/mainboard/hp/dl145_g1/board_info.txt b/src/mainboard/hp/dl145_g1/board_info.txt
deleted file mode 100644
index b06f119a91..0000000000
--- a/src/mainboard/hp/dl145_g1/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: server
-Board URL: http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&objectID=c00346784&prodTypeId=15351&prodSeriesId=3219755
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2004
diff --git a/src/mainboard/hp/dl145_g1/cmos.layout b/src/mainboard/hp/dl145_g1/cmos.layout
deleted file mode 100644
index c4c90f697f..0000000000
--- a/src/mainboard/hp/dl145_g1/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/hp/dl145_g1/devicetree.cb b/src/mainboard/hp/dl145_g1/devicetree.cb
deleted file mode 100644
index 2d4adee0f4..0000000000
--- a/src/mainboard/hp/dl145_g1/devicetree.cb
+++ /dev/null
@@ -1,141 +0,0 @@
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_940
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1022 0x7460 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on end # link 0
- device pci 18.0 on end # link 1
- device pci 18.0 on # link 2
- chip southbridge/amd/amd8131
- # the on/off keyword is mandatory
- device pci 0.0 on # PCIX Bridge A
- # PCI-X expansion slot cards auto-detected here
- end
- device pci 0.1 on end # IOAPIC A
- device pci 1.0 on # PCIX Bridge B
- # On-board BCM5704 dual port ethernet chip auto-detected here
- # Optional SCSI board also (?)
- end
- device pci 1.1 on end # IOAPIC B
- device pci 2.0 off end
- end
- chip southbridge/amd/amd8111
- # this "device pci 0.0" is the parent of the next one
- # PCI bridge
- device pci 0.0 on
- device pci 0.0 on end # OHCI-based USB controller 0
- device pci 0.1 on end # OCHI-based USB controller 1
- device pci 0.2 on end # EHCI-based USB2 controller
- device pci 1.0 off end # LAN Ethernet controller
- #device pci 4.0 on end # VGA PCI-card (auto detected)
- end
- device pci 1.0 on # LPC Bridge
- chip superio/winbond/w83627hf
- device pnp 2e.0 off # Floppy
- #io 0x60 = 0x3f0
- #irq 0x70 = 6
- #drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- #io 0x60 = 0x378
- #irq 0x70 = 7
- #drq 0x74 = 1
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- #io 0x60 = 0x2f8
- #irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # CIR
- end
- device pnp 2e.7 off # GAM_MIDI_GPIO1
- #io 0x60 = 0x201
- #io 0x62 = 0x330
- #irq 0x70 = 9
- end
- device pnp 2e.8 on # GPIO2 (watchdog timer)
- end
- device pnp 2e.9 on # GPIO3
- end
- device pnp 2e.a on # ACPI
- end
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on end # EIDE controller
- device pci 1.2 on
- chip drivers/generic/generic
- device i2c 8 on end # Some HW-monitor/sensor?
- end
- end
- device pci 1.2 on
- chip drivers/i2c/i2cmux # Multplexed DIMM spd eeproms.
- device i2c 18 on #0 pca9516 (?)
- # Some dimms also listen to address 30-33
- # It's some kind of write-protect function
- # The 50-53 addresses are the interesting ones.
- chip drivers/generic/generic #dimm H0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm H0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm H0-2
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm H0-3
- device i2c 53 on end
- end
- end
- device i2c 18 on #1 pca9516 (?)
- chip drivers/generic/generic #dimm H1-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm H1-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm H1-2
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm H1-3
- device i2c 53 on end
- end
- end
- end
- end
- device pci 1.2 on
- chip drivers/generic/generic
- device i2c 69 on end # Texas Instruments cdc960 clock synthesizer
- end
- end # SMBus 2.0 controller
- device pci 1.3 on # System management registers (ACPI)
- end # System management
- #device pci 1.4 off end
- device pci 1.5 off end # AC97 Audio
- device pci 1.6 off end # AC97 Modem
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- end
- end # device pci 18.0
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/hp/dl145_g1/dsdt.asl b/src/mainboard/hp/dl145_g1/dsdt.asl
deleted file mode 100644
index bf9787dc79..0000000000
--- a/src/mainboard/hp/dl145_g1/dsdt.asl
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
-{
- // Name (SPIO, 0x2E) // SuperIO (w83627hf)
- Name (SPI2, 0x4E) // Unknown National Semiconductors (EPM3128A?)
- Name (IO1B, 0x0680) // GPIO Base (?)
- Name (IO1L, 0x80)
- //Name (IO2B, 0x0295) // Hardware monitor
- //Name (IO2L, 0x02)
- Name (PMBS, 0x2000) // Power Management Base
- Name (PMLN, 0xC0) // Power Management Length
- Name (GPBS, 0x20C0)
- Name (GPLN, 0x20)
- Name (SMBS, 0x20E0)
- Name (SMBL, 0x20)
-
-#define NO_W83627HF_FDC // don't expose the floppy disk controller
-#define NO_W83627HF_FDC_ENUM // don't try to enumerate the connected floppy drives
-#define NO_W83627HF_PPORT // don't expose the parallel port
-//#define NO_W83627HF_UARTA // don't expose the first serial port
-#define NO_W83627HF_UARTB // don't expose the second serial port (already hidden
- // if UARTB is configured as IRDA port by firmware)
-#define NO_W83627HF_IRDA // don't expose the IRDA port (already hidden if UARTB is
- // configured as serial port by firmware)
-#define NO_W83627HF_CIR // don't expose the Consumer Infrared functionality
-//#define NO_W83627HF_KBC // don't expose the keyboard controller
-//#define NO_W83627HF_PS2M // don't expose the PS/2 mouse functionality of the
- // keyboard controller
-#define NO_W83627HF_GAME // don't expose the game port
-#define NO_W83627HF_MIDI // don't expose the MIDI port
-// #define NO_W83627HF_HWMON // don't expose the hardware monitor as
- // PnP "Motherboard Resource"
-// Scope (\_PR) and relevant CPU? objects are auto-generated in SSDT
-
- Scope (\_SB) { // Root of the bus hierarchy
- Device (PCI0) { // Top PCI device (AMD K8 Northbridge 1)
-
- Device(MBRS) {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- External(_CRS) /* Resource Template in SSDT */
- }
-
- // The following symbols are assumed to be created by coreboot
- External (BUSN)
- External (PCIO)
- External (MMIO)
- External (SBLK)
- External (CBST)
- External (SBDN)
- External (TOM1) // Top Of Memory 1 (low 4GB ?)
- External (HCLK) // Hypertransport possible CLocK frequencies
- External (HCDN) // Hypertransport Controller Device Numbers
-
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00180000)
- //Name (_UID, 0x00)
- Name (_UID, 0x01)
-
- Name (HCIN, 0x00) // HC1
- Method (_BBN, 0, NotSerialized) {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
- Method (_CRS, 0, Serialized) {
- Name (BUF0, ResourceTemplate () {
- // PCI Configuration address space address/data
- IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08)
- IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
- IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x8100, // Address Range Minimum
- 0xFFFF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x7F00,,,
- , TypeStatic) //8100h-FFFFh
- DWordMemory (ResourceProducer, PosDecode,
- MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, // Address Space Granularity
- 0x000C0000, // Address Range Minimum
- 0x000CFFFF, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00010000,,,
- , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
- Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x03AF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x03B0,,,
- , TypeStatic) //0-CF7h
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x03E0, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0918,,,
- , TypeStatic) //0-CF7h
- })
- \_SB.OSVR ()
- CreateDWordField (BUF0, 0x3E, VLEN)
- CreateDWordField (BUF0, 0x36, VMAX)
- CreateDWordField (BUF0, 0x32, VMIN)
- ShiftLeft (VGA1, 0x09, Local0)
- Add (VMIN, Local0, VMAX)
- Decrement (VMAX)
- Store (Local0, VLEN)
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
- #include "acpi/pci0_hc.asl"
- }
- Device (PCI1) {
- Name (_HID, "PNP0A03")
- Name (_ADR, 0x00190000)
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized) {
- Return (\_SB.PCI0.CBST)
- }
- //Name (HCIN, 0x01) // HC2
- //Method (_BBN, 0, NotSerialized) {
- // Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- //}
- Name (_BBN, 0x00)
- }
- Device (PWRB) {
- Name (_HID, EisaId ("PNP0C0C"))
- Name (_UID, 0xAA)
- Name (_STA, 0x0B)
- }
- }
- Scope (_GPE) {
- Method (_L08, 0, NotSerialized) {
- Notify (\_SB.PCI0, 0x02) //PME# Wakeup
- Notify (\_SB.PCI0.TP2P.ETHR, 0x02)
- Notify (\_SB.PWRB, 0x02)
- }
- Method (_L0F, 0, NotSerialized) {
- Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
- Notify (\_SB.PCI0.TP2P.USB1, 0x02)
- Notify (\_SB.PWRB, 0x02)
- }
- Method (_L22, 0, NotSerialized) { // GPIO18 (LID) - Pogo 0 Bridge B
- Notify (\_SB.PCI0.PG0B, 0x02)
- Notify (\_SB.PWRB, 0x02)
- }
- Method (_L29, 0, NotSerialized) { // GPIO25 (Suspend) - Pogo 0 Bridge A
- Notify (\_SB.PCI0.PG0A, 0x02)
- Notify (\_SB.PWRB, 0x02)
- }
- }
- OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS RAM (?)
- Field (KSB0, ByteAcc, NoLock, Preserve) {
- KSBI, 8, // Index
- KSBD, 8 // Data
- }
-/*
- OperationRegion (IHHM, SystemIO, IO2B, IO2L) // Hardware monitor
- Field (IHHM, ByteAcc, NoLock, Preserve) {
- HHMI, 8, // Index
- HHMD, 8 // Data
- }
-*/
- // Method (_BFS, 1, NotSerialized) {
- // Control method executed immediately following a wake event.
- // Arg0 => Value of the sleeping state from which woken (1=S1, 2=S2 ...)
- // Optional
- //}
-
- Method (_PTS, 1, NotSerialized) {
- // Control method used to Prepare To Sleep.
- // Arg0 => Value of the sleeping state (1=S1, 2=S2 ...)
- Or (Arg0, 0xF0, Local0)
- Store (Local0, DBG8)
- }
-
- // Method (_GTS, 1, NotSerialized) {
- // Control method executed just prior to setting the sleep enable (SLP_EN) bit.
- // Arg0 => Value of the sleeping state (1=S1, 2=S2 ...)
- // Optional
- //}
-
- #include <southbridge/amd/amd8111/acpi/sleepstates.asl>
-
- Name (WAKP, Package (0x02) { 0x00, 0x00 })
- // Status
- // 0: 0 Wake was signaled but failed due to lack of power.
- // 1: 1 Wake was signaled but failed due to thermal condition
- // 2:31 Reserved
- // PSS
- // 0:1f If non-zero, the effective S-state the power supply really entered.
-
- Method (_WAK, 1, NotSerialized) {
- // System Wake
- // Arg0: The value of the sleeping state from which woken (1=S1, ...)
- // Result: (2 DWORD package)
- ShiftLeft (Arg0, 0x04, DBG8)
- Store (0xFF, KSBI) // Clear 0xFF in CMOS RAM
- Store (0x00, KSBD)
- If (LEqual (Arg0, 0x01)) { // Wake from S1 state
- And (\_SB.PCI0.GSTS, 0x10, Local0)
- And (Local0, \_SB.PCI0.GNBL, Local0)
- If (Local0) {
- Notify (\_SB.PWRB, 0x02)
- }
- }
- Store (\_SB.PCI0.GSTS, Local0)
- Store (Local0, \_SB.PCI0.GSTS)
- Store (\_SB.PCI0.STMC, Local0)
- Store (Local0, \_SB.PCI0.STMC)
- Store (\_SB.PCI0.STC0, Local0)
- Store (Local0, \_SB.PCI0.STC0)
- Store (\_SB.PCI0.STC1, Local0)
- Store (Local0, \_SB.PCI0.STC1)
- Store (\_SB.PCI0.STHW, Local0)
- Store (Local0, \_SB.PCI0.STHW)
- If (LEqual (Arg0, 0x03)) { // Wake from S3 state
- Notify (\_SB.PCI0.TP2P.USB0, 0x01)
- }
- Store (0xC0, \_SB.PCI0.SWSM)
- If (DerefOf (Index (WAKP, 0x00))) {
- Store (0x00, Index (WAKP, 0x01))
- } Else {
- Store (Arg0, Index (WAKP, 0x01))
- }
- Return (WAKP)
- }
-
- Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
- Method (_PIC, 1, NotSerialized) { //PIC Flag and Interface Method
- // Control method that conveys interrupt model in use to the system
- // firmware. OS reports interrupt model in use.
- // 0 => PIC Mode
- // 1 => APIC Mode
- // 2 => SAPIC Mode
- // 3.. => Reserved
- Store (Arg0, PICF)
- }
- OperationRegion (DEB8, SystemIO, 0x80, 0x01)
- Field (DEB8, ByteAcc, Lock, Preserve) {
- DBG8, 8
- }
- OperationRegion (DEB9, SystemIO, 0x90, 0x01)
- Field (DEB9, ByteAcc, Lock, Preserve) {
- DBG9, 8
- }
- OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
- Field (EXTM, WordAcc, Lock, Preserve) {
- AMEM, 32
- }
- OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
- Field (VGAM, ByteAcc, Lock, Preserve) {
- VGA1, 8 // Video memory length (in 2k units?)
- }
- OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
- Field (GRAM, ByteAcc, Lock, Preserve) {
- Offset (0x10),
- FLG0, 8
- }
- OperationRegion (Z007, SystemIO, 0x21, 0x01)
- Field (Z007, ByteAcc, NoLock, Preserve) {
- Z008, 8
- }
- OperationRegion (Z009, SystemIO, 0xA1, 0x01)
- Field (Z009, ByteAcc, NoLock, Preserve) {
- Z00A, 8
- }
- #include "northbridge/amd/amdk8/util.asl"
-}
diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c
deleted file mode 100644
index 877cb5b03b..0000000000
--- a/src/mainboard/hp/dl145_g1/fadt.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- * (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-
-extern unsigned pm_base; /* pm_base should be set in sb ACPI */
-
-void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
-
- acpi_header_t *header=&(fadt->header);
-
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
- /* Prepare the header */
- memset((void *)fadt,0,sizeof(acpi_fadt_t));
- memcpy(header->signature,"FACP",4);
- header->length = 244;
- header->revision = 3;
- memcpy(header->oem_id,OEM_ID,6);
- memcpy(header->oem_table_id,"COREBOOT",8);
- memcpy(header->asl_compiler_id,ASLC,4);
- header->asl_compiler_revision = 0;
-
- fadt->firmware_ctrl=(u32)facs;
- fadt->dsdt= (u32)dsdt;
- // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
- fadt->preferred_pm_profile = 0x04;
- fadt->sci_int = 9;
-
- // disable system management mode by setting to 0:
- fadt->smi_cmd = 0;//pm_base+0x2f;
- fadt->acpi_enable = 0xf0;
- fadt->acpi_disable = 0xf1;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0xe2;
-
- fadt->pm1a_evt_blk = pm_base;
- fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = pm_base+0x04;
- fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = 0x0000;
- fadt->pm_tmr_blk = pm_base+0x08;
- fadt->gpe0_blk = pm_base+0x20;
- fadt->gpe1_blk = pm_base+0xb0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 0;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 4;
- fadt->gpe1_blk_len = 8;
- fadt->gpe1_base = 16;
-
- fadt->cst_cnt = 0xe3;
- fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state
- fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state
- fadt->flush_size = 0; // ignored if wbindv = 1 in flags
- fadt->flush_stride = 0; // ignored if wbindv = 1 in flags
- fadt->duty_offset = 1;
- fadt->duty_width = 3; // 0 means duty cycle not supported
- // _alrm value 0 means RTC alarm feature not supported
- fadt->day_alrm = 0; // 0x7d these have to be
- fadt->mon_alrm = 0; // 0x7e added to cmos.layout
- fadt->century = 0; // 0x7f to make rtc alrm work
- fadt->iapc_boot_arch =
- ACPI_FADT_LEGACY_DEVICES |
- ACPI_FADT_8042 |
- // ACPI_FADT_VGA_NOT_PRESENT |
- // ACPI_FADT_MSI_NOT_SUPPORTED|
- // ACPI_FADT_NO_PCIE_ASPM_CONTROL|
- 0;
-
- fadt->res2 = 0;
-
- fadt->flags =
- ACPI_FADT_WBINVD |
- // ACPI_FADT_WBINVD_FLUSH |
- ACPI_FADT_C1_SUPPORTED |
- // ACPI_FADT_C2_MP_SUPPORTED |
- // ACPI_FADT_POWER_BUTTON |
- ACPI_FADT_SLEEP_BUTTON |
- // ACPI_FADT_FIXED_RTC |
- // ACPI_FADT_S4_RTC_WAKE |
- // ACPI_FADT_32BIT_TIMER |
- // ACPI_FADT_DOCKING_SUPPORTED|
- // ACPI_FADT_RESET_REGISTER |
- // ACPI_FADT_SEALED_CASE |
- // ACPI_FADT_HEADLESS |
- // ACPI_FADT_SLEEP_TYPE |
- // ACPI_FADT_PCI_EXPRESS_WAKE |
- // ACPI_FADT_PLATFORM_CLOCK |
- // ACPI_FADT_S4_RTC_VALID |
- // ACPI_FADT_REMOTE_POWER_ON |
- // ACPI_FADT_APIC_CLUSTER |
- // ACPI_FADT_APIC_PHYSICAL |
- 0;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 6;
-
- fadt->res3 = 0;
- fadt->res4 = 0;
- fadt->res5 = 0;
-
- fadt->x_firmware_ctl_l = (u32)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = pm_base;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 4;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = pm_base+4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 2;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = 0x0;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = pm_base+0x08;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 32;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = pm_base+0x20;
- fadt->x_gpe0_blk.addrh = 0x0;
-
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 64;
- fadt->x_gpe1_blk.bit_offset = 16;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = pm_base+0xb0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-
-}
diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c
deleted file mode 100644
index ef768245ad..0000000000
--- a/src/mainboard/hp/dl145_g1/get_bus_conf.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright (c) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
- * Subject to the GNU GPL v2, or (at your option) any later version.
- */
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-static unsigned pci1234x[] =
-{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-static unsigned hcdnx[] =
-{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
-
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.mb = &mb_sysconf;
- struct mb_sysconf_t *m = sysconf.mb;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
- m->sbdn3 = sysconf.hcdn[0] & 0xff;
-
- m->bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff;
- m->bus_8111_0 = m->bus_8131_0;
-
- /* 8111 */
- dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
- if (dev)
- m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- else
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0);
-
- /* 8131-1 */
- dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0));
- if (dev)
- m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- else
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0);
-
- /* 8131-2 */
- dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0));
- if (dev)
- m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- else
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0);
-
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(3);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- m->apicid_8111 = apicid_base+0;
- m->apicid_8131_1 = apicid_base+1;
- m->apicid_8131_2 = apicid_base+2;
-}
diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c
deleted file mode 100644
index 597acca7e6..0000000000
--- a/src/mainboard/hp/dl145_g1/irq_tables.c
+++ /dev/null
@@ -1,98 +0,0 @@
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
- struct mb_sysconf_t *m = sysconf.mb;
-
- uint8_t sum = 0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = m->bus_8111_0;
- pirq->rtr_devfn = ((sysconf.sbdn + 1) << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1022;
- pirq->rtr_device = 0x746b;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-//pcix bridge
-// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-// pirq_info++; slot_num++;
-
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/hp/dl145_g1/mb_sysconf.h b/src/mainboard/hp/dl145_g1/mb_sysconf.h
deleted file mode 100644
index 3dfd5deb01..0000000000
--- a/src/mainboard/hp/dl145_g1/mb_sysconf.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
- * Subject to the GNU GPL v2, or (at your option) any later version.
- */
-#ifndef MB_SYSCONF_H
-
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_8131_0;
- unsigned char bus_8131_1;
- unsigned char bus_8131_2;
- unsigned char bus_8111_0;
- unsigned char bus_8111_1;
-
- unsigned apicid_8111;
- unsigned apicid_8131_1;
- unsigned apicid_8131_2;
-
- unsigned sbdn3;
-};
-
-#endif
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
deleted file mode 100644
index 80ad79d7a0..0000000000
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (c) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
- * Subject to the GNU GPL v2, or (at your option) any later version.
- */
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- struct mb_sysconf_t *m = sysconf.mb;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x20, VIO_APIC_VADDR);
- {
- struct device *dev;
- struct resource *res;
- dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, m->apicid_8131_1, 0x20,
- res2mmio(res, 0, 0));
- }
- }
- dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, m->apicid_8131_2, 0x20,
- res2mmio(res, 0, 0));
- }
- }
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
-
- //
- // The commented-out lines are auto-detected on my servers.
- //
-/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- // Integrated SMBus 2.0
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15);
- // Integrated AMD AC97 Audio
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11);
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12);
- // Integrated AMD USB
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13);
- // On board ATI Rage XL
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14);
- // On board Broadcom nics
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00);
- // On board LSI SCSI
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
-
- // PCIX-133 Slot
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01);
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/hp/dl145_g1/resourcemap.c b/src/mainboard/hp/dl145_g1/resourcemap.c
deleted file mode 100644
index 65a4610d15..0000000000
--- a/src/mainboard/hp/dl145_g1/resourcemap.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * DL145G1 needs a different resource map
- * This file was originally copied from the tyan/s2881 coreboot mainboard.
- *
- * Copyright (c) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
- * Subject to the GNU GPL v2, or (at your option) any later version.
- */
-
-static void setup_dl145g1_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- //PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000b20,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- //PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000a03,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000203,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
deleted file mode 100644
index e991dc6bda..0000000000
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * Copyright (c) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
- * Subject to the GNU GPL v2, or (at your option) any later version.
- */
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <delay.h>
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "southbridge/amd/amd8111/early_smbus.c"
-#include <northbridge/amd/amdk8/raminit.h>
-
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-unsigned get_sbdn(unsigned bus);
-
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- /* Set the memreset low. */
- outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 16);
- /* Ensure the BIOS has control of the memory lines. */
- outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
- } else {
- /* Ensure the CPU has control of the memory lines. */
- outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 17);
- }
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- /* Set memreset high. */
- outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16);
- udelay(90);
- }
-}
-
-#define SMBUS_HUB 0x18
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
- int ret,i;
- unsigned device=(ctrl->channel0[0])>>8;
- /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
- i = 2;
- do {
- ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- } while ((ret != 0) && (i-->0));
- smbus_write_byte(SMBUS_HUB, 0x03, 0);
-}
-
-static inline void change_i2c_mux(unsigned device)
-{
- int ret, i;
- printk(BIOS_DEBUG, "change_i2c_mux i=%02x\n", device);
- i = 2;
- do {
- ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- printk(BIOS_DEBUG, "change_i2c_mux 1 ret=%08x\n", ret);
- } while ((ret != 0) && (i-->0));
- ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
- printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret);
-}
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "southbridge/amd/amd8111/early_ctrl.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "resourcemap.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include "cpu/amd/model_fxx/init_cpus.c"
-#if IS_ENABLED(CONFIG_SET_FIDVID)
-#include "cpu/amd/model_fxx/fidvid.c"
-#endif
-
-#define RC0 ((1 << 1)<<8)
-#define RC1 ((1 << 2)<<8)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr [] = {
- //first node
- RC0|DIMM0, RC0|DIMM2, 0, 0,
- RC0|DIMM1, RC0|DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- //second node
- RC1|DIMM0, RC1|DIMM2, 0, 0,
- RC1|DIMM1, RC1|DIMM3, 0, 0,
-#endif
- };
- struct sys_info *sysinfo = &sysinfo_car;
-
- int needs_reset = 0;
- unsigned bsp_apicid = 0;
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo);
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
- setup_dl145g1_resource_map();
-
- setup_coherent_ht_domain();
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- ht_setup_chains_x(sysinfo);
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- struct cpuid_result cpuid1 = cpuid(0x80000007);
- if ((cpuid1.edx & 0x6) == 0x6) {
- {
- /* Read FIDVID_STATUS */
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
-
- // show final fid and vid
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-
- } else {
- printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
- }
-#endif
-
- needs_reset |= optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
-
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
- }
-
- enable_smbus();
-
- int i;
- for (i = 0; i < 2; i++)
- activate_spd_rom(&sysinfo->ctrl[i]);
- for (i = RC0; i <= RC1; i <<= 1)
- change_i2c_mux(i);
-
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- memreset_setup();
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- init_timer(); // Need to use TMICT to synchronize FID/VID
-#endif
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
-}
diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig
deleted file mode 100644
index da20fb339e..0000000000
--- a/src/mainboard/hp/dl145_g3/Kconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-if BOARD_HP_DL145_G3
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_F
- select DIMM_DDR2
- select DIMM_REGISTERED
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_BROADCOM_BCM21000
- select SOUTHBRIDGE_BROADCOM_BCM5785
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_SERVERENGINES_PILOT
- select SUPERIO_NSC_PC87417
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_512
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select QRANK_DIMM_SUPPORT
- select K8_ALLOCATE_IO_RANGE
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default hp/dl145_g3
-
-config DCACHE_RAM_BASE
- hex
- default 0xcc000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x04000
-
-config APIC_ID_OFFSET
- hex
- default 0x8
-
-config MAINBOARD_PART_NUMBER
- string
- default "ProLiant DL145 G3"
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x6
-
-config IRQ_SLOT_COUNT
- int
- default 15
-
-endif # BOARD_HP_DL145_G3
diff --git a/src/mainboard/hp/dl145_g3/Kconfig.name b/src/mainboard/hp/dl145_g3/Kconfig.name
deleted file mode 100644
index ebbc20fb94..0000000000
--- a/src/mainboard/hp/dl145_g3/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_HP_DL145_G3
- bool "ProLiant DL145 G3"
diff --git a/src/mainboard/hp/dl145_g3/board_info.txt b/src/mainboard/hp/dl145_g3/board_info.txt
deleted file mode 100644
index f6f701d4f5..0000000000
--- a/src/mainboard/hp/dl145_g3/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Category: server
-Board URL: http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c00816835&lang=en&cc=us&taskId=101&prodSeriesId=3219755&prodTypeId=15351
-Release year: 2007
diff --git a/src/mainboard/hp/dl145_g3/cmos.layout b/src/mainboard/hp/dl145_g3/cmos.layout
deleted file mode 100644
index 56ed652b97..0000000000
--- a/src/mainboard/hp/dl145_g3/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 400Mhz
-8 1 333Mhz
-8 2 266Mhz
-8 3 200Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/hp/dl145_g3/devicetree.cb b/src/mainboard/hp/dl145_g3/devicetree.cb
deleted file mode 100644
index b7f450ec06..0000000000
--- a/src/mainboard/hp/dl145_g3/devicetree.cb
+++ /dev/null
@@ -1,85 +0,0 @@
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_F
- device lapic 0 on end
- end
- end
- device domain 0 on
- chip northbridge/amd/amdk8 # northbridge
- device pci 18.0 on # devices on link 0
- chip southbridge/broadcom/bcm21000 # HT2100
- device pci 0.0 on
- end # bridge to slot PCI-E 4x ??
- device pci 1.0 on
- end
- device pci 2.0 on
- end # unused
- device pci 3.0 on # bridge to slot PCI-E 16x ??
- end
- device pci 4.0 on
- end # unused
- device pci 5.0 on
- device pci 4.0 on end # BCM5715 NIC
- device pci 4.1 on end # BCM5715 NIC
- end
- end
- chip southbridge/broadcom/bcm5785 # HT1000
- device pci 0.0 on # HT PXB 0x0036
- device pci d.0 on end # PCI/PCI-X bridge 0x0104
- device pci e.0 on end # SATA 0x024a
- end
- device pci 1.0 on end # Legacy pci main 0x0205
- device pci 1.1 on end # IDE 0x0214
- device pci 1.2 on # LPC 0x0234
- chip superio/nsc/pc87417
- device pnp 4e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 4e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 4e.2 off # Com 2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 4e.3 off # Com 1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 4e.4 off end # SWC
- device pnp 4e.5 off end # Mouse
- device pnp 4e.6 off # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 4e.7 off end # GPIO
- device pnp 4e.f off end # XBUS
- device pnp 4e.10 on #RTC
- io 0x60 = 0x70
- io 0x62 = 0x72
- end
- end # end superio
- end # end pci 1.2
- device pci 1.3 off end # WDTimer 0x0238
- device pci 1.4 on end # XIOAPIC0 0x0235
- device pci 1.5 on end # XIOAPIC1
- device pci 1.6 on end # XIOAPIC2
- device pci 2.0 on end # USB 0x0223
- device pci 2.1 on end # USB
- device pci 2.2 on end # USB
- device pci 3.0 on end # VGA
- end
- end
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end # amdk8
-
- end #domain
-end
diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c
deleted file mode 100644
index fc9c104a6c..0000000000
--- a/src/mainboard/hp/dl145_g3/get_bus_conf.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-static unsigned pci1234x[] =
-{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-static unsigned hcdnx[] =
-{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
-
- struct device *dev;
- int i;
- struct mb_sysconf_t *m;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.mb = &mb_sysconf;
-
- m = sysconf.mb;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
-
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
- m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780
-
- m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff;
- m->bus_bcm5780[0] = m->bus_bcm5785_0;
-
- /* bcm5785 */
- printk(BIOS_DEBUG, "search for def %d.0 on bus %d\n",sysconf.sbdn,m->bus_bcm5785_0);
- dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0));
- if (dev) {
- printk(BIOS_DEBUG, "found dev %s...\n",dev_path(dev));
- m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- printk(BIOS_DEBUG, "secondary is %d...\n",m->bus_bcm5785_1);
- dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0));
- printk(BIOS_DEBUG, "now found %s...\n",dev_path(dev));
- if (dev)
- m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn);
- }
-
- /* bcm5780 */
- for (i = 1; i < 6; i++) {
- dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0));
- if (dev)
- m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- else
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1);
- }
-
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(3);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- for (i = 0; i < 3; i++)
- m->apicid_bcm5785[i] = apicid_base+i;
-}
diff --git a/src/mainboard/hp/dl145_g3/irq_tables.c b/src/mainboard/hp/dl145_g3/irq_tables.c
deleted file mode 100644
index 6ec1fd8e79..0000000000
--- a/src/mainboard/hp/dl145_g3/irq_tables.c
+++ /dev/null
@@ -1,49 +0,0 @@
-#ifdef GETPIR
-#include "pirq_routing.h"
-#else
-#include <arch/pirq_routing.h>
-#endif
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0x0, /* Where the interrupt router lies (bus) */
- (0x2 << 3)|0x4,
- 0, /* IRQs devoted exclusively to PCI usage */
- 0, /* Vendor */
- 0, /* Device */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x2a, /* u8 checksum. This has to be set to some
- value that would give 0 after the sum of all
- bytes for this structure (including checksum) */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
- {0x00,(0x02 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge
- {0x00,(0x03 << 3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb
- {0x00,(0x04 << 3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr
- {0x00,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge
- {0x01,(0x0e << 3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA
- {0x01,(0x0d << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge
- //{0x02,(0x01 << 3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0},
- {0x00,(0x06 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- //{0x03,(0x00 << 3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0},
- {0x00,(0x07 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- {0x00,(0x08 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- {0x00,(0x09 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- //{0x06,(0x00 << 3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0},
- {0x00,(0x0a << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- //{0x07,(0x00 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
- {0x08,(0x04 << 3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet
- {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
- //{0x10,(0x01 << 3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0},
- {0x40,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/hp/dl145_g3/mb_sysconf.h b/src/mainboard/hp/dl145_g3/mb_sysconf.h
deleted file mode 100644
index 8b0e580057..0000000000
--- a/src/mainboard/hp/dl145_g3/mb_sysconf.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2007 University of Mannheim
- * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
- *
- * Copyright (C) 2009 University of Heidelberg
- * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_bcm5780[7];
- unsigned char bus_bcm5785_0;
- unsigned char bus_bcm5785_1;
- unsigned char bus_bcm5785_1_1;
- unsigned apicid_bcm5785[3];
-
- unsigned sbdn2;
-};
-
-#endif
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
deleted file mode 100644
index a6cdfb83d0..0000000000
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2001 Eric W.Biederman <ebiderman@lnxi.com>
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2007 University of Mannheim
- * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
- *
- * Copyright (C) 2009 University of Heidelberg
- * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-#include <cpu/amd/multicore.h>
-#endif
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- struct mb_sysconf_t *m;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- m = sysconf.mb;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev = NULL;
- int i;
- struct resource *res;
- for (i = 0; i < 3; i++) {
- dev = dev_find_device(0x1166, 0x0235, dev);
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i], res->base);
- smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11,
- res2mmio(res, 0, 0));
- }
- }
- }
-
- }
-
- /* IRQ routing as factory BIOS */
- outb(0x01, 0xc00); outb(0x0A, 0xc01);
- outb(0x17, 0xc00); outb(0x05, 0xc01);
-/* outb(0x2E, 0xc00); outb(0x0B, 0xc01); */
-/* outb(0x07, 0xc00); outb(0x07, 0xc01); */
- outb(0x07, 0xc00); outb(0x0b, 0xc01);
-
- outb(0x24, 0xc00); outb(0x05, 0xc01);
- //outb(0x00, 0xc00); outb(0x09, 0xc01);
- outb(0x02, 0xc00); outb(0x0E, 0xc01);
-
- // 8259 registers...
- outb(0xa0, 0x4d0);
- outb(0x0e, 0x4d1);
-
- {
- struct device *dev;
- dev = dev_find_device(0x1166, 0x0205, 0);
- if(dev) {
- uint32_t dword;
- dword = pci_read_config32(dev, 0x64);
- dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7
- pci_write_config32(dev, 0x64, dword);
- }
- // set GEVENT pins to NO OP
- outb(0x33, 0xcd6); outb(0x00, 0xcd7);
- outb(0x34, 0xcd6); outb(0x00, 0xcd7);
- outb(0x35, 0xcd6); outb(0x00, 0xcd7);
- }
-
- // hide XIOAPIC PCI configuration space
- {
- struct device *dev;
- dev = dev_find_device(0x1166, 0x205, 0);
- if (dev) {
- uint32_t dword;
- dword = pci_read_config32(dev, 0x64);
- dword |= (1 << 26);
- pci_write_config32(dev, 0x64, dword);
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
-
- //SATA
-/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */
-/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */
- printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb);
- //USB
- printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x\n",sysconf.sbdn, m->bus_bcm5785_0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03 << 2)|0, m->apicid_bcm5785[0], 0xa);
-
- //VGA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4 << 2)|0, m->apicid_bcm5785[1], 0x7);
-
- //PCIE
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0xe);
-
- //IDE
-// outb(0x02, 0xc00); outb(0x0e, 0xc01);
-// printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe);
-// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02 << 2)|1, m->apicid_bcm5785[0], 0xe);
-
- //onboard Broadcom GbE
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|0, m->apicid_bcm5785[2], 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|1, m->apicid_bcm5785[2], 0x4);
-
-
-
- /* enable int */
- /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
- {
- struct device *dev;
- dev = dev_find_device(0x1166, 0x0205, 0);
- if(dev) {
- uint32_t dword;
- dword = pci_read_config32(dev, 0x6c);
- dword |= (1 << 4); // enable interrupts
- printk(BIOS_DEBUG, "6ch: %x\n",dword);
- pci_write_config32(dev, 0x6c, dword);
- }
- }
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- printk(BIOS_DEBUG, "bus_isa is: %x\n", bus_isa);
- mptable_lintsrc(mc, bus_isa);
-
- //extended table entries
- smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
- smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80);
- smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100);
- smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0);
- smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f);
- smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006);
- smp_write_bus_hierarchy(mc, 9, 0x01, 0);
- smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0);
- smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1);
-
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
deleted file mode 100644
index 1b25e8cd90..0000000000
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Tyan
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
- *
- * Copyright (C) 2007 University of Mannheim
- * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
- * Copyright (C) 2009 University of Heidelberg
- * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/broadcom/bcm5785/early_smbus.c"
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include <superio/serverengines/pilot/pilot.h>
-#include <superio/nsc/pc87417/pc87417.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
-#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
-
-unsigned get_sbdn(unsigned bus);
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#define SMBUS_SWITCH1 0x70
-#define SMBUS_SWITCH2 0x72
- unsigned device = (ctrl->channel0[0]) >> 8;
- smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
- smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
-}
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "southbridge/broadcom/bcm5785/early_setup.c"
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include <spd.h>
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-#if 0
-#include "ipmi.c"
-
-static void setup_early_ipmi_serial()
-{
- unsigned char result;
- char channel_access[]={0x06 << 2,0x40,0x04,0x80,0x05};
- char serialmodem_conf[]={0x0c << 2,0x10,0x04,0x08,0x00,0x0f};
- char serial_mux1[]={0x0c << 2,0x12,0x04,0x06};
- char serial_mux2[]={0x0c << 2,0x12,0x04,0x03};
- char serial_mux3[]={0x0c << 2,0x12,0x04,0x07};
-
-// earlydbg(0x0d);
- //set channel access system only
- ipmi_request(5,channel_access);
-// earlydbg(result);
-/*
- //Set serial/modem config
- result = ipmi_request(6,serialmodem_conf);
- earlydbg(result);
-
- //Set serial mux 1
- result = ipmi_request(4,serial_mux1);
- earlydbg(result);
-
- //Set serial mux 2
- result = ipmi_request(4,serial_mux2);
- earlydbg(result);
-
- //Set serial mux 3
- result = ipmi_request(4,serial_mux3);
- earlydbg(result);
-*/
-// earlydbg(0x0e);
-
-}
-#endif
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // first node
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // second node
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset;
- unsigned bsp_apicid = 0;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- bcm5785_enable_lpc();
- pc87417_enable_dev(RTC_DEV); /* Enable RTC */
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
-// setup_early_ipmi_serial();
- pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
- setup_coherent_ht_domain();
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
- bcm5785_early_setup();
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo);
- }
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo);
- }
-#endif
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
-
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- enable_smbus();
-
- //do we need apci timer, tsc...., only debug need it for better output
- /* all ap stopped? */
- // init_timer(); // Need to use TMICT to synchronize FID/VID
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/iwill/Kconfig b/src/mainboard/iwill/Kconfig
deleted file mode 100644
index 75fa626b60..0000000000
--- a/src/mainboard/iwill/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_IWILL
-
-choice
- prompt "Mainboard model"
-
-source "src/mainboard/iwill/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/iwill/*/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "IWILL"
-
-endif # VENDOR_IWILL
diff --git a/src/mainboard/iwill/Kconfig.name b/src/mainboard/iwill/Kconfig.name
deleted file mode 100644
index 026608bec6..0000000000
--- a/src/mainboard/iwill/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_IWILL
- bool "IWILL"
diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig
deleted file mode 100644
index 929f47f540..0000000000
--- a/src/mainboard/iwill/dk8_htx/Kconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-if BOARD_IWILL_DK8_HTX
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_940
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_AMD8111
- select SOUTHBRIDGE_AMD_AMD8131
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_WINBOND_W83627HF
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_512
- select RAMINIT_SYSINFO
- select QRANK_DIMM_SUPPORT
-
-config MAINBOARD_DIR
- string
- default iwill/dk8_htx
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "DK8-HTX"
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x6
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0xa
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_IWILL_DK8_HTX
diff --git a/src/mainboard/iwill/dk8_htx/Kconfig.name b/src/mainboard/iwill/dk8_htx/Kconfig.name
deleted file mode 100644
index 8d81fc199d..0000000000
--- a/src/mainboard/iwill/dk8_htx/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_IWILL_DK8_HTX
- bool "DK8-HTX"
diff --git a/src/mainboard/iwill/dk8_htx/Makefile.inc b/src/mainboard/iwill/dk8_htx/Makefile.inc
deleted file mode 100644
index e826e8153a..0000000000
--- a/src/mainboard/iwill/dk8_htx/Makefile.inc
+++ /dev/null
@@ -1,4 +0,0 @@
-$(eval $(call asl_template,ssdt2))
-$(eval $(call asl_template,ssdt3))
-$(eval $(call asl_template,ssdt4))
-$(eval $(call asl_template,ssdt5))
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl
deleted file mode 100644
index df722f8862..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright 2005 AMD
- */
-//AMD8111
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
- })
-
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
- // Update the Device Number according to SBDN
- Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
-
- Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) {
- Return (PICM)
- }
- Else {
- Return (APIC)
- }
- }
-
- Device (SBC3)
- {
- /* ACPI smbus it should be 0x00040003 if 8131 present */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
- }
- OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
- Field (PIRQ, ByteAcc, Lock, Preserve)
- {
- PIBA, 8,
- PIDC, 8
- }
-/*
- OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
- Field (TS3_, DWordAcc, NoLock, Preserve)
- {
- PTS3, 16
- }
-*/
- }
-
- Device (HPET)
- {
- Name (HPT, 0x00)
- Name (_HID, EisaId ("PNP0103"))
- Name (_UID, 0x00)
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
- })
- Return (BUF0)
- }
- }
-
- #include "amd8111_pic.asl"
-
- #include "amd8111_isa.asl"
-
- Device (TP2P)
- {
- /* 8111 P2P and it should 0x00030000 when 8131 present*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x08, 0x03 }) }
- Else { Return (Package (0x02) { 0x08, 0x01 }) }
- }
-
- Device (USB0)
- {
- Name (_ADR, 0x00000000)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Device (USB1)
- {
- Name (_ADR, 0x00000001)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Name (APIC, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
- })
-
- Name (PICM, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 6
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 5
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
- })
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl
deleted file mode 100644
index 6054b53d5e..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl
+++ /dev/null
@@ -1,178 +0,0 @@
-#include <arch/ioapic.h>
-#include <cpu/x86/lapic_def.h>
-
-/*
- * Copyright 2005 AMD
- */
-//AMD8111 isa
-
- Device (ISA)
- {
- /* lpc 0x00040000 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
- }
-
- OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
- Field (PIRY, ByteAcc, NoLock, Preserve)
- {
- Z000, 2, // Parallel Port Range
- , 1,
- ECP, 1, // ECP Enable
- FDC1, 1, // Floppy Drive Controller 1
- FDC2, 1, // Floppy Drive Controller 2
- Offset (0x01),
- Z001, 3, // Serial Port A Range
- SAEN, 1, // Serial Post A Enabled
- Z002, 3, // Serial Port B Range
- SBEN, 1 // Serial Post B Enabled
- }
-
- Device (PIC)
- {
- Name (_HID, EisaId ("PNP0000"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
- IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
- IRQ (Edge, ActiveHigh, Exclusive) {2}
- })
- }
-
- Device (DMA1)
- {
- Name (_HID, EisaId ("PNP0200"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
- IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
- IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
- DMA (Compatibility, NotBusMaster, Transfer16) {4}
- })
- }
-
- Device (TMR)
- {
- Name (_HID, EisaId ("PNP0100"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
- IRQ (Edge, ActiveHigh, Exclusive) {0}
- })
- }
-
- Device (RTC)
- {
- Name (_HID, EisaId ("PNP0B00"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
- IRQ (Edge, ActiveHigh, Exclusive) {8}
- })
- }
-
- Device (SPKR)
- {
- Name (_HID, EisaId ("PNP0800"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
- })
- }
-
- Device (COPR)
- {
- Name (_HID, EisaId ("PNP0C04"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
- IRQ (Edge, ActiveHigh, Exclusive) {13}
- })
- }
-
- Device (SYSR)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x00)
- Name (SYR1, ResourceTemplate ()
- {
- IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM
- IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
- IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
- IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
- IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
- IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
- IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
- IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
- IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
- IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
- IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
- IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
- IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- })
- Method (_CRS, 0, NotSerialized)
- {
- Return (SYR1)
- }
- }
-
- Device (MEM)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
- Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404
- Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000)
- Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
- Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000)
- Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
- })
- // Read the Video Memory length
- CreateDWordField (BUF0, 0x14, CLEN)
- CreateDWordField (BUF0, 0x10, CBAS)
-
- ShiftLeft (VGA1, 0x09, Local0)
- Store (Local0, CLEN)
-
- Return (BUF0)
- }
- }
-
- Device (PS2M)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Name (_CRS, ResourceTemplate ()
- {
- IRQNoFlags () {12}
- })
- Method (_STA, 0, NotSerialized)
- {
- And (FLG0, 0x04, Local0)
- If (LEqual (Local0, 0x04)) { Return (0x0F) }
- Else { Return (0x00) }
- }
- }
-
- Device (PS2K)
- {
- Name (_HID, EisaId ("PNP0303"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- }
- #include "superio.asl"
-
- }
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111_pic.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111_pic.asl
deleted file mode 100644
index fd1df7d034..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/amd8111_pic.asl
+++ /dev/null
@@ -1,354 +0,0 @@
-/*
- * Copyright 2005 AMD
- */
-//AMD8111 pic LNKA B C D
-
- Device (LNKA)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x01)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
- Else { Return (0x0B) } //Enabled
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- { // Routing enable
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKB)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKC)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x03)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
-
- Device (LNKD)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x04)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl
deleted file mode 100644
index 6d93e02048..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright 2005 AMD
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x14)
- {
- // Slot 3 - PIRQ BCDA ---- verified
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
-
- //Slot 4 - PIRQ CDAB ---- verified
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //?
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
-
- //Onboard NIC 1 - PIRQ DABC
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //?
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A },
-
- // NIC 2 - PIRQ ABCD -- verified
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //?
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B },
-
- //SERIAL ATA - PIRQ BCDA
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //?
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 }
- })
- Name (PICM, Package (0x14)
- {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-
- Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
-
- Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ CDAB -- verfied
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1E },// Slot 2
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1F },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1C },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1D }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2
- Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl
deleted file mode 100644
index 6eb95ec724..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2005 AMD
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
-
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl
deleted file mode 100644
index 9c0629f779..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2005 AMD
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
-
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl
deleted file mode 100644
index 995aa10475..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl
+++ /dev/null
@@ -1,28 +0,0 @@
-// AMD8151
- Device (AGPB)
- {
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
diff --git a/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl b/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl
deleted file mode 100644
index 7301fef998..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright 2006 AMD
- */
-
- Device (HTXA)
- {
- /* HTX */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- }
diff --git a/src/mainboard/iwill/dk8_htx/acpi/pci0_hc.asl b/src/mainboard/iwill/dk8_htx/acpi/pci0_hc.asl
deleted file mode 100644
index 2fd3b09de4..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/pci0_hc.asl
+++ /dev/null
@@ -1,2 +0,0 @@
- #include "amd8111.asl" //real SB at first
- #include "amd8131.asl"
diff --git a/src/mainboard/iwill/dk8_htx/acpi/pci2_hc.asl b/src/mainboard/iwill/dk8_htx/acpi/pci2_hc.asl
deleted file mode 100644
index fd3ad2c3e3..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/pci2_hc.asl
+++ /dev/null
@@ -1 +0,0 @@
- #include "amd8132_2.asl"
diff --git a/src/mainboard/iwill/dk8_htx/acpi/pci3_hc.asl b/src/mainboard/iwill/dk8_htx/acpi/pci3_hc.asl
deleted file mode 100644
index 070ebe5286..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/pci3_hc.asl
+++ /dev/null
@@ -1 +0,0 @@
- #include "amd8151.asl"
diff --git a/src/mainboard/iwill/dk8_htx/acpi/pci4_hc.asl b/src/mainboard/iwill/dk8_htx/acpi/pci4_hc.asl
deleted file mode 100644
index bd3f70ea0f..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/pci4_hc.asl
+++ /dev/null
@@ -1 +0,0 @@
- #include "amd8131_2.asl"
diff --git a/src/mainboard/iwill/dk8_htx/acpi/pci5_hc.asl b/src/mainboard/iwill/dk8_htx/acpi/pci5_hc.asl
deleted file mode 100644
index f7f0a7dbad..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/pci5_hc.asl
+++ /dev/null
@@ -1 +0,0 @@
- #include "htx_no_ioapic.asl"
diff --git a/src/mainboard/iwill/dk8_htx/acpi/superio.asl b/src/mainboard/iwill/dk8_htx/acpi/superio.asl
deleted file mode 100644
index 83ee58253d..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi/superio.asl
+++ /dev/null
@@ -1 +0,0 @@
-// #include "w83627hf.asl"
diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c
deleted file mode 100644
index 957be79ca3..0000000000
--- a/src/mainboard/iwill/dk8_htx/acpi_tables.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Island Aruma ACPI support
- * written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
- *
- *
- * Copyright 2005 AMD
- * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include "mb_sysconf.h"
-#include "mainboard.h"
-#include <cbfs.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
-
- struct mb_sysconf_t *m;
-
- get_bus_conf();
-
- m = sysconf.mb;
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write 8111 IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111,
- IO_APIC_ADDR, 0);
-
- /* Write all 8131 IOAPICs */
- {
- struct device *dev;
- struct resource *res;
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1,
- res->base, gsi_base );
- gsi_base+=4;
-
- }
- }
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2,
- res->base, gsi_base );
- gsi_base+=4;
- }
- }
-
- int i;
- int j = 0;
-
- for(i = 1; i< sysconf.hc_possible_num; i++) {
- unsigned d = 0;
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
- // 8131 need to use +4
-
- switch (sysconf.hcid[i]) {
- case 1:
- d = 7;
- break;
- case 3:
- d = 4;
- break;
- }
- switch (sysconf.hcid[i]) {
- case 1:
- case 3:
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
- res->base, gsi_base );
- gsi_base+=d;
- }
- }
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
- res->base, gsi_base );
- gsi_base+=d;
-
- }
- }
- break;
- }
-
- j++;
- }
-
- }
-
- current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 5 );
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high*/
-
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapic_nmis(current, 5, 1);
- /* 1: LINT1 connect to NMI */
-
-
- return current;
-}
-
-unsigned long mainboard_write_acpi_tables(struct device *device,
- unsigned long start,
- acpi_rsdp_t *rsdp)
-{
- unsigned long current;
- acpi_header_t *ssdtx;
- const void *p;
- size_t p_size;
-
- int i;
-
- get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
-
- /* Align ACPI tables to 16byte */
- start = ALIGN(start, 16);
- current = start;
-
- //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
-
- for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink
- const char *file_name;
- if((sysconf.pci1234[i] & 1) != 1 ) continue;
- uint8_t c;
- if(i < 7) {
- c = (uint8_t) ('4' + i - 1);
- }
- else {
- c = (uint8_t) ('A' + i - 1 - 6);
- }
- printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
- current = ALIGN(current, 8);
- ssdtx = (acpi_header_t *)current;
- switch(sysconf.hcid[i]) {
- case 1: //8132
- file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml";
- break;
- case 2: //8151
- file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml";
- break;
- case 3: //8131
- file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml";
- break;
- default:
- //HTX no io apic
- file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml";
- break;
- }
- p = cbfs_boot_map_with_leak(
- file_name,
- CBFS_TYPE_RAW, &p_size);
- if (!p || p_size < sizeof(acpi_header_t))
- continue;
-
- memcpy(ssdtx, p, sizeof(acpi_header_t));
- current += ssdtx->length;
- memcpy(ssdtx, p, ssdtx->length);
- update_ssdtx((void *)ssdtx, i);
- ssdtx->checksum = 0;
- ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length);
- acpi_add_table(rsdp,ssdtx);
- }
-
- return current;
-}
diff --git a/src/mainboard/iwill/dk8_htx/board_info.txt b/src/mainboard/iwill/dk8_htx/board_info.txt
deleted file mode 100644
index 4211c8d532..0000000000
--- a/src/mainboard/iwill/dk8_htx/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Category: server
-Board URL: http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.asp?p_id=98
-Flashrom support: y
diff --git a/src/mainboard/iwill/dk8_htx/cmos.layout b/src/mainboard/iwill/dk8_htx/cmos.layout
deleted file mode 100644
index 56ed652b97..0000000000
--- a/src/mainboard/iwill/dk8_htx/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 400Mhz
-8 1 333Mhz
-8 2 266Mhz
-8 3 200Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb
deleted file mode 100644
index c49c97a048..0000000000
--- a/src/mainboard/iwill/dk8_htx/devicetree.cb
+++ /dev/null
@@ -1,117 +0,0 @@
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_940
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1022 0x2b80 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.0 on # northbridge
- chip southbridge/amd/amd8131
- # the on/off keyword is mandatory
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on end
- device pci 1.1 on end
- end
- chip southbridge/amd/amd8111
- # this "device pci 0.0" is the parent the next one
- # PCI bridge
- device pci 0.0 on
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 0.2 off end
- device pci 1.0 off end
- end
- device pci 1.0 on
- chip superio/winbond/w83627hf
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # CIR
- io 0x60 = 0x100
- end
- device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 on # GPIO2
- io 0x07 = 0x08ff
- io 0x30 = 0x01ff
- io 0x2b = 0xd0ff
- io 0xf0 = 0xef16
- end
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on end
- device pci 1.2 on end
- device pci 1.3 on
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic #dimm 1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic #dimm 1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic #dimm 1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic #dimm 1-1-1
- device i2c 57 on end
- end
- end # acpi
- device pci 1.5 off end
- device pci 1.6 off end
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- end
- end # device pci 18.0
-
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
-
- end #domain
-end
diff --git a/src/mainboard/iwill/dk8_htx/dsdt.asl b/src/mainboard/iwill/dk8_htx/dsdt.asl
deleted file mode 100644
index e1e6341a72..0000000000
--- a/src/mainboard/iwill/dk8_htx/dsdt.asl
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_PR)
- {
- Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
- Processor (CPU1, 0x01, 0x00000000, 0x00) {}
- Processor (CPU2, 0x02, 0x00000000, 0x00) {}
- Processor (CPU3, 0x03, 0x00000000, 0x00) {}
-
- }
-
- Method (FWSO, 0, NotSerialized) { }
-
- Scope (_SB)
- {
- Device (PCI0)
- {
- /* BUS0 root bus */
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
- External (CBST)
-
-
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00180000)
- Name (_UID, 0x01)
-
- Name (HCIN, 0x00) // HC1
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
- IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
- IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x8100, // Address Range Minimum
- 0xFFFF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x7F00,,,
- , TypeStatic) //8100h-FFFFh
-
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, // Address Space Granularity
- 0x000C0000, // Address Range Minimum
- 0x000CFFFF, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00010000,,,
- , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
-
- Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x03AF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x03B0,,,
- , TypeStatic) //0-CF7h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x03E0, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0918,,,
- , TypeStatic) //0-CF7h
- })
- \_SB.OSVR ()
- CreateDWordField (BUF0, 0x3E, VLEN)
- CreateDWordField (BUF0, 0x36, VMAX)
- CreateDWordField (BUF0, 0x32, VMIN)
- ShiftLeft (VGA1, 0x09, Local0)
- Add (VMIN, Local0, VMAX)
- Decrement (VMAX)
- Store (Local0, VLEN)
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- #include "acpi/pci0_hc.asl"
-
- }
- Device (PCI1)
- {
- Name (_HID, "PNP0A03")
- Name (_ADR, 0x00000000)
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.PCI0.CBST)
- }
- Name (_BBN, 0x00)
- }
-
-
- }
-
- Scope (_GPE)
- {
- Method (_L08, 0, NotSerialized)
- {
- Notify (\_SB.PCI0, 0x02) //PME# Wakeup
- }
-
- Method (_L0F, 0, NotSerialized)
- {
- Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
- }
-
- Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
- {
- Notify (\_SB.PCI0.PG0B, 0x02)
- }
-
- Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
- {
- Notify (\_SB.PCI0.PG0A, 0x02)
- }
- }
-
- Method (_PTS, 1, NotSerialized)
- {
- Or (Arg0, 0xF0, Local0)
- Store (Local0, DBG1)
- }
-/*
- Method (_WAK, 1, NotSerialized)
- {
- Or (Arg0, 0xE0, Local0)
- Store (Local0, DBG1)
- }
-*/
- Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
- Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
- {
- Store (Arg0, PICF)
- }
-
- OperationRegion (DEBG, SystemIO, 0x80, 0x01)
- Field (DEBG, ByteAcc, Lock, Preserve)
- {
- DBG1, 8
- }
-
- OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
- Field (EXTM, WordAcc, Lock, Preserve)
- {
- AMEM, 32
- }
-
- OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
- Field (VGAM, ByteAcc, Lock, Preserve)
- {
- VGA1, 8
- }
-
- OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
- Field (GRAM, ByteAcc, Lock, Preserve)
- {
- Offset (0x10),
- FLG0, 8
- }
-
- OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
- Field (GSTS, ByteAcc, NoLock, Preserve)
- {
- , 4,
- IRQR, 1
- }
-
- OperationRegion (Z007, SystemIO, 0x21, 0x01)
- Field (Z007, ByteAcc, NoLock, Preserve)
- {
- Z008, 8
- }
-
- OperationRegion (Z009, SystemIO, 0xA1, 0x01)
- Field (Z009, ByteAcc, NoLock, Preserve)
- {
- Z00A, 8
- }
-
- #include "northbridge/amd/amdk8/util.asl"
-
-}
diff --git a/src/mainboard/iwill/dk8_htx/fadt.c b/src/mainboard/iwill/dk8_htx/fadt.c
deleted file mode 100644
index 5a7c2a789f..0000000000
--- a/src/mainboard/iwill/dk8_htx/fadt.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- * (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org>
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-
-extern unsigned pm_base; /* pm_base should be set in sb ACPI */
-
-void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
-
- acpi_header_t *header=&(fadt->header);
-
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
- /* Prepare the header */
- memset((void *)fadt,0,sizeof(acpi_fadt_t));
- memcpy(header->signature,"FACP",4);
- header->length = 244;
- header->revision = 3;
- memcpy(header->oem_id,OEM_ID,6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id,ASLC,4);
- header->asl_compiler_revision = 0;
-
- fadt->firmware_ctrl=(u32)facs;
- fadt->dsdt= (u32)dsdt;
- // 3=Workstation, 4=Enterprise Server, 7=Performance Server
- fadt->preferred_pm_profile = 0x03;
- fadt->sci_int = 9;
- // disable system management mode by setting to 0:
- fadt->smi_cmd = 0;//pm_base+0x2f;
- fadt->acpi_enable = 0xf0;
- fadt->acpi_disable = 0xf1;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0xe2;
-
- fadt->pm1a_evt_blk = pm_base;
- fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = pm_base+0x04;
- fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = 0x0000;
- fadt->pm_tmr_blk = pm_base+0x08;
- fadt->gpe0_blk = pm_base+0x20;
- fadt->gpe1_blk = pm_base+0xb0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 0;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 4;
- fadt->gpe1_blk_len = 8;
- fadt->gpe1_base = 16;
-
- fadt->cst_cnt = 0xe3;
- fadt->p_lvl2_lat = 101;
- fadt->p_lvl3_lat = 1001;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 1;
- fadt->duty_width = 3;
- fadt->day_alrm = 0; // 0x7d these have to be
- fadt->mon_alrm = 0; // 0x7e added to cmos.layout
- fadt->century = 0; // 0x7f to make rtc alrm work
- fadt->iapc_boot_arch = 0x3; // See table 5-11
- fadt->flags = 0x25;
-
- fadt->res2 = 0;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 6;
- fadt->x_firmware_ctl_l = (u32)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = pm_base;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 4;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = pm_base+4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 2;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = 0x0;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = pm_base+0x08;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 32;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = pm_base+0x20;
- fadt->x_gpe0_blk.addrh = 0x0;
-
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 64;
- fadt->x_gpe1_blk.bit_offset = 16;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = pm_base+0xb0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-
-}
diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
deleted file mode 100644
index 1121fb3689..0000000000
--- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c
+++ /dev/null
@@ -1,217 +0,0 @@
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include <stdlib.h>
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0, // SB chain m
- 0x0000000, // HTX
- 0x0000100, // co processor on socket 1
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
- 0x20202020,
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-static unsigned get_hcid(unsigned i)
-{
- unsigned id = 0;
-
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-
- unsigned devn = sysconf.hcdn[i] & 0xff;
-
- struct device *dev;
-
- dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
-
- switch (dev->device) {
- case 0x7458: //8132
- id = 1;
- break;
- case 0x7454: //8151
- id = 2;
- break;
- case 0x7450: //8131
- id = 3;
- break;
- }
-
- // we may need more way to find out hcid: subsystem id? GPIO read ?
-
- // we need use id for 1. bus num, 2. mptable, 3. ACPI table
-
- return id;
-}
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
-
- struct device *dev;
- int i, j;
- struct mb_sysconf_t *m;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.mb = &mb_sysconf;
-
- m = sysconf.mb;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
- m->sbdn3 = sysconf.hcdn[0] & 0xff;
-
- m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff;
- m->bus_8111_0 = m->bus_8132_0;
-
- /* 8111 */
- dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn, 0));
- if (dev) {
- m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_8111_0, sysconf.sbdn);
- }
-
- /* 8132-1 */
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 0));
- if (dev) {
- m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_8132_0, m->sbdn3);
- }
-
- /* 8132-2 */
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3 + 1, 0));
- if (dev) {
- m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_8132_0, m->sbdn3 + 1);
- }
-
- /* HT chain 1 */
- j = 0;
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
-
- // check hcid type here
- sysconf.hcid[i] = get_hcid(i);
-
- switch (sysconf.hcid[i]) {
-
- case 1: //8132
- case 3: //8131
-
- m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
-
- m->sbdn3a[j] = sysconf.hcdn[i] & 0xff;
-
- /* 8132-1 */
- dev =
- dev_find_slot(m->bus_8132a[j][0],
- PCI_DEVFN(m->sbdn3a[j], 0));
- if (dev) {
- m->bus_8132a[j][1] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_8132a[j][0], m->sbdn3a[j]);
- }
-
- /* 8132-2 */
- dev =
- dev_find_slot(m->bus_8132a[j][0],
- PCI_DEVFN(m->sbdn3a[j] + 1, 0));
- if (dev) {
- m->bus_8132a[j][2] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_8132a[j][0], m->sbdn3a[j] + 1);
- }
-
- break;
-
- case 2: //8151
-
- m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
- m->sbdn5[j] = sysconf.hcdn[i] & 0xff;
- /* 8151 */
- dev =
- dev_find_slot(m->bus_8151[j][0],
- PCI_DEVFN(m->sbdn5[j] + 1, 0));
-
- if (dev) {
- m->bus_8151[j][1] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_8151[j][0], m->sbdn5[j] + 1);
- }
-
- break;
- }
-
- j++;
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(3);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- m->apicid_8111 = apicid_base + 0;
- m->apicid_8132_1 = apicid_base + 1;
- m->apicid_8132_2 = apicid_base + 2;
- for (i = 0; i < j; i++) {
- m->apicid_8132a[i][0] = apicid_base + 3 + i * 2;
- m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1;
- }
-
-}
diff --git a/src/mainboard/iwill/dk8_htx/irq_tables.c b/src/mainboard/iwill/dk8_htx/irq_tables.c
deleted file mode 100644
index 33d4837a5d..0000000000
--- a/src/mainboard/iwill/dk8_htx/irq_tables.c
+++ /dev/null
@@ -1,148 +0,0 @@
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
-
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
-
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
-
- uint8_t sum = 0;
- int i;
-
- struct mb_sysconf_t *m;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
-
- m = sysconf.mb;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = m->bus_8111_0;
- pirq->rtr_devfn = ((sysconf.sbdn + 1) << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1022;
- pirq->rtr_device = 0x746b;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- {
- struct device *dev;
- dev =
- dev_find_slot(m->bus_8111_0,
- PCI_DEVFN(sysconf.sbdn + 1, 3));
- if (dev) {
- /* initialize PCI interupts - these assignments depend
- on the PCB routing of PINTA-D
-
- PINTA = IRQ3
- PINTB = IRQ5
- PINTC = IRQ10
- PINTD = IRQ11
- */
- pci_write_config16(dev, 0x56, 0xba53);
- }
- }
-
-//pci bridge
- printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n");
- static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 };
- pci_assign_irqs(m->bus_8111_0, sysconf.sbdn + 1, slotIrqs_1_4);
- write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-
- printk(BIOS_DEBUG, "setting Onboard AMD USB\n");
- static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11 };
- pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0);
- write_pirq_info(pirq_info, m->bus_8111_1, 0, 0, 0, 0, 0, 0, 0, 0x4,
- 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
-//pcix bridge
-// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-// pirq_info++; slot_num++;
-
- int j = 0;
-
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
- unsigned devn = sysconf.hcdn[i] & 0xff;
-
- write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8,
- 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
- j++;
-
- }
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/iwill/dk8_htx/mainboard.c b/src/mainboard/iwill/dk8_htx/mainboard.c
deleted file mode 100644
index 905a0d5f8f..0000000000
--- a/src/mainboard/iwill/dk8_htx/mainboard.c
+++ /dev/null
@@ -1,17 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/acpi.h>
-#include <cpu/amd/powernow.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mainboard.h"
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/iwill/dk8_htx/mainboard.h b/src/mainboard/iwill/dk8_htx/mainboard.h
deleted file mode 100644
index 111b4457ca..0000000000
--- a/src/mainboard/iwill/dk8_htx/mainboard.h
+++ /dev/null
@@ -1 +0,0 @@
-unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start, acpi_rsdp_t *rsdp);
diff --git a/src/mainboard/iwill/dk8_htx/mb_sysconf.h b/src/mainboard/iwill/dk8_htx/mb_sysconf.h
deleted file mode 100644
index 4933d480ed..0000000000
--- a/src/mainboard/iwill/dk8_htx/mb_sysconf.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef MB_SYSCONF_H
-
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_8132_0;
- unsigned char bus_8132_1;
- unsigned char bus_8132_2;
- unsigned char bus_8111_0;
- unsigned char bus_8111_1;
-
- unsigned char bus_8132a[7][3];
-
- unsigned char bus_8151[7][2];
-
- unsigned apicid_8111;
- unsigned apicid_8132_1;
- unsigned apicid_8132_2;
- unsigned apicid_8132a[7][2];
-
- unsigned sbdn3;
- unsigned sbdn3a[7];
- unsigned sbdn5[7];
-
-};
-
-#endif
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
deleted file mode 100644
index daf9b421f0..0000000000
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ /dev/null
@@ -1,186 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-#include <cpu/amd/multicore.h>
-#endif
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int i, j, bus_isa;
- struct mb_sysconf_t *m;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- m = sysconf.mb;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
- {
- struct device *dev;
- struct resource *res;
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
- res2mmio(res, 0, 0));
- }
- }
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
- res2mmio(res, 0, 0));
- }
- }
-
- j = 0;
-
- for(i = 1; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
-
- switch(sysconf.hcid[i]) {
- case 1: // 8132
- case 3: // 8131
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
- res2mmio(res, 0, 0));
- }
- }
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
- res2mmio(res, 0, 0));
- }
- }
- break;
- }
- j++;
- }
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
-
-//??? What
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
-
-// Onboard AMD USB
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
-
-// Onboard VGA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6 << 2)|0, m->apicid_8111, 0x12);
-
-//Slot 5 PCI 32
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
- }
-
-//Slot 6 PCI 32
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
- }
-//Slot 1: HTX
-
-//Slot 2 PCI-X 133/100/66
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2 << 2)|i, m->apicid_8132_2, (2+i)%4); //30
- }
-
-//Slot 3 PCI-X 133/100/66
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
- }
-
-//Slot 4 PCI-X 133/100/66
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2 << 2)|i, m->apicid_8132_1, (2+i)%4); //26
- }
-
-//Onboard NICS
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3 << 2)|0, m->apicid_8132_1, 3); //27
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4 << 2)|0, m->apicid_8132_1, 0); //24
-
-//Onboard SATA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5 << 2)|0, m->apicid_8132_1, 1); //25
-
- j = 0;
-
- for(i = 1; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
- int ii;
- struct device *dev;
- struct resource *res;
- switch(sysconf.hcid[i]) {
- case 1:
- case 3:
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- //Slot 1 PCI-X 133/100/66
- for(ii = 0; ii < 4; ii++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
- }
- }
- }
-
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- //Slot 2 PCI-X 133/100/66
- for(ii = 0; ii < 4; ii++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
- }
- }
- }
-
- break;
- case 2:
-
- // Slot AGP
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
- break;
- }
-
- j++;
- }
-
-
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/iwill/dk8_htx/resourcemap.c b/src/mainboard/iwill/dk8_htx/resourcemap.c
deleted file mode 100644
index 11e80eadce..0000000000
--- a/src/mainboard/iwill/dk8_htx/resourcemap.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- *
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000203, // AMD 8111 on link0 of CPU 0
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
deleted file mode 100644
index f573cf58f9..0000000000
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ /dev/null
@@ -1,163 +0,0 @@
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/early_smbus.c"
-#include <northbridge/amd/amdk8/raminit.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include <delay.h>
-
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-unsigned get_sbdn(unsigned bus);
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- /* Set the memreset low. */
- outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines. */
- outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 29);
- } else {
- /* Ensure the CPU has control of the memory lines. */
- outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 29);
- }
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- /* Set memreset_high */
- outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 28);
- udelay(90);
- }
-}
-
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "southbridge/amd/amd8111/early_ctrl.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // first node
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // second node
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset;
- unsigned bsp_apicid = 0;
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
- setup_mb_resource_map();
-
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- setup_coherent_ht_domain(); // routing table and start other core0
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-#endif
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
-
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
-#if 0
- dump_smbus_registers();
-#endif
-
- memreset_setup();
-
- //do we need apci timer, tsc...., only debug need it for better output
- /* all ap stopped? */
- init_timer(); // Need to use TMICT to synchronize FID/VID
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
-#if 0
- dump_pci_devices();
-#endif
-}
diff --git a/src/mainboard/iwill/dk8_htx/ssdt2.asl b/src/mainboard/iwill/dk8_htx/ssdt2.asl
deleted file mode 100644
index a86594bf9f..0000000000
--- a/src/mainboard/iwill/dk8_htx/ssdt2.asl
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- #include "acpi/pci2_hc.asl"
- }
- }
-
-}
diff --git a/src/mainboard/iwill/dk8_htx/ssdt3.asl b/src/mainboard/iwill/dk8_htx/ssdt3.asl
deleted file mode 100644
index e4f299096f..0000000000
--- a/src/mainboard/iwill/dk8_htx/ssdt3.asl
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- #include "acpi/pci3_hc.asl"
- }
- }
-
-}
diff --git a/src/mainboard/iwill/dk8_htx/ssdt4.asl b/src/mainboard/iwill/dk8_htx/ssdt4.asl
deleted file mode 100644
index 71a02efd8a..0000000000
--- a/src/mainboard/iwill/dk8_htx/ssdt4.asl
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- #include "acpi/pci4_hc.asl"
- }
- }
-
-}
diff --git a/src/mainboard/iwill/dk8_htx/ssdt5.asl b/src/mainboard/iwill/dk8_htx/ssdt5.asl
deleted file mode 100644
index 37886a9f99..0000000000
--- a/src/mainboard/iwill/dk8_htx/ssdt5.asl
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- #include "acpi/pci5_hc.asl"
- }
- }
-
-}
diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig
deleted file mode 100644
index e679e66154..0000000000
--- a/src/mainboard/kontron/kt690/Kconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-if BOARD_KONTRON_KT690
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_S1G1
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_RS690
- select SOUTHBRIDGE_AMD_SB600
- select SUPERIO_WINBOND_W83627DHG
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select GFXUMA
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_1024
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select QRANK_DIMM_SUPPORT
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default kontron/kt690
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "KT690/mITX"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_KONTRON_KT690
diff --git a/src/mainboard/kontron/kt690/Kconfig.name b/src/mainboard/kontron/kt690/Kconfig.name
deleted file mode 100644
index 1a9313cf3f..0000000000
--- a/src/mainboard/kontron/kt690/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_KONTRON_KT690
- bool "KT690/mITX"
diff --git a/src/mainboard/kontron/kt690/acpi/ide.asl b/src/mainboard/kontron/kt690/acpi/ide.asl
deleted file mode 100644
index d5badfcb6b..0000000000
--- a/src/mainboard/kontron/kt690/acpi/ide.asl
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "ide.asl"
- }
- }
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
- 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
- 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
- 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
- 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
- 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
- Field(ICRG, AnyAcc, NoLock, Preserve)
-{
- PPTS, 8, /* Primary PIO Slave Timing */
- PPTM, 8, /* Primary PIO Master Timing */
- OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
- PMTM, 8, /* Primary MWDMA Master Timing */
- OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
- OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
- PPSM, 4, /* Primary PIO slave Mode */
- OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
- OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
- PDSM, 4, /* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
- Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
- Increment(Local0)
- Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
- Increment(Local1)
- Return(Multiply(30, Add(Local0, Local1)))
-}
-
-Device(PRID)
-{
- Name (_ADR, Zero)
- Method(_GTM, 0)
- {
- NAME(OTBF, Buffer(20) { /* out buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
- CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
- /* Just return if the channel is disabled */
- If(And(PPCR, 0x01)) { /* primary PIO control */
- Return(OTBF)
- }
-
- /* Always tell them independent timing available and IOChannelReady used on both drives */
- Or(BFFG, 0x1A, BFFG)
-
- Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
- Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
-
- If(And(PDCR, 0x01)) { /* It's under UDMA mode */
- Or(BFFG, 0x01, BFFG)
- Store(DerefOf(Index(UDTT, PDMM)), DSD0)
- }
- Else {
- Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
- }
-
- If(And(PDCR, 0x02)) { /* It's under UDMA mode */
- Or(BFFG, 0x04, BFFG)
- Store(DerefOf(Index(UDTT, PDSM)), DSD1)
- }
- Else {
- Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
- }
-
- Return(OTBF) /* out buffer */
- } /* End Method(_GTM) */
-
- Method(_STM, 3, NotSerialized)
- {
- NAME(INBF, Buffer(20) { /* in buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
- CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
- Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
- Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
- Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
- Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
-
- Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
- Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
-
- If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDMM,)
- Or(PDCR, 0x01, PDCR)
- }
- Else {
- If(LNotEqual(DSD0, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTM)
- }
- }
-
- If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDSM,)
- Or(PDCR, 0x02, PDCR)
- }
- Else {
- If(LNotEqual(DSD1, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTS)
- }
- }
- /* Return(INBF) */
- } /*End Method(_STM) */
- Device(MST)
- {
- Name(_ADR, 0)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xA0, CMDA)
- Store(0xA0, CMDB)
- Store(0xA0, CMDC)
-
- Or(PPMM, 0x08, POMD)
-
- If(And(PDCR, 0x01)) {
- Or(PDMM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTM),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(MST) */
-
- Device(SLAV)
- {
- Name(_ADR, 1)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xB0, CMDA)
- Store(0xB0, CMDB)
- Store(0xB0, CMDC)
-
- Or(PPSM, 0x08, POMD)
-
- If(And(PDCR, 0x02)) {
- Or(PDSM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTS),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(SLAV) */
-}
diff --git a/src/mainboard/kontron/kt690/acpi/routing.asl b/src/mainboard/kontron/kt690/acpi/routing.asl
deleted file mode 100644
index 97cd733521..0000000000
--- a/src/mainboard/kontron/kt690/acpi/routing.asl
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "routing.asl"
- }
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
- Name(PR0, Package(){
- /* NB devices */
- /* Bus 0, Dev 0 - RS690 Host Controller */
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, INTC, 0 },
- Package(){0x0002FFFF, 1, INTD, 0 },
- Package(){0x0002FFFF, 2, INTA, 0 },
- Package(){0x0002FFFF, 3, INTB, 0 },
-
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){0x0003FFFF, 0, INTD, 0 },
- Package(){0x0003FFFF, 1, INTA, 0 },
- Package(){0x0003FFFF, 2, INTB, 0 },
- Package(){0x0003FFFF, 3, INTC, 0 },
-
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, INTA, 0 },
- Package(){0x0004FFFF, 1, INTB, 0 },
- Package(){0x0004FFFF, 2, INTC, 0 },
- Package(){0x0004FFFF, 3, INTD, 0 },
-
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- Package(){0x0005FFFF, 0, INTB, 0 },
- Package(){0x0005FFFF, 1, INTC, 0 },
- Package(){0x0005FFFF, 2, INTD, 0 },
- Package(){0x0005FFFF, 3, INTA, 0 },
-
- /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
- Package(){0x0006FFFF, 0, INTC, 0 },
- Package(){0x0006FFFF, 1, INTD, 0 },
- Package(){0x0006FFFF, 2, INTA, 0 },
- Package(){0x0006FFFF, 3, INTB, 0 },
-
- /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
- Package(){0x0007FFFF, 0, INTD, 0 },
- Package(){0x0007FFFF, 1, INTA, 0 },
- Package(){0x0007FFFF, 2, INTB, 0 },
- Package(){0x0007FFFF, 3, INTC, 0 },
-
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0012FFFF, 1, INTA, 0 }, // Link G?
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){0x0013FFFF, 0, INTA, 0 },
- Package(){0x0013FFFF, 1, INTB, 0 },
- Package(){0x0013FFFF, 2, INTC, 0 },
- Package(){0x0013FFFF, 3, INTD, 0 },
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
- Package(){0x0014FFFF, 0, INTA, 0 },
- Package(){0x0014FFFF, 1, INTB, 0 },
- Package(){0x0014FFFF, 2, INTC, 0 },
- Package(){0x0014FFFF, 3, INTD, 0 },
- })
-
- Name(APR0, Package(){
- /* NB devices in APIC mode */
- /* Bus 0, Dev 0 - RS690 Host Controller */
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){ 0x0002FFFF, 0, 0, 18 },
- Package(){ 0x0002FFFF, 1, 0, 19 },
- Package(){ 0x0002FFFF, 2, 0, 16 },
- Package(){ 0x0002FFFF, 3, 0, 17 },
-
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){ 0x0003FFFF, 0, 0, 19 },
- Package(){ 0x0003FFFF, 1, 0, 16 },
- Package(){ 0x0003FFFF, 2, 0, 17 },
- Package(){ 0x0003FFFF, 3, 0, 18 },
-
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){ 0x0004FFFF, 0, 0, 16 },
- Package(){ 0x0004FFFF, 1, 0, 17 },
- Package(){ 0x0004FFFF, 2, 0, 18 },
- Package(){ 0x0004FFFF, 3, 0, 19 },
-
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- Package(){ 0x0005FFFF, 0, 0, 17 },
- Package(){ 0x0005FFFF, 1, 0, 18 },
- Package(){ 0x0005FFFF, 2, 0, 19 },
- Package(){ 0x0005FFFF, 3, 0, 16 },
-
- /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
- Package(){ 0x0006FFFF, 0, 0, 18 },
- Package(){ 0x0006FFFF, 1, 0, 19 },
- Package(){ 0x0006FFFF, 2, 0, 16 },
- Package(){ 0x0006FFFF, 3, 0, 17 },
-
- /* Bus 0, Dev 7 - PCIe Bridge for network card */
- Package(){ 0x0007FFFF, 0, 0, 19 },
- Package(){ 0x0007FFFF, 1, 0, 16 },
- Package(){ 0x0007FFFF, 2, 0, 17 },
- Package(){ 0x0007FFFF, 3, 0, 18 },
-
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices in APIC mode */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){ 0x0012FFFF, 0, 0, 22 },
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){ 0x0013FFFF, 0, 0, 16 },
- Package(){ 0x0013FFFF, 1, 0, 17 },
- Package(){ 0x0013FFFF, 2, 0, 18 },
- Package(){ 0x0013FFFF, 3, 0, 19 },
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
- Package(){ 0x0014FFFF, 0, 0, 16 },
- Package(){ 0x0014FFFF, 1, 0, 17 },
- Package(){ 0x0014FFFF, 2, 0, 18 },
- Package(){ 0x0014FFFF, 3, 0, 19 },
-
- })
-
- Name(PR1, Package(){
- /* Internal graphics - RS690 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, INTC, 0 },
- Package(){0x0005FFFF, 1, INTD, 0 },
- Package(){0x0005FFFF, 2, INTA, 0 },
- Package(){0x0005FFFF, 3, INTB, 0 },
- })
-
- Name(APR1, Package(){
- /* Internal graphics - RS690 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, 0, 18 },
- Package(){0x0005FFFF, 1, 0, 19 },
- Package(){0x0005FFFF, 2, 0, 16 },
- Package(){0x0005FFFF, 3, 0, 17 },
- })
-
- Name(PS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, INTA, 0 },
- Package(){0x0000FFFF, 1, INTB, 0 },
- Package(){0x0000FFFF, 2, INTC, 0 },
- Package(){0x0000FFFF, 3, INTD, 0 },
- })
-
- Name(APS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, 0, 16 },
- Package(){0x0000FFFF, 1, 0, 17 },
- Package(){0x0000FFFF, 2, 0, 18 },
- Package(){0x0000FFFF, 3, 0, 19 },
- })
-
- Name(PS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, INTB, 0 },
- Package(){0x0000FFFF, 1, INTC, 0 },
- Package(){0x0000FFFF, 2, INTD, 0 },
- Package(){0x0000FFFF, 3, INTA, 0 },
- })
-
- Name(APS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
-
- Name(APS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, 0, 19 },
- Package(){0x0000FFFF, 1, 0, 16 },
- Package(){0x0000FFFF, 2, 0, 17 },
- Package(){0x0000FFFF, 3, 0, 18 },
- })
-
- Name(PCIB, Package(){
- /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
- Package(){0x0005FFFF, 0, 0, 0x14 },
- Package(){0x0005FFFF, 1, 0, 0x15 },
- Package(){0x0005FFFF, 2, 0, 0x16 },
- Package(){0x0005FFFF, 3, 0, 0x17 },
- Package(){0x0006FFFF, 0, 0, 0x15 },
- Package(){0x0006FFFF, 1, 0, 0x16 },
- Package(){0x0006FFFF, 2, 0, 0x17 },
- Package(){0x0006FFFF, 3, 0, 0x14 },
- Package(){0x0007FFFF, 0, 0, 0x16 },
- Package(){0x0007FFFF, 1, 0, 0x17 },
- Package(){0x0007FFFF, 2, 0, 0x14 },
- Package(){0x0007FFFF, 3, 0, 0x15 },
- })
-}
diff --git a/src/mainboard/kontron/kt690/acpi/sata.asl b/src/mainboard/kontron/kt690/acpi/sata.asl
deleted file mode 100644
index 474e5ed6d2..0000000000
--- a/src/mainboard/kontron/kt690/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(SATA) {
- Name(_ADR, 0x00120000)
- #include "sata.asl"
- }
- }
-}
-*/
-
-Name(STTM, Buffer(20) {
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
- \_GPE._L1F()
-}
-
-Device(PMRY)
-{
- Name(_ADR, 0)
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(PMST) {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P0IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- }/* end of PMST */
-
- Device(PSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P1IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of PSLA */
-} /* end of PMRY */
-
-
-Device(SEDY)
-{
- Name(_ADR, 1) /* IDE Scondary Channel */
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(SMST)
- {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P2IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SMST */
-
- Device(SSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P3IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SSLA */
-} /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
- Method(_L1F,0x0,NotSerialized) {
- if (\_SB.P0PR) {
- if (LGreater(\_SB.P0IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P0PR)
- }
-
- if (\_SB.P1PR) {
- if (LGreater(\_SB.P1IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P1PR)
- }
-
- if (\_SB.P2PR) {
- if (LGreater(\_SB.P2IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P2PR)
- }
-
- if (\_SB.P3PR) {
- if (LGreater(\_SB.P3IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P3PR)
- }
- }
-}
diff --git a/src/mainboard/kontron/kt690/acpi/usb.asl b/src/mainboard/kontron/kt690/acpi/usb.asl
deleted file mode 100644
index 638690697c..0000000000
--- a/src/mainboard/kontron/kt690/acpi/usb.asl
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "usb.asl"
- }
-*/
-Method(UCOC, 0) {
- Sleep(20)
- Store(0x13,CMTI)
- Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
- Scope (\_GPE) {
- Method (_L13) {
- UCOC()
- if(LEqual(GPB0,PLC0)) {
- Not(PLC0,PLC0)
- Store(PLC0, \_SB.PT0D)
- }
- }
- }
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
- Scope (\_GPE) {
- Method (_L14) {
- UCOC()
- if (LEqual(GPB1,PLC1)) {
- Not(PLC1,PLC1)
- Store(PLC1, \_SB.PT1D)
- }
- }
- }
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
- Scope (\_GPE) {
- Method (_L15) {
- UCOC()
- if (LEqual(GPB2,PLC2)) {
- Not(PLC2,PLC2)
- Store(PLC2, \_SB.PT2D)
- }
- }
- }
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
- Scope (\_GPE) {
- Method (_L16) {
- UCOC()
- if (LEqual(GPB3,PLC3)) {
- Not(PLC3,PLC3)
- Store(PLC3, \_SB.PT3D)
- }
- }
- }
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
- Scope (\_GPE) {
- Method (_L19) {
- UCOC()
- if (LEqual(GPB4,PLC4)) {
- Not(PLC4,PLC4)
- Store(PLC4, \_SB.PT4D)
- }
- }
- }
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
- Scope (\_GPE) {
- Method (_L1A) {
- UCOC()
- if (LEqual(GPB5,PLC5)) {
- Not(PLC5,PLC5)
- Store(PLC5, \_SB.PT5D)
- }
- }
- }
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
- Scope (\_GPE) {
- /* Method (_L1C) { */
- Method (_L06) {
- UCOC()
- if (LEqual(GPB6,PLC6)) {
- Not(PLC6,PLC6)
- Store(PLC6, \_SB.PT6D)
- }
- }
- }
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
- Scope (\_GPE) {
- /* Method (_L1D) { */
- Method (_L07) {
- UCOC()
- if (LEqual(GPB7,PLC7)) {
- Not(PLC7,PLC7)
- Store(PLC7, \_SB.PT7D)
- }
- }
- }
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
- Scope (\_GPE) {
- Method (_L17) {
- if (LEqual(G8IS,PLC8)) {
- Not(PLC8,PLC8)
- Store(PLC8, \_SB.PT8D)
- }
- }
- }
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
- Scope (\_GPE) {
- Method (_L0E) {
- if (LEqual(G9IS,0)) {
- Store(1,\_SB.PT9D)
- }
- }
- }
-}
diff --git a/src/mainboard/kontron/kt690/acpi_tables.c b/src/mainboard/kontron/kt690/acpi_tables.c
deleted file mode 100644
index 75834b6c7f..0000000000
--- a/src/mainboard/kontron/kt690/acpi_tables.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include <arch/cpu.h>
-#include <cpu/amd/powernow.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- get_bus_conf();
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB600 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
- IO_APIC_ADDR, 0);
-
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high */
-
- /* create all subtables for processors */
- /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
- /* 1: LINT1 connect to NMI */
-
- return current;
-}
diff --git a/src/mainboard/kontron/kt690/board_info.txt b/src/mainboard/kontron/kt690/board_info.txt
deleted file mode 100644
index fc42f537d6..0000000000
--- a/src/mainboard/kontron/kt690/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: mini
-Board URL: http://emea.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/kt690mitx+bga.html?searchtermresultpage=kt690%2Fmitx
diff --git a/src/mainboard/kontron/kt690/cmos.layout b/src/mainboard/kontron/kt690/cmos.layout
deleted file mode 100644
index 104d51f4c2..0000000000
--- a/src/mainboard/kontron/kt690/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-##
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/kontron/kt690/devicetree.cb b/src/mainboard/kontron/kt690/devicetree.cb
deleted file mode 100644
index 3ab33378a3..0000000000
--- a/src/mainboard/kontron/kt690/devicetree.cb
+++ /dev/null
@@ -1,125 +0,0 @@
-#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_S1G1
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1488 0x6900 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on # southbridge
- chip southbridge/amd/rs690
- device pci 0.0 on end # HT 0x7910
- device pci 1.0 on # Internal Graphics P2P bridge 0x7912
- device pci 5.0 on end # Internal Graphics 0x791F
- end
- device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
- device pci 3.0 off end # PCIE P2P bridge 0x791b
- device pci 4.0 on end # PCIE P2P bridge 0x7914
- device pci 5.0 on end # PCIE P2P bridge 0x7915
- device pci 6.0 on end # PCIE P2P bridge 0x7916
- device pci 7.0 on end # PCIE P2P bridge 0x7917
- device pci 8.0 off end # NB/SB Link P2P bridge
- register "gpp_configuration" = "4"
- register "port_enable" = "0xfc"
- register "gfx_dev2_dev3" = "1"
- register "gfx_dual_slot" = "0"
- register "gfx_lane_reversal" = "0"
- register "gfx_tmds" = "0"
- register "gfx_compliance" = "0"
- register "gfx_reconfiguration" = "1"
- register "gfx_link_width" = "0"
- end
- chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
- device pci 12.0 on end # SATA 0x4380
- device pci 13.0 on end # USB 0x4387
- device pci 13.1 on end # USB 0x4388
- device pci 13.2 on end # USB 0x4389
- device pci 13.3 on end # USB 0x438a
- device pci 13.4 on end # USB 0x438b
- device pci 13.5 on end # USB 2 0x4386
- device pci 14.0 on # SM 0x4385
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- end # SM
- device pci 14.1 on end # IDE 0x438c
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC 0x438d
- chip superio/winbond/w83627dhg
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- #device pnp 2e.6 off # SPI
- #end
- device pnp 2e.307 off # GPIO 1
- end
- device pnp 2e.8 on # WDTO#, PLED
- end
- device pnp 2e.009 off # GPIO2
- end
- device pnp 2e.109 off # GPIO3
- end
- device pnp 2e.209 off # GPIO4
- end
- device pnp 2e.309 off # GPIO5
- end
- device pnp 2e.a off # ACPI
- end
- device pnp 2e.b on # HWM
- io 0x60 = 0xa10
- end
- device pnp 2e.c off # PECI, SST
- end
- end #superio/winbond/w83627dhg
- #chip superio/smsc/fdc37n972
- # seems this chip is not used?
- #end
- end #LPC
- device pci 14.4 on end # PCI 0x4384
- device pci 14.5 on end # ACI 0x4382
- device pci 14.6 on end # MCI 0x438e
- register "hda_viddid" = "0x10ec0888"
- end #southbridge/amd/sb600
- end # device pci 18.0
-
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end #northbridge/amd/amdk8
- end #domain
-end #northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/kontron/kt690/dsdt.asl b/src/mainboard/kontron/kt690/dsdt.asl
deleted file mode 100644
index 889293f84b..0000000000
--- a/src/mainboard/kontron/kt690/dsdt.asl
+++ /dev/null
@@ -1,1675 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <southbridge/amd/sb600/sb600.h>
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
- "dsdt.aml", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "COREv2", /* OEMID */
- "COREBOOT", /* TABLE ID */
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
-
- /* Data to be patched by the BIOS during POST */
- /* FIXME the patching is not done yet! */
- /* Memory related values */
- Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
-
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
-
- /* USB overcurrent mapping pins. */
- Name(UOM0, 0)
- Name(UOM1, 2)
- Name(UOM2, 0)
- Name(UOM3, 7)
- Name(UOM4, 2)
- Name(UOM5, 2)
- Name(UOM6, 6)
- Name(UOM7, 2)
- Name(UOM8, 6)
- Name(UOM9, 6)
-
- /* Some global data */
- Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PMOD, One) /* Assume APIC */
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- /* PCI Error control register */
- OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
- Field(PERC, ByteAcc, NoLock, Preserve) {
- SENS, 0x00000001,
- PENS, 0x00000001,
- SENE, 0x00000001,
- PENE, 0x00000001,
- }
-
- /* Client Management index/data registers */
- OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
- Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
- /* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
- }
-
- /* GPM Port register */
- OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
- Field(GPT, ByteAcc, NoLock, Preserve) {
- GPB0,1,
- GPB1,1,
- GPB2,1,
- GPB3,1,
- GPB4,1,
- GPB5,1,
- GPB6,1,
- GPB7,1,
- }
-
- /* Flash ROM program enable register */
- OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
- Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
- FLRE, 0x00000001,
- }
-
- /* PM2 index/data registers */
- OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
- Field(PM2R, ByteAcc, NoLock, Preserve) {
- PM2I, 0x00000008,
- PM2D, 0x00000008,
- }
-
- /* Power Management I/O registers */
- OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
- Field(PIOR, ByteAcc, NoLock, Preserve) {
- PIOI, 0x00000008,
- PIOD, 0x00000008,
- }
- IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
- Offset(0x00), /* MiscControl */
- , 1,
- T1EE, 1,
- T2EE, 1,
- Offset(0x01), /* MiscStatus */
- , 1,
- T1E, 1,
- T2E, 1,
- Offset(0x04), /* SmiWakeUpEventEnable3 */
- , 7,
- SSEN, 1,
- Offset(0x07), /* SmiWakeUpEventStatus3 */
- , 7,
- CSSM, 1,
- Offset(0x10), /* AcpiEnable */
- , 6,
- PWDE, 1,
- Offset(0x1C), /* ProgramIoEnable */
- , 3,
- MKME, 1,
- IO3E, 1,
- IO2E, 1,
- IO1E, 1,
- IO0E, 1,
- Offset(0x1D), /* IOMonitorStatus */
- , 3,
- MKMS, 1,
- IO3S, 1,
- IO2S, 1,
- IO1S, 1,
- IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
- APEB, 16,
- Offset(0x36), /* GEvtLevelConfig */
- , 6,
- ELC6, 1,
- ELC7, 1,
- Offset(0x37), /* GPMLevelConfig0 */
- , 3,
- PLC0, 1,
- PLC1, 1,
- PLC2, 1,
- PLC3, 1,
- PLC8, 1,
- Offset(0x38), /* GPMLevelConfig1 */
- , 1,
- PLC4, 1,
- PLC5, 1,
- , 1,
- PLC6, 1,
- PLC7, 1,
- Offset(0x3B), /* PMEStatus1 */
- GP0S, 1,
- GM4S, 1,
- GM5S, 1,
- APS, 1,
- GM6S, 1,
- GM7S, 1,
- GP2S, 1,
- STSS, 1,
- Offset(0x55), /* SoftPciRst */
- SPRE, 1,
- , 1,
- , 1,
- PNAT, 1,
- PWMK, 1,
- PWNS, 1,
-
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
-
- Offset(0x65), /* UsbPMControl */
- , 4,
- URRE, 1,
- Offset(0x68), /* MiscEnable68 */
- , 3,
- TMTE, 1,
- , 1,
- Offset(0x92), /* GEVENTIN */
- , 7,
- E7IS, 1,
- Offset(0x96), /* GPM98IN */
- G8IS, 1,
- G9IS, 1,
- Offset(0x9A), /* EnhanceControl */
- ,7,
- HPDE, 1,
- Offset(0xA8), /* PIO7654Enable */
- IO4E, 1,
- IO5E, 1,
- IO6E, 1,
- IO7E, 1,
- Offset(0xA9), /* PIO7654Status */
- IO4S, 1,
- IO5S, 1,
- IO6S, 1,
- IO7S, 1,
- }
-
- /* PM1 Event Block
- * First word is PM1_Status, Second word is PM1_Enable
- */
- OperationRegion(P1EB, SystemIO, APEB, 0x04)
- Field(P1EB, ByteAcc, NoLock, Preserve) {
- TMST, 1,
- , 3,
- BMST, 1,
- GBST, 1,
- Offset(0x01),
- PBST, 1,
- , 1,
- RTST, 1,
- , 3,
- PWST, 1,
- SPWS, 1,
- Offset(0x02),
- TMEN, 1,
- , 4,
- GBEN, 1,
- Offset(0x03),
- PBEN, 1,
- , 1,
- RTEN, 1,
- , 3,
- PWDA, 1,
- }
-
- Scope(\_SB) {
-
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
- /* Byte offsets are computed using the following technique:
- * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
- * The 8 comes from 8 functions per device, and 4096 bytes per function config space
- */
- Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
- STB5, 32,
- Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
- PT0D, 1,
- PT1D, 1,
- PT2D, 1,
- PT3D, 1,
- PT4D, 1,
- PT5D, 1,
- PT6D, 1,
- PT7D, 1,
- PT8D, 1,
- PT9D, 1,
- Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
- SBIE, 1,
- SBME, 1,
- Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
- SBRI, 8,
- Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
- SBB1, 32,
- Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
- ,14,
- P92E, 1, /* Port92 decode enable */
- }
-
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
- Field(SB5, AnyAcc, NoLock, Preserve)
- {
- /* Port 0 */
- Offset(0x120), /* Port 0 Task file status */
- P0ER, 1,
- , 2,
- P0DQ, 1,
- , 3,
- P0BY, 1,
- Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
- , 4,
- P0IS, 4,
- Offset(0x12C), /* Port 0 Serial ATA control */
- P0DI, 4,
- Offset(0x130), /* Port 0 Serial ATA error */
- , 16,
- P0PR, 1,
-
- /* Port 1 */
- offset(0x1A0), /* Port 1 Task file status */
- P1ER, 1,
- , 2,
- P1DQ, 1,
- , 3,
- P1BY, 1,
- Offset(0x1A8), /* Port 1 Serial ATA status */
- P1DD, 4,
- , 4,
- P1IS, 4,
- Offset(0x1AC), /* Port 1 Serial ATA control */
- P1DI, 4,
- Offset(0x1B0), /* Port 1 Serial ATA error */
- , 16,
- P1PR, 1,
-
- /* Port 2 */
- Offset(0x220), /* Port 2 Task file status */
- P2ER, 1,
- , 2,
- P2DQ, 1,
- , 3,
- P2BY, 1,
- Offset(0x228), /* Port 2 Serial ATA status */
- P2DD, 4,
- , 4,
- P2IS, 4,
- Offset(0x22C), /* Port 2 Serial ATA control */
- P2DI, 4,
- Offset(0x230), /* Port 2 Serial ATA error */
- , 16,
- P2PR, 1,
-
- /* Port 3 */
- Offset(0x2A0), /* Port 3 Task file status */
- P3ER, 1,
- , 2,
- P3DQ, 1,
- , 3,
- P3BY, 1,
- Offset(0x2A8), /* Port 3 Serial ATA status */
- P3DD, 4,
- , 4,
- P3IS, 4,
- Offset(0x2AC), /* Port 3 Serial ATA control */
- P3DI, 4,
- Offset(0x2B0), /* Port 3 Serial ATA error */
- , 16,
- P3PR, 1,
- }
- }
-
- #include "acpi/routing.asl"
-
- Scope(\_SB) {
-
- Method(OSFL, 0){
-
- if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
-
- if(CondRefOf(\_OSI))
- {
- Store(1, OSVR) /* Assume some form of XP */
- if (\_OSI("Windows 2006")) /* Vista */
- {
- Store(2, OSVR)
- }
- } else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSVR) /* Linux */
- } Else {
- Store(4, OSVR) /* Gotta be WinCE */
- }
- }
- Return(OSVR)
- }
-
- Method(_PIC, 0x01, NotSerialized)
- {
- If (Arg0)
- {
- \_SB.CIRQ()
- }
- Store(Arg0, PMOD)
- }
-
- Method(CIRQ, 0x00, NotSerialized)
- {
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTA._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTE._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_PRS\n") */
- Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
- } /* End Scope(_SB) */
-
- #include <southbridge/amd/common/acpi/sleepstates.asl>
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- \_SB.PCI0.SIOS (Arg0)
- } /* End Method(\_PTS) */
-
- /*
- * The following method results in a "not a valid reserved NameSeg"
- * warning so I have commented it out for the duration. It isn't
- * used, so it could be removed.
- *
- *
- * \_GTS OEM Going To Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- *
- * Method(\_GTS, 1) {
- * DBGO("\\_GTS\n")
- * DBGO("From S0 to S")
- * DBGO(Arg0)
- * DBGO("\n")
- * }
- */
-
- /*
- * \_BFS OEM Back From Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- */
- Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
- }
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- Store(1,HPDE)
-
- /* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, Local1)
- Store(Local1, PWST)
-
-
- /* if(DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
- * } else {
- * Store(Arg0, Index(WKST,1))
- * }
- */
- \_SB.PCI0.SIOW ()
- Return(WKST)
- } /* End Method(\_WAK) */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* General event 0 */
- /* Method(_L00) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 1 */
- /* Method(_L01) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 2 */
- /* Method(_L02) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 3 */
- Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* General event 4 */
- /* Method(_L04) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 5 */
- /* Method(_L05) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 6 - Used for GPM6, moved to USB.asl */
- /* Method(_L06) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 7 - Used for GPM7, moved to USB.asl */
- /* Method(_L07) {
- * DBGO("\\_GPE\\_L07\n")
- * }
- */
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
- }
-
- /* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
-
- /* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
-
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
-
- /* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
-
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event - Moved to USB.asl */
- /* Method(_L1A) {
- * DBGO("\\_GPE\\_L1A\n")
- * }
- */
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
-
- /* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
-
- /* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
-
- /* SATA SCI event - Moved to sata.asl */
- /* Method(_L1F) {
- * DBGO("\\_GPE\\_L1F\n")
- * }
- */
-
- } /* End Scope GPE */
-
- #include "acpi/usb.asl"
-
- /* System Bus */
- Scope(\_SB) { /* Start \_SB scope */
- #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0) {
- External (TOM1)
- External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* Dev3 is also an external GFX bridge, not used in Herring */
-
- Device(PBR4) {
- Name(_ADR, 0x00040000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR4 */
-
- Device(PBR5) {
- Name(_ADR, 0x00050000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR5 */
-
- Device(PBR6) {
- Name(_ADR, 0x00060000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR6 */
-
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR7 */
-
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
-
- /* Describe the Southbridge devices */
- Device(STCR) {
- Name(_ADR, 0x00120000)
- #include "acpi/sata.asl"
- } /* end STCR */
-
- Device(UOH1) {
- Name(_ADR, 0x00130000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH1 */
-
- Device(UOH2) {
- Name(_ADR, 0x00130001)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH2 */
-
- Device(UOH3) {
- Name(_ADR, 0x00130002)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH3 */
-
- Device(UOH4) {
- Name(_ADR, 0x00130003)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH4 */
-
- Device(UOH5) {
- Name(_ADR, 0x00130004)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UEH1) {
- Name(_ADR, 0x00130005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(SBUS) {
- Name(_ADR, 0x00140000)
- } /* end SBUS */
-
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "acpi/ide.asl"
- } /* end IDEC */
-
- Device(AZHD) {
- Name(_ADR, 0x00140002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6C),
- MMDT, 16,
- }
-
- Method(_INI) {
- If(LEqual(OSVR,3)){ /* If we are running Linux */
- Store(zero, NSEN)
- Store(one, NSDO)
- Store(one, NSDI)
- }
- }
- } /* end AZHD */
-
- Device(LIBR) {
- Name(_ADR, 0x00140003)
- /* Method(_INI) {
- * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
- } */ /* End Method(_SB.SBRDG._INI) */
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){8}
- IO(Decode16,0x0070, 0x0070, 0, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){0}
- IO(Decode16, 0x0040, 0x0040, 0, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 0, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){2}
- IO(Decode16,0x0020, 0x0020, 0, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,BusMaster,Transfer8){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
- IRQNoFlags(){13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPTM) { /* HPET */
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* HPET is visible */
- }
- Method(_CRS, 0) {
- Return(CRS)
- }
- } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
- } /* end LIBR */
-
- Device(HPBR) {
- Name(_ADR, 0x00140004)
- } /* end HostPciBr */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- } /* end Ac97modem */
-
- /* ITE IT8712F Support */
- OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
- Field (IOID, ByteAcc, NoLock, Preserve)
- {
- SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
- }
-
- IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
- {
- Offset (0x07),
- LDN, 8, /* Logical Device Number */
- Offset (0x20),
- CID1, 8, /* Chip ID Byte 1, 0x87 */
- CID2, 8, /* Chip ID Byte 2, 0x12 */
- Offset (0x30),
- ACTR, 8, /* Function activate */
- Offset (0xF0),
- APC0, 8, /* APC/PME Event Enable Register */
- APC1, 8, /* APC/PME Status Register */
- APC2, 8, /* APC/PME Control Register 1 */
- APC3, 8, /* Environment Controller Special Configuration Register */
- APC4, 8 /* APC/PME Control Register 2 */
- }
-
- /* Enter the IT8712F MB PnP Mode */
- Method (EPNP)
- {
- Store(0x87, SIOI)
- Store(0x01, SIOI)
- Store(0x55, SIOI)
- Store(0x55, SIOI) /* IT8712F magic number */
- }
- /* Exit the IT8712F MB PnP Mode */
- Method (XPNP)
- {
- Store (0x02, SIOI)
- Store (0x02, SIOD)
- }
-
- /*
- * Keyboard PME is routed to SB600 Gevent3. We can wake
- * up the system by pressing the key.
- */
- Method (SIOS, 1)
- {
- /* We only enable KBD PME for S5. */
- If (LLess (Arg0, 0x05))
- {
- EPNP()
- /* DBGO("IT8712F\n") */
-
- Store (0x4, LDN)
- Store (One, ACTR) /* Enable EC */
- /*
- Store (0x4, LDN)
- Store (0x04, APC4)
- */ /* falling edge. which mode? Not sure. */
-
- Store (0x4, LDN)
- Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
- Store (0x4, LDN)
- Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
- XPNP()
- }
- }
- Method (SIOW, 0)
- {
- EPNP()
- Store (0x4, LDN)
- Store (Zero, APC0) /* disable keyboard PME */
- Store (0x4, LDN)
- Store (0xFF, APC1) /* clear keyboard PME status */
- XPNP()
- }
-
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
-
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
- }
-
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * ShiftLeft(TOM2, 20, Local0)
- * Subtract(Local0, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-
- Return(CRES) /* note to change the Name buffer */
- } /* end of Method(_SB.PCI0._CRS) */
-
- /*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
- Method(_INI, 0) {
- /* DBGO("\\_SB\\_INI\n") */
- /* DBGO(" DSDT.ASL code from ") */
- /* DBGO(__DATE__) */
- /* DBGO(" ") */
- /* DBGO(__TIME__) */
- /* DBGO("\n Sleep states supported: ") */
- /* DBGO("\n") */
- /* DBGO(" \\_OS=") */
- /* DBGO(\_OS) */
- /* DBGO("\n \\_REV=") */
- /* DBGO(\_REV) */
- /* DBGO("\n") */
-
- /* Determine the OS we're running on */
- OSFL()
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
- * }
- */
- } /* End Method(_SB._INI) */
- } /* End Device(PCI0) */
-
- Device(PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
- } /* End \_SB scope */
-
- Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
- } /* End Scope SI */
-
- #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
-
- /* THERMAL */
- Scope(\_TZ) {
- Name (KELV, 2732)
- Name (THOT, 800)
- Name (TCRT, 850)
-
- ThermalZone(TZ00) {
- Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
- /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
- Return(Add(0, 2730))
- }
- Method(_AL0,0) { /* Returns package of cooling device to turn on */
- /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
- Return(Package() {\_TZ.TZ00.FAN0})
- }
- Device (FAN0) {
- Name(_HID, EISAID("PNP0C0B"))
- Name(_PR0, Package() {PFN0})
- }
-
- PowerResource(PFN0,0,0) {
- Method(_STA) {
- Store(0xF,Local0)
- Return(Local0)
- }
- Method(_ON) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
- }
- Method(_OFF) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
- }
- }
-
- Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
- Return (Add (THOT, KELV))
- }
- Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
- Return (Add (TCRT, KELV))
- }
- Method(_TMP,0) { /* return current temp of this zone */
- Store (SMBR (0x07, 0x4C,, 0x00), Local0)
- If (LGreater (Local0, 0x10)) {
- Store (Local0, Local1)
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400, KELV))
- }
-
- Store (SMBR (0x07, 0x4C, 0x01), Local0)
- /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
- /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
- If (LGreater (Local0, 0x10)) {
- If (LGreater (Local0, Local1)) {
- Store (Local0, Local1)
- }
-
- Multiply (Local1, 10, Local1)
- Return (Add (Local1, KELV))
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400 , KELV))
- }
- } /* end of _TMP */
- } /* end of TZ00 */
- }
-}
-/* End of ASL file */
diff --git a/src/mainboard/kontron/kt690/fadt.c b/src/mainboard/kontron/kt690/fadt.c
deleted file mode 100644
index 6ebd04897f..0000000000
--- a/src/mainboard/kontron/kt690/fadt.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include "southbridge/amd/sb600/sb600.h"
-
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb ACPI */
-/* pm_base should be got from bar2 of rs690. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
-
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
- /* Prepare the header */
- memset((void *)fadt, 0, sizeof(acpi_fadt_t));
- memcpy(header->signature, "FACP", 4);
- header->length = 244;
- header->revision = 3;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->asl_compiler_revision = 0;
-
- fadt->firmware_ctrl = (u32) facs;
- fadt->dsdt = (u32) dsdt;
- /* 3=Workstation, 4=Enterprise Server, 7=Performance Server */
- fadt->preferred_pm_profile = 0x03;
- fadt->sci_int = 9;
- /* disable system management mode by setting to 0: */
- fadt->smi_cmd = 0;
- fadt->acpi_enable = 0xf0;
- fadt->acpi_disable = 0xf1;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0xe2;
-
- pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
-
- /* CpuControl is in \_PR.CP00, 6 bytes */
- pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
-
- pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
-
- pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
-
- pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 20-2B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
- pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
-
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
- fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
- fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
- fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
-
- fadt->cst_cnt = 0xe3;
- fadt->p_lvl2_lat = 101;
- fadt->p_lvl3_lat = 1001;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 1;
- fadt->duty_width = 3;
- fadt->day_alrm = 0; /* 0x7d these have to be */
- fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
- fadt->century = 0; /* 0x7f to make rtc alrm work */
- fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
- fadt->flags = 0x0001c1a5;/* 0x25; */
-
- fadt->res2 = 0;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 6;
- fadt->x_firmware_ctl_l = (u32) facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32) dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 4;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 2;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 32;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/kontron/kt690/get_bus_conf.c b/src/mainboard/kontron/kt690/get_bus_conf.c
deleted file mode 100644
index b1b7270802..0000000000
--- a/src/mainboard/kontron/kt690/get_bus_conf.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_rs690[8];
-u8 bus_sb600[2];
-u32 apicid_sb600;
-
-/*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
-u32 pci1234x[] = {
- 0x0000ff0,
-};
-
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
- 0x20202020,
-};
-
-u32 sbdn_rs690;
-u32 sbdn_sb600;
-
-
-
-static u32 get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- u32 apicid_base;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* do it only once */
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
- sbdn_rs690 = sysconf.sbdn;
- sbdn_sb600 = 0;
-
- for (i = 0; i < 2; i++) {
- bus_sb600[i] = 0;
- }
- for (i = 0; i < 8; i++) {
- bus_rs690[i] = 0;
- }
-
- bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_sb600[0] = bus_rs690[0];
-
- /* sb600 */
- dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
- if (dev) {
- bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- /* rs690 */
- for (i = 1; i < 8; i++) {
- dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
- if (dev) {
- bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
- /* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_sb600 = apicid_base + 0;
-}
diff --git a/src/mainboard/kontron/kt690/irq_tables.c b/src/mainboard/kontron/kt690/irq_tables.c
deleted file mode 100644
index 4c2a48dff7..0000000000
--- a/src/mainboard/kontron/kt690/irq_tables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern u8 bus_rs690[8];
-extern u8 bus_sb600[2];
-extern unsigned long sbdn_sb600;
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_sb600[0];
- pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c
deleted file mode 100644
index de6c0bb5c9..0000000000
--- a/src/mainboard/kontron/kt690/mainboard.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb600/sb600.h>
-
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS 0x0C /* Alert Response Address */
-#define SMBUS_IO_BASE 0x1000
-
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-#define ADT7461_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
- do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-
-
-/********************************************************
-* dbm690t uses a BCM5789 as on-board NIC.
-* It has a pin named LOW_POWER to enable it into LOW POWER state.
-* In order to run NIC, we should let it out of Low power state. This pin is
-* controlled by sb600 GPM3.
-* RRG4.2.3 GPM as GPIO
-* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
-* I/O C50, C51, C52, PM I/O94, 95, 96.
-* RRG4.2.3.1 GPM pins as Input
-* RRG4.2.3.2 GPM pins as Output
-********************************************************/
-static void enable_onboard_nic(void)
-{
- u8 byte;
-
- printk(BIOS_INFO, "%s.\n", __func__);
-
- /* set index register 0C50h to 13h (miscellaneous control) */
- outb(0x13, 0xC50); /* CMIndex */
-
- /* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
- byte = inb(0xC51);
- byte &= 0x3F;
- byte |= 0x40;
- outb(byte, 0xC51);
-
- /* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */
- byte = inb(0xC52);
- byte &= ~0x8;
- outb(byte, 0xC52);
-
- /* set CM data register 0C51h bits [7:6] to 10b to set Output state control */
- byte = inb(0xC51);
- byte &= 0x3F;
- byte |= 0x80; /* 7:6=10 */
- outb(byte, 0xC51);
-
- /* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */
- byte = inb(0xC52);
- byte &= ~0x8;
- outb(byte, 0xC52);
-}
-
-/********************************************************
-* dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
- u8 byte;
- struct device *sm_dev;
- struct device *ide_dev;
-
- printk(BIOS_INFO, "%s.\n", __func__);
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- pci_write_config8(ide_dev, 0x56, byte);
-}
-
-/*
- * set thermal config
- */
-static void set_thermal_config(void)
-{
- u8 byte;
- u16 word;
- struct device *sm_dev;
-
- /* set ADT 7461 */
- ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
- ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
- ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
- ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
-
- ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
- ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
-
- byte = ADT7461_read_byte(0x02); /* read status register to clear it */
- ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
- printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
-
- /* sb600 settings for thermal config */
- /* set SB600 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to input */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
-}
-
-/*************************************************
-* enable the dedicated function in dbm690t board.
-* This function called early than rs690_enable.
-*************************************************/
-static void mainboard_enable(struct device *dev)
-{
- printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev);
-
- enable_onboard_nic();
- get_ide_dma66();
- set_thermal_config();
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c
deleted file mode 100644
index 9515931627..0000000000
--- a/src/mainboard/kontron/kt690/mptable.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern u8 bus_rs690[8];
-extern u8 bus_sb600[2];
-
-extern u32 apicid_sb600;
-
-extern u32 sbdn_rs690;
-extern u32 sbdn_sb600;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- u32 dword;
- u8 byte;
-
- dev =
- dev_find_slot(bus_sb600[0],
- PCI_DEVFN(sbdn_sb600 + 0x14, 0));
- if (dev) {
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600,
- 0x11,(void *) dword);
-
- /* Initialize interrupt mapping */
- /* aza */
- byte = pci_read_config8(dev, 0x63);
- byte &= 0xf8;
- byte |= 0; /* 0: INTA, ...., 7: INTH */
- pci_write_config8(dev, 0x63, byte);
-
- /* SATA */
- dword = pci_read_config32(dev, 0xac);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
- /* dword |= 1 << 22; PIC and APIC co exists */
- pci_write_config32(dev, 0xac, dword);
-
- /*
- * 00:12.0: PROG SATA : INT F
- * 00:13.0: INTA USB_0
- * 00:13.1: INTB USB_1
- * 00:13.2: INTC USB_2
- * 00:13.3: INTD USB_3
- * 00:13.4: INTC USB_4
- * 00:13.5: INTD USB2
- * 00:14.1: INTA IDE
- * 00:14.2: Prog HDA : INT E
- * 00:14.5: INTB ACI
- * 00:14.6: INTB MCI
- */
- }
- }
-
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/kontron/kt690/resourcemap.c b/src/mainboard/kontron/kt690/resourcemap.c
deleted file mode 100644
index ff6aa305f0..0000000000
--- a/src/mainboard/kontron/kt690/resourcemap.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_kt690_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
deleted file mode 100644
index b7bde00e1c..0000000000
--- a/src/mainboard/kontron/kt690/romstage.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <spd.h>
-#include <cpu/x86/lapic.h>
-
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627dhg/w83627dhg.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/early_setup.c"
-#include "southbridge/amd/sb600/early_setup.c"
-#include <northbridge/amd/amdk8/f.h>
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(u32 device, u32 address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
- int needs_reset = 0;
- u32 bsp_apicid = 0;
- msr_t msr;
- struct cpuid_result cpuid1;
- struct sys_info *sysinfo = &sysinfo_car;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- /* sb600_lpc_port80(); */
- sb600_pci_port80();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- enable_rs690_dev8();
- sb600_lpc_init();
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
- printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
-
- setup_kt690_resource_map();
-
- setup_coherent_ht_domain();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched */
- wait_all_core0_started();
- start_other_cores();
-#endif
- wait_all_aps_started(bsp_apicid);
-
- ht_setup_chains_x(sysinfo);
-
- /* run _early_setup before soft-reset. */
- rs690_early_setup();
- sb600_early_setup();
-
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- cpuid1 = cpuid(0x80000007);
- if ((cpuid1.edx & 0x6) == 0x6) {
- /* Read FIDVID_STATUS */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
-
- /* show final fid and vid */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
- } else {
- printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
- printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx);
- }
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- rs690_htinit();
- printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
-
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now; */
- printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
- sysinfo->nodes, sysinfo->ctrl, spd_addr);
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
- rs690_before_pci_init();
- sb600_before_pci_init();
-}
diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig
deleted file mode 100644
index 3affb6a2a1..0000000000
--- a/src/mainboard/msi/ms7135/Kconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-if BOARD_MSI_MS7135
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_754
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_CK804
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_WINBOND_W83627THG
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_512
- select CK804_USE_NIC
- select CK804_USE_ACI
- select QRANK_DIMM_SUPPORT
- select HAVE_ACPI_TABLES
-
-config MAINBOARD_DIR
- string
- default msi/ms7135
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "MS-7135"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 13
-
-config CK804_PCI_E_X
- int
- default 0
-
-endif # BOARD_MSI_MS7135
diff --git a/src/mainboard/msi/ms7135/Kconfig.name b/src/mainboard/msi/ms7135/Kconfig.name
deleted file mode 100644
index d087e684f9..0000000000
--- a/src/mainboard/msi/ms7135/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_MSI_MS7135
- bool "MS-7135 (K8N Neo3)"
diff --git a/src/mainboard/msi/ms7135/acpi_tables.c b/src/mainboard/msi/ms7135/acpi_tables.c
deleted file mode 100644
index a637637a84..0000000000
--- a/src/mainboard/msi/ms7135/acpi_tables.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * ACPI support
- * written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
- *
- *
- * Copyright 2005 AMD
- * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
- */
-
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <assert.h>
-
-/* APIC */
-unsigned long acpi_fill_madt(unsigned long current)
-{
- struct device *dev;
- struct resource *res;
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write NVIDIA CK804 IOAPIC. */
- dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
- ASSERT(dev != NULL);
-
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- ASSERT(res != NULL);
-
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
- CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0);
-
- /* Initialize interrupt mapping if mptable.c didn't. */
-#if (!CONFIG_GENERATE_MP_TABLE)
-#error untested config
- pci_write_config32(dev, 0x7c, 0x0120d218);
- pci_write_config32(dev, 0x80, 0x12008a00);
- pci_write_config32(dev, 0x84, 0x0000007d);
-#endif
-
- /* IRQ9 */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* create all subtables for processors */
- /* acpi_create_madt_lapic_nmis returns current, not size. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/msi/ms7135/board_info.txt b/src/mainboard/msi/ms7135/board_info.txt
deleted file mode 100644
index caae90a766..0000000000
--- a/src/mainboard/msi/ms7135/board_info.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-Board name: MS-7135 (K8N Neo3)
-Category: desktop
-Board URL: http://no.msi.com/product/mb/K8N-Neo3.html
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: variable
-Flashrom support: y
-Release year: 2005
diff --git a/src/mainboard/msi/ms7135/cmos.layout b/src/mainboard/msi/ms7135/cmos.layout
deleted file mode 100644
index 531b2d62cc..0000000000
--- a/src/mainboard/msi/ms7135/cmos.layout
+++ /dev/null
@@ -1,65 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 8 h 0 century
-408 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-448 4 e 10 ram_voltage
-452 4 e 11 nf4_voltage
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 400Mhz
-8 1 333Mhz
-8 2 266Mhz
-8 3 200Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-10 0 2.55
-10 1 2.50
-10 2 2.60
-10 3 2.65
-10 4 2.70
-
-11 0 1.50
-11 1 1.55
-11 2 1.60
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/msi/ms7135/devicetree.cb b/src/mainboard/msi/ms7135/devicetree.cb
deleted file mode 100644
index e3f0c8c98a..0000000000
--- a/src/mainboard/msi/ms7135/devicetree.cb
+++ /dev/null
@@ -1,75 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_754 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
-
- device domain 0 on # PCI domain
- subsystemid 0x1462 0x7135 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/ck804 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627thg # Super I/O
- device pnp 4e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 4e.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 4e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 4e.3 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 4e.5 on # PS/2 keyboard & mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 4e.7 off end # Game port, MIDI, GPIO 1 & 5
- device pnp 4e.8 off end # GPIO 2
- device pnp 4e.9 off end # GPIO 3, GPIO 4
- device pnp 4e.a off end # ACPI
- device pnp 4e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on end # SMbus
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # Onboard audio (ACI)
- device pci 4.1 off end # Onboard modem (MCI), N/A
- device pci 6.0 on end # IDE
- device pci 7.0 on end # SATA 1
- device pci 8.0 on end # SATA 0
- device pci 9.0 on end # PCI
- device pci a.0 on end # NIC
- device pci b.0 off end # PCI E 3 (N/A)
- device pci c.0 off end # PCI E 2 (N/A)
- device pci d.0 on end # PCI E 1
- device pci e.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/msi/ms7135/dsdt.asl b/src/mainboard/msi/ms7135/dsdt.asl
deleted file mode 100644
index e906270b68..0000000000
--- a/src/mainboard/msi/ms7135/dsdt.asl
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * Any others would involve declaring the wake up methods.
- */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
-
- Name (PICM, 0x00)
- Method (_PIC, 1, Serialized) {
- Store (Arg0, PICM)
- }
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device (CK804) */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
-#include "southbridge/nvidia/ck804/acpi/ck804.asl"
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LLAS, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LLAS, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LUOH, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LUEH, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LAUD, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LMOD, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LPA0, 0x00 },
- Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 },
-
- Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 },
-
- Package (0x04) { 0x000BFFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x000CFFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x000DFFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
-
- Package (0x04) { 0x000EFFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
- })
-
- Device (PCIC)
- {
- Name (_ADR, 0x00090000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- /* AGR slot "AGP1" */
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-
- /* PCI slot "PCI1" */
- Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0007FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0007FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- /* Not sure INTD is right, but this is what the OEM BIOS does. */
- Package (0x04) { 0x0007FFFF, 0x03, \_SB.PCI0.LNKE, 0x00 },
-
- /* PCI slot "PCI2" */
- Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
-
- /* PCI slot "PCI3" */
- Package (0x04) { 0x0009FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
- })
- }
-
- /* 2:00 PCIe x1 */
- Device (PEX1)
- {
- Name (_ADR, 0x000d0000)
- Name (_UID, 0x00)
- }
-
- /* 3:00 PCIe x16 */
- Device (PEX0)
- {
- Name (_ADR, 0x000e0000)
- Name (_UID, 0x00)
- }
-
- Device (LPC) {
- Name (_HID, EisaId ("PNP0A05"))
- Name (_ADR, 0x00010000)
-
- OperationRegion (CF44, PCI_Config, 0x44, 0x04)
- Field (CF44, ByteAcc, NoLock, Preserve)
- {
- ETBA, 32,
- }
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* Parallel port */
- Device (LP0)
- {
- Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- FixedIO (0x0378, 0x10)
- IRQNoFlags () {7}
- })
- Return (TMP)
- }
- }
-
- /* Floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- FixedIO (0x03F0, 0x08)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
-#if 0
- Device (HPET)
- {
- Name (_HID, EisaId ("PNP0103"))
- Name (CRS, ResourceTemplate ()
- {
- Memory32Fixed (ReadOnly,
- 0x00000000,
- 0x00001000,
- _Y02)
- })
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
- Method (_CRS, 0, NotSerialized)
- {
- CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT)
- Store (ETBA, HPT)
- Return (CRS)
- }
-
- }
-#endif
- }
- }
- }
-}
diff --git a/src/mainboard/msi/ms7135/get_bus_conf.c b/src/mainboard/msi/ms7135/get_bus_conf.c
deleted file mode 100644
index 19b520fda0..0000000000
--- a/src/mainboard/msi/ms7135/get_bus_conf.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable,
- * mptable and acpi_tables.
- */
-/* busnum is default */
-unsigned char bus_ck804[6];
-unsigned apicid_ck804;
-
-unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0, //no HTIO for ms7135
-};
-unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020, //ms7135 has only one ht-chain
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- unsigned apicid_base;
-
- struct device *dev;
- unsigned sbdn;
- int i;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- sbdn = sysconf.sbdn;
-
- for (i = 0; i < 6; i++) {
- bus_ck804[i] = 0;
- }
-
- bus_ck804[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* CK804 */
- int dn = -1;
- for (i = 1; i < 4; i++) {
- switch (i) {
- case 1: dn = 9; break;
- case 2: dn = 13; break;
- case 3: dn = 14; break;
- default: dn = -1; break;
- }
- dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + dn, 0));
- if (dev) {
- bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(3);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_ck804 = apicid_base + 0;
-}
diff --git a/src/mainboard/msi/ms7135/irq_tables.c b/src/mainboard/msi/ms7135/irq_tables.c
deleted file mode 100644
index e40794ef3c..0000000000
--- a/src/mainboard/msi/ms7135/irq_tables.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Documentation at: http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */
-
-/* This is probably not right, feel free to fix this if you don't want
- * to use the mptable.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_ck804[6];
-
-/**
- * Add one line to IRQ table.
- */
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-/**
- * Create the IRQ routing table.
- * Values are derived from getpir generated code.
- */
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
-
- uint8_t sum = 0;
- int i;
- unsigned sbdn;
-
- /* get_bus_conf() will find out all bus num and apic that share with
- * mptable.c and mptable.c
- */
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_ck804[0];
- pirq->rtr_devfn = ((sbdn + 9) << 3) | 0;
-
- pirq->exclusive_irqs = 0x828;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x005c;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
-//Slot1 PCIE 16x
- write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4,
- 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0);
- pirq_info++;
- slot_num++;
-
-//Slot2 PCIE 1x
- write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0);
- pirq_info++;
- slot_num++;
-
-//Slot3 PCIE 1x
- write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2,
- 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0);
- pirq_info++;
- slot_num++;
-
-//Slot4 PCIE 4x
- write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0,
- 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8,
- 7, 0);
- pirq_info++;
- slot_num++;
-
-//Slot5 - 7 PCI
- for (i = 0; i < 3; i++) {
- write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0,
- ((i + 0) % 4) + 1, 0xdeb8,
- ((i + 1) % 4) + 1, 0xdeb8,
- ((i + 2) % 4) + 1, 0xdeb8,
- ((i + 3) % 4) + 1, 0xdeb8, i, 0);
- pirq_info++;
- slot_num++;
- }
-
-//pci bridge
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0);
- pirq_info++;
- slot_num++;
-
-//smbus
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-//usb
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-//audio
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 4) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-//sata
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-//sata
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-//nic
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 0xa) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
-#if 0
- unsigned char irq[4];
- irq[0] = 0;
- irq[1] = 0;
- irq[2] = 0;
- irq[3] = 0;
-
- /* Bus, device, slots IRQs for {A,B,C,D}. */
-
- irq[0] = 10; /* SMBus *//* test me */
- pci_assign_irqs(bus_ck804[0], 1, irq);
-
- irq[0] = 10; /* USB */
- irq[1] = 10;
- pci_assign_irqs(bus_ck804[0], 2, irq);
-
- irq[0] = 10; /* AC97 */
- irq[1] = 0;
- pci_assign_irqs(bus_ck804[0], 4, irq);
-
- irq[0] = 11; /* SATA */
- pci_assign_irqs(bus_ck804[0], 7, irq);
-
- irq[0] = 5; /* SATA */
- pci_assign_irqs(bus_ck804[0], 8, irq);
-
- irq[0] = 10; /* Ethernet */
- pci_assign_irqs(bus_ck804[0], 10, irq);
-
- /* physical slots */
-
- irq[0] = 5; /* PCI E1 - x1 */
- pci_assign_irqs(bus_ck804[2], 0, irq);
-
- irq[0] = 11; /* PCI E2 - x16 */
- pci_assign_irqs(bus_ck804[3], 0, irq);
-
- /* AGP-on-PCI "AGR" ignored */
-
- irq[0] = 10; /* PCI1 */
- irq[1] = 11;
- irq[2] = 5;
- irq[3] = 0;
- pci_assign_irqs(bus_ck804[1], 7, irq);
-
- irq[0] = 11; /* PCI2 */
- irq[1] = 10;
- irq[2] = 5;
- irq[3] = 0;
- pci_assign_irqs(bus_ck804[1], 8, irq);
-
- irq[0] = 5; /* PCI3 */
- irq[1] = 10;
- irq[2] = 11;
- irq[3] = 0;
- pci_assign_irqs(bus_ck804[1], 9, irq);
-#endif
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c
deleted file mode 100644
index 35dc02c482..0000000000
--- a/src/mainboard/msi/ms7135/mptable.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_ck804[6];
-extern unsigned apicid_ck804;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
- unsigned sbdn;
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/* I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev;
- struct resource *res;
- u32 dword;
-
- dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11,
- res2mmio(res, 0, 0));
- }
-
- /* Initialize interrupt mapping */
-
- /* copied from stock bios */
- /*0x01800500,0x1800d509,0x00520d08*/
-
- dword = 0x08d0d218;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x8d001509;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0x00010271;
- pci_write_config32(dev, 0x84, dword);
-
- }
- }
-
- /* Now, assemble the table. */
- mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
-
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \
- bus_ck804[bus], (((dev)<<2)|(fn)), apicid_ck804, (pin))
-
-#if 0
- // Onboard ck804 smbus
- PCI_INT(0, sbdn+1, 1, 10); /* (this seems odd, how to test?) */
-
-#endif
- // Onboard ck804 USB
- PCI_INT(0, sbdn+2, 0, 23);
- PCI_INT(0, sbdn+2, 1, 23);
-
- // Onboard ck804 AC-97
- PCI_INT(0, sbdn+4, 0, 23);
-
- // Onboard ck804 SATA 0
- PCI_INT(0, sbdn+7, 0, 20);
-
- // Onboard ck804 SATA 1
- PCI_INT(0, sbdn+8, 0, 21);
-
- // Onboard ck804 NIC
- PCI_INT(0, sbdn+10, 0, 22);
-
-
- /* "AGR" slot */
- PCI_INT(1, 0, 0, 16);
- PCI_INT(1, 0, 1, 17);
-
- /* legacy PCI */
- PCI_INT(1, 7, 0, 17);
- PCI_INT(1, 7, 1, 18);
- PCI_INT(1, 7, 2, 19);
- PCI_INT(1, 7, 3, 16);
-
- PCI_INT(1, 8, 0, 18);
- PCI_INT(1, 8, 1, 19);
- PCI_INT(1, 8, 2, 16);
- PCI_INT(1, 8, 3, 17);
-
- PCI_INT(1, 9, 0, 19);
- PCI_INT(1, 9, 1, 16);
- PCI_INT(1, 9, 2, 17);
- PCI_INT(1, 9, 3, 18);
-
-
- /* PCI-E x1 port */
- PCI_INT(2, 0, 0, 19);
- /* XXX guesses */
- PCI_INT(2, 0, 1, 16);
- PCI_INT(2, 0, 2, 17);
- PCI_INT(2, 0, 3, 18);
-
- /* PCI-E x16 port */ /* XXX fix me ? */
- PCI_INT(3, 0, 0, 18);
- /* XXX guesses */
- PCI_INT(3, 0, 1, 19);
- PCI_INT(3, 0, 2, 16);
- PCI_INT(3, 0, 3, 17);
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_ck804[0]);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
deleted file mode 100644
index 39afe47749..0000000000
--- a/src/mainboard/msi/ms7135/romstage.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <cpu/x86/lapic.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627thg/w83627thg.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <console/console.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include <southbridge/nvidia/ck804/early_smbus.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
-#include "option_table.h"
-#endif
-
-#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include <southbridge/nvidia/ck804/early_setup_ss.h>
-#include "southbridge/nvidia/ck804/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void ms7135_set_ram_voltage(void)
-{
- u8 b;
- b = read_option(ram_voltage, 0);
- if (b > 4) /* default if above 2.70v */
- b = 0;
- printk(BIOS_INFO, "setting RAM voltage %08x\n", b);
- ck804_smbus_write_byte(1, 0x2f, 0x00, b);
-}
-
-static void ms7135_set_nf4_voltage(void)
-{
- u8 b;
- b = read_option(nf4_voltage, 0);
- if (b > 2) /* default if above 1.60v */
- b = 0;
- b |= 0x10;
- printk(BIOS_INFO, "setting NF4 voltage %08x\n", b);
- ck804_smbus_write_byte(1, 0x2f, 0x02, b);
-}
-
-static void sio_setup(void)
-{
- u32 dword;
- u8 byte;
-
- /* Subject decoding */
- byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
-
- /* LPC Positive Decode 0 */
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
- /* Serial 0, Serial 1 */
- dword |= (1 << 0) | (1 << 1);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const u16 spd_addr[] = {
- DIMM0, DIMM1, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- };
-
- int needs_reset;
- unsigned bsp_apicid = 0, nodes;
- struct mem_controller ctrl[8];
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx);
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- needs_reset = setup_coherent_ht_domain();
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- needs_reset |= ht_setup_chains_x();
- needs_reset |= ck804_early_setup_x();
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- nodes = get_nodes();
- //It's the time to set ctrl now;
- fill_mem_ctrl(nodes, ctrl, spd_addr);
-
- enable_smbus();
-
- ms7135_set_nf4_voltage();
- ms7135_set_ram_voltage();
-
-#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
- dump_spd_registers(&ctrl[0]);
- dump_smbus_registers();
-#endif
-
- sdram_initialize(nodes, ctrl);
-}
diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig
deleted file mode 100644
index dcc74717a0..0000000000
--- a/src/mainboard/msi/ms7260/Kconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-if BOARD_MSI_MS7260
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_AM2
- select DIMM_DDR2
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_MCP55
- select HT_CHAIN_DISTRIBUTE
- select MCP55_USE_NIC
- select MCP55_USE_AZA
- select SUPERIO_WINBOND_W83627EHG
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_512
- select QRANK_DIMM_SUPPORT
- select K8_ALLOCATE_IO_RANGE
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default msi/ms7260
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MEM_TRAIN_SEQ
- int
- default 2
-
-config MAINBOARD_PART_NUMBER
- string
- default "MS-7260"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-config MCP55_PCI_E_X_0
- int
- default 0
-
-endif # BOARD_MSI_MS7260
diff --git a/src/mainboard/msi/ms7260/Kconfig.name b/src/mainboard/msi/ms7260/Kconfig.name
deleted file mode 100644
index f5be5e9cf3..0000000000
--- a/src/mainboard/msi/ms7260/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_MSI_MS7260
- bool "MS-7260 (K9N Neo)"
diff --git a/src/mainboard/msi/ms7260/board_info.txt b/src/mainboard/msi/ms7260/board_info.txt
deleted file mode 100644
index 40ae7a4784..0000000000
--- a/src/mainboard/msi/ms7260/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Board name: MS-7260 (K9N Neo)
-Category: desktop
-Board URL: http://no.msi.com/product/mb/K9N-Neo--PCB-1-0-.html
-ROM package: PLCC
-ROM socketed: y
-Flashrom support: coreboot-only
-Release year: 2007
diff --git a/src/mainboard/msi/ms7260/cmos.layout b/src/mainboard/msi/ms7260/cmos.layout
deleted file mode 100644
index 78dc3e23a9..0000000000
--- a/src/mainboard/msi/ms7260/cmos.layout
+++ /dev/null
@@ -1,70 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# TODO: Check and fix up the values as needed.
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 200Mhz
-8 1 166Mhz
-8 2 133Mhz
-8 3 100Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/msi/ms7260/devicetree.cb b/src/mainboard/msi/ms7260/devicetree.cb
deleted file mode 100644
index 717ad009cf..0000000000
--- a/src/mainboard/msi/ms7260/devicetree.cb
+++ /dev/null
@@ -1,143 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_AM2 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1462 0x7260 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627ehg # Super I/O
- device pnp 4e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 4e.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 4e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 4e.3 on # Com2 / IrDA
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 4e.5 on # PS/2 keyboard & mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # PS/2 keyboard IRQ
- irq 0x72 = 12 # PS/2 mouse IRQ
- end
- device pnp 4e.106 off # Serial flash interface (SFI)
- # io 0x62 = 0x100
- end
- device pnp 4e.007 off # GPIO 1
- end
- device pnp 4e.107 off # Game port
- # io 0x60 = 0x220 # Datasheet: 0x201
- end
- device pnp 4e.207 off # MIDI
- # io 0x62 = 0x300 # Datasheet: 0x330
- # irq 0x70 = 9
- end
- device pnp 4e.307 off # GPIO 6
- end
- device pnp 4e.8 off # WDTO#, PLED
- end
- device pnp 4e.009 off # GPIO 2
- end
- device pnp 4e.109 off # GPIO 3
- end
- device pnp 4e.209 off # GPIO 4
- end
- device pnp 4e.309 off # GPIO 5
- end
- device pnp 4e.a off # ACPI
- end
- device pnp 4e.b on # Hardware monitor
- io 0x60 = 0xa10
- # TODO: IRQ?
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- end
- # TODO: Check if the stuff below is correct / needed.
- device pci 1.1 on # SM 1
- # PCI device SMBus address will
- # depend on addon PCI device, do
- # we need to scan_smbus_bus?
- # chip drivers/generic/generic # PCIXA slot 1
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 2
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # PCI slot 1
- # device i2c 53 on end
- # end
- # chip drivers/generic/generic # Master MCP55 PCI-E
- # device i2c 54 on end
- # end
- # chip drivers/generic/generic # Slave MCP55 PCI-E
- # device i2c 55 on end
- # end
- chip drivers/generic/generic # MAC EEPROM
- device i2c 51 on end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 off end # SATA 2 (N/A on this board)
- device pci 6.0 on end # PCI
- device pci 6.1 on end # AZA (HD Audio)
- device pci 8.0 on end # NIC
- device pci 9.0 off end # NIC (N/A on this board)
- device pci a.0 off end # PCI E 5 (N/A on this board?)
- device pci b.0 on end # PCI E 4
- device pci c.0 on end # PCI E 3
- device pci d.0 on end # PCI E 2
- device pci e.0 on end # PCI E 1
- device pci f.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # TODO: Check the two lines below.
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.0 on end # Link 1
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/msi/ms7260/get_bus_conf.c b/src/mainboard/msi/ms7260/get_bus_conf.c
deleted file mode 100644
index d768041e70..0000000000
--- a/src/mainboard/msi/ms7260/get_bus_conf.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-/* Global variables for MB layouts (shared by irqtable/mptable/acpi_table). */
-// busnum is default.
-unsigned char bus_mcp55[8]; // 1
-unsigned apicid_mcp55;
-
-unsigned pci1234x[] = {
- /* Here you only need to set value in pci1234 for HT-IO that could
- * be installed or not. You may need to preset pci1234 for HTIO board,
- * please refer to * src/northbridge/amd/amdk8/get_sblk_pci1234.c.
- */
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-unsigned hcdnx[] = {
- /* HT Chain device num, actually it is unit id base of every ht
- * device in chain, assume every chain only have 4 ht device at most.
- */
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- unsigned int apicid_base, sbdn;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* Do it only once. */
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* First byte of first chain */
- sbdn = sysconf.sbdn;
-
- for (i = 0; i < 8; i++)
- bus_mcp55[i] = 0;
-
- bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* MCP55 */
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0));
- if (dev) {
- bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_mcp55[2]++;
- } else {
- printk
- (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x06);
-
- bus_mcp55[1] = 2;
- bus_mcp55[2] = 3;
- }
-
- for (i = 2; i < 8; i++) {
- dev = dev_find_slot(bus_mcp55[0],
- PCI_DEVFN(sbdn + 0x0a + i - 2, 0));
- if (dev) {
- bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_mcp55 = apicid_base + 0;
-}
diff --git a/src/mainboard/msi/ms7260/hda_verb.c b/src/mainboard/msi/ms7260/hda_verb.c
deleted file mode 100644
index 072a306131..0000000000
--- a/src/mainboard/msi/ms7260/hda_verb.c
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[0] = {};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/msi/ms7260/irq_tables.c b/src/mainboard/msi/ms7260/irq_tables.c
deleted file mode 100644
index 359c1d4648..0000000000
--- a/src/mainboard/msi/ms7260/irq_tables.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern unsigned char bus_mcp55[8]; // 1
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned int slot_num, sbdn;
- uint8_t *v;
- uint8_t sum = 0;
- int i;
-
- /* Will find out all bus num and apic that share with mptable.c
- * and mptable.c and acpi_tables.c.
- */
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 and 0x100000. */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *)(addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
- pirq->rtr_bus = bus_mcp55[0];
- pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
- pirq->exclusive_irqs = 0;
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x0370; /* TODO: Hm, getpir suggests 0x0364 !? */
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* PCI bridge (00:06.0) */
- write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum)
- pirq->checksum = sum;
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c
deleted file mode 100644
index 6450d2da68..0000000000
--- a/src/mainboard/msi/ms7260/mptable.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_mcp55[8]; // 1
-extern unsigned apicid_mcp55;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned int sbdn;
- int i, j, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x1, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res)
- smp_write_ioapic(mc, apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
-
- dword = 0x43c6c643;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x81001a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0xd0001202;
- pci_write_config32(dev, 0x84, dword);
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
-
- /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 1) << 2) | 1, apicid_mcp55, 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 2) << 2) | 0, apicid_mcp55, 0x16); // 22
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 2) << 2) | 1, apicid_mcp55, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 6) << 2) | 1, apicid_mcp55, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 0, apicid_mcp55, 0x14); // 20
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 1, apicid_mcp55, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 2, apicid_mcp55, 0x15); // 21
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 8) << 2) | 0, apicid_mcp55, 0x16); // 22
-
- for (j = 7; j >= 2; j--) {
- if (!bus_mcp55[j])
- continue;
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2) | i, apicid_mcp55, 0x10 + (2 + j + i + 4 - sbdn % 4) % 4);
- }
-
- for (j = 0; j < 2; j++) {
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x06 + j) << 2) | i, apicid_mcp55, 0x10 + (2 + i + j) % 4);
- }
-
- /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_isa);
-
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/msi/ms7260/resourcemap.c b/src/mainboard/msi/ms7260/resourcemap.c
deleted file mode 100644
index f17fadf1a0..0000000000
--- a/src/mainboard/msi/ms7260/resourcemap.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* TODO: This is copied from the GIGABYTE GA-M57SLI-S4 target. */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
deleted file mode 100644
index 1da8ba9355..0000000000
--- a/src/mainboard/msi/ms7260/romstage.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <southbridge/nvidia/mcp55/mcp55.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/x86/lapic.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627ehg/w83627ehg.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
-
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl) {}
-void activate_spd_rom(const struct mem_controller *ctrl) {}
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define MCP55_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
-
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset = 0;
- unsigned bsp_apicid = 0;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0. */
- /* Allow the HT devices to be found. */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- /* FIXME: This should be part of the Super I/O code/config. */
- pnp_enter_conf_state(SERIAL_DEV);
- /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
- pnp_write_config(SERIAL_DEV, 0x24, 0);
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- pnp_exit_conf_state(SERIAL_DEV);
-
- setup_mb_resource_map();
- console_init();
- report_bist_failure(bist); /* Halt upon BIST failure. */
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- /* In BSP so could hold all AP until sysinfo is in RAM. */
- set_sysinfo_in_ram(0);
-
- setup_coherent_ht_domain(); /* Routing table and start other core0. */
- wait_all_core0_started();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched
- * becase optimize_link_coherent_ht is moved out from
- * setup_coherent_ht_domain, so here need to make sure last core0 is
- * started, esp for two way system (there may be APIC ID conflicts in
- * that case).
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* Set up chains and store link pair for optimization later. */
- ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- {
- msr_t msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
- {
- msr_t msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-#endif
-
- init_timer(); /* Need to use TMICT to synchronize FID/VID. */
-
- needs_reset |= optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= mcp55_early_setup_x();
-
- /* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl in sysinfo now. */
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
- /* All AP stopped? */
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
-}
diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig
deleted file mode 100644
index 355fdcfa35..0000000000
--- a/src/mainboard/msi/ms9185/Kconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-if BOARD_MSI_MS9185
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_F
- select DIMM_DDR2
- select DIMM_REGISTERED
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_BROADCOM_BCM5780
- select SOUTHBRIDGE_BROADCOM_BCM5785
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_NSC_PC87417
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_512
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select QRANK_DIMM_SUPPORT
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default msi/ms9185
-
-config DCACHE_RAM_BASE
- hex
- default 0xcc000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x04000
-
-config APIC_ID_OFFSET
- hex
- default 0x8
-
-config MAINBOARD_PART_NUMBER
- string
- default "MS-9185"
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x6
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_MSI_MS9185
diff --git a/src/mainboard/msi/ms9185/Kconfig.name b/src/mainboard/msi/ms9185/Kconfig.name
deleted file mode 100644
index 00594c059d..0000000000
--- a/src/mainboard/msi/ms9185/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_MSI_MS9185
- bool "MS-9185 (K9SD Master-S2R)"
diff --git a/src/mainboard/msi/ms9185/board_info.txt b/src/mainboard/msi/ms9185/board_info.txt
deleted file mode 100644
index e5081f9922..0000000000
--- a/src/mainboard/msi/ms9185/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Board name: K9SD Master-S2R (MS-9185)
-Category: server
-Board URL: http://www.msiserver.de/de/Produkte/Server_Mainboards/K9SD_Master_S2R_MS_9185.aspx
-Release year: 2006
diff --git a/src/mainboard/msi/ms9185/cmos.layout b/src/mainboard/msi/ms9185/cmos.layout
deleted file mode 100644
index e42037e1a1..0000000000
--- a/src/mainboard/msi/ms9185/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 400Mhz
-8 1 333Mhz
-8 2 266Mhz
-8 3 200Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/msi/ms9185/devicetree.cb b/src/mainboard/msi/ms9185/devicetree.cb
deleted file mode 100644
index 3c9168d2ee..0000000000
--- a/src/mainboard/msi/ms9185/devicetree.cb
+++ /dev/null
@@ -1,85 +0,0 @@
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_F
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1022 0x2b80 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.0 on # northbridge
- # devices on link 0
- chip southbridge/broadcom/bcm5780 # HT2000
- device pci 0.0 on end # PXB 1 0x0130
- device pci 1.0 on # PXB 2 0x0130
- device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
- device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
- end
- device pci 2.0 on end # PCI E 1 #0x0132
- device pci 3.0 on end # PCI E 2
- device pci 4.0 on end # PCI E 3
- device pci 5.0 on end # PCI E 4
- end
- chip southbridge/broadcom/bcm5785 # HT1000
- device pci 0.0 on # HT PXB 0x0036
- device pci d.0 on end # PPBX 0x0104
- device pci e.0 on end # SATA 0x024a
- device pci e.1 on end # SATA 0x024a bx_a001
- device pci e.2 on end # SATA 0x024a bx_a001
- device pci e.3 on end # SATA 0x024a bx_a001
- end
- device pci 1.0 on # Legacy pci main 0x0205
- end
- device pci 1.1 on end # IDE 0x0214
- device pci 1.2 on # LPC 0x0234
- chip superio/nsc/pc87417
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 off # Com 2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Com 1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.4 off end # SWC
- device pnp 2e.5 off end # Mouse
- device pnp 2e.6 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.7 off end # GPIO
- device pnp 2e.f off end # XBUS
- device pnp 2e.10 on #RTC
- io 0x60 = 0x70
- io 0x62 = 0x72
- end
- end
- end
- device pci 1.3 on end # WDTimer 0x0238
- device pci 1.4 on end # XIOAPIC0 0x0235
- device pci 1.5 on end # XIOAPIC1
- device pci 1.6 on end # XIOAPIC2
- device pci 2.0 on end # USB 0x0223
- device pci 2.1 on end # USB
- device pci 2.2 on end # USB
- device pci 3.0 on end # it is in bcm5785_0 bus
- end
- end # device pci 18.0
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end # amdk8
- end #domain
-end
diff --git a/src/mainboard/msi/ms9185/get_bus_conf.c b/src/mainboard/msi/ms9185/get_bus_conf.c
deleted file mode 100644
index d02f30687a..0000000000
--- a/src/mainboard/msi/ms9185/get_bus_conf.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include <stdlib.h>
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
-
- struct device *dev;
- int i;
- struct mb_sysconf_t *m;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.mb = &mb_sysconf;
-
- m = sysconf.mb;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
-
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
- m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780
-
- m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff;
- m->bus_bcm5780[0] = m->bus_bcm5785_0;
-
- /* bcm5785 */
- dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn, 0));
- if (dev) {
- m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd, 0));
- if (dev) {
- m->bus_bcm5785_1_1 =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_bcm5785_0, sysconf.sbdn);
- }
-
- /* bcm5780 */
- for (i = 1; i < 7; i++) {
- dev =
- dev_find_slot(m->bus_bcm5780[0],
- PCI_DEVFN(m->sbdn2 + i - 1, 0));
- if (dev) {
- m->bus_bcm5780[i] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_bcm5780[0], m->sbdn2 + i - 1);
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(3);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- for (i = 0; i < 3; i++)
- m->apicid_bcm5785[i] = apicid_base + i;
-}
diff --git a/src/mainboard/msi/ms9185/irq_tables.c b/src/mainboard/msi/ms9185/irq_tables.c
deleted file mode 100644
index 65f82a2823..0000000000
--- a/src/mainboard/msi/ms9185/irq_tables.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
-
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
-
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
-
- uint8_t sum = 0;
- int i;
-
- struct mb_sysconf_t *m;
-
- get_bus_conf();
-
- m = sysconf.mb;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = m->bus_bcm5785_0;
- pirq->rtr_devfn = (sysconf.sbdn << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1166;
- pirq->rtr_device = 0x0036;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, m->bus_bcm5785_0, (sysconf.sbdn << 3) | 0,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/msi/ms9185/mb_sysconf.h b/src/mainboard/msi/ms9185/mb_sysconf.h
deleted file mode 100644
index 6944c2465c..0000000000
--- a/src/mainboard/msi/ms9185/mb_sysconf.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_bcm5780[7];
- unsigned char bus_bcm5785_0;
- unsigned char bus_bcm5785_1;
- unsigned char bus_bcm5785_1_1;
- unsigned apicid_bcm5785[3];
-
- unsigned sbdn2;
-};
-
-#endif
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
deleted file mode 100644
index ea7c905af0..0000000000
--- a/src/mainboard/msi/ms9185/mptable.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2001 Eric W.Biederman <ebiderman@lnxi.com>
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-#include <cpu/amd/multicore.h>
-#endif
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
-
- int i, bus_isa;
- struct mb_sysconf_t *m;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- m = sysconf.mb;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev = NULL;
- struct resource *res;
- for (i = 0; i < 3; i++) {
- dev = dev_find_device(0x1166, 0x0235, dev);
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11,
- res2mmio(res, 0, 0));
- }
- }
- }
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
-
-//IDE
- outb(0x02, 0xc00); outb(0x0e, 0xc01);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
- m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE
-
-//SATA
- outb(0x07, 0xc00); outb(0x0f, 0xc01);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xf);
-
-//USB
- outb(0x01, 0xc00); outb(0x0a, 0xc01);
- for (i = 0; i < 3; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); //
-
-
-
- /* enable int */
- /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
- {
- struct device *dev;
- dev = dev_find_device(0x1166, 0x0205, 0);
- if (dev) {
- uint32_t dword;
- dword = pci_read_config32(dev, 0x6c);
- dword |= (1 << 4); // enable interrupts
- pci_write_config32(dev, 0x6c, dword);
- }
- }
-
-//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
- // AIC 8130 Galileo Technology...
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- m->bus_bcm5785_1_1, (6 << 2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
-
-
-//pci slot (on bcm5785)
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- m->bus_bcm5785_0, (5 << 2)|i, m->apicid_bcm5785[1], 8+i%4); //
-
-
-//onboard ati
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- m->bus_bcm5785_0, (4 << 2)|0, m->apicid_bcm5785[1], 0x1);
-
-//PCI-X on bcm5780
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- m->bus_bcm5780[1], (4 << 2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
-
-//onboard Broadcom
- for (i = 0; i < 2; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- m->bus_bcm5780[2], (4 << 2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
-
-
-// First PCI-E x8
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- m->bus_bcm5780[5], (0 << 2)|i, m->apicid_bcm5785[1], 0xe); //
-
-
-// Second PCI-E x8
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- m->bus_bcm5780[3], (0 << 2)|i, m->apicid_bcm5785[1], 0xc); //
-
-// Third PCI-E x1
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- m->bus_bcm5780[4], (0 << 2)|i, m->apicid_bcm5785[1], 0xd); //
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/msi/ms9185/resourcemap.c b/src/mainboard/msi/ms9185/resourcemap.c
deleted file mode 100644
index 533f31a49a..0000000000
--- a/src/mainboard/msi/ms9185/resourcemap.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2003 Stefan Reinauer <stepan@coresystems.de>
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ms9185 needs a different resource map
- *
- */
-
-static void setup_ms9185_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000203,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
deleted file mode 100644
index d8cff07ff3..0000000000
--- a/src/mainboard/msi/ms9185/romstage.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Tyan
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/broadcom/bcm5785/early_smbus.c"
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <reset.h>
-#include <cpu/x86/lapic.h>
-
-#include <superio/nsc/pc87417/pc87417.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
-#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-
-unsigned get_sbdn(unsigned bus);
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#define SMBUS_SWITCH1 0x70
-#define SMBUS_SWITCH2 0x72
- unsigned device = (ctrl->channel0[0]) >> 8;
- smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
- smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
-}
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "southbridge/broadcom/bcm5785/early_setup.c"
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-#define RC0 (0x10 << 8)
-#define RC1 (0x01 << 8)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- //first node
- RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
- RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
- //second node
- RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
- RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
-
- int needs_reset;
- unsigned bsp_apicid = 0;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- bcm5785_enable_lpc();
- //enable RTC
- pc87417_enable_dev(RTC_DEV);
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
- setup_ms9185_resource_map();
-
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- setup_coherent_ht_domain();
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
-//bx_a010- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
- bcm5785_early_setup();
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-#endif
-
-#if 1
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
-
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-#endif
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
- //do we need apci timer, tsc...., only debug need it for better output
- /* all ap stopped? */
-// init_timer(); // Need to use TMICT to synchronize FID/VID
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
-}
diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig
deleted file mode 100644
index 9314492074..0000000000
--- a/src/mainboard/msi/ms9282/Kconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-if BOARD_MSI_MS9282
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_F
- select DIMM_DDR2
- select DIMM_REGISTERED
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_MCP55
- select SUPERIO_WINBOND_W83627EHG
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_512
- select QRANK_DIMM_SUPPORT
- select DRIVERS_I2C_ADM1027
- select DRIVERS_I2C_I2CMUX2
-
-config MAINBOARD_DIR
- string
- default msi/ms9282
-
-config DCACHE_RAM_BASE
- hex
- default 0xcc000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x04000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "MS-9282"
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_MSI_MS9282
diff --git a/src/mainboard/msi/ms9282/Kconfig.name b/src/mainboard/msi/ms9282/Kconfig.name
deleted file mode 100644
index 260c7de96e..0000000000
--- a/src/mainboard/msi/ms9282/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_MSI_MS9282
- bool "MS-9282 (K9SD Master)"
diff --git a/src/mainboard/msi/ms9282/board_info.txt b/src/mainboard/msi/ms9282/board_info.txt
deleted file mode 100644
index 01c035f93a..0000000000
--- a/src/mainboard/msi/ms9282/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Board name: K9SD Master (MS-9282)
-Category: server
-Board URL: http://cweb.msi.com.tw/program/products/server/svr/pro_svr_detail.php?UID=632
-Release year: 2006
diff --git a/src/mainboard/msi/ms9282/cmos.layout b/src/mainboard/msi/ms9282/cmos.layout
deleted file mode 100644
index c4c90f697f..0000000000
--- a/src/mainboard/msi/ms9282/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/msi/ms9282/devicetree.cb b/src/mainboard/msi/ms9282/devicetree.cb
deleted file mode 100644
index 747347e504..0000000000
--- a/src/mainboard/msi/ms9282/devicetree.cb
+++ /dev/null
@@ -1,182 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_F # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1462 0x9282 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627ehg # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # PS/2 keyboard & mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.106 off # Serial flash interface (SFI)
- io 0x60 = 0x100
- end
- device pnp 2e.007 off # GPIO 1
- end
- device pnp 2e.107 off # Game port
- io 0x60 = 0x220
- end
- device pnp 2e.207 off # MIDI
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.307 off # GPIO 6
- end
- device pnp 2e.8 off end # WDTO#, PLED
- device pnp 2e.009 off # GPIO 2
- end
- device pnp 2e.109 off # GPIO 3
- end
- device pnp 2e.209 off # GPIO 4
- end
- device pnp 2e.309 off # GPIO 5
- end
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/i2c/i2cmux2 # PCA9554 SMBus mux
- device i2c 70 on # 0 pca9554 1
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 57 on end
- end
- end
- device i2c 70 on # 0 pca9554 2
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 57 on end
- end
- end
- end
- end
- device pci 1.1 on # SM 1
- chip drivers/i2c/i2cmux2 # pca9554 SMBus mux
- device i2c 72 on # PCA9554 channel 1
- chip drivers/i2c/adm1027 # HWM ADT7476 1
- device i2c 2e on end
- end
- end
- device i2c 72 on # PCA9545 channel 2
- chip drivers/i2c/adm1027 # HWM ADT7463
- device i2c 2e on end
- end
- end
- device i2c 72 on end # PCA9545 channel 3
- device i2c 72 on # PCA9545 channel 4
- chip drivers/i2c/adm1027 # HWM ADT7476 2
- device i2c 2e on end
- end
- end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
- device pci 6.0 on # P2P
- device pci 4.0 on end
- end
- device pci 7.0 on end # reserve
- device pci 8.0 on end # MAC0
- device pci 9.0 on end # MAC1
- device pci a.0 on
- device pci 0.0 on
- device pci 4.0 on end # PCI-E LAN1
- device pci 4.1 on end # PCI-E LAN2
- end
- end # 0x376
- device pci b.0 on end # PCI E 0x374
- device pci c.0 on end
- device pci d.0 on # SAS
- device pci 0.0 on end
- end # PCI E 1 0x378
- device pci e.0 on end # PCI E 0 0x375
- device pci f.0 on end # PCI E 0x377, PCI-E slot
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- end
- end
- device pci 18.0 on end # Link 1
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/msi/ms9282/get_bus_conf.c b/src/mainboard/msi/ms9282/get_bus_conf.c
deleted file mode 100644
index a072d6aa36..0000000000
--- a/src/mainboard/msi/ms9282/get_bus_conf.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include <stdlib.h>
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
- 0x0000ff0,
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
- 0x20202020,
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
- struct mb_sysconf_t *m;
-
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.mb = &mb_sysconf;
-
- m = sysconf.mb;
- memset(m, 0, sizeof(struct mb_sysconf_t));
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
-
- m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* MCP55 */
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06, 0));
- if (dev) {
- m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sysconf.sbdn + 0x06);
- }
-
- for (i = 2; i < 8; i++) {
- dev =
- dev_find_slot(m->bus_mcp55[0],
- PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
- if (dev) {
- m->bus_mcp55[i] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- m->apicid_mcp55 = apicid_base + 0;
-
-}
diff --git a/src/mainboard/msi/ms9282/irq_tables.c b/src/mainboard/msi/ms9282/irq_tables.c
deleted file mode 100644
index cbb621a906..0000000000
--- a/src/mainboard/msi/ms9282/irq_tables.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
- struct mb_sysconf_t *m;
- unsigned sbdn;
-
- uint8_t sum = 0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = m->bus_mcp55[0];
- pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x0370;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
- unsigned devn = sysconf.hcdn[i] & 0xff;
-
- write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8,
- 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
- }
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/msi/ms9282/mb_sysconf.h b/src/mainboard/msi/ms9282/mb_sysconf.h
deleted file mode 100644
index 3edba64696..0000000000
--- a/src/mainboard/msi/ms9282/mb_sysconf.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_mcp55[8]; //1
- unsigned apicid_mcp55;
-};
-
-#endif
diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c
deleted file mode 100644
index d3a4287b96..0000000000
--- a/src/mainboard/msi/ms9282/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- struct mb_sysconf_t *m;
- unsigned sbdn;
-
- int i, j, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
- }
-
- dword = 0x43c6c643;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x81001a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0xd00002d2;
- pci_write_config32(dev, 0x84, dword);
-
- }
-
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
-
-//SMBUS
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
-
-//USB1.1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
-
-//USB2.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
-
-//SATA1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
-
-//SATA2
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
-
-//SATA3
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
-
-//NIC1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
-//NIC2
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
-
- for (j = 7; j >= 2; j--) {
- if (!m->bus_mcp55[j])
- continue;
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
- }
-
- for (j = 0; j < 1; j++)
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/msi/ms9282/resourcemap.c b/src/mainboard/msi/ms9282/resourcemap.c
deleted file mode 100644
index 53b470a5e4..0000000000
--- a/src/mainboard/msi/ms9282/resourcemap.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2003 Stefan Reinauer <stepan@coresystems.de>
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * MSI ms9282 needs a different resource map
- *
- */
-
-static void setup_ms9282_resource_map(void)
-{
- static const unsigned int register_values[] = {
-#if 1
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-#endif
-#if 1
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-#endif
-#if 1
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-#endif
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
-#if 1
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003,
-// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-#endif
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
deleted file mode 100644
index 6bde880622..0000000000
--- a/src/mainboard/msi/ms9282/romstage.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <southbridge/nvidia/mcp55/mcp55.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627ehg/w83627ehg.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include <spd.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <device/pci_ids.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#define SMBUS_SWITCH1 0x70
-#define SMBUS_SWITCH2 0x72
- unsigned device=(ctrl->channel0[0])>>8;
- smbus_send_byte(SMBUS_SWITCH1, device);
- smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
-}
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-
-//set GPIO to input mode
-#define MCP55_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
-
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-/* FIXME
- * Dummy method to allow build
- * Determine if this board / CPU should support
- * FID/VID and implement proper support if so
- */
-#if IS_ENABLED(CONFIG_SET_FIDVID)
-void init_fidvid_ap(u32 bsp_apicid, u32 apicid) { }
-#endif
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-}
-
-//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
-#define RC0 (2 << 8)
-#define RC1 (1 << 8)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // Node 0
- RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
- RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
- // node 1
- RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
- RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
- };
-
- unsigned bsp_apicid = 0;
- int needs_reset;
- struct sys_info *sysinfo = &sysinfo_car;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0) {
- //init_cpus(cpu_init_detectedx);
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- setup_ms9282_resource_map();
-
- setup_coherent_ht_domain();
-
- wait_all_core0_started();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- start_other_cores();
- //wait_all_other_cores_started(bsp_apicid);
-#endif
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
- init_timer(); /* Need to use TMICT to synchronize FID/VID. */
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= mcp55_early_setup_x();
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- //It's the time to set ctrl now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/nvidia/Kconfig b/src/mainboard/nvidia/Kconfig
deleted file mode 100644
index b06b7286f3..0000000000
--- a/src/mainboard/nvidia/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_NVIDIA
-
-choice
- prompt "Mainboard model"
-
-source "src/mainboard/nvidia/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/nvidia/*/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "NVIDIA"
-
-endif # VENDOR_NVIDIA
diff --git a/src/mainboard/nvidia/Kconfig.name b/src/mainboard/nvidia/Kconfig.name
deleted file mode 100644
index 44b0fa6fab..0000000000
--- a/src/mainboard/nvidia/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_NVIDIA
- bool "NVIDIA"
diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig
deleted file mode 100644
index b5e51c5ff0..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/Kconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-if BOARD_NVIDIA_L1_2PVV
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_F
- select DIMM_DDR2
- select DIMM_REGISTERED
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_MCP55
- select HT_CHAIN_DISTRIBUTE
- select MCP55_USE_NIC
- select MCP55_USE_AZA
- select SUPERIO_WINBOND_W83627EHG
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_512
- select QRANK_DIMM_SUPPORT
- select K8_ALLOCATE_IO_RANGE
-
-config MAINBOARD_DIR
- string
- default nvidia/l1_2pvv
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MEM_TRAIN_SEQ
- int
- default 1
-
-config MCP55_NUM
- int
- default 2
-
-config MAINBOARD_PART_NUMBER
- string
- default "l1_2pvv"
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-config MCP55_PCI_E_X_0
- int
- default 2
-
-endif # BOARD_NVIDIA_L1_2PVV
diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig.name b/src/mainboard/nvidia/l1_2pvv/Kconfig.name
deleted file mode 100644
index 40dffc643f..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_NVIDIA_L1_2PVV
- bool "l1_2pvv"
diff --git a/src/mainboard/nvidia/l1_2pvv/board_info.txt b/src/mainboard/nvidia/l1_2pvv/board_info.txt
deleted file mode 100644
index b351b8e696..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: eval
diff --git a/src/mainboard/nvidia/l1_2pvv/cmos.layout b/src/mainboard/nvidia/l1_2pvv/cmos.layout
deleted file mode 100644
index 9e6a9e56f2..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 200Mhz
-8 1 166Mhz
-8 2 133Mhz
-8 3 100Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/nvidia/l1_2pvv/devicetree.cb b/src/mainboard/nvidia/l1_2pvv/devicetree.cb
deleted file mode 100644
index d713e3f7cc..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/devicetree.cb
+++ /dev/null
@@ -1,180 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_F # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1022 0x2b80 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627ehg # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # PS/2 keyboard & mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.106 off # Serial flash interface (SFI)
- io 0x60 = 0x100
- end
- device pnp 2e.007 off # GPIO 1
- end
- device pnp 2e.107 off # Game port
- io 0x60 = 0x220
- end
- device pnp 2e.207 off # MIDI
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.307 off # GPIO 6
- end
- device pnp 2e.8 off # WDTO#, PLED
- end
- device pnp 2e.009 off # GPIO 2
- end
- device pnp 2e.109 off # GPIO 3
- end
- device pnp 2e.209 off # GPIO 4
- end
- device pnp 2e.309 off # GPIO 5
- end
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic # DIMM 1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic # DIMM 1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic # DIMM 1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic # DIMM 1-1-1
- device i2c 57 on end
- end
- end
- device pci 1.1 on # SM 1
- # PCI device SMBus address will
- # depend on addon PCI device, do
- # we need to scan_smbus_bus?
- # chip drivers/generic/generic # PCIXA slot 1
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 2
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # PCI slot 1
- # device i2c 53 on end
- # end
- # chip drivers/generic/generic # Master MCP55 PCI-E
- # device i2c 54 on end
- # end
- # chip drivers/generic/generic # Slave MCP55 PCI-E
- # device i2c 55 on end
- # end
- chip drivers/generic/generic # MAC EEPROM
- device i2c 51 on end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
- device pci 6.0 on end # PCI
- device pci 6.1 on end # AZA
- device pci 8.0 on end # NIC
- device pci 9.0 on end # NIC
- device pci a.0 on end # PCI E 5
- device pci b.0 off end # PCI E 4
- device pci c.0 off end # PCI E 3
- device pci d.0 on end # PCI E 2
- device pci e.0 off end # PCI E 1
- device pci f.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.0 on end # Link 1
- device pci 18.0 on # Link 2 == LDT 2
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on end # LPC
- device pci 1.1 on end # SM 0
- device pci 2.0 off end # USB 1.1
- device pci 2.1 off end # USB 2
- device pci 4.0 off end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
- device pci 6.0 off end # PCI
- device pci 6.1 off end # AZA
- device pci 8.0 on end # NIC
- device pci 9.0 on end # NIC
- device pci a.0 on end # PCI E 5
- device pci b.0 off end # PCI E 4
- device pci c.0 off end # PCI E 3
- device pci d.0 on end # PCI E 2
- device pci e.0 on end # PCI E 1
- device pci f.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
deleted file mode 100644
index 2a10eeb7a8..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include <stdlib.h>
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-unsigned pci1234x[] =
-{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
- 0x0000ff0,
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-unsigned hcdnx[] =
-{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
- 0x20202020,
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-
-
-
-static unsigned get_bus_conf_done = 0;
-
-static unsigned get_hcid(unsigned i)
-{
- unsigned id = 0;
-
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-
- unsigned devn = sysconf.hcdn[i] & 0xff;
-
- struct device *dev;
-
- dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
-
- switch (dev->device) {
- case 0x0369: //IO55
- id = 4;
- break;
- }
-
- // we may need more way to find out hcid: subsystem id? GPIO read ?
-
- // we need use id for 1. bus num, 2. mptable, 3. ACPI table
-
- return id;
-}
-
-void get_bus_conf(void)
-{
- unsigned apicid_base;
- struct mb_sysconf_t *m;
-
- int i;
-
- if (get_bus_conf_done)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.mb = &mb_sysconf;
-
- m = sysconf.mb;
- memset(m, 0, sizeof(struct mb_sysconf_t));
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
-
- m->sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain
-
- m->bus_mcp55 = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* MCP55b */
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x0f))
- continue;
- // check hcid type here
- sysconf.hcid[i] = get_hcid(i);
- if (!sysconf.hcid[i])
- continue; //unknown co processor
-
- m->bus_mcp55b = (sysconf.pci1234[1]>>16) & 0xff;
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(2);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- m->apicid_mcp55 = apicid_base+0;
- m->apicid_mcp55b = apicid_base+1;
-}
diff --git a/src/mainboard/nvidia/l1_2pvv/hda_verb.c b/src/mainboard/nvidia/l1_2pvv/hda_verb.c
deleted file mode 100644
index 31052f2a15..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/hda_verb.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Tyan Computer
- * Copyright (C) 2006-2007 AMD
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
- /* coreboot specific header */
- 0x10ec0880, // Codec Vendor / Device ID: Realtek ALC880
- 0x00000000, // Subsystem ID
- 0x0000000d, // Number of jacks
-
- /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x0000e601 */
- AZALIA_SUBVENDOR(0x0, 0x0000e601),
-
- /* NID 0x14, FRONT-OUT-L/R */
- AZALIA_PIN_CFG(0x0, 0x14, 0x01014410),
-
- /* NID 0x15, SURR-OUT-L/R */
- AZALIA_PIN_CFG(0x0, 0x15, 0x01011412),
-
- /* NID 0x16, CEN/LFE-OUT */
- AZALIA_PIN_CFG(0x0, 0x16, 0x01016011),
-
- /* NID 0x17, SIDE-SURR-L/R */
- AZALIA_PIN_CFG(0x0, 0x17, 0x01012014),
-
- /* NID 0x18, MIC1-L/R, VREFO */
- AZALIA_PIN_CFG(0x0, 0x18, 0x01a19c30),
-
- /* NID 0x19, MIC2-L/R, VREFO */
- AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c40),
-
- /* NID 0x1a, LINE1-L/R, VREFO */
- AZALIA_PIN_CFG(0x0, 0x1a, 0x01813431),
-
- /* NID 0x1b, LINE2-L/R, VREFO */
- AZALIA_PIN_CFG(0x0, 0x1b, 0x0221441f),
-
- /* NID 0x1c, CD-L/R / GND */
- AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),
-
- /* NID 0x1d, PCBEEP */
- AZALIA_PIN_CFG(0x0, 0x1d, 0x9983013e),
-
- /* NID 0x1e, S/PDIF-OUT */
- AZALIA_PIN_CFG(0x0, 0x1e, 0x01454120),
-
- /* NID 0x1f, S/PDIF-IN */
- AZALIA_PIN_CFG(0x0, 0x1f, 0x01c59150),
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/nvidia/l1_2pvv/irq_tables.c b/src/mainboard/nvidia/l1_2pvv/irq_tables.c
deleted file mode 100644
index 061d276b78..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/irq_tables.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
- struct mb_sysconf_t *m;
- unsigned sbdn;
-
- uint8_t sum = 0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = m->bus_mcp55;
- pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x0370;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, m->bus_mcp55, ((sbdn + 6) << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
- unsigned devn = sysconf.hcdn[i] & 0xff;
-
- write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8,
- 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
- }
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/nvidia/l1_2pvv/mb_sysconf.h b/src/mainboard/nvidia/l1_2pvv/mb_sysconf.h
deleted file mode 100644
index 64837f6174..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/mb_sysconf.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_mcp55;
- unsigned char bus_mcp55b;
- unsigned apicid_mcp55;
- unsigned apicid_mcp55b;
- unsigned sbdnb;
-};
-
-#endif
diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c
deleted file mode 100644
index 76d2b81f79..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/mptable.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- struct mb_sysconf_t *m;
- unsigned sbdn;
- int i, j, bus_isa;
- unsigned char apicpin[4];
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res)
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
-
- /* Initialize interrupt mapping*/
- dword = pci_read_config32(dev, 0x74);
- dword &= ~(1 << 15);
- dword |= 1 << 2;
- pci_write_config32(dev, 0x74, dword);
-
- dword = 0x43c6c643;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x81001a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0xd00012d2;
- pci_write_config32(dev, 0x84, dword);
-
- }
-
- if (m->bus_mcp55b) {
- dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res)
- smp_write_ioapic(mc, m->apicid_mcp55b, 0x11,
- res2mmio(res, 0, 0));
-
- dword = 0x43c60000;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x81000000;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0xd00002d0;
- pci_write_config32(dev, 0x84, dword);
-
- }
-
- }
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); // 10
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
-
-//Slot PCIE
- for (j = 2; j < 8; j++) {
- struct device *dev;
- dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0));
- if (!dev || !dev->enabled)
- continue;
- for (i = 0; i < 4; i++)
- apicpin[i] = 0x10 + (2+j+i+4-sbdn%4)%4;
- smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin);
- }
-
-//Slot PCI 32
- {
- struct device *dev;
- dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0));
- if (dev && dev->enabled) {
- for (i = 0; i < 4; i++)
- apicpin[i] = 0x10 + (2+i)%4;
- smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin);
- }
- }
-
- if (m->bus_mcp55b) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|0, m->apicid_mcp55b, 0x14); // 20
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|1, m->apicid_mcp55b, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|2, m->apicid_mcp55b, 0x15); // 21
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+8)<<2)|0, m->apicid_mcp55b, 0x16); // 22
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+9)<<2)|0, m->apicid_mcp55b, 0x15); // 21
-
-
- //Slot PCIE
- for (j = 2; j < 8; j++) {
- struct device *dev;
- dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x0a + j - 2 , 0));
- if (!dev || !dev->enabled)
- continue;
- for (i = 0; i < 4; i++) {
- apicpin[i] = 0x10 + (2+j+i+4-m->sbdnb%4)%4;
- }
- smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55b, apicpin);
- }
-
- }
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/nvidia/l1_2pvv/resourcemap.c b/src/mainboard/nvidia/l1_2pvv/resourcemap.c
deleted file mode 100644
index 85782b78da..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/resourcemap.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
-// PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
-// PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
-// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
deleted file mode 100644
index d6962f0458..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <southbridge/nvidia/mcp55/mcp55.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627ehg/w83627ehg.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define MCP55_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
-
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset = 0;
- unsigned bsp_apicid = 0;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- pnp_enter_conf_state(SERIAL_DEV);
- pnp_write_config(SERIAL_DEV, 0x24, 0);
- pnp_exit_conf_state(SERIAL_DEV);
-
- setup_mb_resource_map();
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
- setup_coherent_ht_domain(); // routing table and start other core0
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-#endif
-
- init_timer(); /* Need to use TMICT to synchronize FID/VID. */
-
- needs_reset |= optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= mcp55_early_setup_x();
-
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
- /* all ap stopped? */
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig
deleted file mode 100644
index d9ad74b212..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/Kconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-if BOARD_SIEMENS_SITEMP_G1P1
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_S1G1
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_RS690
- select SOUTHBRIDGE_AMD_SB600
- select SUPERIO_ITE_IT8712F
- select HAVE_ACPI_TABLES
- select HAVE_MP_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_OPTION_TABLE
- select HAVE_CMOS_DEFAULT
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select BOARD_ROMSIZE_KB_1024
- select QRANK_DIMM_SUPPORT
- select SET_FIDVID
- select GFXUMA
- select EXT_CONF_SUPPORT
-
-config MAINBOARD_DIR
- string
- default siemens/sitemp_g1p1
-
-config LINT01_CONVERSION
- bool
- default y
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "MB SITEMP-G1 (U1P0/U1P1)"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-config IOMMU
- bool
- default n
-
-config HW_SCRUBBER
- bool
- default n
-
-config ECC_MEMORY
- bool
- default n
-
-endif # BOARD_SIEMENS_SITEMP_G1P1
diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig.name b/src/mainboard/siemens/sitemp_g1p1/Kconfig.name
deleted file mode 100644
index 4c48ecbc2b..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_SIEMENS_SITEMP_G1P1
- bool "MB SITEMP-G1 (U1P0/U1P1)"
diff --git a/src/mainboard/siemens/sitemp_g1p1/Makefile.inc b/src/mainboard/siemens/sitemp_g1p1/Makefile.inc
deleted file mode 100644
index e1348ca423..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-## Copyright (C) 2010 Siemens AG, Inc.
-## (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) += int15_func.c
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/debug.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/debug.asl
deleted file mode 100644
index 44c37bb9a0..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/acpi/debug.asl
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- DefinitionBlock (
- "DSDT.AML",
- "DSDT",
- 0x01,
- "XXXXXX",
- "XXXXXXXX",
- 0x00010001
- )
- {
- #include "debug.asl"
- }
-*/
-
-/*
-* 0x80: POST_BASE
-* 0x3F8: DEBCOM_BASE
-* X80: POST_REGION
-* P80: PORT80
-*
-* CREG: DEBCOM_REGION
-* CUAR: DEBCOM_UART
-* CDAT: DEBCOM_DATA
-* CDLM: DEBCOM_DLM
-* DLCR: DEBCOM_LCR
-* CMCR: DEBCOM_MCR
-* CLSR: DEBCOM_LSR
-*
-* DEBUG_INIT DINI
-*/
-
-OperationRegion(X80, SystemIO, 0x80, 1)
- Field(X80, ByteAcc, NoLock, Preserve)
-{
- P80, 8
-}
-
-OperationRegion(CREG, SystemIO, 0x3F8, 8)
- Field(CREG, ByteAcc, NoLock, Preserve)
-{
- CDAT, 8,
- CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8
-}
-
-/*
-* DINI
-* Initialize the COM port to 115,200 8-N-1
-*/
-Method(DINI)
-{
- store(0x83, DLCR)
- store(0x01, CDAT) /* 115200 baud (low) */
- store(0x00, CDLM) /* 115200 baud (high) */
- store(0x03, DLCR) /* word=8 stop=1 parity=none */
- store(0x03, CMCR) /* DTR=1 RTS=1 Out2=Off Loop=Off */
- store(0x00, CDLM) /* turn off interrupts */
-}
-
-/*
-* THRE
-* Wait for COM port transmitter holding register to go empty
-*/
-Method(THRE)
-{
- and(CLSR, 0x20, local0)
- while (Lequal(local0, Zero)) {
- and(CLSR, 0x20, local0)
- }
-}
-
-/*
-* OUTX
-* Send a single raw character
-*/
-Method(OUTX, 1)
-{
- THRE()
- store(Arg0, CDAT)
-}
-
-/*
-* OUTC
-* Send a single character, expanding LF into CR/LF
-*/
-Method(OUTC, 1)
-{
- if (LEqual(Arg0, 0x0a)) {
- OUTX(0x0d)
- }
- OUTX(Arg0)
-}
-
-/*
-* DBGN
-* Send a single hex nibble
-*/
-Method(DBGN, 1)
-{
- and(Arg0, 0x0f, Local0)
- if (LLess(Local0, 10)) {
- add(Local0, 0x30, Local0)
- } else {
- add(Local0, 0x37, Local0)
- }
- OUTC(Local0)
-}
-
-/*
-* DBGB
-* Send a hex byte
-*/
-Method(DBGB, 1)
-{
- ShiftRight(Arg0, 4, Local0)
- DBGN(Local0)
- DBGN(Arg0)
-}
-
-/*
-* DBGW
-* Send a hex word
-*/
-Method(DBGW, 1)
-{
- ShiftRight(Arg0, 8, Local0)
- DBGB(Local0)
- DBGB(Arg0)
-}
-
-/*
-* DBGD
-* Send a hex Dword
-*/
-Method(DBGD, 1)
-{
- ShiftRight(Arg0, 16, Local0)
- DBGW(Local0)
- DBGW(Arg0)
-}
-
-/*
-* DBGO
-* Send either a string or an integer
-*/
-Method(DBGO, 1)
-{
- /* DINI() */
- if (LEqual(ObjectType(Arg0), 1)) {
- if (LGreater(Arg0, 0xffff)) {
- DBGD(Arg0)
- } else {
- if (LGreater(Arg0, 0xff)) {
- DBGW(Arg0)
- } else {
- DBGB(Arg0)
- }
- }
- } else {
- Name(BDBG, Buffer(80) {})
- store(Arg0, BDBG)
- store(0, Local1)
- while (One) {
- store(GETC(BDBG, Local1), Local0)
- if (LEqual(Local0, 0)) {
- return (0)
- }
- OUTC(Local0)
- Increment(Local1)
- }
- }
- return (0)
-}
-
-/* Get a char from a string */
-Method(GETC, 2)
-{
- CreateByteField(Arg0, Arg1, DBGC)
- return (DBGC)
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl
deleted file mode 100644
index fafb0acc2a..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Siemens AG, Inc.
- * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-* Entry:
-* Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-* -none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method. This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver. This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- \_SB.PCI0.SIOS (Arg0)
-} /* End Method(\_PTS) */
-
-/*
-* The following method results in a "not a valid reserved NameSeg"
-* warning so I have commented it out for the duration. It isn't
-* used, so it could be removed.
-*
-*
-* \_GTS OEM Going To Sleep method
-*
-* Entry:
-* Arg0=The value of the sleeping state S1=1, S2=2
-*
-* Exit:
-* -none-
-*
-* Method(\_GTS, 1) {
-* DBGO("\\_GTS\n")
-* DBGO("From S0 to S")
-* DBGO(Arg0)
-* DBGO("\n")
-* }
-*/
-
-/*
-* \_BFS OEM Back From Sleep method
-*
-* Entry:
-* Arg0=The value of the sleeping state S1=1, S2=2
-*
-* Exit:
-* -none-
-*/
-Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-}
-
-/*
-* \_WAK System Wake method
-*
-* Entry:
-* Arg0=The value of the sleeping state S1=1, S2=2
-*
-* Exit:
-* Return package of 2 DWords
-* Dword 1 - Status
-* 0x00000000 wake succeeded
-* 0x00000001 Wake was signaled but failed due to lack of power
-* 0x00000002 Wake was signaled but failed due to thermal condition
-* Dword 2 - Power Supply state
-* if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- Store(1,HPDE)
-
- /* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, Local1)
- Store(Local1, PWST)
-
- /* if(DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
- * } else {
- * Store(Arg0, Index(WKST,1))
- * }
- */
- \_SB.PCI0.SIOW ()
- Return(WKST)
-} /* End Method(\_WAK) */
-
-Scope(\_GPE) { /* Start Scope GPE */
- /* General event 3 */
- Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
- }
-
- /* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
-
- /* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
-
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
-
- /* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
-
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event - Moved to USB.asl */
- /* Method(_L1A) {
- * DBGO("\\_GPE\\_L1A\n")
- * }
- */
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
-
- /* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
-
- /* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
-
- /* SATA SCI event */
- /* SATA Hot Plug Support -> acpi/sata.asl */
-} /* End Scope GPE */
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/globutil.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/globutil.asl
deleted file mode 100644
index bca300d2f0..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/acpi/globutil.asl
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Siemens AG, Inc.
- * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-Scope(\_SB) {
- #include "globutil.asl"
-}
-*/
-
-/* string compare functions */
-Method(MIN, 2)
-{
- if (LLess(Arg0, Arg1)) {
- Return(Arg0)
- } else {
- Return(Arg1)
- }
-}
-
-Method(SLEN, 1)
-{
- Store(Arg0, Local0)
- Return(Sizeof(Local0))
-}
-
-Method(S2BF, 1)
-{
- Add(SLEN(Arg0), One, Local0)
- Name(BUFF, Buffer(Local0) {})
- Store(Arg0, BUFF)
- Return(BUFF)
-}
-
-/* Strong string compare. Checks both length and content */
-Method(SCMP, 2)
-{
- Store(S2BF(Arg0), Local0)
- Store(S2BF(Arg1), Local1)
- Store(Zero, Local4)
- Store(SLEN(Arg0), Local5)
- Store(SLEN(Arg1), Local6)
- Store(MIN(Local5, Local6), Local7)
-
- While(LLess(Local4, Local7)) {
- Store(Derefof(Index(Local0, Local4)), Local2)
- Store(Derefof(Index(Local1, Local4)), Local3)
- if (LGreater(Local2, Local3)) {
- Return(One)
- } else {
- if (LLess(Local2, Local3)) {
- Return(Ones)
- }
- }
- Increment(Local4)
- }
- if (LLess(Local4, Local5)) {
- Return(One)
- } else {
- if (LLess(Local4, Local6)) {
- Return(Ones)
- } else {
- Return(Zero)
- }
- }
-}
-
-/* Weak string compare. Checks to find Arg1 at beginning of Arg0.
-* Fails if length(Arg0) < length(Arg1). Returns 0 on Fail, 1 on
-* Pass.
-*/
-Method(WCMP, 2)
-{
- Store(S2BF(Arg0), Local0)
- Store(S2BF(Arg1), Local1)
- if (LLess(SLEN(Arg0), SLEN(Arg1))) {
- Return(0)
- }
- Store(Zero, Local2)
- Store(SLEN(Arg1), Local3)
-
- While(LLess(Local2, Local3)) {
- if (LNotEqual(Derefof(Index(Local0, Local2)),
- Derefof(Index(Local1, Local2)))) {
- Return(0)
- }
- Increment(Local2)
- }
- Return(One)
-}
-
-/* ARG0 = IRQ Number(0-15)
-* Returns Bit Map
-*/
-Method(I2BM, 1)
-{
- Store(0, Local0)
- if (LNotEqual(ARG0, 0)) {
- Store(1, Local1)
- ShiftLeft(Local1, ARG0, Local0)
- }
- Return(Local0)
-}
-Method (SEQL, 2, Serialized)
-{
- Store (SizeOf (Arg0), Local0)
- Store (SizeOf (Arg1), Local1)
- If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
-
- Name (BUF0, Buffer (Local0) {})
- Store (Arg0, BUF0)
- Name (BUF1, Buffer (Local0) {})
- Store (Arg1, BUF1)
- Store (Zero, Local2)
- While (LLess (Local2, Local0))
- {
- Store (DerefOf (Index (BUF0, Local2)), Local3)
- Store (DerefOf (Index (BUF1, Local2)), Local4)
- If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
-
- Increment (Local2)
- }
-
- Return (One)
-}
-
-/* GetMemoryResources(Node, Link) */
-Method (GMEM, 2, NotSerialized)
-{
- Name (BUF0, ResourceTemplate ()
- {
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
- 0x00000000, // Address Space Granularity
- 0x00000000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000001,,,
- , AddressRangeMemory, TypeStatic)
- })
- CreateDWordField (BUF0, 0x0A, MMIN)
- CreateDWordField (BUF0, 0x0E, MMAX)
- CreateDWordField (BUF0, 0x16, MLEN)
- Store (0x00, Local0)
- Store (0x00, Local4)
- Store (0x00, Local3)
- While (LLess (Local0, 0x10))
- {
- /* Get value of the first register */
- Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
- Increment (Local0)
- Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
- If (LEqual (And (Local1, 0x03), 0x03)) /* Pair enabled? */
- {
- If (LEqual (Arg0, And (Local2, 0x07))) /* Node matches? */
- {
- /* If Link Matches (or we got passed 0xFF) */
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
- {
- /* Extract the Base and Limit values */
- Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
- Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
- Or (MMAX, 0xFFFF, MMAX)
- Subtract (MMAX, MMIN, MLEN)
- Increment (MLEN)
-
- If (Local4) /* I've already done this once */
- {
- Concatenate (RTAG (BUF0), Local3, Local5)
- Store (Local5, Local3)
- }
- Else
- {
- Store (RTAG (BUF0), Local3)
- }
-
- Increment (Local4)
- }
- }
- }
-
- Increment (Local0)
- }
-
- If (LNot (Local4)) /* No resources for this node and link. */
- {
- Store (RTAG (BUF0), Local3)
- }
-
- Return (Local3)
-}
-
-Method (RTAG, 1, NotSerialized)
-{
- Store (Arg0, Local0)
- Store (SizeOf (Local0), Local1)
- Subtract (Local1, 0x02, Local1)
- Multiply (Local1, 0x08, Local1)
- CreateField (Local0, 0x00, Local1, RETB)
- Store (RETB, Local2)
- Return (Local2)
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl
deleted file mode 100644
index 82e54d8e4e..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "ide.asl"
- }
- }
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
- 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
- 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
- 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
- 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
- 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
-})
-
-OperationRegion(IDEC, PCI_Config, 0x40, 0x20) /* ide control registers */
- Field(IDEC, AnyAcc, NoLock, Preserve)
-{
- PPTS, 8, /* 0x40: 0:7 Primary PIO Slave Timing */
- PPTM, 8, /* 0x40: 8:15 Primary PIO Master Timing */
- OFFSET(0x04),
- PMTS, 8, /* 0x44: 0:7 Primary MWDMA Slave Timing */
- PMTM, 8, /* 0x44: 7:15 Primary MWDMA Master Timing */
- OFFSET(0x08),
- PPCR, 8, /* Primary PIO Control */
- OFFSET(0x0A),
- PPMM, 4, /* Primary PIO master Mode */
- PPSM, 4, /* Primary PIO slave Mode */
- OFFSET(0x14),
- PDCR, 2, /* Primary UDMA Control */
- OFFSET(0x16),
- PDMM, 4, /* Primary UltraDMA Mode */
- PDSM, 4, /* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
- Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
- Increment(Local0)
- Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
- Increment(Local1)
- Return(Multiply(30, Add(Local0, Local1)))
-}
-
-Device(PRIM)
-{
- Name (_ADR, 0)
- Method(_GTM, 0)
- {
- NAME(OTBF, Buffer(20) { /* out buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
- CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
- /* Just return if the channel is disabled */
- If(And(PPCR, 0x01)) { /* primary PIO control */
- Return(OTBF)
- }
-
- /* Always tell them independent timing available and IOChannelReady used on both drives */
- Or(BFFG, 0x1A, BFFG)
-
- Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
- Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
-
- If(And(PDCR, 0x01)) { /* It's under UDMA mode */
- Or(BFFG, 0x01, BFFG)
- Store(DerefOf(Index(UDTT, PDMM)), DSD0)
- }
- Else {
- Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
- }
-
- If(And(PDCR, 0x02)) { /* It's under UDMA mode */
- Or(BFFG, 0x04, BFFG)
- Store(DerefOf(Index(UDTT, PDSM)), DSD1)
- }
- Else {
- Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
- }
-
- Return(OTBF) /* out buffer */
- } /* End Method(_GTM) */
-
- Method(_STM, 3, NotSerialized)
- {
- NAME(INBF, Buffer(20) { /* in buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
- CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
- Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
- Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
- Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
- Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
-
- Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
- Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
-
- If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDMM,)
- Or(PDCR, 0x01, PDCR)
- }
- Else {
- If(LNotEqual(DSD0, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTM)
- }
- }
-
- If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDSM,)
- Or(PDCR, 0x02, PDCR)
- }
- Else {
- If(LNotEqual(DSD1, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTS)
- }
- }
- /* Return(INBF) */
- } /*End Method(_STM) */
- Device(MST)
- {
- Name(_ADR, 0)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xA0, CMDA)
- Store(0xA0, CMDB)
- Store(0xA0, CMDC)
-
- Or(PPMM, 0x08, POMD)
-
- If(And(PDCR, 0x01)) {
- Or(PDMM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTM),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(MST) */
-
- Device(SLV)
- {
- Name(_ADR, 1)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xB0, CMDA)
- Store(0xB0, CMDB)
- Store(0xB0, CMDC)
-
- Or(PPSM, 0x08, POMD)
-
- If(And(PDCR, 0x02)) {
- Or(PDSM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTS),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(SLAV) */
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl
deleted file mode 100644
index bda467a2c1..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2010 Siemens AG, Inc.
- * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(PCIF, 0)
-
-Method(_PIC, 1, NotSerialized)
-{
- Store(Arg0, PCIF)
- If (Arg0)
- {
- \_SB.PCI0.LPC0.CIRQ()
- }
-}
-
-External (\_PR.CP00, DeviceObj)
-External (\_PR.CP01, DeviceObj)
-
-Scope(\_SB)
-{
-
- Method(_INI, 0)
- {
- Store (2000, OSYS)
-
- If (CondRefOf(_OSI)) {
-
- If (_OSI("Linux")) {
- Store (1, LINX)
- }
-
- If (_OSI("Windows 2001")) {
- Store (2001, OSYS)
- }
-
- If (_OSI("Windows 2001 SP1")) {
- Store (2001, OSYS)
- }
-
- If (_OSI("Windows 2001 SP2")) {
- Store (2002, OSYS)
- }
-
- If (_OSI("Windows 2006")) {
- Store (2006, OSYS)
- }
- }
- }
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl
deleted file mode 100644
index 926188ce05..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Siemens AG, Inc.
- * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Routing is in System Bus scope */
-Scope(\_SB)
-{
- Name(PR0, Package(){
- /* NB devices */
- /* SB devices */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0012FFFF, 1, \_SB.PCI0.LPC0.INTG, 0 },
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){0x0013FFFF, 0, \_SB.PCI0.LPC0.INTA, 0 },
- Package(){0x0013FFFF, 1, \_SB.PCI0.LPC0.INTB, 0 },
- Package(){0x0013FFFF, 2, \_SB.PCI0.LPC0.INTC, 0 },
- Package(){0x0013FFFF, 3, \_SB.PCI0.LPC0.INTD, 0 },
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
- Package(){0x0014FFFF, 0, \_SB.PCI0.LPC0.INTA, 0 },
- Package(){0x0014FFFF, 1, \_SB.PCI0.LPC0.INTB, 0 },
- Package(){0x0014FFFF, 2, \_SB.PCI0.LPC0.INTC, 0 },
- Package(){0x0014FFFF, 3, \_SB.PCI0.LPC0.INTD, 0 },
- })
-
- Name(APR0, Package(){
- /* NB devices in APIC mode */
- /* Bus 0, Dev 0 - RS690 Host Controller */
- /* SB devices in APIC mode */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0012FFFF, 0, 0, 22 },
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){0x0013FFFF, 0, 0, 16 },
- Package(){0x0013FFFF, 1, 0, 17 },
- Package(){0x0013FFFF, 2, 0, 18 },
- Package(){0x0013FFFF, 3, 0, 19 },
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
- Package(){0x0014FFFF, 0, 0, 16 },
- Package(){0x0014FFFF, 1, 0, 17 },
- Package(){0x0014FFFF, 2, 0, 18 },
- Package(){0x0014FFFF, 3, 0, 19 },
- })
-
- Name(PR1, Package(){
- /* Internal graphics - RS690 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, \_SB.PCI0.LPC0.INTA, 0 },
- Package(){0x0005FFFF, 1, \_SB.PCI0.LPC0.INTB, 0 },
- Package(){0x0005FFFF, 2, \_SB.PCI0.LPC0.INTC, 0 },
- Package(){0x0005FFFF, 3, \_SB.PCI0.LPC0.INTD, 0 },
- })
-
- Name(APR1, Package(){
- /* Internal graphics - RS690 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, 0, 18 },
- Package(){0x0005FFFF, 1, 0, 19 },
- })
-
- Name(PS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTC, 0 },
- Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTD, 0 },
- Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTA, 0 },
- Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTB, 0 },
- })
-
- Name(APS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTA, 0 },
- Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTB, 0 },
- Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTC, 0 },
- Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTD, 0 },
- })
-
- Name(APS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, 0, 16 },
- Package(){0x0000FFFF, 1, 0, 17 },
- Package(){0x0000FFFF, 2, 0, 18 },
- Package(){0x0000FFFF, 3, 0, 19 },
- })
-
- Name(PS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTB, 0 },
- Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTC, 0 },
- Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTD, 0 },
- Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTA, 0 },
- })
-
- Name(APS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTC, 0 },
- Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTD, 0 },
- Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTA, 0 },
- Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTB, 0 },
- })
-
- Name(APS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS7, Package(){
- /* PCIe slot - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTD, 0 },
- Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTA, 0 },
- Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTB, 0 },
- Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTC, 0 },
- })
-
- Name(APS7, Package(){
- /* PCIe slot - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, 0, 19 },
- Package(){0x0000FFFF, 1, 0, 16 },
- Package(){0x0000FFFF, 2, 0, 17 },
- Package(){0x0000FFFF, 3, 0, 18 },
- })
-
- Name(PCIB, Package(){
- /* PCI slots: slot 1 behind Dev14, Fun4. */
- Package(){0x005FFFF, 0, \_SB.PCI0.LPC0.INTF, 0 }, // Phoenix does it
- Package(){0x005FFFF, 1, \_SB.PCI0.LPC0.INTG, 0 }, // Phoenix does it
- Package(){0x004FFFF, 0, \_SB.PCI0.LPC0.INTE, 0 },
- Package(){0x004FFFF, 1, \_SB.PCI0.LPC0.INTF, 0 },
- Package(){0x004FFFF, 2, \_SB.PCI0.LPC0.INTG, 0 },
- Package(){0x004FFFF, 3, \_SB.PCI0.LPC0.INTH, 0 },
- })
-
- Name(AP2P, Package(){
- /* PCI slots: slot 0 behind Dev14, Fun4. */
- Package(){0x0005FFFF, 0, 0, 21 }, // Phoenix does it
- Package(){0x0005FFFF, 1, 0, 22 }, // Phoenix does it
- Package(){0x0004FFFF, 0, 0, 20 },
- Package(){0x0004FFFF, 1, 0, 21 },
- Package(){0x0004FFFF, 2, 0, 22 },
- Package(){0x0004FFFF, 3, 0, 23 },
- })
-
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/sata.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/sata.asl
deleted file mode 100644
index 286d20a700..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(SATA) {
- Name(_ADR, 0x00120000)
- #include "sata.asl"
- }
- }
-}
-*/
-
-Name(STTM, Buffer(20) {
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
- \_GPE._L1F()
-}
-
-Device(PMRY)
-{
- Name(_ADR, 0)
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(PMST) {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P0IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- }/* end of PMST */
-
- Device(PSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P1IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of PSLA */
-} /* end of PMRY */
-
-
-Device(SEDY)
-{
- Name(_ADR, 1) /* IDE Scondary Channel */
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(SMST)
- {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P2IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SMST */
-
- Device(SSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P3IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SSLA */
-} /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
- Method(_L1F,0x0,NotSerialized) {
- if (\_SB.P0PR) {
- if (LGreater(\_SB.P0IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.SATA.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P0PR)
- }
-
- if (\_SB.P1PR) {
- if (LGreater(\_SB.P1IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.SATA.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P1PR)
- }
-
- if (\_SB.P2PR) {
- if (LGreater(\_SB.P2IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.SATA.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P2PR)
- }
-
- if (\_SB.P3PR) {
- if (LGreater(\_SB.P3IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.SATA.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P3PR)
- }
- }
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl
deleted file mode 100644
index 3de9620c71..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-/* Status and notification definitions */
-
-#define STA_MISSING 0x00
-#define STA_PRESENT 0x01
-#define STA_ENABLED 0x03
-#define STA_DISABLED 0x09
-#define STA_INVISIBLE 0x0B
-#define STA_UNAVAILABLE 0x0D
-#define STA_VISIBLE 0x0F
-
-/* SMBus status codes */
-#define SMB_OK 0x00
-#define SMB_UnknownFail 0x07
-#define SMB_DevAddrNAK 0x10
-#define SMB_DeviceError 0x11
-#define SMB_DevCmdDenied 0x12
-#define SMB_UnknownErr 0x13
-#define SMB_DevAccDenied 0x17
-#define SMB_Timeout 0x18
-#define SMB_HstUnsuppProtocol 0x19
-#define SMB_Busy 0x1A
-#define SMB_PktChkError 0x1F
-
-/* Device Object Notification Values */
-#define NOTIFY_BUS_CHECK 0x00
-#define NOTIFY_DEVICE_CHECK 0x01
-#define NOTIFY_DEVICE_WAKE 0x02
-#define NOTIFY_EJECT_REQUEST 0x03
-#define NOTIFY_DEVICE_CHECK_JR 0x04
-#define NOTIFY_FREQUENCY_ERROR 0x05
-#define NOTIFY_BUS_MODE 0x06
-#define NOTIFY_POWER_FAULT 0x07
-#define NOTIFY_CAPABILITIES 0x08
-#define NOTIFY_PLD_CHECK 0x09
-#define NOTIFY_SLIT_UPDATE 0x0B
-
-/* Battery Device Notification Values */
-#define NOTIFY_BAT_STATUSCHG 0x80
-#define NOTIFY_BAT_INFOCHG 0x81
-#define NOTIFY_BAT_MAINTDATA 0x82
-
-/* Power Source Object Notification Values */
-#define NOTIFY_PWR_STATUSCHG 0x80
-
-/* Thermal Zone Object Notification Values */
-#define NOTIFY_TZ_STATUSCHG 0x80
-#define NOTIFY_TZ_TRIPPTCHG 0x81
-#define NOTIFY_TZ_DEVLISTCHG 0x82
-#define NOTIFY_TZ_RELTBLCHG 0x83
-
-/* Power Button Notification Values */
-#define NOTIFY_POWER_BUTTON 0x80
-
-/* Sleep Button Notification Values */
-#define NOTIFY_SLEEP_BUTTON 0x80
-
-/* Lid Notification Values */
-#define NOTIFY_LID_STATUSCHG 0x80
-
-/* Processor Device Notification Values */
-#define NOTIFY_CPU_PPCCHG 0x80
-#define NOTIFY_CPU_CSTATECHG 0x81
-#define NOTIFY_CPU_THROTLCHG 0x82
-
-/* User Presence Device Notification Values */
-#define NOTIFY_USR_PRESNCECHG 0x80
-
-/* Battery Device Notification Values */
-#define NOTIFY_ALS_ILLUMCHG 0x80
-#define NOTIFY_ALS_COLORTMPCHG 0x81
-#define NOTIFY_ALS_RESPCHG 0x82
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl
deleted file mode 100644
index 188c91e57a..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Siemens AG, Inc.
- * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-/* THERMAL */
-Scope(\_TZ) {
- Name (KELV, 2732)
- Name (THOT, 800)
- Name (TCRT, 850)
-
- ThermalZone(TZ00) {
- Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
- /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
- Return(Add(0, 2730))
- }
- Method(_AL0,0) { /* Returns package of cooling device to turn on */
- /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
- Return(Package() {\_TZ.TZ00.FAN0})
- }
- Device (FAN0) {
- Name(_HID, EISAID("PNP0C0B"))
- Name(_PR0, Package() {PFN0})
- }
-
- PowerResource(PFN0,0,0) {
- Method(_STA) {
- Store(0xF,Local0)
- Return(Local0)
- }
- Method(_ON) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
- }
- Method(_OFF) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
- }
- }
-
- // Processors used for active cooling
- Method (_PSL, 0, Serialized)
- {
- If (MPEN) {
- Return (Package() {\_PR.CP00, \_PR.CP01})
- }
- Return (Package() {\_PR.CP00})
- }
-
- Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
- Return (Add (THOT, KELV))
- }
- Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
- Return (Add (TCRT, KELV))
- }
- Method(_TMP,0) { /* return current temp of this zone */
- Store (SMBR (0x07, 0x4C,, 0x00), Local0)
- If (LGreater (Local0, 0x10)) {
- Store (Local0, Local1)
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400, KELV))
- }
-
- Store (SMBR (0x07, 0x4C, 0x01), Local0)
- /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
- /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
- If (LGreater (Local0, 0x10)) {
- If (LGreater (Local0, Local1)) {
- Store (Local0, Local1)
- }
-
- Multiply (Local1, 10, Local1)
- Return (Add (Local1, KELV))
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400 , KELV))
- }
- } /* end of _TMP */
- } /* end of TZ00 */
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl
deleted file mode 100644
index 54613a8b41..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-Method(UCOC, 0) {
- Sleep(20)
- Store(0x13,CMTI)
- Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
- Scope (\_GPE) {
- Method (_L13) {
- UCOC()
- if(LEqual(GPB0,PLC0)) {
- Not(PLC0,PLC0)
- Store(PLC0, \_SB_.PT0D)
- }
- }
- }
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
- Scope (\_GPE) {
- Method (_L14) {
- UCOC()
- if (LEqual(GPB1,PLC1)) {
- Not(PLC1,PLC1)
- Store(PLC1, \_SB_.PT1D)
- }
- }
- }
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
- Scope (\_GPE) {
- Method (_L15) {
- UCOC()
- if (LEqual(GPB2,PLC2)) {
- Not(PLC2,PLC2)
- Store(PLC2, \_SB_.PT2D)
- }
- }
- }
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
- Scope (\_GPE) {
- Method (_L16) {
- UCOC()
- if (LEqual(GPB3,PLC3)) {
- Not(PLC3,PLC3)
- Store(PLC3, \_SB_.PT3D)
- }
- }
- }
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
- Scope (\_GPE) {
- Method (_L19) {
- UCOC()
- if (LEqual(GPB4,PLC4)) {
- Not(PLC4,PLC4)
- Store(PLC4, \_SB_.PT4D)
- }
- }
- }
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
- Scope (\_GPE) {
- Method (_L1A) {
- UCOC()
- if (LEqual(GPB5,PLC5)) {
- Not(PLC5,PLC5)
- Store(PLC5, \_SB_.PT5D)
- }
- }
- }
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
- Scope (\_GPE) {
- /* Method (_L1C) { */
- Method (_L06) {
- UCOC()
- if (LEqual(GPB6,PLC6)) {
- Not(PLC6,PLC6)
- Store(PLC6, \_SB_.PT6D)
- }
- }
- }
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
- Scope (\_GPE) {
- /* Method (_L1D) { */
- Method (_L07) {
- UCOC()
- if (LEqual(GPB7,PLC7)) {
- Not(PLC7,PLC7)
- Store(PLC7, \_SB_.PT7D)
- }
- }
- }
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
- Scope (\_GPE) {
- Method (_L17) {
- if (LEqual(G8IS,PLC8)) {
- Not(PLC8,PLC8)
- Store(PLC8, \_SB_.PT8D)
- }
- }
- }
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
- Scope (\_GPE) {
- Method (_L0E) {
- if (LEqual(G9IS,0)) {
- Store(1,\_SB_.PT9D)
- }
- }
- }
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
deleted file mode 100644
index 0ced54b457..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Siemens AG, Inc.
- * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <compiler.h>
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include <../../../northbridge/amd/amdk8/acpi.h>
-#include <arch/cpu.h>
-#include <cpu/amd/powernow.h>
-#include <southbridge/amd/rs690/rs690.h>
-#include "mainboard.h"
-#include <cbmem.h>
-
-#define GLOBAL_VARS_SIZE 0x100
-
-typedef struct {
- /* Miscellaneous */
- u16 osys;
- u16 linx;
- u32 pcba;
- u8 mpen;
- u8 reserv[247];
-} __packed global_vars_t;
-
-static void acpi_write_gvars(global_vars_t *gvars)
-{
- struct device *dev;
- struct resource *res;
-
- memset((void *)gvars, 0, GLOBAL_VARS_SIZE);
-
- gvars->pcba = EXT_CONF_BASE_ADDRESS;
- dev = dev_find_slot(0, PCI_DEVFN(0,0));
- res = probe_resource(dev, 0x1C);
- if( res )
- gvars->pcba = res->base;
-
- gvars->mpen = 1;
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB600 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
- IO_APIC_ADDR, 0);
-#if !IS_ENABLED(CONFIG_LINT01_CONVERSION)
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
-
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-#else
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high */
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapic_nmis(current, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
- /* 1: LINT1 connect to NMI */
- set_nbcfg_enable_bits(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x68, 1 << 16, 1 << 16); // Local Interrupt Conversion Enable
-#endif
- return current;
-}
-
-void mainboard_inject_dsdt(struct device *device)
-{
- global_vars_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, GLOBAL_VARS_SIZE);
-
- if (gnvs) {
- memset(gnvs, 0, sizeof(*gnvs));
- acpi_write_gvars(gnvs);
-
- /* Add it to SSDT. */
- acpigen_write_scope("\\");
- acpigen_write_name_dword("NVSA", (u32) gnvs);
- acpigen_pop_len();
- }
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/board_info.txt b/src/mainboard/siemens/sitemp_g1p1/board_info.txt
deleted file mode 100644
index 7680e6f854..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: half
diff --git a/src/mainboard/siemens/sitemp_g1p1/cmos.default b/src/mainboard/siemens/sitemp_g1p1/cmos.default
deleted file mode 100644
index 3440a20c10..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/cmos.default
+++ /dev/null
@@ -1,23 +0,0 @@
-boot_option=Fallback
-cmos_defaults_loaded=Yes
-debug_level=Spew
-power_on_after_fail=Enable
-nmi=Enable
-sata_mode=AHCI
-boot_devices=''
-multi_core=Enable
-cpu_fan_control=Disable
-chassis_fan_control=Disable
-cpu_fan_polarity=Active_high
-chassis_fan_polarity=Active_high
-cpu_t_min=45
-cpu_t_max=65
-cpu_dutycycle_min=30%
-cpu_dutycycle_max=90%
-chassis_t_min=40
-chassis_t_max=70
-chassis_dutycycle_min=25%
-chassis_dutycycle_max=90%
-lcd_panel_id=no_panel
-boot_delay=off
-boot_default=0
diff --git a/src/mainboard/siemens/sitemp_g1p1/cmos.layout b/src/mainboard/siemens/sitemp_g1p1/cmos.layout
deleted file mode 100644
index f7571cc309..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/cmos.layout
+++ /dev/null
@@ -1,172 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-## Copyright (C) 2010 Siemens AG, Inc.
-## (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-##
-##
-
-entries
-
-# =======================================================
-# =======================================================
-# ========================================================
-0 384 r 0 reserved_memory
-# ========================================================
-#384 1 r 0 unused
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384 1 e 4 boot_option
-#386 1 r 1 unused
-387 1 e 16 cmos_defaults_loaded
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-#395 1 r 1 unused
-#396 1 r 1 unused
-#397 2 r 8 unused
-399 1 e 2 multi_core
-#400 8 r 18 reserved
-408 4 e 6 debug_level
-412 1 e 1 power_on_after_fail
-#413 1 r 1 unused
-414 1 e 17 sata_mode
-415 1 e 1 nmi
-416 1 e 1 cpu_fan_control
-417 1 e 1 chassis_fan_control
-418 1 e 13 cpu_fan_polarity
-419 1 e 13 chassis_fan_polarity
-420 4 e 14 cpu_t_min
-424 4 e 14 cpu_t_max
-428 4 e 15 cpu_dutycycle_min
-432 4 e 15 cpu_dutycycle_max
-
-436 4 e 14 chassis_t_min
-440 4 e 14 chassis_t_max
-
-444 4 e 15 chassis_dutycycle_min
-
-448 4 e 15 chassis_dutycycle_max
-
-#452 4 r 9 unused
-
-456 4 e 10 boot_delay
-460 4 e 11 lcd_panel_id
-#===========================================================
-464 512 s 0 boot_devices
-976 8 h 0 boot_default
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 4 Warning
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-# boot delay
-10 0 off
-10 1 1s
-10 2 2s
-10 3 3s
-10 4 4s
-10 5 5s
-10 6 6s
-10 7 7s
-10 8 8s
-10 9 9s
-10 10 10s
-# LCD Panel ID
-11 0 no_panel
-11 1 1024x768_65MHz_Dual
-11 2 1920x1200_162MHz
-11 3 1600x1200_162MHz
-11 4 1024x768_65MHz
-11 5 1400x1050_108MHz
-11 6 1680x1050_119MHz
-11 7 2048x1536_164MHz
-11 8 1280x1024_108MHz
-11 9 1366x768_86MHz_chimei_V32B1L01
-# TV Standard
-#12 0 NTSC
-#12 1 PAL
-#12 2 PALM
-#12 3 PAL60
-#12 4 NTSCJ
-#12 5 PALCN
-#12 6 PALN
-#12 9 SCART-RGB
-#12 15 no_tv
-# CPU/Chassis FAN Control: polarity
-13 0 Active_high
-13 1 Active_low
-# Temperature °C
-14 0 30
-14 1 35
-14 2 40
-14 3 45
-14 4 50
-14 5 55
-14 6 60
-14 7 65
-14 8 70
-14 9 75
-14 10 80
-14 11 85
-14 12 90
-14 13 95
-14 14 100
-# Dutycycle %
-15 0 25%
-15 1 30%
-15 2 35%
-15 3 40%
-15 4 45%
-15 5 50%
-15 6 55%
-15 7 60%
-15 8 65%
-15 9 70%
-15 10 75%
-15 11 80%
-15 12 85%
-15 13 90%
-15 14 95%
-15 15 100%
-# cmos_defaults_loaded
-16 0 No
-16 1 Yes
-# sata_mode
-17 0 AHCI
-17 1 IDE
-# reserved
-18 32 2000
-# ==============================
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/siemens/sitemp_g1p1/devicetree.cb b/src/mainboard/siemens/sitemp_g1p1/devicetree.cb
deleted file mode 100644
index e47703f738..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/devicetree.cb
+++ /dev/null
@@ -1,134 +0,0 @@
-#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_S1G1
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x110a 0x4076 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on # southbridge
- chip southbridge/amd/rs690
- device pci 0.0 on # Northbridge configuration space (0x7910)
- end
- device pci 1.0 on # Internal Graphics P2P bridge 0x7912
- device pci 5.0 on # Internal Graphics 0x791F
- end
- device pci 5.2 on #
- end
- end
- device pci 2.0 on # PCIE P2P bridge 0x7913 (external GFX-port0)
- end
- device pci 3.0 off # PCIE P2P bridge 0x791b (external GFX-port1)
- end
- device pci 4.0 on # PCIE P2P bridge port 0 (0x7914)
- end
- device pci 5.0 on # PCIE P2P bridge port 1 (0x7915)
- end
- device pci 6.0 on # PCIE P2P bridge port 2 (0x7916)
- end
- device pci 7.0 on # PCIE P2P bridge port 3 (0x7917)
- end
- device pci 8.0 off # NB/SB Link P2P bridge
- end
- register "gpp_configuration" = "4"
- register "port_enable" = "0xfc"
- register "gfx_dev2_dev3" = "1"
- register "gfx_dual_slot" = "0"
- register "gfx_lane_reversal" = "0"
- register "gfx_tmds" = "1" # needed for DVI output, but this results in a conflict if PLX installed !
- register "gfx_compliance" = "0"
- register "gfx_reconfiguration" = "1"
- register "gfx_link_width" = "0" # 4 (0x8) if PLX installed
- end
- chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
- device pci 12.0 on end # SATA 0x4380
- device pci 13.0 on end # USB 0x4387
- device pci 13.1 on end # USB 0x4388
- device pci 13.2 on end # USB 0x4389
- device pci 13.3 on end # USB 0x438a
- device pci 13.4 on end # USB 0x438b
- device pci 13.5 on end # USB 2 0x4386
- device pci 14.0 on # SM 0x4385
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 0-1-1
- device i2c 53 on end
- end
- end # SM
- device pci 14.1 on end # IDE 0x438c
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC 0x438d
- chip superio/ite/it8712f
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 off end # EC
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.6 on # Mouse
- irq 0x70 = 12
- end
- device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
- end
- device pnp 2e.8 off # MIDI
- io 0x60 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.9 off # GAME
- io 0x60 = 0x220
- end
- device pnp 2e.a off end # CIR
- end #superio/ite/it8712f
- end #LPC
- device pci 14.4 on end # PCI 0x4384
- device pci 14.5 on end # ACI 0x4382
- device pci 14.6 on end # MCI 0x438e
-# register "ide0_enable" = "1"
-# register "sata0_enable" = "1"
- register "hda_viddid" = "0x10ec0882"
- end #southbridge/amd/sb600
- end # device pci 18.0
-
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end #northbridge/amd/amdk8
- end #domain
-end #northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
deleted file mode 100644
index 121aaf9edd..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
+++ /dev/null
@@ -1,1211 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Siemens AG, Inc.
- * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <arch/ioapic.h>
-#include <cpu/x86/lapic_def.h>
-#include <southbridge/amd/sb600/sb600.h>
-
-DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMEN", "SITEMP ", 0x20101005)
-{
- /* Data to be patched by the BIOS during POST */
- /* Memory related values */
- Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
-
- /* USB overcurrent mapping pins. */
- Name(UOM0, 0)
- Name(UOM1, 2)
- Name(UOM2, 0)
- Name(UOM3, 7)
- Name(UOM4, 2)
- Name(UOM5, 2)
- Name(UOM6, 6)
- Name(UOM7, 2)
- Name(UOM8, 6)
- Name(UOM9, 6)
-
- Name(DSEN, 1) // Display Output Switching Enable
- // Power notification
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- SINT, 0x00000008, /* Index 4 */
- Offset(0x09),
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- /* PCI Error control register */
- OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
- Field(PERC, ByteAcc, NoLock, Preserve) {
- SENS, 0x00000001,
- PENS, 0x00000001,
- SENE, 0x00000001,
- PENE, 0x00000001,
- }
-
- /* Client Management index/data registers */
- OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
- Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
- /* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
- }
-
- /* GPM Port register */
- OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
- Field(GPT, ByteAcc, NoLock, Preserve) {
- GPB0,1,
- GPB1,1,
- GPB2,1,
- GPB3,1,
- GPB4,1,
- GPB5,1,
- GPB6,1,
- GPB7,1,
- }
-
- /* Flash ROM program enable register */
- OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
- Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
- FLRE, 0x00000001,
- }
-
- /* PM2 index/data registers */
- OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
- Field(PM2R, ByteAcc, NoLock, Preserve) {
- PM2I, 0x00000008,
- PM2D, 0x00000008,
- }
-
- /* Power Management I/O registers */
- OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
- Field(PIOR, ByteAcc, NoLock, Preserve) {
- PIOI, 0x00000008,
- PIOD, 0x00000008,
- }
- IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
- Offset(0x00), /* MiscControl */
- , 1,
- T1EE, 1,
- T2EE, 1,
- Offset(0x01), /* MiscStatus */
- , 1,
- T1E, 1,
- T2E, 1,
- Offset(0x04), /* SmiWakeUpEventEnable3 */
- , 7,
- SSEN, 1,
- Offset(0x07), /* SmiWakeUpEventStatus3 */
- , 7,
- CSSM, 1,
- Offset(0x10), /* AcpiEnable */
- , 6,
- PWDE, 1,
- Offset(0x1C), /* ProgramIoEnable */
- , 3,
- MKME, 1,
- IO3E, 1,
- IO2E, 1,
- IO1E, 1,
- IO0E, 1,
- Offset(0x1D), /* IOMonitorStatus */
- , 3,
- MKMS, 1,
- IO3S, 1,
- IO2S, 1,
- IO1S, 1,
- IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
- APEB, 16,
- Offset(0x36), /* GEvtLevelConfig */
- , 6,
- ELC6, 1,
- ELC7, 1,
- Offset(0x37), /* GPMLevelConfig0 */
- , 3,
- PLC0, 1,
- PLC1, 1,
- PLC2, 1,
- PLC3, 1,
- PLC8, 1,
- Offset(0x38), /* GPMLevelConfig1 */
- , 1,
- PLC4, 1,
- PLC5, 1,
- , 1,
- PLC6, 1,
- PLC7, 1,
- Offset(0x3B), /* PMEStatus1 */
- GP0S, 1,
- GM4S, 1,
- GM5S, 1,
- APS, 1,
- GM6S, 1,
- GM7S, 1,
- GP2S, 1,
- STSS, 1,
- Offset(0x55), /* SoftPciRst */
- SPRE, 1,
- , 1,
- , 1,
- PNAT, 1,
- PWMK, 1,
- PWNS, 1,
-
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
-
- Offset(0x65), /* UsbPMControl */
- , 4,
- URRE, 1,
- Offset(0x68), /* MiscEnable68 */
- , 3,
- TMTE, 1,
- , 1,
- Offset(0x92), /* GEVENTIN */
- , 7,
- E7IS, 1,
- Offset(0x96), /* GPM98IN */
- G8IS, 1,
- G9IS, 1,
- Offset(0x9A), /* EnhanceControl */
- ,7,
- HPDE, 1,
- Offset(0xA8), /* PIO7654Enable */
- IO4E, 1,
- IO5E, 1,
- IO6E, 1,
- IO7E, 1,
- Offset(0xA9), /* PIO7654Status */
- IO4S, 1,
- IO5S, 1,
- IO6S, 1,
- IO7S, 1,
- }
-
- /* PM1 Event Block
- * First word is PM1_Status, Second word is PM1_Enable
- */
- OperationRegion(P1EB, SystemIO, APEB, 0x04)
- Field(P1EB, ByteAcc, NoLock, Preserve) {
- TMST, 1,
- , 3,
- BMST, 1,
- GBST, 1,
- Offset(0x01),
- PBST, 1,
- , 1,
- RTST, 1,
- , 3,
- PWST, 1,
- SPWS, 1,
- Offset(0x02),
- TMEN, 1,
- , 4,
- GBEN, 1,
- Offset(0x03),
- PBEN, 1,
- , 1,
- RTEN, 1,
- , 3,
- PWDA, 1,
- }
-
- External(\NVSA)
-
- OperationRegion (GVAR, SystemMemory, \NVSA, 0x100)
- Field (GVAR, ByteAcc, NoLock, Preserve)
- {
- Offset (0x00),
- OSYS, 16,
- LINX, 16,
- PCBA, 32,
- MPEN, 8
- }
-
- Name (IOLM,0xe0000000)
-
-#include "acpi/platform.asl"
-
- Scope(\_SB) {
-
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x2000000) /* PCIe reserved space for 31 busses */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
- Offset(0x00090024), /* Byte offset to SATA BAR5 register 24h - Bus 0, Device 18, Function 0 */
- STB5, 32,
- Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
- PT0D, 1,
- PT1D, 1,
- PT2D, 1,
- PT3D, 1,
- PT4D, 1,
- PT5D, 1,
- PT6D, 1,
- PT7D, 1,
- PT8D, 1,
- PT9D, 1,
- Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
- SBIE, 1,
- SBME, 1,
- Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
- SBRI, 8,
- Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
- SBB1, 32,
- Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
- ,14,
- P92E, 1, /* Port92 decode enable */
- }
-
- OperationRegion(BAR5, SystemMemory, STB5, 0x1000)
- Field(BAR5, AnyAcc, NoLock, Preserve)
- {
- /* Port 0 */
- Offset(0x120), /* Port 0 Task file status */
- P0ER, 1,
- , 2,
- P0DQ, 1,
- , 3,
- P0BY, 1,
- Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
- , 4,
- P0IS, 4,
- Offset(0x12C), /* Port 0 Serial ATA control */
- P0DI, 4,
- Offset(0x130), /* Port 0 Serial ATA error */
- , 16,
- P0PR, 1,
-
- /* Port 1 */
- offset(0x1A0), /* Port 1 Task file status */
- P1ER, 1,
- , 2,
- P1DQ, 1,
- , 3,
- P1BY, 1,
- Offset(0x1A8), /* Port 1 Serial ATA status */
- P1DD, 4,
- , 4,
- P1IS, 4,
- Offset(0x1AC), /* Port 1 Serial ATA control */
- P1DI, 4,
- Offset(0x1B0), /* Port 1 Serial ATA error */
- , 16,
- P1PR, 1,
-
- /* Port 2 */
- Offset(0x220), /* Port 2 Task file status */
- P2ER, 1,
- , 2,
- P2DQ, 1,
- , 3,
- P2BY, 1,
- Offset(0x228), /* Port 2 Serial ATA status */
- P2DD, 4,
- , 4,
- P2IS, 4,
- Offset(0x22C), /* Port 2 Serial ATA control */
- P2DI, 4,
- Offset(0x230), /* Port 2 Serial ATA error */
- , 16,
- P2PR, 1,
-
- /* Port 3 */
- Offset(0x2A0), /* Port 3 Task file status */
- P3ER, 1,
- , 2,
- P3DQ, 1,
- , 3,
- P3BY, 1,
- Offset(0x2A8), /* Port 3 Serial ATA status */
- P3DD, 4,
- , 4,
- P3IS, 4,
- Offset(0x2AC), /* Port 3 Serial ATA control */
- P3DI, 4,
- Offset(0x2B0), /* Port 3 Serial ATA error */
- , 16,
- P3PR, 1,
- }
- }
-#include "acpi/event.asl"
-#include "acpi/routing.asl"
-#include "acpi/usb.asl"
-
- /* System Bus */
- Scope(\_SB)
- {
- /* Start \_SB scope */
-
-#include "acpi/globutil.asl"
-
- Device(PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0)
- {
- External (MMIO)
- External (TOM1)
- External (TOM2)
-
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
-
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
-
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Device (MEMR)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (MEM1, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0x00000000, // Address Base
- 0x00000000, // Address Length
- _Y1A)
- Memory32Fixed (ReadWrite,
- 0x00000000, // Address Base
- 0x00000000, // Address Length
- _Y1B)
- })
- Method (_CRS, 0, NotSerialized)
- {
- CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._BAS, MB01)
- CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._LEN, ML01)
- CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._BAS, MB02)
- CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._LEN, ML02)
- If (PCIF)
- {
- Store (IO_APIC_ADDR, MB01)
- Store (LOCAL_APIC_ADDR, MB02)
- Store (0x1000, ML01)
- Store (0x1000, ML02)
- }
-
- Return (MEM1)
- }
- }
-
- Method(_PRT,0) {
- If(PCIF){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- OperationRegion (BAR1, PCI_Config, 0x14, 0x04)
- Field (BAR1, ByteAcc, NoLock, Preserve)
- {
- Z009, 32
- }
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) { Return (APR1) }
-
- Device (VGA)
- {
- Name (_ADR, 0x00050000)
- Method (_DOS, 1)
- {
- /* Windows 2000 and Windows XP call _DOS to enable/disable
- * Display Output Switching during init and while a switch
- * is already active
- */
- Store (And(Arg0, 7), DSEN)
- }
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PCIF){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* Dev3 is also an external GFX bridge */
-
- Device(PBR4) {
- Name(_ADR, 0x00040000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PCIF){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR4 */
-
- Device(PBR5) {
- Name(_ADR, 0x00050000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PCIF){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR5 */
-
- Device(PBR6) {
- Name(_ADR, 0x00060000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PCIF){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR6 */
-
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PCIF){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR7 */
-
- /* PCI slot 1 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {4, 5}) // Phoenix doeas it so
- Method(_PRT, 0) {
- If(PCIF){ Return(AP2P) } /* APIC Mode */
- Return (PCIB) /* PIC Mode */
- }
- }
-
- /* Describe the Southbridge devices */
- Device(SATA) {
- Name(_ADR, 0x00120000)
-#include "acpi/sata.asl"
- } /* end SATA */
-
- Device(UOH1) {
- Name(_ADR, 0x00130000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH1 */
-
- Device(UOH2) {
- Name(_ADR, 0x00130001)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH2 */
-
- Device(UOH3) {
- Name(_ADR, 0x00130002)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH3 */
-
- Device(UOH4) {
- Name(_ADR, 0x00130003)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH4 */
-
- Device(UOH5) {
- Name(_ADR, 0x00130004)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UEH1) {
- Name(_ADR, 0x00130005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(SBUS) {
- Name(_ADR, 0x00140000)
- } /* end SBUS */
-
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "acpi/ide.asl"
- } /* end IDEC */
-
- Device(AZHD) {
- Name(_ADR, 0x00140002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6C),
- MMDT, 16,
- }
-
- Method(_INI) {
- If(LEqual(LINX,1)){ /* If we are running Linux */
- Store(zero, NSEN)
- Store(one, NSDO)
- Store(one, NSDI)
- }
- }
- } /* end AZHD */
-
- Device(LPC0)
- {
- Name (_ADR, 0x00140003)
- Mutex (PSMX, 0x00)
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
-
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- SINT, 0x00000008, /* Index 4 */
- Offset(0x09),
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- Method(CIRQ, 0x00, NotSerialized)
- {
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, SINT)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){10,11}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- Return(IRQB) // Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- Store (IRQB, Local0) //
- CreateWordField(Local0, 0x1, IRQ0)
- ShiftLeft(1, PINA, IRQ0)
- Return(Local0)
- } /* Method(_SB.INTA._CRS) */
- Method(_SRS, 1) {
- CreateWordField(ARG0, 1, IRQ0)
- /* Use lowest available IRQ */
- FindSetRightBit(IRQ0, Local0)
- Decrement (Local0)
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- Return(IRQB) // Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- Store (IRQB, Local0) // {10,11}
- CreateWordField(Local0, 0x1, IRQ0)
- ShiftLeft(1, PINB, IRQ0)
- Return(Local0)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- CreateWordField(ARG0, 1, IRQ0)
- /* Use lowest available IRQ */
- FindSetRightBit(IRQ0, Local0)
- Decrement(Local0)
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- Return(IRQB) // Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- Store (IRQB, Local0) // {10,11}
- CreateWordField(Local0, 0x1, IRQ0)
- ShiftLeft(1, PINC, IRQ0)
- Return(Local0)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- CreateWordField(ARG0, 1, IRQ0)
- /* Use lowest available IRQ */
- FindSetRightBit(IRQ0, Local0)
- Decrement(Local0)
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- Return(IRQB) // Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- Store (IRQB, Local0) // {10,11}
- CreateWordField(Local0, 0x1, IRQ0)
- ShiftLeft(1, PIND, IRQ0)
- Return(Local0)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- CreateWordField(ARG0, 1, IRQ0)
- /* Use lowest available IRQ */
- FindSetRightBit(IRQ0, Local0)
- Decrement(Local0)
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- Return(IRQB) // Return(IRQP)
- }
-
- Method(_CRS ,0) {
- Store (IRQB, Local0) // {10,11}
- CreateWordField(Local0, 0x1, IRQ0)
- ShiftLeft(1, PINE, IRQ0)
- Return(Local0)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- CreateWordField(ARG0, 1, IRQ0)
- /* Use lowest available IRQ */
- FindSetRightBit(IRQ0, Local0)
- Decrement(Local0)
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- Return(IRQB) // Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- Store (IRQB, Local0) // {10,11}
- CreateWordField(Local0, 0x1, IRQ0)
- ShiftLeft(1, PINF, IRQ0)
- Return(Local0)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- CreateWordField(ARG0, 1, IRQ0)
- /* Use lowest available IRQ */
- FindSetRightBit(IRQ0, Local0)
- Decrement(Local0)
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- Return(IRQB) // Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- Store (IRQB, Local0) // {10,11}
- CreateWordField(Local0, 0x1, IRQ0)
- ShiftLeft(1, PING, IRQ0)
- Return(Local0)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- CreateWordField(ARG0, 1, IRQ0)
- /* Use lowest available IRQ */
- FindSetRightBit(IRQ0, Local0)
- Decrement(Local0)
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- Return(IRQB) // Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- Store (IRQB, Local0) // {10,11}
- CreateWordField(Local0, 0x1, IRQ0)
- ShiftLeft(1, PINH, IRQ0)
- Return(Local0)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- CreateWordField(ARG0, 1, IRQ0)
- /* Use lowest available IRQ */
- FindSetRightBit(IRQ0, Local0)
- Decrement(Local0)
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible)*/
- Name(_CRS, ResourceTemplate() {
- IRQ (Edge, ActiveHigh, Exclusive, ) {8}
- IO(Decode16,0x0070, 0x0070, 1, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQ (Edge, ActiveHigh, Exclusive, ) {0}
- IO(Decode16, 0x0040, 0x0040, 1, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 1, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQ (Edge, ActiveHigh, Exclusive, ) {2}
- IO(Decode16,0x0020, 0x0020, 1, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,NotBusMaster,Transfer8_16){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 1, 0x10)
- IRQ (Edge, ActiveHigh, Exclusive, ) {13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPET) { /* HPET */
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* HPET is visible */
- }
- Method(_CRS, 0) {
- Return(CRS)
- }
- }
-
- Device (KBC0)
- {
- Name (_HID, EisaId ("PNP0303"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0060, // Range Minimum
- 0x0060, // Range Maximum
- 0x01, // Alignment
- 0x01, // Length
- )
- IO (Decode16,
- 0x0064, // Range Minimum
- 0x0064, // Range Maximum
- 0x01, // Alignment
- 0x01, // Length
- )
- IRQ (Edge, ActiveHigh, Exclusive, ) {1}
- })
- }
-
- Device (MSE0)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Name (_CRS, ResourceTemplate ()
- {
- IRQ (Edge, ActiveHigh, Exclusive, ) {12}
- })
- }
- } /* end LPC0 */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- Name (_PRW, Package (0x02)
- {
- 0x0C,
- 0x04
- })
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- Name (_PRW, Package (0x02)
- {
- 0x0C,
- 0x04
- })
- } /* end Ac97modem */
-
- /* ITE IT8712F Support */
- OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
- Field (IOID, ByteAcc, NoLock, Preserve)
- {
- SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
- }
-
- IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
- {
- Offset (0x07),
- LDN, 8, /* Logical Device Number */
- Offset (0x20),
- CID1, 8, /* Chip ID Byte 1, 0x87 */
- CID2, 8, /* Chip ID Byte 2, 0x12 */
- Offset (0x30),
- ACTR, 8, /* Function activate */
- Offset (0xF0),
- APC0, 8, /* APC/PME Event Enable Register */
- APC1, 8, /* APC/PME Status Register */
- APC2, 8, /* APC/PME Control Register 1 */
- APC3, 8, /* Environment Controller Special Configuration Register */
- APC4, 8 /* APC/PME Control Register 2 */
- }
-
- /* Enter the IT8712F MB PnP Mode */
- Method (EPNP)
- {
- Store(0x87, SIOI)
- Store(0x01, SIOI)
- Store(0x55, SIOI)
- Store(0x55, SIOI) /* IT8712F magic number */
- }
- /* Exit the IT8712F MB PnP Mode */
- Method (XPNP)
- {
- Store (0x02, SIOI)
- Store (0x02, SIOD)
- }
-
- /*
- * Keyboard PME is routed to SB600 Gevent3. We can wake
- * up the system by pressing the key.
- */
- Method (SIOS, 1)
- {
- /* We only enable KBD PME for S5. */
- If (LLess (Arg0, 0x05))
- {
- EPNP()
- /* DBGO("IT8712F\n") */
-
- Store (0x4, LDN)
- Store (One, ACTR) /* Enable EC */
- /*
- Store (0x4, LDN)
- Store (0x04, APC4)
- */ /* falling edge. which mode? Not sure. */
-
- Store (0x4, LDN)
- Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
- Store (0x4, LDN)
- Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
- XPNP()
- }
- }
- Method (SIOW, 0)
- {
- EPNP()
- Store (0x4, LDN)
- Store (Zero, APC0) /* disable keyboard PME */
- Store (0x4, LDN)
- Store (0xFF, APC1) /* clear keyboard PME status */
- XPNP()
- }
-
-/* ############################################################################################### */
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- DWORDMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0, 0, 0, 0x00, 1, ,, EMM2)
- WORDIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x00, 0x0D00, 0xffff, 0x00, 0xf300)
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
-
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
-
- CreateDWordField(CRES, ^EMM2._MIN, EM2B)
- CreateDWordField(CRES, ^EMM2._MAX, EM2E)
- CreateDWordField(CRES, ^EMM2._LEN, EM2L)
-
- Store(TOM1, EM2B)
- Subtract(IOLM, 1, EM2E)
- Subtract(IOLM, TOM1, EM2L)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
- }
-
- Return(CRES) /* note to change the Name buffer */
- }
-/* ########################################################################################## */
- } /* End Device(PCI0) */
- } /* End \_SB scope */
-
- Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
- } /* End Scope SI */
-
-#include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
-#include "acpi/thermal.asl"
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/fadt.c b/src/mainboard/siemens/sitemp_g1p1/fadt.c
deleted file mode 100644
index 360a427c21..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/fadt.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <../southbridge/amd/sb600/sb600.h>
-
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb ACPI */
-/* pm_base should be got from bar2 of rs690. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
-
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
- /* Prepare the header */
- memset((void *)fadt, 0, sizeof(acpi_fadt_t));
- memcpy(header->signature, "FACP", 4);
- header->length = 244;
- header->revision = 3;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->oem_revision = 0x20101005;
- header->asl_compiler_revision = 3;
-
- fadt->firmware_ctrl = (u32) facs;
- fadt->dsdt = (u32) dsdt;
- /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
- fadt->preferred_pm_profile = 0x03;
- fadt->sci_int = 9;
- /* disable system management mode by setting to 0: */
- fadt->smi_cmd = 0;
- fadt->acpi_enable = 0xf0;
- fadt->acpi_disable = 0xf1;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0xe2;
-
- pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
-
- /* CpuControl is in \_PR.CP00, 6 bytes */
- pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
-
- pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
-
- pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
-
- pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 20-2B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
- pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
-
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
- fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
- fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
- fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
-
- fadt->cst_cnt = 0xe3;
- fadt->p_lvl2_lat = 101;
- fadt->p_lvl3_lat = 1001;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 1;
- fadt->duty_width = 3;
- fadt->day_alrm = 0; /* 0x7d these have to be */
- fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
- fadt->century = 0; /* 0x7f to make rtc alrm work */
- fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
- fadt->flags = 0x0001c1a5;/* 0x25; */
-
- fadt->res2 = 0;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 6;
- fadt->x_firmware_ctl_l = (u32) facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32) dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 4;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 2;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 32;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
deleted file mode 100644
index b1b7270802..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_rs690[8];
-u8 bus_sb600[2];
-u32 apicid_sb600;
-
-/*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
-u32 pci1234x[] = {
- 0x0000ff0,
-};
-
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
- 0x20202020,
-};
-
-u32 sbdn_rs690;
-u32 sbdn_sb600;
-
-
-
-static u32 get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- u32 apicid_base;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* do it only once */
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
- sbdn_rs690 = sysconf.sbdn;
- sbdn_sb600 = 0;
-
- for (i = 0; i < 2; i++) {
- bus_sb600[i] = 0;
- }
- for (i = 0; i < 8; i++) {
- bus_rs690[i] = 0;
- }
-
- bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_sb600[0] = bus_rs690[0];
-
- /* sb600 */
- dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
- if (dev) {
- bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- /* rs690 */
- for (i = 1; i < 8; i++) {
- dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
- if (dev) {
- bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
- /* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_sb600 = apicid_base + 0;
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/int15_func.c b/src/mainboard/siemens/sitemp_g1p1/int15_func.c
deleted file mode 100644
index b01a292411..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/int15_func.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2009 Libra Li <libra.li@technexion.com>
- * Copyright (C) 2010 Siemens AG, Inc.
- * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <console/console.h>
-#include <arch/interrupt.h>
-#include <x86emu/regs.h>
-#include "int15_func.h"
-
-int sbios_INT15_handler(void);
-/*extern*/ unsigned long vgainfo_addr;
-
-static INT15_function_extensions __int15_func;
-
-/* System BIOS int15 function */
-int sbios_INT15_handler(void)
-{
- int res = -1;
-
- printk(BIOS_DEBUG, "System BIOS INT 15h\n");
-
- switch (X86_EAX & 0xffff) {
-#define BOOT_DISPLAY_DEFAULT 0
-#define BOOT_DISPLAY_CRT (1 << 0)
-#define BOOT_DISPLAY_TV (1 << 1)
-#define BOOT_DISPLAY_EFP (1 << 2)
-#define BOOT_DISPLAY_LCD (1 << 3)
-#define BOOT_DISPLAY_CRT2 (1 << 4)
-#define BOOT_DISPLAY_TV2 (1 << 5)
-#define BOOT_DISPLAY_EFP2 (1 << 6)
-#define BOOT_DISPLAY_LCD2 (1 << 7)
- case 0x5f35:
- X86_EAX = 0x5f;
- X86_ECX = BOOT_DISPLAY_DEFAULT;
- res = 0;
- break;
- case 0x5f40:
- X86_EAX = 0x5f;
- X86_ECX = 3; // This is mainboard specific
- printk(BIOS_DEBUG, "DISPLAY=%x\n", X86_ECX);
- res = 0;
- break;
- case 0x4e08:
- switch (X86_EBX & 0xff) {
- case 0x00:
- X86_EAX &= ~(0xff);
- X86_EBX = (X86_EBX & ~(0xff)) | __int15_func.regs.func00_LCD_panel_id;
- printk(BIOS_DEBUG, "DISPLAY = %x\n", X86_EBX & 0xff);
- res = 0;
- break;
- case 0x02:
- break;
- case 0x05:
- X86_EAX &= ~(0xff);
- X86_EBX = (X86_EBX & ~(0xff)) | __int15_func.regs.func05_TV_standard;
- printk(BIOS_DEBUG, "TV = %x\n", X86_EBX & 0xff);
- res = 0;
- break;
- case 0x80:
- X86_EAX &= ~(0xff);
- X86_EBX &= ~(0xff);
- printk(BIOS_DEBUG, "Integrated System Information = %x:%x\n", X86_EDX, X86_EDI);
- vgainfo_addr = (X86_EDX * 16) + X86_EDI;
- res = 0;
- break;
- case 0x89:
- X86_EAX &= ~(0xff);
- X86_EBX &= ~(0xff);
- printk(BIOS_DEBUG, "Get supported display device information\n");
- res = 0;
- break;
- default:
- break;
- }
- break;
- default:
- printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff);
- break;
- }
-
- return res;
-}
-
-/* Initialization VBIOS function extensions */
-void install_INT15_function_extensions(INT15_function_extensions *int15_func)
-{
- printk(BIOS_DEBUG, "Initialize function extensions for Callback function number 04E08h ..\n");
- __int15_func.regs.func00_LCD_panel_id = int15_func->regs.func00_LCD_panel_id;
- __int15_func.regs.func05_TV_standard = int15_func->regs.func05_TV_standard;
- mainboard_interrupt_handlers(0x15, &sbios_INT15_handler);
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/int15_func.h b/src/mainboard/siemens/sitemp_g1p1/int15_func.h
deleted file mode 100644
index 298b9d1690..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/int15_func.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2009 Libra Li <libra.li@technexion.com>
- * Copyright (C) 2010 Siemens AG, Inc.
- * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-typedef struct {
- u8 func00_LCD_panel_id; // Callback Sub-Function 00h - Get LCD Panel ID
- u8 func02_set_expansion;
- u8 func05_TV_standard; // Callback Sub-Function 05h - Select Boot-up TV Standard
- u16 func80_sysinfo_table;
-}INT15_regs;
-
-typedef struct {
- INT15_regs regs;
-}INT15_function_extensions;
-
-extern void install_INT15_function_extensions(INT15_function_extensions *);
diff --git a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c b/src/mainboard/siemens/sitemp_g1p1/irq_tables.c
deleted file mode 100644
index dccbe12243..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-/* Platform IRQs */
-#define PIRQA 10
-#define PIRQB 11
-#define PIRQC 5
-#define PIRQD 15
-
-/* Map */
-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern u8 bus_rs690[8];
-extern u8 bus_sb600[2];
-extern unsigned long sbdn_sb600;
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_sb600[0];
- pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 1,
- 0);
- pirq_info++;
- slot_num++;
-
- /* ide */
- write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 1,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 1,
- 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
deleted file mode 100644
index d4cb5828a7..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c
+++ /dev/null
@@ -1,825 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Siemens AG, Inc.
- * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <delay.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <pc80/mc146818rtc.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/sb600/sb600.h>
-#include <southbridge/amd/rs690/chip.h>
-#include <southbridge/amd/rs690/rs690.h>
-#include <superio/ite/it8712f/it8712f.h>
-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
-#include <x86emu/x86emu.h>
-#endif
-#include "int15_func.h"
-#include "mainboard.h"
-
-// ****LCD panel ID support: *****
-// Callback Sub-Function 00h - Get LCD Panel ID
-#define PANEL_TABLE_ID_NO 0 // no LCD
-#define PANEL_TABLE_ID1 1 // 1024x768_65MHz_Dual
-#define PANEL_TABLE_ID2 2 // 920x1200_162MHz
-#define PANEL_TABLE_ID3 3 // 600x1200_162MHz
-#define PANEL_TABLE_ID4 4 // 1024x768_65MHz
-#define PANEL_TABLE_ID5 5 // 1400x1050_108MHz
-#define PANEL_TABLE_ID6 6 // 1680x1050_119MHz
-#define PANEL_TABLE_ID7 7 // 2048x1536_164MHz
-#define PANEL_TABLE_ID8 8 // 1280x1024_108MHz
-#define PANEL_TABLE_ID9 9 // 1366x768_86MHz_chimei_V32B1L01
-
-// Callback Sub-Function 05h - Select Boot-up TV Standard
-#define TV_MODE_00 0x00 /* NTSC */
-#define TV_MODE_01 0x01 /* PAL */
-#define TV_MODE_02 0x02 /* PALM */
-#define TV_MODE_03 0x03 /* PAL60 */
-#define TV_MODE_04 0x04 /* NTSCJ */
-#define TV_MODE_05 0x05 /* PALCN */
-#define TV_MODE_06 0x06 /* PALN */
-#define TV_MODE_09 0x09 /* SCART-RGB */
-#define TV_MODE_NO 0xff /* No TV Support */
-
-#define PLX_VIDDID 0x861610b5
-
-/* 7475 Common Registers */
-#define REG_DEVREV2 0x12 /* ADT7490 only */
-#define REG_VTT 0x1E /* ADT7490 only */
-#define REG_EXTEND3 0x1F /* ADT7490 only */
-#define REG_VOLTAGE_BASE 0x20
-#define REG_TEMP_BASE 0x25
-#define REG_TACH_BASE 0x28
-#define REG_PWM_BASE 0x30
-#define REG_PWM_MAX_BASE 0x38
-#define REG_DEVID 0x3D
-#define REG_VENDID 0x3E
-#define REG_DEVID2 0x3F
-#define REG_STATUS1 0x41
-#define REG_STATUS2 0x42
-#define REG_VID 0x43 /* ADT7476 only */
-#define REG_VOLTAGE_MIN_BASE 0x44
-#define REG_VOLTAGE_MAX_BASE 0x45
-#define REG_TEMP_MIN_BASE 0x4E
-#define REG_TEMP_MAX_BASE 0x4F
-#define REG_TACH_MIN_BASE 0x54
-#define REG_PWM_CONFIG_BASE 0x5C
-#define REG_TEMP_TRANGE_BASE 0x5F
-#define REG_PWM_MIN_BASE 0x64
-#define REG_TEMP_TMIN_BASE 0x67
-#define REG_TEMP_THERM_BASE 0x6A
-#define REG_REMOTE1_HYSTERSIS 0x6D
-#define REG_REMOTE2_HYSTERSIS 0x6E
-#define REG_TEMP_OFFSET_BASE 0x70
-#define REG_CONFIG2 0x73
-#define REG_EXTEND1 0x76
-#define REG_EXTEND2 0x77
-#define REG_CONFIG1 0x40 // ADT7475
-#define REG_CONFIG3 0x78
-#define REG_CONFIG5 0x7C
-#define REG_CONFIG6 0x10 // ADT7475
-#define REG_CONFIG7 0x11 // ADT7475
-#define REG_CONFIG4 0x7D
-#define REG_STATUS4 0x81 /* ADT7490 only */
-#define REG_VTT_MIN 0x84 /* ADT7490 only */
-#define REG_VTT_MAX 0x86 /* ADT7490 only */
-
-#define VID_VIDSEL 0x80 /* ADT7476 only */
-
-#define CONFIG2_ATTN 0x20
-#define CONFIG3_SMBALERT 0x01
-#define CONFIG3_THERM 0x02
-#define CONFIG4_PINFUNC 0x03
-#define CONFIG4_MAXDUTY 0x08
-#define CONFIG4_ATTN_IN10 0x30
-#define CONFIG4_ATTN_IN43 0xC0
-#define CONFIG5_TWOSCOMP 0x01
-#define CONFIG5_TEMPOFFSET 0x02
-#define CONFIG5_VIDGPIO 0x10 /* ADT7476 only */
-#define REMOTE1 0
-#define LOCAL 1
-#define REMOTE2 2
-
-/* ADT7475 Settings */
-#define ADT7475_VOLTAGE_COUNT 5 /* Not counting Vtt */
-#define ADT7475_TEMP_COUNT 3
-#define ADT7475_TACH_COUNT 4
-#define ADT7475_PWM_COUNT 3
-
-/* Macros to easily index the registers */
-#define TACH_REG(idx) (REG_TACH_BASE + ((idx) * 2))
-#define TACH_MIN_REG(idx) (REG_TACH_MIN_BASE + ((idx) * 2))
-
-#define PWM_REG(idx) (REG_PWM_BASE + (idx))
-#define PWM_MAX_REG(idx) (REG_PWM_MAX_BASE + (idx))
-#define PWM_MIN_REG(idx) (REG_PWM_MIN_BASE + (idx))
-#define PWM_CONFIG_REG(idx) (REG_PWM_CONFIG_BASE + (idx))
-
-#define VOLTAGE_REG(idx) (REG_VOLTAGE_BASE + (idx))
-#define VOLTAGE_MIN_REG(idx) (REG_VOLTAGE_MIN_BASE + ((idx) * 2))
-#define VOLTAGE_MAX_REG(idx) (REG_VOLTAGE_MAX_BASE + ((idx) * 2))
-
-#define TEMP_REG(idx) (REG_TEMP_BASE + (idx))
-#define TEMP_MIN_REG(idx) (REG_TEMP_MIN_BASE + ((idx) * 2))
-#define TEMP_MAX_REG(idx) (REG_TEMP_MAX_BASE + ((idx) * 2))
-#define TEMP_TMIN_REG(idx) (REG_TEMP_TMIN_BASE + (idx))
-#define TEMP_THERM_REG(idx) (REG_TEMP_THERM_BASE + (idx))
-#define TEMP_OFFSET_REG(idx) (REG_TEMP_OFFSET_BASE + (idx))
-#define TEMP_TRANGE_REG(idx) (REG_TEMP_TRANGE_BASE + (idx))
-
-#define SMBUS_IO_BASE 0x1000
-#define ADT7475_ADDRESS 0x2E
-
-#define D_OPEN (1 << 6)
-#define D_CLS (1 << 5)
-#define D_LCK (1 << 4)
-#define G_SMRAME (1 << 3)
-#define A_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) // 0x2: SMM space at 640KB-768KB
-
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
-
-static u32 smbus_io_base = SMBUS_IO_BASE;
-static u32 adt7475_address = ADT7475_ADDRESS;
-
-/* Macro to read the registers */
-#define adt7475_read_byte(reg) \
- do_smbus_read_byte(smbus_io_base, adt7475_address, reg)
-
-#define adt7475_write_byte(reg, val) \
- do_smbus_write_byte(smbus_io_base, adt7475_address, reg, val)
-
-#define TWOS_COMPL 1
-
-struct __table__{
- const char *info;
- u8 val;
-};
-
-struct __table__ dutycycles[] = {
- {"25%", 0x3f},{"30%", 0x4c},{"35%", 0x59},{"40%", 0x66},{"45%", 0x73},
- {"50%", 0x80},{"55%", 0x8d},{"60%", 0x9a},{"65%", 0xa7},{"70%", 0xb4},
- {"75%", 0xc1},{"80%", 0xce},{"85%", 0xdb},{"90%", 0xe8},{"95%", 0xf5},
- {"100%", 0xff}
-};
-#define SIZEOF_DUTYCYCLES sizeof(dutycycles)/sizeof(struct __table__)
-#define DUTYCYCLE(i,d) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].val : dutycycles[d].val // hopefully d is a correct value !!! fix
-#define DUTYCYCLE_INFO(i) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].info : "out_of_range"
-#if TWOS_COMPL == 0
-struct __table__ temperatures[] = {
- {"30C", 0x5e},{"35C", 0x63},{"40C", 0x68},{"45C", 0x6d},{"50C", 0x72},
- {"55C", 0x77},{"60C", 0x7c},{"65C", 0x81},{"70C", 0x86},{"75C", 0x8b},
- {"80C", 0x90}
-};
-#else
-struct __table__ temperatures[] = {
- {"30C", 30},{"35C", 35},{"40C", 40},{"45C", 45},{"50C", 50},
- {"55C", 55},{"60C", 60},{"65C", 65},{"70C", 70},{"75C", 75},
- {"80C", 80}
-};
-#endif
-// FIXME: implicit conversion from 'double' to 'int'
-// int trange[] = {2.0,2.5,3.33,4.0,5.0,6.67,8.0,10.0,13.33,16.0,20.0,26.67,32.0,40.0,53.33,80.0};
-int trange[] = {2,2,3,4,5,6,8,10,13,16,20,26,32,40,53,80};
-
-#define SIZEOF_TEMPERATURES sizeof(temperatures)/sizeof(struct __table__)
-#define TEMPERATURE(i,d) (i < SIZEOF_TEMPERATURES) ? temperatures[i].val : temperatures[d].val // hopefully d is a correct value !!! fix
-#define TEMPERATURE_INFO(i) (i < SIZEOF_TEMPERATURES) ? temperatures[i].info : "out of range"
-
-struct fan_control {
- unsigned int enable : 1;
- u8 polarity;
- u8 t_min;
- u8 t_max;
- u8 pwm_min;
- u8 pwm_max;
- u8 t_range;
-};
-/* ############################################################################################# */
-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
-static int int15_handler(void)
-{
-#define BOOT_DISPLAY_DEFAULT 0
-#define BOOT_DISPLAY_CRT (1 << 0)
-#define BOOT_DISPLAY_TV (1 << 1)
-#define BOOT_DISPLAY_EFP (1 << 2)
-#define BOOT_DISPLAY_LCD (1 << 3)
-#define BOOT_DISPLAY_CRT2 (1 << 4)
-#define BOOT_DISPLAY_TV2 (1 << 5)
-#define BOOT_DISPLAY_EFP2 (1 << 6)
-#define BOOT_DISPLAY_LCD2 (1 << 7)
-
- printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
- __func__, X86_AX, X86_BX, X86_CX, X86_DX);
-
- switch (X86_AX) {
- case 0x4e08: /* Boot Display */
- switch (X86_BX) {
- case 0x80:
- X86_AX &= ~(0xff); // Success
- X86_BX &= ~(0xff);
- printk(BIOS_DEBUG, "Integrated System Information\n");
- break;
- case 0x00:
- X86_AX &= ~(0xff);
- X86_BX = 0x00;
- printk(BIOS_DEBUG, "Panel ID = 0\n");
- break;
- case 0x05:
- X86_AX &= ~(0xff);
- X86_BX = 0xff;
- printk(BIOS_DEBUG, "TV = off\n");
- break;
- default:
- return 0;
- }
- break;
- case 0x5f35: /* Boot Display */
- X86_AX = 0x005f; // Success
- X86_CL = BOOT_DISPLAY_DEFAULT;
- break;
- case 0x5f40: /* Boot Panel Type */
- // M.x86.R_AX = 0x015f; // Supported but failed
- X86_AX = 0x005f; // Success
- X86_CL = 3; // Display ID
- break;
- default:
- /* Interrupt was not handled */
- return 0;
- }
-
- /* Interrupt handled */
- return 1;
-}
-#endif
-/* ############################################################################################# */
-
-static u8 calc_trange(u8 t_min, u8 t_max) {
-
- u8 prev;
- int i;
- int diff = t_max - t_min;
-
- // walk through the trange table
- for(i = 0, prev = 0; i < sizeof(trange)/sizeof(int); i++) {
- if( trange[i] < diff ) {
- prev = i; // save last val
- continue;
- }
- if( diff == trange[i] ) return i;
- if( (diff - trange[prev]) < (trange[i] - diff) ) break; // return with last val index
- return i;
- }
- return prev;
-}
-
-/********************************************************
-* sina uses SB600 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void cable_detect(void)
-{
-
- u8 byte;
- struct device *sm_dev;
- struct device *ide_dev;
-
- /* SMBus Module and ACPI Block (Device 20, Function 0) on SB600 */
- printk(BIOS_DEBUG, "%s.\n", __func__);
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- /* IDE Controller (Device 20, Function 1) on SB600 */
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
-
- byte = pci_read_config8(ide_dev, 9);
- printk(BIOS_INFO, "IDE controller in %s Mode\n", byte & (1 << 0) ? "Native" : "Compatibility");
-
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if( pci_read_config8(sm_dev, 0xAA) & (1 << 5) )
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- printk(BIOS_INFO, "DMA mode %d selected\n", byte & (7 << 0));
- pci_write_config8(ide_dev, 0x56, byte);
-}
-
-/**
- * @brief Detect the ADT7475 device
- *
- */
-
-static const char * adt7475_detect( void ) {
-
- int vendid, devid, devid2;
- const char *name = NULL;
-
- vendid = adt7475_read_byte(REG_VENDID);
- devid2 = adt7475_read_byte(REG_DEVID2);
- if (vendid != 0x41 || (devid2 & 0xf8) != 0x68) /* Analog Devices */
- return name;
-
- devid = adt7475_read_byte(REG_DEVID);
- if (devid == 0x73)
- name = "adt7473";
- else if (devid == 0x75 && adt7475_address == 0x2e)
- name = "adt7475";
- else if (devid == 0x76)
- name = "adt7476";
- else if ((devid2 & 0xfc) == 0x6c)
- name = "adt7490";
-
- return name;
-}
-
-// thermal control defaults
-const struct fan_control cpu_fan_control_defaults = {
- .enable = 0, // disable by default
- .polarity = 0, // high by default
- .t_min = 3, // default = 45°C
- .t_max = 7, // 65°C
- .pwm_min = 1, // default dutycycle = 30%
- .pwm_max = 13, // 90%
-};
-const struct fan_control case_fan_control_defaults = {
- .enable = 0, // disable by default
- .polarity = 0, // high by default
- .t_min = 2, // default = 40°C
- .t_max = 8, // 70°C
- .pwm_min = 0, // default dutycycle = 25%
- .pwm_max = 13, // 90%
-};
-
-static void pm_init( void )
-{
- u16 word;
- u8 byte;
- struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- /* set SB600 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to tristate */
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* set GPM5 to not wake from s5 */
- byte = pm_ioread(0x77);
- byte &= ~(1 << 5);
- pm_iowrite(0x77, byte);
-}
-
- /**
- * @brief Setup thermal config on SINA Mainboard
- *
- */
-
-static void set_thermal_config(void)
-{
- u8 byte, byte2;
- u8 cpu_pwm_conf, case_pwm_conf;
- struct device *sm_dev;
- struct fan_control cpu_fan_control, case_fan_control;
- const char *name = NULL;
-
-
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- smbus_io_base = pci_read_config32(sm_dev, 0x10) & ~(0xf); // get BAR0-Address which holds the SMBUS_IO_BASE
-
- if( (name = adt7475_detect()) == NULL ) {
- printk(BIOS_NOTICE, "Couldn't detect an ADT7473/75/76/90 part at %x:%x\n", smbus_io_base, adt7475_address);
- return;
- }
- printk(BIOS_DEBUG, "Found %s part at %x:%x\n", name, smbus_io_base, adt7475_address);
-
- cpu_fan_control = cpu_fan_control_defaults;
- case_fan_control = case_fan_control_defaults;
-
- if (get_option(&byte, "cpu_fan_control") == CB_CMOS_CHECKSUM_INVALID) {
- printk(BIOS_WARNING, "%s: CMOS checksum invalid, keeping default values\n",__func__);
- } else {
- // get all the options needed
- if( get_option(&byte, "cpu_fan_control") == CB_SUCCESS )
- cpu_fan_control.enable = byte ? 1 : 0;
-
- get_option(&cpu_fan_control.polarity, "cpu_fan_polarity");
- get_option(&cpu_fan_control.t_min, "cpu_t_min");
- get_option(&cpu_fan_control.t_max, "cpu_t_max");
- get_option(&cpu_fan_control.pwm_min, "cpu_dutycycle_min");
- get_option(&cpu_fan_control.pwm_max, "cpu_dutycycle_max");
-
- if( get_option(&byte, "chassis_fan_control") == CB_SUCCESS)
- case_fan_control.enable = byte ? 1 : 0;
- get_option(&case_fan_control.polarity, "chassis_fan_polarity");
- get_option(&case_fan_control.t_min, "chassis_t_min");
- get_option(&case_fan_control.t_max, "chassis_t_max");
- get_option(&case_fan_control.pwm_min, "chassis_dutycycle_min");
- get_option(&case_fan_control.pwm_max, "chassis_dutycycle_max");
-
- }
-
- printk(BIOS_DEBUG, "cpu_fan_control:%s", cpu_fan_control.enable ? "enable" : "disable");
- printk(BIOS_DEBUG, " cpu_fan_polarity:%s", cpu_fan_control.polarity ? "low" : "high");
-
- printk(BIOS_DEBUG, " cpu_t_min:%s", TEMPERATURE_INFO(cpu_fan_control.t_min));
- cpu_fan_control.t_min = TEMPERATURE(cpu_fan_control.t_min, cpu_fan_control_defaults.t_min);
-
- printk(BIOS_DEBUG, " cpu_t_max:%s", TEMPERATURE_INFO(cpu_fan_control.t_max));
- cpu_fan_control.t_max = TEMPERATURE(cpu_fan_control.t_max, cpu_fan_control_defaults.t_max);
-
- printk(BIOS_DEBUG, " cpu_pwm_min:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_min));
- cpu_fan_control.pwm_min = DUTYCYCLE(cpu_fan_control.pwm_min, cpu_fan_control_defaults.pwm_min);
-
- printk(BIOS_DEBUG, " cpu_pwm_max:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_max));
- cpu_fan_control.pwm_max = DUTYCYCLE(cpu_fan_control.pwm_max, cpu_fan_control_defaults.pwm_max);
-
- cpu_fan_control.t_range = calc_trange(cpu_fan_control.t_min, cpu_fan_control.t_max);
- printk(BIOS_DEBUG, " cpu_t_range:0x%02x\n", cpu_fan_control.t_range);
- cpu_fan_control.t_range <<= 4;
- cpu_fan_control.t_range |= (4 << 0); // 35.3Hz
-
- printk(BIOS_DEBUG, "chassis_fan_control:%s", case_fan_control.enable ? "enable" : "disable");
- printk(BIOS_DEBUG, " chassis_fan_polarity:%s", case_fan_control.polarity ? "low" : "high");
-
- printk(BIOS_DEBUG, " chassis_t_min:%s", TEMPERATURE_INFO(case_fan_control.t_min));
- case_fan_control.t_min = TEMPERATURE(case_fan_control.t_min, case_fan_control_defaults.t_min);
-
- printk(BIOS_DEBUG, " chassis_t_max:%s", TEMPERATURE_INFO(case_fan_control.t_max));
- case_fan_control.t_max = TEMPERATURE(case_fan_control.t_max, case_fan_control_defaults.t_max);
-
- printk(BIOS_DEBUG, " chassis_pwm_min:%s", DUTYCYCLE_INFO(case_fan_control.pwm_min));
- case_fan_control.pwm_min = DUTYCYCLE(case_fan_control.pwm_min, case_fan_control_defaults.pwm_min);
-
- printk(BIOS_DEBUG, " chassis_pwm_max:%s", DUTYCYCLE_INFO(case_fan_control.pwm_max));
- case_fan_control.pwm_max = DUTYCYCLE(case_fan_control.pwm_max, case_fan_control_defaults.pwm_max);
-
- case_fan_control.t_range = calc_trange(case_fan_control.t_min, case_fan_control.t_max);
- printk(BIOS_DEBUG, " case_t_range:0x%02x\n", case_fan_control.t_range);
- case_fan_control.t_range <<= 4;
- case_fan_control.t_range |= (4 << 0); // 35.3Hz
-
- cpu_pwm_conf = (((cpu_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
- case_pwm_conf = (((case_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
- cpu_pwm_conf |= cpu_fan_control.enable ? (0 << 5) : (7 << 5); // manual control
- case_pwm_conf |= case_fan_control.enable ? (1 << 5) : (7 << 5); // local temp
-
- /* set adt7475 */
-
- adt7475_write_byte(REG_CONFIG1, 0x04); // clear register, bit 2 is read only
-
- /* Config Register 6: */
- adt7475_write_byte(REG_CONFIG6, 0x00);
- /* Config Register 7 */
- adt7475_write_byte(REG_CONFIG7, 0x00);
-
- /* Config Register 5: */
- /* set Offset 64 format, enable THERM on Remote 1& Local */
- adt7475_write_byte(REG_CONFIG5, TWOS_COMPL ? 0x61 : 0x60);
- /* No offset for remote 1 */
- adt7475_write_byte(TEMP_OFFSET_REG(0), 0x00);
- /* No offset for local */
- adt7475_write_byte(TEMP_OFFSET_REG(1), 0x00);
- /* No offset for remote 2 */
- adt7475_write_byte(TEMP_OFFSET_REG(2), 0x00);
-
- /* remote 1 low temp limit */
- adt7475_write_byte(TEMP_MIN_REG(0), 0x00);
- /* remote 1 High temp limit (90C) */
- adt7475_write_byte(TEMP_MAX_REG(0), 0x9a);
-
- /* local Low Temp Limit */
- adt7475_write_byte(TEMP_MIN_REG(1), 0x00);
- /* local High Limit (90C) */
- adt7475_write_byte(TEMP_MAX_REG(1), 0x9a);
-
- /* remote 1 therm temp limit (95C) */
- adt7475_write_byte(TEMP_THERM_REG(0), 0x9f);
- /* local therm temp limit (95C) */
- adt7475_write_byte(TEMP_THERM_REG(1), 0x9f);
-
- /* PWM 1 configuration register CPU fan controlled by CPU Thermal Diode */
- adt7475_write_byte(PWM_CONFIG_REG(0), cpu_pwm_conf);
- /* PWM 3 configuration register Case fan controlled by ADTxxxx temp */
- adt7475_write_byte(PWM_CONFIG_REG(2), case_pwm_conf);
-
- if( cpu_fan_control.enable ) {
- /* PWM 1 minimum duty cycle (37%) */
- adt7475_write_byte(PWM_MIN_REG(0), cpu_fan_control.pwm_min);
- /* PWM 1 Maximum duty cycle (100%) */
- adt7475_write_byte(PWM_MAX_REG(0), cpu_fan_control.pwm_max);
- /* Remote 1 temperature Tmin (32C) */
- adt7475_write_byte(TEMP_TMIN_REG(0), cpu_fan_control.t_min);
- /* remote 1 Trange (53C ramp range) */
- adt7475_write_byte(TEMP_TRANGE_REG(0), cpu_fan_control.t_range);
- } else {
- adt7475_write_byte(PWM_REG(0), cpu_fan_control.pwm_max);
- }
-
- if( case_fan_control.enable ) {
- /* PWM 2 minimum duty cycle (37%) */
- adt7475_write_byte(PWM_MIN_REG(2), case_fan_control.pwm_min);
- /* PWM 2 Maximum Duty Cycle (100%) */
- adt7475_write_byte(PWM_MAX_REG(2), case_fan_control.pwm_max);
- /* local temperature Tmin (32C) */
- adt7475_write_byte(TEMP_TMIN_REG(1), case_fan_control.t_min);
- /* local Trange (53C ramp range) */
- adt7475_write_byte(TEMP_TRANGE_REG(1), case_fan_control.t_range); // Local TRange
- adt7475_write_byte(TEMP_TRANGE_REG(2), case_fan_control.t_range); // PWM2 Freq
- } else {
- adt7475_write_byte(PWM_REG(2), case_fan_control.pwm_max);
- }
-
- /* Config Register 3 - enable smbalert & therm */
- adt7475_write_byte(0x78, 0x03);
- /* Config Register 4 - enable therm output */
- adt7475_write_byte(0x7d, 0x09);
- /* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 3 fault, SmbAlert Fan for Therm Timer event */
- adt7475_write_byte(0x75, 0x2e);
-
- /* Config Register 1 Set Start bit */
- adt7475_write_byte(0x40, 0x05);
-
- /* Read status register to clear any old errors */
- byte2 = adt7475_read_byte(0x42);
- byte = adt7475_read_byte(0x41);
-
- printk(BIOS_DEBUG, "Init 'Thermal Monitor' end , status 0x42 = 0x%02x, status 0x41 = 0x%02x\n",
- byte2, byte);
-
-}
-
-static void patch_mmio_nonposted( void )
-{
- unsigned reg, index;
- resource_t rbase, rend;
- u32 base, limit;
- struct resource *resource;
- struct device *dev;
- struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1));
-
- printk(BIOS_DEBUG,"%s ...\n", __func__);
-
- dev = dev_find_slot(1, PCI_DEVFN(5,0));
- // the uma frame buffer
- index = 0x10;
- resource = probe_resource(dev, index);
- if( resource ) {
- // fixup resource nonposted in k8 mmio
- /* Get the base address */
- rbase = (resource->base >> 8) & ~(0xff);
- /* Get the limit (rounded up) */
- rend = (resource_end(resource) >> 8) & ~(0xff);
-
- printk(BIOS_DEBUG,"%s %x base = %0llx limit = %0llx\n", dev_path(dev), index, rbase, rend);
-
- for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
- base = pci_read_config32(k8_f1,reg);
- limit = pci_read_config32(k8_f1,reg+4);
- printk(BIOS_DEBUG," %02x[%08x] %02x[%08x]", reg, base, reg+4, limit);
- if( ((base & ~(0xff)) == rbase) && ((limit & ~(0xff)) == rend) ) {
- limit |= (1 << 7);
- printk(BIOS_DEBUG, "\nPatching %s %x <- %08x", dev_path(k8_f1), reg, limit);
- pci_write_config32(k8_f1, reg+4, limit);
- break;
- }
- }
- printk(BIOS_DEBUG, "\n");
- }
-}
-
-struct {
- unsigned int bus;
- unsigned int devfn;
-} slot[] = {
- {0, PCI_DEVFN(0,0)},
- {0, PCI_DEVFN(18,0)},
- {0, PCI_DEVFN(19,0)},{0, PCI_DEVFN(19,1)},{0, PCI_DEVFN(19,2)},{0, PCI_DEVFN(19,3)},{0, PCI_DEVFN(19,4)},{0, PCI_DEVFN(19,5)},
- {0, PCI_DEVFN(20,0)},{0, PCI_DEVFN(20,1)},{0, PCI_DEVFN(20,2)},{0, PCI_DEVFN(20,3)},{0, PCI_DEVFN(20,5)},{0, PCI_DEVFN(20,6)},
- {0, PCI_DEVFN(5,0)},{0, PCI_DEVFN(5,2)},
- {255,0},
-};
-
-
-unsigned int plx_present = 0;
-
-static void update_subsystemid( struct device *dev )
-{
- int i;
-
- dev->subsystem_vendor = 0x110a;
- if( plx_present ){
- dev->subsystem_device = 0x4076; // U1P1 = 0x4076, U1P0 = 0x4077
- } else {
- dev->subsystem_device = 0x4077; // U1P0 = 0x4077
- }
- printk(BIOS_INFO, "%s [%x/%x]\n", dev_name(dev), dev->subsystem_vendor, dev->subsystem_device );
- for( i = 0; slot[i].bus < 255; i++) {
- struct device *d;
- d = dev_find_slot(slot[i].bus,slot[i].devfn);
- if( d ) {
- printk(BIOS_DEBUG,"%s subsystem <- %x/%x\n", dev_path(d), dev->subsystem_vendor, dev->subsystem_device);
- d->subsystem_device = dev->subsystem_device;
- }
- }
-}
-
-static void detect_hw_variant( struct device *dev )
-{
-
- struct device *nb_dev = NULL, *dev2 = NULL;
- struct southbridge_amd_rs690_config *cfg;
- u32 lc_state, id = 0;
-
- printk(BIOS_INFO, "Scan for PLX device ...\n");
- nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
- if (!nb_dev) {
- die("CAN NOT FIND RS690 DEVICE, HALT!\n");
- /* NOT REACHED */
- }
-
- dev2 = dev_find_slot(0, PCI_DEVFN(2, 0));
- if (!dev2) {
- die("CAN NOT FIND GFX DEVICE 2, HALT!\n");
- /* NOT REACHED */
- }
- PcieReleasePortTraining(nb_dev, dev2, 2); // we assume PLX is connected to port 2
-
- mdelay(40);
- lc_state = nbpcie_p_read_index(dev2, 0xa5); /* lc_state */
- printk(BIOS_DEBUG, "lc current state=%x\n", lc_state);
- /* LC_CURRENT_STATE = bit0-5 */
- switch( lc_state & 0x3f ){
- case 0x00:
- case 0x01:
- case 0x02:
- case 0x03:
- case 0x04:
- printk(BIOS_NOTICE, "No device present, skipping PLX scan ..\n");
- break;
- case 0x07:
- case 0x10:
- {
- struct device dummy;
- u32 pci_primary_bus, buses;
- u16 secondary, subordinate;
-
- printk(BIOS_DEBUG, "Scan for PLX bridge behind %s[%x]\n", dev_path(dev2), pci_read_config32(dev2, PCI_VENDOR_ID));
- // save the existing primary/secondary/subordinate bus number configuration.
- secondary = dev2->bus->secondary;
- subordinate = dev2->bus->subordinate;
- buses = pci_primary_bus = pci_read_config32(dev2, PCI_PRIMARY_BUS);
-
- // Configure the bus numbers for this bridge
- // bus number 1 is for internal gfx device, so we start with busnumber 2
-
- buses &= 0xff000000;
- buses |= ((2 << 8) | (0xff << 16));
- // setup the buses in device 2
- pci_write_config32(dev2,PCI_PRIMARY_BUS, buses);
-
- // fake a device descriptor for a device behind device 2
- dummy.bus = dev2->bus;
- dummy.bus->secondary = (buses >> 8) & 0xff;
- dummy.bus->subordinate = (buses >> 16) & 0xff;
- dummy.path.type = DEVICE_PATH_PCI;
- dummy.path.pci.devfn = PCI_DEVFN(0,0); // PLX: device number 0, function 0
-
- id = pci_read_config32(&dummy, PCI_VENDOR_ID);
- /* Have we found something?
- * Some broken boards return 0 if a slot is empty, but
- * the expected answer is 0xffffffff
- */
- if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) {
- printk(BIOS_DEBUG, "%s, bad id 0x%x\n", dev_path(&dummy), id);
- } else {
- printk(BIOS_DEBUG, "found device [%x]\n", id);
- }
- // restore changes made for device 2
- dev2->bus->secondary = secondary;
- dev2->bus->subordinate = subordinate;
- pci_write_config32(dev2, PCI_PRIMARY_BUS, pci_primary_bus);
- }
- break;
- default:
- break;
- }
-
- plx_present = 0;
- if( id == PLX_VIDDID ){
- printk(BIOS_INFO, "found PLX device\n");
- plx_present = 1;
- cfg = (struct southbridge_amd_rs690_config *)dev2->chip_info;
- if( cfg->gfx_tmds ) {
- printk(BIOS_INFO, "Disable 'gfx_tmds' support\n");
- cfg->gfx_tmds = 0;
- cfg->gfx_link_width = 4;
- }
- return;
- }
-}
-
-void smm_lock(void)
-{
- /* LOCK the SMM memory window and enable normal SMM.
- * After running this function, only a full reset can
- * make the SMM registers writable again.
- */
- printk(BIOS_DEBUG, "Locking SMM.\n");
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x69,
- D_LCK | G_SMRAME | A_BASE_SEG);
-}
-
- /**
- * @brief Init
- *
- * @param dev - the root device
- */
-
-static void mainboard_init(struct device *dev)
-{
-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)
- INT15_function_extensions int15_func;
-#endif
-
- printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n",
- dev_name(dev), dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
-
-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)
- if (get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") != CB_SUCCESS)
- int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO;
- int15_func.regs.func05_TV_standard = TV_MODE_NO;
- install_INT15_function_extensions(&int15_func);
-#endif
- set_thermal_config();
- pm_init();
- cable_detect();
- patch_mmio_nonposted();
- smm_lock();
-}
-
-/*************************************************
-* enable the dedicated function in sina board.
-* This function called early than rs690_enable.
-*************************************************/
-static void mainboard_enable(struct device *dev)
-{
-
- printk(BIOS_INFO, "%s %s[%x/%x] %s\n",
- dev_name(dev), dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
- /* Install custom int15 handler for VGA OPROM */
- mainboard_interrupt_handlers(0x15, &int15_handler);
-#endif
-
- detect_hw_variant(dev);
- update_subsystemid(dev);
-
- dev->ops->init = mainboard_init; // rest of mainboard init later
- dev->ops->acpi_inject_dsdt_generator = mainboard_inject_dsdt;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.h b/src/mainboard/siemens/sitemp_g1p1/mainboard.h
deleted file mode 100644
index 33d0a5e68e..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/mainboard.h
+++ /dev/null
@@ -1 +0,0 @@
-void mainboard_inject_dsdt(device_t device);
diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
deleted file mode 100644
index 3515d304fb..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern u8 bus_rs690[8];
-extern u8 bus_sb600[2];
-
-extern u32 apicid_sb600;
-
-extern u32 sbdn_rs690;
-extern u32 sbdn_sb600;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int isa_bus;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
- mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc);
-
- get_bus_conf();
- printk(BIOS_DEBUG, "%s: apic_id=0x%x\n", __func__, apicid_sb600);
-
- mptable_write_buses(mc, NULL, &isa_bus);
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
-
- dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0));
- if (dev) {
- struct resource *res;
- res = find_resource(dev, 0x74);
- smp_write_ioapic(mc, apicid_sb600, 0x20,
- res2mmio(res, 0, 0));
- }
- }
- mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0);
-
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
-
- /* usb */
- PCI_INT(0x0, 0x13, 0x0, 0x10);
- PCI_INT(0x0, 0x13, 0x1, 0x11);
- PCI_INT(0x0, 0x13, 0x2, 0x12);
- PCI_INT(0x0, 0x13, 0x3, 0x13);
-
- /* sata */
- PCI_INT(0x0, 0x12, 0x1, 0x16);
-
- /* SMBus/ACPI */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, 0x11);
- /* HDA */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, 0x13);
-
- /* GFX ? */
- PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
- PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
-
- /* PCIe slots */
- PCI_INT(0x2, 0x00, 0x00, 0x10);
- PCI_INT(0x2, 0x00, 0x01, 0x11);
- PCI_INT(0x2, 0x00, 0x02, 0x12);
- PCI_INT(0x2, 0x00, 0x03, 0x13);
-
- /* PCIe slots */
- PCI_INT(0x3, 0x00, 0x00, 0x11);
- PCI_INT(0x3, 0x00, 0x01, 0x12);
- PCI_INT(0x3, 0x00, 0x02, 0x13);
- PCI_INT(0x3, 0x00, 0x03, 0x10);
-
- /* PCIe slots */
- PCI_INT(0x4, 0x00, 0x00, 0x12);
- PCI_INT(0x4, 0x00, 0x01, 0x13);
- PCI_INT(0x4, 0x00, 0x02, 0x10);
- PCI_INT(0x4, 0x00, 0x03, 0x11);
-
- /* PCIe slots */
- PCI_INT(0x5, 0x00, 0x00, 0x13);
- PCI_INT(0x5, 0x00, 0x01, 0x10);
- PCI_INT(0x5, 0x00, 0x02, 0x11);
- PCI_INT(0x5, 0x00, 0x03, 0x12);
-
- /* onboard NIC ? */
- PCI_INT(bus_sb600[1], 0x7, 0x0, 0x13);
- PCI_INT(bus_sb600[1], 0x7, 0x1, 0x10);
- PCI_INT(bus_sb600[1], 0x7, 0x2, 0x11);
- PCI_INT(bus_sb600[1], 0x7, 0x3, 0x12);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, isa_bus);
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/resourcemap.c b/src/mainboard/siemens/sitemp_g1p1/resourcemap.c
deleted file mode 100644
index 84e107b8b3..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/resourcemap.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_sitemp_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c
deleted file mode 100644
index 5f910ea4b2..0000000000
--- a/src/mainboard/siemens/sitemp_g1p1/romstage.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Siemens AG, Inc.
- * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <spd.h>
-
-#include <cpu/amd/model_fxx_rev.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-
-#include <cpu/x86/lapic.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#include "southbridge/amd/rs690/early_setup.c"
-#include "southbridge/amd/sb600/early_setup.c"
-#include <northbridge/amd/amdk8/f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, CONFIG_UART_FOR_CONSOLE == 1 ? IT8712F_SP2 : IT8712F_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
-/*called in raminit_f.c */
-int spd_read_byte(u32 device, u32 address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-#define __WARNING__(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg)
-#define __DEBUG__(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg)
-#define __INFO__(fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
- int needs_reset = 0;
- u32 bsp_apicid = 0;
- msr_t msr;
- struct cpuid_result cpuid1;
- struct sys_info *sysinfo = &sysinfo_car;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
-
- /* sb600_lpc_port80(); */
- sb600_pci_port80();
- }
-
- if (bist == 0) {
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
-
- enable_rs690_dev8(); // enable CFG access to Dev8, which is the SB P2P Bridge
- sb600_lpc_init();
-#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0)
- check_cmos(); // rebooting in case of corrupted cmos !!!!!
-#endif
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- ite_kill_watchdog(GPIO_DEV);
-
- console_init();
-#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1)
- check_cmos(); // rebooting in case of corrupted cmos !!!!!
-#endif
- post_code(0x03);
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
- __DEBUG__("bsp_apicid=0x%x\n", bsp_apicid);
-
- setup_sitemp_resource_map();
-
- setup_coherent_ht_domain();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched */
- wait_all_core0_started();
- start_other_cores();
-#endif
- wait_all_aps_started(bsp_apicid);
-
- ht_setup_chains_x(sysinfo);
-
- /* run _early_setup before soft-reset. */
- rs690_early_setup();
- sb600_early_setup();
-
- post_code(0x04);
-
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
- /* Read FIDVID_STATUS */
- msr = rdmsr(0xc0010042);
- __DEBUG__("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
-
- /* show final fid and vid */
- msr = rdmsr(0xc0010042);
- __DEBUG__("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
- } else {
- __DEBUG__("Changing FIDVID not supported\n");
- }
-
- post_code(0x05);
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- rs690_htinit();
- __DEBUG__("needs_reset=0x%x\n", needs_reset);
-
- post_code(0x06);
-
- if (needs_reset) {
- __INFO__("ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now; */
- __DEBUG__("sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
- sysinfo->nodes, sysinfo->ctrl, spd_addr);
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- post_code(0x07);
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
- post_code(0x08);
-
- rs690_before_pci_init(); // does nothing
- sb600_before_pci_init();
-}
diff --git a/src/mainboard/sunw/Kconfig b/src/mainboard/sunw/Kconfig
deleted file mode 100644
index ea76e23c7b..0000000000
--- a/src/mainboard/sunw/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_SUNW
-
-choice
- prompt "Mainboard model"
-
-source "src/mainboard/sunw/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/sunw/*/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "Sun"
-
-endif # VENDOR_SUNW
diff --git a/src/mainboard/sunw/Kconfig.name b/src/mainboard/sunw/Kconfig.name
deleted file mode 100644
index c3783a3cc0..0000000000
--- a/src/mainboard/sunw/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_SUNW
- bool "Sun Microsystems"
diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig
deleted file mode 100644
index a29cf16ea5..0000000000
--- a/src/mainboard/sunw/ultra40/Kconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-if BOARD_SUNW_ULTRA40
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_940
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_CK804
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_SMSC_LPC47B397
- select SUPERIO_SMSC_LPC47M10X
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_1024
- select CK804_USE_NIC
- select CK804_USE_ACI
- select QRANK_DIMM_SUPPORT
- select K8_ALLOCATE_IO_RANGE
-
-config MAINBOARD_DIR
- string
- default sunw/ultra40
-
-config DCACHE_RAM_BASE
- hex
- default 0xcf000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x01000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config CK804_NUM
- int
- default 2
-
-config MAINBOARD_PART_NUMBER
- string
- default "Ultra 40"
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_SUNW_ULTRA40
diff --git a/src/mainboard/sunw/ultra40/Kconfig.name b/src/mainboard/sunw/ultra40/Kconfig.name
deleted file mode 100644
index 7a4f562f30..0000000000
--- a/src/mainboard/sunw/ultra40/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_SUNW_ULTRA40
- bool "Ultra 40"
diff --git a/src/mainboard/sunw/ultra40/board_info.txt b/src/mainboard/sunw/ultra40/board_info.txt
deleted file mode 100644
index 76b41dceee..0000000000
--- a/src/mainboard/sunw/ultra40/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: desktop
-Board URL: http://docs.oracle.com/cd/E19127-01/ultra40.ws/820-0123-13/intro.html
diff --git a/src/mainboard/sunw/ultra40/cmos.layout b/src/mainboard/sunw/ultra40/cmos.layout
deleted file mode 100644
index c4c90f697f..0000000000
--- a/src/mainboard/sunw/ultra40/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/sunw/ultra40/devicetree.cb b/src/mainboard/sunw/ultra40/devicetree.cb
deleted file mode 100644
index 9f9bb67556..0000000000
--- a/src/mainboard/sunw/ultra40/devicetree.cb
+++ /dev/null
@@ -1,151 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_940 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x108e 0x0040 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on end
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/ck804 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/smsc/lpc47m10x # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.3 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.5 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.7 off # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic # DIMM 1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic # DIMM 1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic # DIMM 1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic # DIMM 1-1-1
- device i2c 57 on end
- end
- end
- device pci 1.1 on # SM 1
- # PCI device SMBus address will
- # depend on addon PCI device, do
- # we need to scan_smbus_bus?
- # chip drivers/generic/generic # PCIXA slot 1
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 2
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # PCI slot 1
- # device i2c 53 on end
- # end
- # chip drivers/generic/generic # Master CK804 PCI-E
- # device i2c 54 on end
- # end
- # chip drivers/generic/generic # Slave CK804 PCI-E
- # device i2c 55 on end
- # end
- chip drivers/generic/generic # MAC EEPROM
- device i2c 51 on end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # ACI
- device pci 4.1 off end # MCI
- device pci 6.0 on end # IDE
- device pci 7.0 on end # SATA 1
- device pci 8.0 on end # SATA 0
- device pci 9.0 on end # PCI
- device pci a.0 on end # NIC
- device pci b.0 off end # PCI E 3
- device pci c.0 off end # PCI E 2
- device pci d.0 off end # PCI E 1
- device pci e.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.0 on end # Link 2
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 19.0 on end # Link 0
- device pci 19.0 on # Link 1 == LDT 1
- chip southbridge/nvidia/ck804 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on end # LPC
- device pci 1.1 off end # SM
- device pci 2.0 off end # USB 1.1
- device pci 2.1 off end # USB 2
- device pci 4.0 off end # ACI
- device pci 4.1 off end # MCI
- device pci 6.0 off end # IDE
- device pci 7.0 off end # SATA 1
- device pci 8.0 off end # SATA 0
- device pci 9.0 off end # PCI
- device pci a.0 on end # NIC
- device pci b.0 off end # PCI E 3
- device pci c.0 off end # PCI E 2
- device pci d.0 off end # PCI E 1
- device pci e.0 on end # PCI E 0
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 19.0 on end
- device pci 19.1 on end
- device pci 19.2 on end
- device pci 19.3 on end
- end
- end
-end
diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c
deleted file mode 100644
index e7096f31bf..0000000000
--- a/src/mainboard/sunw/ultra40/get_bus_conf.c
+++ /dev/null
@@ -1,276 +0,0 @@
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-#include <stdlib.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_ck804_0; //1
-unsigned char bus_ck804_1; //2
-unsigned char bus_ck804_2; //3
-unsigned char bus_ck804_3; //4
-unsigned char bus_ck804_4; //5
-unsigned char bus_ck804_5; //6
-unsigned char bus_8131_0; //7
-unsigned char bus_8131_1; //8
-unsigned char bus_8131_2; //9
-unsigned char bus_ck804b_0; //a
-unsigned char bus_ck804b_1; //b
-unsigned char bus_ck804b_2; //c
-unsigned char bus_ck804b_3; //d
-unsigned char bus_ck804b_4; //e
-unsigned char bus_ck804b_5; //f
-unsigned apicid_ck804;
-unsigned apicid_8131_1;
-unsigned apicid_8131_2;
-unsigned apicid_ck804b;
-
-unsigned sblk;
-unsigned pci1234[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
- 0x0000ff0,
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-unsigned hc_possible_num;
-unsigned sbdn;
-unsigned hcdn[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
- 0x20202020,
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-unsigned sbdn3;
-unsigned sbdnb;
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
-
- struct device *dev;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- hc_possible_num = ARRAY_SIZE(pci1234);
-
- get_sblk_pci1234();
-
- sbdn = (hcdn[0] & 0xff); // first byte of first chain
-
- sbdn3 = (hcdn[1] & 0xff);
-
- sbdnb = (hcdn[2] & 0xff); // first byte of second chain
-
-// bus_ck804_0 = node_link_to_bus(0, sblk);
- bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
-
- /* CK804 */
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09, 0));
- if (dev) {
- bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if 0
- bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_2++;
-#else
- bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_5++;
-#endif
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x09);
-
- bus_ck804_1 = 2;
-#if 0
- bus_ck804_2 = 3;
-#else
- bus_ck804_5 = 3;
-#endif
-
- }
-#if 0
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b, 0));
- if (dev) {
- bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_3++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x0b);
-
- bus_ck804_3 = bus_ck804_2 + 1;
- }
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c, 0));
- if (dev) {
- bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_4++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x0c);
-
- bus_ck804_4 = bus_ck804_3 + 1;
- }
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d, 0));
- if (dev) {
- bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_5++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x0d);
-
- bus_ck804_5 = bus_ck804_4 + 1;
- }
-#endif
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0e, 0));
- if (dev) {
- bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x0e);
- }
-
- bus_8131_0 = (pci1234[1] >> 16) & 0xff;
- /* 8131-1 */
- dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0));
- if (dev) {
- bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_8131_2++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:01.0, using defaults\n",
- bus_8131_0);
-
- bus_8131_1 = bus_8131_0 + 1;
- bus_8131_2 = bus_8131_0 + 2;
- }
- /* 8131-2 */
- dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0));
- if (dev) {
- bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:02.0, using defaults\n",
- bus_8131_0);
-
- bus_8131_2 = bus_8131_1 + 1;
- }
-
- /* CK804b */
-
- if (pci1234[2] & 0xf) { //if the second CPU is installed
- bus_ck804b_0 = (pci1234[2] >> 16) & 0xff;
-#if 0
- dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09, 0));
- if (dev) {
- bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804b_2 =
- pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804b_2++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804b_0, sbdnb + 0x09);
-
- bus_ck804b_1 = bus_ck804b_0 + 1;
- bus_ck804b_2 = bus_ck804b_0 + 2;
- }
-
- dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0b, 0));
- if (dev) {
- bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804b_3 =
- pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804b_3++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804b_0, sbdnb + 0x0b);
-
- bus_ck804b_2 = bus_ck804b_0 + 1;
- bus_ck804b_3 = bus_ck804b_0 + 2;
- }
-
- dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0c, 0));
- if (dev) {
- bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804b_4 =
- pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804b_4++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804b_0, sbdnb + 0x0c);
-
- bus_ck804b_4 = bus_ck804b_3 + 1;
- }
- dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0d, 0));
- if (dev) {
- bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804b_5 =
- pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804b_5++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804b_0, sbdnb + 0x0d);
-
- bus_ck804b_5 = bus_ck804b_4 + 1;
- }
-#endif
-
- dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e, 0));
- if (dev) {
- bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804b_0, sbdnb + 0x0e);
-#if 1
- bus_ck804b_5 = bus_ck804b_4 + 1;
-#endif
-
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(4);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_ck804 = apicid_base + 0;
- apicid_8131_1 = apicid_base + 1;
- apicid_8131_2 = apicid_base + 2;
- apicid_ck804b = apicid_base + 3;
-
-}
diff --git a/src/mainboard/sunw/ultra40/irq_tables.c b/src/mainboard/sunw/ultra40/irq_tables.c
deleted file mode 100644
index f895291b4c..0000000000
--- a/src/mainboard/sunw/ultra40/irq_tables.c
+++ /dev/null
@@ -1,212 +0,0 @@
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern unsigned char bus_ck804_0; //1
-extern unsigned char bus_ck804_1; //2
-extern unsigned char bus_ck804_2; //3
-extern unsigned char bus_ck804_3; //4
-extern unsigned char bus_ck804_4; //5
-extern unsigned char bus_ck804_5; //6
-extern unsigned char bus_8131_0; //7
-extern unsigned char bus_8131_1; //8
-extern unsigned char bus_8131_2; //9
-extern unsigned char bus_ck804b_0; //a
-extern unsigned char bus_ck804b_1; //b
-extern unsigned char bus_ck804b_2; //c
-extern unsigned char bus_ck804b_3; //d
-extern unsigned char bus_ck804b_4; //e
-extern unsigned char bus_ck804b_5; //f
-
-extern unsigned pci1234[];
-
-extern unsigned sbdn;
-extern unsigned hcdn[];
-extern unsigned sbdn3;
-extern unsigned sbdnb;
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
-
- uint8_t sum = 0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_ck804_0;
- pirq->rtr_devfn = ((sbdn + 9) << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x005c;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 9) << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-//pcix bridge
- write_pirq_info(pirq_info, bus_8131_0, (sbdn3 << 3) | 0, 0x1, 0xdef8,
- 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- if (pci1234[2] & 0xf) {
- //second pci beidge
- write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb + 9) << 3) | 0,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4,
- 0xdef8, 0x0, 0);
- pirq_info++;
- slot_num++;
- }
-#if 0
-//smbus
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 1) << 3) | 0, 0x2,
- 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-//usb
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 2) << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-//audio
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 4) << 3) | 0, 0x1,
- 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-//sata
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 7) << 3) | 0, 0x1,
- 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-//sata
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 8) << 3) | 0, 0x1,
- 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-//nic
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 0xa) << 3) | 0, 0x1,
- 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-//Slot1 PCIE x16
- write_pirq_info(pirq_info, bus_ck804_5, (0 << 3) | 0, 0x3, 0xdef8, 0x4,
- 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
- pirq_info++;
- slot_num++;
-
-//firewire
- write_pirq_info(pirq_info, bus_ck804_1, (0x5 << 3) | 0, 0x3, 0xdef8, 0,
- 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-//Slot2 pci
- write_pirq_info(pirq_info, bus_ck804_1, (0x4 << 3) | 0, 0x1, 0xdef8,
- 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
- pirq_info++;
- slot_num++;
-//nic
- write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb + 0xa) << 3) | 0, 0x1,
- 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-//Slot3 PCIE x16
- write_pirq_info(pirq_info, bus_ck804b_5, (0 << 3) | 0, 0x3, 0xdef8, 0x4,
- 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
- pirq_info++;
- slot_num++;
-
-//Slot4 PCIX
- write_pirq_info(pirq_info, bus_8131_2, (4 << 3) | 0, 0x1, 0xdef8, 0x2,
- 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
- pirq_info++;
- slot_num++;
-
-//Slot5 PCIX
- write_pirq_info(pirq_info, bus_8131_2, (9 << 3) | 0, 0x2, 0xdef8, 0x3,
- 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
- pirq_info++;
- slot_num++;
-
-//onboard scsi
- write_pirq_info(pirq_info, bus_8131_2, (6 << 3) | 0, 0x2, 0xdef8, 0x3,
- 0xdef8, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-//Slot6 PCIX
- write_pirq_info(pirq_info, bus_8131_1, (4 << 3) | 0, 0x1, 0xdef8, 0x2,
- 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
- pirq_info++;
- slot_num++;
-#endif
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
deleted file mode 100644
index b66b91d012..0000000000
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ /dev/null
@@ -1,201 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_ck804_0; //1
-extern unsigned char bus_ck804_1; //2
-extern unsigned char bus_ck804_2; //3
-extern unsigned char bus_ck804_3; //4
-extern unsigned char bus_ck804_4; //5
-extern unsigned char bus_ck804_5; //6
-extern unsigned char bus_8131_0; //7
-extern unsigned char bus_8131_1; //8
-extern unsigned char bus_8131_2; //9
-extern unsigned char bus_ck804b_0;//a
-extern unsigned char bus_ck804b_1;//b
-extern unsigned char bus_ck804b_2;//c
-extern unsigned char bus_ck804b_3;//d
-extern unsigned char bus_ck804b_4;//e
-extern unsigned char bus_ck804b_5;//f
-extern unsigned apicid_ck804;
-extern unsigned apicid_8131_1;
-extern unsigned apicid_8131_2;
-extern unsigned apicid_ck804b;
-
-extern unsigned pci1234[];
-
-extern unsigned sbdn;
-extern unsigned hcdn[];
-extern unsigned sbdn3;
-extern unsigned sbdnb;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int i, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11,
- res2mmio(res, 0, 0));
- }
-
- /* Initialize interrupt mapping*/
-
- dword = 0x0120d218;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x12008a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0x00080d7d;
- pci_write_config32(dev, 0x84, dword);
-
- }
-
- dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11,
- res2mmio(res, 0, 0));
- }
- }
- dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11,
- res2mmio(res, 0, 0));
- }
- }
-
- if(pci1234[2] & 0xf) {
- dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_ck804b, 0x11,
- res2mmio(res, 0, 0));
- }
-
- dword = 0x0000d218;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x00000000;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0x00000d00;
- pci_write_config32(dev, 0x84, dword);
-
- }
- }
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
-
-// Onboard ck804 smbus
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
-// 10
-
-// Onboard ck804 USB 1.1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
-
-// Onboard ck804 USB 2
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
-
-// Onboard ck804 Audio
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
-
-// Onboard ck804 SATA 0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
-
-// Onboard ck804 SATA 1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
-
-// Onboard ck804 NIC
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
-
-//Slot 1 PCIE x16
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00 << 2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
- }
-
-//Onboard Firewire
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05 << 2)|0, apicid_ck804, 0x13); // 19
-
-//Slot 2 PCI 32
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04 << 2)|i, apicid_ck804, 0x10 + (0+i)%4);
- }
-
- if(pci1234[2] & 0xf) {
-//Onboard ck804b NIC
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21 = 53
-
-//Slot 3 PCIE x16
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00 << 2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
- }
- }
-
-//Channel B of 8131
-
-//Slot 4 PCI-X 100/66
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4 << 2)|i, apicid_8131_2, (0+i)%4);
- }
-
-//Slot 5 PCIX 100/66
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9 << 2)|i, apicid_8131_2, (1+i)%4); // 29
- }
-
-//OnBoard LSI SCSI
- for(i = 0; i < 2; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6 << 2)|i, apicid_8131_2, (2+i)%4); //30
- }
-
-//Channel A of 8131
-
-//Slot 6 PCIX 133/100/66
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4 << 2)|i, apicid_8131_1, (0+i)%4); //24
- }
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/sunw/ultra40/resourcemap.c b/src/mainboard/sunw/ultra40/resourcemap.c
deleted file mode 100644
index 964be503bb..0000000000
--- a/src/mainboard/sunw/ultra40/resourcemap.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * needs a different resource map
- *
- */
-
-static void setup_ultra40_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
- PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000, 0x7f000103,
- PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000, 0xff800113,
- PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xec), 0x0000, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
deleted file mode 100644
index 9325a19b34..0000000000
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ /dev/null
@@ -1,150 +0,0 @@
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include <southbridge/nvidia/ck804/early_smbus.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-
-#include <superio/smsc/lpc47b397/lpc47b397.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "superio/smsc/lpc47b397/early_gpio.c"
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-#define SUPERIO_GPIO_IO_BASE 0x400
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-
-#ifdef ENABLE_ONBOARD_SCSI
-static void sio_gpio_setup(void)
-{
- unsigned value;
-
- /*Enable onboard scsi*/
- lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1 << 7)|(0 << 2)|(0 << 1)|(0 << 0)); // GP21, offset 0x2c, DISABLE_SCSI_L
- value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
- lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1 << 1)));
-}
-#endif
-
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <southbridge/nvidia/ck804/early_setup_ss.h>
-
-//set GPIO to input mode
-#define CK804_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
-
-#include "southbridge/nvidia/ck804/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- unsigned value;
- uint32_t dword;
- uint8_t byte;
-
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
-
- byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1 << 29)|(1 << 0);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
- lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
-
- value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
- value &= 0xbf;
- lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
-
- int needs_reset;
- unsigned bsp_apicid = 0, nodes;
- struct mem_controller ctrl[8];
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx);
-
- lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- setup_ultra40_resource_map();
-
- needs_reset = setup_coherent_ht_domain();
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- needs_reset |= ht_setup_chains_x();
- needs_reset |= ck804_early_setup_x();
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- nodes = get_nodes();
- //It's the time to set ctrl now;
- fill_mem_ctrl(nodes, ctrl, spd_addr);
-
- enable_smbus();
-
- sdram_initialize(nodes, ctrl);
-}
diff --git a/src/mainboard/sunw/ultra40m2/Kconfig b/src/mainboard/sunw/ultra40m2/Kconfig
deleted file mode 100644
index 2913ae8c30..0000000000
--- a/src/mainboard/sunw/ultra40m2/Kconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-if BOARD_SUNW_ULTRA40M2
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_F
- select DIMM_DDR2
- select DIMM_REGISTERED
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_MCP55
- select HT_CHAIN_DISTRIBUTE
- select MCP55_USE_NIC
- select MCP55_USE_AZA
- select SUPERIO_SMSC_DME1737
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_1024
- select QRANK_DIMM_SUPPORT
- select K8_ALLOCATE_IO_RANGE
-
-config MAINBOARD_DIR
- string
- default sunw/ultra40m2
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MEM_TRAIN_SEQ
- int
- default 1
-
-config MCP55_NUM
- int
- default 2
-
-config MAINBOARD_PART_NUMBER
- string
- default "Ultra 40 M2"
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-config MCP55_PCI_E_X_0
- int
- default 1
-
-config MCP55_PCI_E_X_1
- int
- default 1
-
-endif # BOARD_SUNW_ULTRA40M2
diff --git a/src/mainboard/sunw/ultra40m2/Kconfig.name b/src/mainboard/sunw/ultra40m2/Kconfig.name
deleted file mode 100644
index f6bc5517c6..0000000000
--- a/src/mainboard/sunw/ultra40m2/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_SUNW_ULTRA40M2
- bool "Ultra 40 M2"
diff --git a/src/mainboard/sunw/ultra40m2/board_info.txt b/src/mainboard/sunw/ultra40m2/board_info.txt
deleted file mode 100644
index b68555c038..0000000000
--- a/src/mainboard/sunw/ultra40m2/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Board URL: http://docs.oracle.com/cd/E19127-01/ultra40.ws/820-0123-13/intro.html
-Board name: Ultra 40 M2
-Category: desktop
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
diff --git a/src/mainboard/sunw/ultra40m2/cmos.layout b/src/mainboard/sunw/ultra40m2/cmos.layout
deleted file mode 100644
index d774c2f662..0000000000
--- a/src/mainboard/sunw/ultra40m2/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-408 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 200Mhz
-8 1 166Mhz
-8 2 133Mhz
-8 3 100Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/sunw/ultra40m2/devicetree.cb b/src/mainboard/sunw/ultra40m2/devicetree.cb
deleted file mode 100644
index 998245950c..0000000000
--- a/src/mainboard/sunw/ultra40m2/devicetree.cb
+++ /dev/null
@@ -1,147 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_F # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x108e 0x6676 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on end # Link 0 == LDT 0
- device pci 18.0 on # Link 1 == LDT 1
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/smsc/dme1737 # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.3 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 2
- end
- device pnp 2e.4 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.5 off # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.7 on # PS/2 (connectors not populated)
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.a on # Runtime Registers
- io 0x60 = 0x600
- end
- end
- # There's an Infineon SLB9635TT12 TPM on this LPC bus.
- # There's also an Akom AK2001 7-segment port 0x80 decoder on
- # this LPC bus.
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic # DIMM 1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic # DIMM 1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic # DIMM 1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic # DIMM 1-1-1
- device i2c 57 on end
- end
- end
- device pci 1.1 on # SM 1
- #chip drivers/generic/generic # PCA9556 GPIO on HDD backplanes (address conflict!)
- # device i2c 18 on end
- #end
- chip drivers/generic/generic # EMC6D103 HWM (for CPUs)
- device i2c 2d on end
- end
- chip drivers/generic/generic # DME1737 HWM
- device i2c 2e on end
- end
- #chip drivers/generic/generic # HDD 4-7 backplane FRU 24C64 EEPROM
- # device i2c 51 on end
- #end
- #chip drivers/generic/generic # front panel module FRU 24C64 EEPROM
- # device i2c 52 on end
- #end
- #chip drivers/generic/generic # HDD 0-3 backplane FRU 24C64 EEPROM
- # device i2c 53 on end
- #end
- # there are more SMbus devices on this bus
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 off end # SATA 2
- device pci 6.0 on end # PCI
- device pci 6.1 on end # AZA
- device pci 8.0 off end # NIC
- device pci 9.0 off end # NIC
- device pci a.0 on end # PCI E 5
- device pci b.0 off end # PCI E 4
- device pci c.0 off end # PCI E 3
- device pci d.0 on end # PCI E 2
- device pci e.0 off end # PCI E 1
- device pci f.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- end
- end
- device pci 18.0 on # Link 2 == LDT 2
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on end # LPC
- device pci 1.1 on end # SM 0
- device pci 2.0 off end # USB 1.1
- device pci 2.1 off end # USB 2
- device pci 4.0 off end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 off end # SATA 2
- device pci 6.0 off end # PCI
- device pci 6.1 off end # AZA
- device pci 8.0 on end # NIC
- device pci 9.0 on end # NIC
- device pci a.0 on end # PCI E 5
- device pci b.0 off end # PCI E 4
- device pci c.0 off end # PCI E 3
- device pci d.0 on end # PCI E 2
- device pci e.0 off end # PCI E 1
- device pci f.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/sunw/ultra40m2/get_bus_conf.c b/src/mainboard/sunw/ultra40m2/get_bus_conf.c
deleted file mode 100644
index 2a10eeb7a8..0000000000
--- a/src/mainboard/sunw/ultra40m2/get_bus_conf.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include <stdlib.h>
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-unsigned pci1234x[] =
-{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
- 0x0000ff0,
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-unsigned hcdnx[] =
-{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
- 0x20202020,
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-
-
-
-static unsigned get_bus_conf_done = 0;
-
-static unsigned get_hcid(unsigned i)
-{
- unsigned id = 0;
-
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-
- unsigned devn = sysconf.hcdn[i] & 0xff;
-
- struct device *dev;
-
- dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
-
- switch (dev->device) {
- case 0x0369: //IO55
- id = 4;
- break;
- }
-
- // we may need more way to find out hcid: subsystem id? GPIO read ?
-
- // we need use id for 1. bus num, 2. mptable, 3. ACPI table
-
- return id;
-}
-
-void get_bus_conf(void)
-{
- unsigned apicid_base;
- struct mb_sysconf_t *m;
-
- int i;
-
- if (get_bus_conf_done)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.mb = &mb_sysconf;
-
- m = sysconf.mb;
- memset(m, 0, sizeof(struct mb_sysconf_t));
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
-
- m->sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain
-
- m->bus_mcp55 = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* MCP55b */
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x0f))
- continue;
- // check hcid type here
- sysconf.hcid[i] = get_hcid(i);
- if (!sysconf.hcid[i])
- continue; //unknown co processor
-
- m->bus_mcp55b = (sysconf.pci1234[1]>>16) & 0xff;
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(2);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- m->apicid_mcp55 = apicid_base+0;
- m->apicid_mcp55b = apicid_base+1;
-}
diff --git a/src/mainboard/sunw/ultra40m2/hda_verb.c b/src/mainboard/sunw/ultra40m2/hda_verb.c
deleted file mode 100644
index 137196c6e2..0000000000
--- a/src/mainboard/sunw/ultra40m2/hda_verb.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Tyan Computer
- * Copyright (C) 2006-2007 AMD
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
- /* coreboot specific header */
- 0x10ec0885, // Codec Vendor / Device ID: Realtek ALC889A
- 0x00000000, // Subsystem ID
- 0x0000000d, // Number of jacks
-
- /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x108ee601 */
- AZALIA_SUBVENDOR(0x0, 0x108ee601),
-
- /* NID 0x14, FRONT-OUT-L/R */
- AZALIA_PIN_CFG(0x0, 0x14, 0x01014010),
-
- /* NID 0x15, SURR-OUT-L/R */
- AZALIA_PIN_CFG(0x0, 0x15, 0x01011012),
-
- /* NID 0x16, CEN/LFE-OUT */
- AZALIA_PIN_CFG(0x0, 0x16, 0x01016011),
-
- /* NID 0x17, SIDE-SURR-L/R */
- AZALIA_PIN_CFG(0x0, 0x17, 0x01012014),
-
- /* NID 0x18, MIC1-L/R, VREFO */
- AZALIA_PIN_CFG(0x0, 0x18, 0x01a19840),
-
- /* NID 0x19, MIC2-L/R, VREFO */
- AZALIA_PIN_CFG(0x0, 0x19, 0x02a19850),
-
- /* NID 0x1a, LINE1-L/R, VREFO */
- AZALIA_PIN_CFG(0x0, 0x1a, 0x01813041),
-
- /* NID 0x1b, LINE2-L/R, VREFO */
- AZALIA_PIN_CFG(0x0, 0x1b, 0x02214020),
-
- /* NID 0x1c, CD-L/R / GND */
- AZALIA_PIN_CFG(0x0, 0x1c, 0x9933014f),
-
- /* NID 0x1d, PCBEEP */
- AZALIA_PIN_CFG(0x0, 0x1d, 0x99830142),
-
- /* NID 0x1e, S/PDIF-OUT */
- AZALIA_PIN_CFG(0x0, 0x1e, 0x014b4130),
-
- /* NID 0x1f, S/PDIF-IN */
- AZALIA_PIN_CFG(0x0, 0x1f, 0x01cb9160),
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/sunw/ultra40m2/irq_tables.c b/src/mainboard/sunw/ultra40m2/irq_tables.c
deleted file mode 100644
index 061d276b78..0000000000
--- a/src/mainboard/sunw/ultra40m2/irq_tables.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
- struct mb_sysconf_t *m;
- unsigned sbdn;
-
- uint8_t sum = 0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = m->bus_mcp55;
- pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x0370;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, m->bus_mcp55, ((sbdn + 6) << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
- unsigned devn = sysconf.hcdn[i] & 0xff;
-
- write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8,
- 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
- }
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/sunw/ultra40m2/mainboard.c b/src/mainboard/sunw/ultra40m2/mainboard.c
deleted file mode 100644
index 750ae6c6ba..0000000000
--- a/src/mainboard/sunw/ultra40m2/mainboard.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pnp_def.h>
-#include <device/smbus.h>
-#include <stdlib.h>
-#include <superio/smsc/dme1737/dme1737.h>
-
-static void emc6d103_init(void)
-{
- size_t i;
- int reg;
-
- static const struct { uint8_t idx; uint8_t msk; uint8_t set; } script[] = {
- { 0x7f, 0x7f, 0x80 }, // INIT
- { 0x4f, 0x00, 0x64 }, // Diode 1 High 100°C
- { 0x53, 0x00, 0x64 }, // Diode 2 High 100°C (Sun firmware didn't set this)
- { 0x54, 0x00, 0x30 }, // Tach1 Minimum LSB
- { 0x55, 0x00, 0x2a }, // Tach1 Minimum MSB
- { 0x56, 0x00, 0x30 }, // Tach2 Minimum LSB
- { 0x57, 0x00, 0x2a }, // Tach2 Minimum MSB
- { 0x5c, 0x00, 0x02 }, // PWM 1 Config
- { 0x5d, 0x00, 0x42 }, // PWM 2 Config
- { 0x5f, 0x00, 0x8a }, // Zone 1 range, Fan 1 freq
- { 0x60, 0x00, 0xca }, // Zone 2 range, Fan 2 freq
- { 0x61, 0x00, 0x8a }, // Zone 3 range, Fan 3 freq
- { 0x62, 0x00, 0x67 }, // Min/Off, PWM 1 ramp rate
- { 0x63, 0x00, 0x70 }, // PWM 2, PWM 3 ramp rate
- { 0x64, 0x00, 0x59 }, // PWM1 Minimum Duty Cycle
- { 0x65, 0x00, 0x59 }, // PWM2 Minimum Duty Cycle
- { 0x67, 0x00, 0x47 }, // Zone 1 Low Temp Limit
- { 0x69, 0x00, 0x47 }, // Zone 3 Low Temp Limit
- { 0x80, 0x00, 0x07 }, // Interrupt Enable 2
- { 0x40, 0xfe, 0x01 }, // START
- };
-
- struct device * const dev = dev_find_slot_on_smbus(2, 0x2d);
- if (dev == NULL) {
- printk(BIOS_WARNING, "EMC6D103 not found\n");
- return;
- }
-
- printk(BIOS_SPEW, "%s EMC6D103 id: %x %x\n", __func__, smbus_read_byte(dev, 0x3e), smbus_read_byte(dev, 0x3f));
-
- for (i = 0; i < ARRAY_SIZE(script); i++) {
- reg = smbus_read_byte(dev, script[i].idx);
- if (reg < 0)
- goto fail;
- reg &= script[i].msk;
- reg |= script[i].set;
- reg = smbus_write_byte(dev, script[i].idx, reg & 0xff);
- if (reg < 0)
- goto fail;
- }
-
- return;
-
-fail:
- printk(BIOS_WARNING, "failed to initialize EMC6D103\n");
-}
-
-/* set up DME1737 runtime registers for FAN/PWM 5/6 */
-static void dme1737_runtime_init(void)
-{
- size_t i;
- uint8_t reg;
-
- static const struct { uint8_t idx; uint8_t msk; uint8_t set; } rttab[] = {
- { 0x43, 0xf3, 0x08 },
- { 0x44, 0xf0, 0x08 },
- { 0x45, 0xf3, 0x08 },
- { 0x46, 0xf0, 0x08 },
- };
-
- /* find DME1737 runtime device (LDN 10) */
- struct device * const dev = dev_find_slot_pnp(0x2e, DME1737_RT);
- if (dev == NULL)
- return;
-
- struct resource * const res = find_resource(dev, PNP_IDX_IO0);
- if (res == NULL)
- return;
-
- for (i = 0; i < ARRAY_SIZE(rttab); i++) {
- reg = inb(res->base + rttab[i].idx);
- reg &= rttab[i].msk;
- reg |= rttab[i].set;
- outb(reg, res->base + rttab[i].idx);
- }
-}
-
-static void dme1737_hwm_init(void)
-{
- size_t i;
- int reg;
-
- static const struct { uint8_t idx; uint8_t msk; uint8_t set; } script[] = {
- //{ 0x7f, 0x7f, 0x80 }, // INIT
- { 0x4f, 0x00, 0x32 }, // High
- { 0x54, 0x00, 0x30 }, // Tach0 Minimum LSB
- { 0x55, 0x00, 0x2a }, // Tach0 Minimum MSB
- { 0x56, 0x00, 0x30 }, // Tach1 Minimum LSB
- { 0x57, 0x00, 0x2a }, // Tach1 Minimum MSB
- { 0x5a, 0x00, 0x30 }, // Tach3 Minimum LSB
- { 0x5b, 0x00, 0x2a }, // Tach3 Minimum MSB
- { 0x5d, 0x00, 0x07 }, // PWM 1 Config: Zone 0
- { 0x5f, 0x0f, 0x50 }, // Zone 0 range, PWM freq
- { 0x62, 0x00, 0x67 }, // Ramp Rate
- { 0x63, 0x00, 0x80 }, // Ramp Rate
- { 0x65, 0x00, 0x0d }, // PWM 1 Minimum
- { 0x67, 0x00, 0x23 }, // Zone 0 Low
- { 0x6a, 0x00, 0x32 }, // Zone 0 High
- { 0x6c, 0x00, 0x5a }, // Zone 2 Abs
- { 0x80, 0x00, 0x17 }, // Interrupt Enable 2?
- { 0xa5, 0x00, 0x40 }, // PMW 4: 25% duty
- { 0xa6, 0x00, 0x40 }, // PWM 5: 25% duty
- { 0x40, 0xfe, 0x01 }, // START
- };
-
- struct device * const dev = dev_find_slot_on_smbus(2, 0x2e);
- if (dev == NULL) {
- printk(BIOS_INFO, "SMBus DME1737 not found\n");
- return;
- }
-
- printk(BIOS_SPEW, "%s DME1737 id: %x %x\n", __func__, smbus_read_byte(dev, 0x3e), smbus_read_byte(dev, 0x3f));
-
- for (i = 0; i < ARRAY_SIZE(script); i++) {
- reg = smbus_read_byte(dev, script[i].idx);
- if (reg < 0)
- goto fail;
- reg &= script[i].msk;
- reg |= script[i].set;
- reg = smbus_write_byte(dev, script[i].idx, reg & 0xff);
- if (reg < 0)
- goto fail;
- }
-
- return;
-
-fail:
- printk(BIOS_WARNING, "failed to initialize EMC6D103\n");
-}
-
-static void mainboard_init(struct device *dev)
-{
- emc6d103_init();
- dme1737_runtime_init();
- dme1737_hwm_init();
-
- printk(BIOS_DEBUG, "%s done\n", __func__);
-}
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->init = mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/sunw/ultra40m2/mb_sysconf.h b/src/mainboard/sunw/ultra40m2/mb_sysconf.h
deleted file mode 100644
index 64837f6174..0000000000
--- a/src/mainboard/sunw/ultra40m2/mb_sysconf.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_mcp55;
- unsigned char bus_mcp55b;
- unsigned apicid_mcp55;
- unsigned apicid_mcp55b;
- unsigned sbdnb;
-};
-
-#endif
diff --git a/src/mainboard/sunw/ultra40m2/mptable.c b/src/mainboard/sunw/ultra40m2/mptable.c
deleted file mode 100644
index 56266a5c2b..0000000000
--- a/src/mainboard/sunw/ultra40m2/mptable.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- struct mb_sysconf_t *m;
- unsigned sbdn;
- int i, j, bus_isa;
- unsigned char apicpin[4];
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res)
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
-
- /* Initialize interrupt mapping*/
- dword = pci_read_config32(dev, 0x74);
- dword &= ~(1 << 15);
- dword |= 1 << 2;
- pci_write_config32(dev, 0x74, dword);
-
- dword = 0x43c6c643;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x81001a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0xd00012d2;
- pci_write_config32(dev, 0x84, dword);
-
- }
-
- if (m->bus_mcp55b) {
- dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res)
- smp_write_ioapic(mc, m->apicid_mcp55b, 0x11,
- res2mmio(res, 0, 0));
-
- dword = 0x43c60000;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x81000000;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0xd00002d0;
- pci_write_config32(dev, 0x84, dword);
-
- }
-
- }
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); // 10
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
-
-//Slot PCIE
- for (j = 2; j < 8; j++) {
- struct device *dev;
- dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0));
- if (!dev || !dev->enabled)
- continue;
- for (i = 0; i < 4; i++)
- apicpin[i] = 0x10 + (2+j+i+4-sbdn%4)%4;
- smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin);
- }
-
-//Slot PCI 32
- {
- struct device *dev;
- dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0));
- if (dev && dev->enabled) {
- for (i = 0; i < 4; i++)
- apicpin[i] = 0x10 + i%4;
- smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin);
- }
- }
-
- if (m->bus_mcp55b) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|0, m->apicid_mcp55b, 0x14); // 20
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|1, m->apicid_mcp55b, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|2, m->apicid_mcp55b, 0x15); // 21
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+8)<<2)|0, m->apicid_mcp55b, 0x16); // 22
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+9)<<2)|0, m->apicid_mcp55b, 0x15); // 21
-
-
- //Slot PCIE
- for (j = 2; j < 8; j++) {
- struct device *dev;
- dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x0a + j - 2 , 0));
- if (!dev || !dev->enabled)
- continue;
- for (i = 0; i < 4; i++) {
- apicpin[i] = 0x10 + (2+j+i+4-m->sbdnb%4)%4;
- }
- smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55b, apicpin);
- }
-
- }
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/sunw/ultra40m2/resourcemap.c b/src/mainboard/sunw/ultra40m2/resourcemap.c
deleted file mode 100644
index 30ce9ea661..0000000000
--- a/src/mainboard/sunw/ultra40m2/resourcemap.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007010,
-// PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
-// PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000103, /* link 1 of CPU 0 --> Nvidia MCP55 Pro */
-// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c
deleted file mode 100644
index d3d579df6a..0000000000
--- a/src/mainboard/sunw/ultra40m2/romstage.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <southbridge/nvidia/mcp55/mcp55.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include <superio/smsc/dme1737/dme1737.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1)
-
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define NMI_SC 0x0061
-#define PCI_SERR_EN 0x04
-
-#define MCP55_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+61, 0x00, 0x05,/* GPIO62: enable/not-disable on-board TSB43AB22A Firewire */
-
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset = 0;
- unsigned bsp_apicid = 0;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- setup_mb_resource_map();
-
- dme1737_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
- setup_coherent_ht_domain(); // routing table and start other core0
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-#endif
-
- init_timer(); /* Need to use TMICT to synchronize FID/VID. */
-
- needs_reset |= optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= mcp55_early_setup_x();
-
- /* mask NMI from constantly-asserted-on-this-board SERR# */
- outb((inb(NMI_SC) & 0x0f) | PCI_SERR_EN, NMI_SC);
-
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
- /* all ap stopped? */
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig
deleted file mode 100644
index 35f9bf0aaf..0000000000
--- a/src/mainboard/supermicro/h8dme/Kconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-if BOARD_SUPERMICRO_H8DME
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_F
- select DIMM_DDR2
- select DIMM_REGISTERED
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_MCP55
- select HT_CHAIN_DISTRIBUTE
- select MCP55_USE_NIC
- select MCP55_USE_AZA
- select SUPERIO_WINBOND_W83627HF
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_1024
- select QRANK_DIMM_SUPPORT
- select K8_ALLOCATE_IO_RANGE
- select SET_FIDVID
- select DRIVERS_I2C_I2CMUX2
-
-config MAINBOARD_DIR
- string
- default supermicro/h8dme
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MEM_TRAIN_SEQ
- int
- default 1
-
-config MAINBOARD_PART_NUMBER
- string
- default "H8DME-2"
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_SUPERMICRO_H8DME
diff --git a/src/mainboard/supermicro/h8dme/Kconfig.name b/src/mainboard/supermicro/h8dme/Kconfig.name
deleted file mode 100644
index 867b967591..0000000000
--- a/src/mainboard/supermicro/h8dme/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_SUPERMICRO_H8DME
- bool "H8DME-2"
diff --git a/src/mainboard/supermicro/h8dme/board_info.txt b/src/mainboard/supermicro/h8dme/board_info.txt
deleted file mode 100644
index bd2a32b61d..0000000000
--- a/src/mainboard/supermicro/h8dme/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: server
-Board URL: http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DME-2.cfm
diff --git a/src/mainboard/supermicro/h8dme/cmos.layout b/src/mainboard/supermicro/h8dme/cmos.layout
deleted file mode 100644
index 9e6a9e56f2..0000000000
--- a/src/mainboard/supermicro/h8dme/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 200Mhz
-8 1 166Mhz
-8 2 133Mhz
-8 3 100Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb
deleted file mode 100644
index 754e3163ea..0000000000
--- a/src/mainboard/supermicro/h8dme/devicetree.cb
+++ /dev/null
@@ -1,126 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_F # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x15d9 0x1511 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627hf # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # SFI
- io 0x62 = 0x100
- end
- device pnp 2e.7 off # GPIO, game port, MIDI
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # WDTO PLED
- device pnp 2e.9 off end # GPIO SUSLED
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/i2c/i2cmux2
- device i2c 48 off end
- device i2c 49 off end
- end
- end
- device pci 1.1 on # SM 1
- # PCI device SMBus address will
- # depend on addon PCI device, do
- # we need to scan_smbus_bus?
- # chip drivers/generic/generic # PCIXA slot 1
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 2
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # PCI slot 1
- # device i2c 53 on end
- # end
- # chip drivers/generic/generic # Master MCP55 PCI-E
- # device i2c 54 on end
- # end
- # chip drivers/generic/generic # Slave MCP55 PCI-E
- # device i2c 55 on end
- # end
- chip drivers/generic/generic # MAC EEPROM
- device i2c 51 on end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
- device pci 6.0 on # PCI
- device pci 6.0 on end
- end
- device pci 6.1 on end # AZA
- device pci 8.0 on end # NIC
- device pci 9.0 on end # NIC
- device pci a.0 on # PCI E 5
- device pci 0.0 on end # NEC PCI-X
- device pci 0.1 on # NEC PCI-X
- device pci 4.0 on end # SCSI
- device pci 4.1 on end # SCSI
- end
- end
- device pci b.0 on end # PCI E 4
- device pci c.0 on end # PCI E 3
- device pci d.0 on end # PCI E 2
- device pci e.0 on end # PCI E 1
- device pci f.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c
deleted file mode 100644
index 8b8b2f9ea0..0000000000
--- a/src/mainboard/supermicro/h8dme/get_bus_conf.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_mcp55[8]; //1
-unsigned apicid_mcp55;
-
-unsigned char bus_pcix[3]; // under bus_mcp55_2
-
-unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-unsigned sbdnb;
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
- unsigned sbdn;
-
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- sbdn = sysconf.sbdn;
-
- sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain
-
- for (i = 0; i < 8; i++) {
- bus_mcp55[i] = 0;
- }
-
- for (i = 0; i < 3; i++) {
- bus_pcix[i] = 0;
- }
-
- bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* MCP55 */
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0));
- if (dev) {
- bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_mcp55[2]++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x06);
-
- bus_mcp55[1] = 2;
- bus_mcp55[2] = 3;
- }
-
- for (i = 2; i < 8; i++) {
- dev =
- dev_find_slot(bus_mcp55[0],
- PCI_DEVFN(sbdn + 0x0a + i - 2, 0));
- if (dev) {
- bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_mcp55[0], sbdn + 0x0a + i - 2);
- }
- }
-
- if (bus_mcp55[2]) {
- for (i = 0; i < 2; i++) {
- dev = dev_find_slot(bus_mcp55[2], PCI_DEVFN(0, i));
- if (dev) {
- bus_pcix[0] = bus_mcp55[2];
- bus_pcix[i + 1] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_mcp55 = apicid_base + 0;
-
-}
diff --git a/src/mainboard/supermicro/h8dme/hda_verb.c b/src/mainboard/supermicro/h8dme/hda_verb.c
deleted file mode 100644
index 072a306131..0000000000
--- a/src/mainboard/supermicro/h8dme/hda_verb.c
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[0] = {};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/supermicro/h8dme/irq_tables.c b/src/mainboard/supermicro/h8dme/irq_tables.c
deleted file mode 100644
index 2e9bbb8e87..0000000000
--- a/src/mainboard/supermicro/h8dme/irq_tables.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern unsigned char bus_isa;
-extern unsigned char bus_mcp55[8]; //1
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
- unsigned sbdn;
-
- uint8_t sum = 0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_mcp55[0];
- pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x0370;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c
deleted file mode 100644
index 295df50a31..0000000000
--- a/src/mainboard/supermicro/h8dme/mptable.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_mcp55[8]; //1
-
-extern unsigned apicid_mcp55;
-
-extern unsigned char bus_pcix[3]; // under bus_mcp55_2
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned sbdn;
- int i, j, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
- }
-
- dword = 0x43c6c643;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x81001a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0xd00012d2;
- pci_write_config32(dev, 0x84, dword);
-
- }
-
-
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
-
- for(j = 7; j >= 2; j--) {
- if(!bus_mcp55[j]) continue;
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
- }
- }
-
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04 << 2)|i, apicid_mcp55, 0x10 + (0+i)%4);
- }
-
-
- if(bus_pcix[0]) {
- for(i = 0; i < 2; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4 << 2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17
- }
-
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4 << 2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
- }
- }
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/supermicro/h8dme/resourcemap.c b/src/mainboard/supermicro/h8dme/resourcemap.c
deleted file mode 100644
index 22c61f49d2..0000000000
--- a/src/mainboard/supermicro/h8dme/resourcemap.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
deleted file mode 100644
index 13cb038102..0000000000
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#define SUPERIO_DEV PNP_DEV(0x2e, 0)
-
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#if 0
-/* We don't do any switching yet. */
-#define SMBUS_SWITCH1 0x48
-#define SMBUS_SWITCH2 0x49
- unsigned device=(ctrl->channel0[0])>>8;
- smbus_send_byte(SMBUS_SWITCH1, device);
- smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
-#endif
-}
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- enable_smbus();
-// smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */
- smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
-
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
-}
-
-/* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */
-#define RC0 (2 << 8)
-#define RC1 (1 << 8)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-/* The SPD is being read from the CPU1 (marked CPU2 on the board) and we
- don't know how to switch the SMBus to decode the CPU0 SPDs. So, The
- memory on each CPU must be an exact match.
- */
- static const uint16_t spd_addr[] = {
- // Node 0
- RC0 | DIMM0, RC0 | DIMM2,
- RC0 | DIMM4, RC0 | DIMM6,
- RC0 | DIMM1, RC0 | DIMM3,
- RC0 | DIMM5, RC0 | DIMM7,
- // Node 1
- RC1 | DIMM0, RC1 | DIMM2,
- RC1 | DIMM4, RC1 | DIMM6,
- RC1 | DIMM1, RC1 | DIMM3,
- RC1 | DIMM5, RC1 | DIMM7,
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset = 0;
- unsigned bsp_apicid = 0;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- winbond_set_clksel_48(SUPERIO_DEV);
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
- setup_mb_resource_map();
-
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
- dump_smbus_registers();
-#endif
- setup_coherent_ht_domain(); // routing table and start other core0
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-#endif
-
- init_timer(); /* Need to use TMICT to synchronize FID/VID. */
-
- needs_reset |= optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= mcp55_early_setup_x();
-
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus(); /* enable in sio_setup */
-
- /* all ap stopped? */
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig
deleted file mode 100644
index 9efc5d2ee2..0000000000
--- a/src/mainboard/supermicro/h8dmr/Kconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-if BOARD_SUPERMICRO_H8DMR
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_F
- select DIMM_DDR2
- select DIMM_REGISTERED
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_MCP55
- select HT_CHAIN_DISTRIBUTE
- select MCP55_USE_NIC
- select MCP55_USE_AZA
- select SUPERIO_WINBOND_W83627HF
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_1024
- select QRANK_DIMM_SUPPORT
- select K8_ALLOCATE_IO_RANGE
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default supermicro/h8dmr
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MEM_TRAIN_SEQ
- int
- default 1
-
-config MAINBOARD_PART_NUMBER
- string
- default "H8DMR-i2"
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_SUPERMICRO_H8DMR
diff --git a/src/mainboard/supermicro/h8dmr/Kconfig.name b/src/mainboard/supermicro/h8dmr/Kconfig.name
deleted file mode 100644
index 9754fb6f4a..0000000000
--- a/src/mainboard/supermicro/h8dmr/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_SUPERMICRO_H8DMR
- bool "H8DMR-i2"
diff --git a/src/mainboard/supermicro/h8dmr/board_info.txt b/src/mainboard/supermicro/h8dmr/board_info.txt
deleted file mode 100644
index b4f8f0b66d..0000000000
--- a/src/mainboard/supermicro/h8dmr/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: server
-Board URL: http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DMR-i2.cfm
diff --git a/src/mainboard/supermicro/h8dmr/cmos.layout b/src/mainboard/supermicro/h8dmr/cmos.layout
deleted file mode 100644
index 9e6a9e56f2..0000000000
--- a/src/mainboard/supermicro/h8dmr/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 200Mhz
-8 1 166Mhz
-8 2 133Mhz
-8 3 100Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/supermicro/h8dmr/devicetree.cb b/src/mainboard/supermicro/h8dmr/devicetree.cb
deleted file mode 100644
index b36367477d..0000000000
--- a/src/mainboard/supermicro/h8dmr/devicetree.cb
+++ /dev/null
@@ -1,146 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_F # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x15d9 0x1511 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627hf # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # SFI
- io 0x62 = 0x100
- end
- device pnp 2e.7 off # GPIO, game port, MIDI
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # WDTO PLED
- device pnp 2e.9 off end # GPIO SUSLED
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic # DIMM 1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic # DIMM 1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic # DIMM 1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic # DIMM 1-1-1
- device i2c 57 on end
- end
- end
- device pci 1.1 on # SM 1
- # PCI device SMBus address will
- # depend on addon PCI device, do
- # we need to scan_smbus_bus?
- # chip drivers/generic/generic # PCIXA slot 1
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 2
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # PCI slot 1
- # device i2c 53 on end
- # end
- # chip drivers/generic/generic # Master MCP55 PCI-E
- # device i2c 54 on end
- # end
- # chip drivers/generic/generic # Slave MCP55 PCI-E
- # device i2c 55 on end
- # end
- chip drivers/generic/generic # MAC EEPROM
- device i2c 51 on end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
- device pci 6.0 on # PCI
- device pci 6.0 on end
- end
- device pci 6.1 on end # AZA
- device pci 8.0 on end # NIC
- device pci 9.0 on end # NIC
- device pci a.0 on # PCI E 5
- device pci 0.0 on end # NEC PCI-X
- device pci 0.1 on # NEC PCI-X
- device pci 4.0 on end # SCSI
- device pci 4.1 on end # SCSI
- end
- end
- device pci b.0 on end # PCI E 4
- device pci c.0 on end # PCI E 3
- device pci d.0 on end # PCI E 2
- device pci e.0 on end # PCI E 1
- device pci f.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c
deleted file mode 100644
index 8b8b2f9ea0..0000000000
--- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_mcp55[8]; //1
-unsigned apicid_mcp55;
-
-unsigned char bus_pcix[3]; // under bus_mcp55_2
-
-unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-unsigned sbdnb;
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
- unsigned sbdn;
-
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- sbdn = sysconf.sbdn;
-
- sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain
-
- for (i = 0; i < 8; i++) {
- bus_mcp55[i] = 0;
- }
-
- for (i = 0; i < 3; i++) {
- bus_pcix[i] = 0;
- }
-
- bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* MCP55 */
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0));
- if (dev) {
- bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_mcp55[2]++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x06);
-
- bus_mcp55[1] = 2;
- bus_mcp55[2] = 3;
- }
-
- for (i = 2; i < 8; i++) {
- dev =
- dev_find_slot(bus_mcp55[0],
- PCI_DEVFN(sbdn + 0x0a + i - 2, 0));
- if (dev) {
- bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_mcp55[0], sbdn + 0x0a + i - 2);
- }
- }
-
- if (bus_mcp55[2]) {
- for (i = 0; i < 2; i++) {
- dev = dev_find_slot(bus_mcp55[2], PCI_DEVFN(0, i));
- if (dev) {
- bus_pcix[0] = bus_mcp55[2];
- bus_pcix[i + 1] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_mcp55 = apicid_base + 0;
-
-}
diff --git a/src/mainboard/supermicro/h8dmr/hda_verb.c b/src/mainboard/supermicro/h8dmr/hda_verb.c
deleted file mode 100644
index 072a306131..0000000000
--- a/src/mainboard/supermicro/h8dmr/hda_verb.c
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[0] = {};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/supermicro/h8dmr/irq_tables.c b/src/mainboard/supermicro/h8dmr/irq_tables.c
deleted file mode 100644
index 2e9bbb8e87..0000000000
--- a/src/mainboard/supermicro/h8dmr/irq_tables.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern unsigned char bus_isa;
-extern unsigned char bus_mcp55[8]; //1
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
- unsigned sbdn;
-
- uint8_t sum = 0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_mcp55[0];
- pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x0370;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c
deleted file mode 100644
index bb080e515f..0000000000
--- a/src/mainboard/supermicro/h8dmr/mptable.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_mcp55[8]; //1
-
-extern unsigned apicid_mcp55;
-
-extern unsigned char bus_pcix[3]; // under bus_mcp55_2
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned sbdn;
- int i, j, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
- }
-
- dword = 0x43c6c643;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x81001a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0xd00012d2;
- pci_write_config32(dev, 0x84, dword);
-
- }
-
-
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
-
- /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
-
- for(j = 7; j >= 2; j--) {
- if(!bus_mcp55[j]) continue;
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
- }
- }
-
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04 << 2)|i, apicid_mcp55, 0x10 + (0+i)%4);
- }
-
-
- if(bus_pcix[0]) {
- for(i = 0; i < 2; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4 << 2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17
- }
-
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4 << 2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
- }
- }
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/supermicro/h8dmr/resourcemap.c b/src/mainboard/supermicro/h8dmr/resourcemap.c
deleted file mode 100644
index 22c61f49d2..0000000000
--- a/src/mainboard/supermicro/h8dmr/resourcemap.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
deleted file mode 100644
index a766f01396..0000000000
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#define SUPERIO_DEV PNP_DEV(0x2e, 0)
-
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- enable_smbus();
-// smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */
- smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
-
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset = 0;
- unsigned bsp_apicid = 0;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- winbond_set_clksel_48(SUPERIO_DEV);
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
- setup_mb_resource_map();
-
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
- setup_coherent_ht_domain(); // routing table and start other core0
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
- }
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
- }
-#endif
-
- init_timer(); // Need to use TMICT to synchronize FID/VID
-
- needs_reset |= optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= mcp55_early_setup_x();
-
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
-// enable_smbus(); /* enable in sio_setup */
-
- /* all ap stopped? */
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/technexion/Kconfig b/src/mainboard/technexion/Kconfig
deleted file mode 100644
index 163a4bfe6a..0000000000
--- a/src/mainboard/technexion/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_TECHNEXION
-
-choice
- prompt "Mainboard model"
-
-source "src/mainboard/technexion/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/technexion/*/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "Technexion"
-
-endif # VENDOR_TECHNEXION
diff --git a/src/mainboard/technexion/Kconfig.name b/src/mainboard/technexion/Kconfig.name
deleted file mode 100644
index 6366ff59b6..0000000000
--- a/src/mainboard/technexion/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_TECHNEXION
- bool "Technexion"
diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig
deleted file mode 100644
index 0220d7762b..0000000000
--- a/src/mainboard/technexion/tim5690/Kconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-if BOARD_TECHNEXION_TIM5690
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_S1G1
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_RS690
- select SOUTHBRIDGE_AMD_SB600
- select SUPERIO_ITE_IT8712F
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select HAVE_ACPI_TABLES
- select GFXUMA
- select BOARD_ROMSIZE_KB_512
- select QRANK_DIMM_SUPPORT
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default technexion/tim5690
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "TIM-5690"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_TECHNEXION_TIM5690
diff --git a/src/mainboard/technexion/tim5690/Kconfig.name b/src/mainboard/technexion/tim5690/Kconfig.name
deleted file mode 100644
index 24aad25c2c..0000000000
--- a/src/mainboard/technexion/tim5690/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_TECHNEXION_TIM5690
- bool "TIM-5690"
diff --git a/src/mainboard/technexion/tim5690/Makefile.inc b/src/mainboard/technexion/tim5690/Makefile.inc
deleted file mode 100644
index 51202179f1..0000000000
--- a/src/mainboard/technexion/tim5690/Makefile.inc
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# Needed by irq_tables and mptable and acpi_tables.
-
-# This is debug message for products of Technexion.
-ramstage-y += tn_post_code.c
-
-ramstage-y += speaker.c
-ramstage-$(CONFIG_VGA_ROM_RUN) += vgabios.c
diff --git a/src/mainboard/technexion/tim5690/acpi/ide.asl b/src/mainboard/technexion/tim5690/acpi/ide.asl
deleted file mode 100644
index d5badfcb6b..0000000000
--- a/src/mainboard/technexion/tim5690/acpi/ide.asl
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "ide.asl"
- }
- }
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
- 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
- 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
- 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
- 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
- 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
- Field(ICRG, AnyAcc, NoLock, Preserve)
-{
- PPTS, 8, /* Primary PIO Slave Timing */
- PPTM, 8, /* Primary PIO Master Timing */
- OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
- PMTM, 8, /* Primary MWDMA Master Timing */
- OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
- OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
- PPSM, 4, /* Primary PIO slave Mode */
- OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
- OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
- PDSM, 4, /* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
- Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
- Increment(Local0)
- Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
- Increment(Local1)
- Return(Multiply(30, Add(Local0, Local1)))
-}
-
-Device(PRID)
-{
- Name (_ADR, Zero)
- Method(_GTM, 0)
- {
- NAME(OTBF, Buffer(20) { /* out buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
- CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
- /* Just return if the channel is disabled */
- If(And(PPCR, 0x01)) { /* primary PIO control */
- Return(OTBF)
- }
-
- /* Always tell them independent timing available and IOChannelReady used on both drives */
- Or(BFFG, 0x1A, BFFG)
-
- Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
- Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
-
- If(And(PDCR, 0x01)) { /* It's under UDMA mode */
- Or(BFFG, 0x01, BFFG)
- Store(DerefOf(Index(UDTT, PDMM)), DSD0)
- }
- Else {
- Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
- }
-
- If(And(PDCR, 0x02)) { /* It's under UDMA mode */
- Or(BFFG, 0x04, BFFG)
- Store(DerefOf(Index(UDTT, PDSM)), DSD1)
- }
- Else {
- Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
- }
-
- Return(OTBF) /* out buffer */
- } /* End Method(_GTM) */
-
- Method(_STM, 3, NotSerialized)
- {
- NAME(INBF, Buffer(20) { /* in buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
- CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
- Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
- Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
- Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
- Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
-
- Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
- Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
-
- If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDMM,)
- Or(PDCR, 0x01, PDCR)
- }
- Else {
- If(LNotEqual(DSD0, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTM)
- }
- }
-
- If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDSM,)
- Or(PDCR, 0x02, PDCR)
- }
- Else {
- If(LNotEqual(DSD1, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTS)
- }
- }
- /* Return(INBF) */
- } /*End Method(_STM) */
- Device(MST)
- {
- Name(_ADR, 0)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xA0, CMDA)
- Store(0xA0, CMDB)
- Store(0xA0, CMDC)
-
- Or(PPMM, 0x08, POMD)
-
- If(And(PDCR, 0x01)) {
- Or(PDMM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTM),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(MST) */
-
- Device(SLAV)
- {
- Name(_ADR, 1)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xB0, CMDA)
- Store(0xB0, CMDB)
- Store(0xB0, CMDC)
-
- Or(PPSM, 0x08, POMD)
-
- If(And(PDCR, 0x02)) {
- Or(PDSM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTS),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(SLAV) */
-}
diff --git a/src/mainboard/technexion/tim5690/acpi/routing.asl b/src/mainboard/technexion/tim5690/acpi/routing.asl
deleted file mode 100644
index bcb14e7e37..0000000000
--- a/src/mainboard/technexion/tim5690/acpi/routing.asl
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "routing.asl"
- }
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
- Name(PR0, Package(){
- /* NB devices */
- /* Bus 0, Dev 0 - RS690 Host Controller */
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, INTC, 0 },
- Package(){0x0002FFFF, 1, INTD, 0 },
- Package(){0x0002FFFF, 2, INTA, 0 },
- Package(){0x0002FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, INTA, 0 },
- Package(){0x0004FFFF, 1, INTB, 0 },
- Package(){0x0004FFFF, 2, INTC, 0 },
- Package(){0x0004FFFF, 3, INTD, 0 },
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- /* Package(){0x0005FFFF, 0, INTB, 0 }, */
- /* Package(){0x0005FFFF, 1, INTC, 0 }, */
- /* Package(){0x0005FFFF, 2, INTD, 0 }, */
- /* Package(){0x0005FFFF, 3, INTA, 0 }, */
- /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
- Package(){0x0006FFFF, 0, INTC, 0 },
- Package(){0x0006FFFF, 1, INTD, 0 },
- Package(){0x0006FFFF, 2, INTA, 0 },
- Package(){0x0006FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
- Package(){0x0007FFFF, 0, INTD, 0 },
- Package(){0x0007FFFF, 1, INTA, 0 },
- Package(){0x0007FFFF, 2, INTB, 0 },
- Package(){0x0007FFFF, 3, INTC, 0 },
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0012FFFF, 1, INTA, 0 },
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){0x0013FFFF, 0, INTA, 0 },
- Package(){0x0013FFFF, 1, INTB, 0 },
- Package(){0x0013FFFF, 2, INTC, 0 },
- Package(){0x0013FFFF, 3, INTD, 0 },
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
- Package(){0x0014FFFF, 0, INTA, 0 },
- Package(){0x0014FFFF, 1, INTB, 0 },
- Package(){0x0014FFFF, 2, INTC, 0 },
- Package(){0x0014FFFF, 3, INTD, 0 },
- })
-
- Name(APR0, Package(){
- /* NB devices in APIC mode */
- /* Bus 0, Dev 0 - RS690 Host Controller */
-
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Package(){0x0001FFFF, 0, 0, 18 }, */
- /* Package(){0x0001FFFF, 1, 0, 19 }, */
-
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, 0, 18 },
- /* Package(){0x0002FFFF, 1, 0, 19 }, */
- /* Package(){0x0002FFFF, 2, 0, 16 }, */
- /* Package(){0x0002FFFF, 3, 0, 17 }, */
-
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){0x0003FFFF, 0, 0, 19 },
-
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, 0, 16 },
- /* Package(){0x0004FFFF, 1, 0, 17 }, */
- /* Package(){0x0004FFFF, 2, 0, 18 }, */
- /* Package(){0x0004FFFF, 3, 0, 19 }, */
-
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- Package(){0x0005FFFF, 0, 0, 17 },
- /* Package(){0x0005FFFF, 1, 0, 18 }, */
- /* Package(){0x0005FFFF, 2, 0, 19 }, */
- /* Package(){0x0005FFFF, 3, 0, 16 }, */
-
- /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
- Package(){0x0006FFFF, 0, 0, 18 },
- /* Package(){0x0006FFFF, 1, 0, 19 }, */
- /* Package(){0x0006FFFF, 2, 0, 16 }, */
- /* Package(){0x0006FFFF, 3, 0, 17 }, */
-
- /* Bus 0, Dev 7 - PCIe Bridge for network card */
- Package(){0x0007FFFF, 0, 0, 19 },
- /* Package(){0x0007FFFF, 1, 0, 16 }, */
- /* Package(){0x0007FFFF, 2, 0, 17 }, */
- /* Package(){0x0007FFFF, 3, 0, 18 }, */
-
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices in APIC mode */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0012FFFF, 0, 0, 22 },
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){0x0013FFFF, 0, 0, 16 },
- Package(){0x0013FFFF, 1, 0, 17 },
- Package(){0x0013FFFF, 2, 0, 18 },
- Package(){0x0013FFFF, 3, 0, 19 },
- /* Package(){0x00130004, 2, 0, 18 }, */
- /* Package(){0x00130005, 3, 0, 19 }, */
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
- Package(){0x0014FFFF, 0, 0, 16 },
- Package(){0x0014FFFF, 1, 0, 17 },
- Package(){0x0014FFFF, 2, 0, 18 },
- Package(){0x0014FFFF, 3, 0, 19 },
- /* Package(){0x00140004, 2, 0, 18 }, */
- /* Package(){0x00140004, 3, 0, 19 }, */
- /* Package(){0x00140005, 1, 0, 17 }, */
- /* Package(){0x00140006, 1, 0, 17 }, */
- })
-
- Name(PR1, Package(){
- /* Internal graphics - RS690 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, INTA, 0 },
- Package(){0x0005FFFF, 1, INTB, 0 },
- Package(){0x0005FFFF, 2, INTC, 0 },
- Package(){0x0005FFFF, 3, INTD, 0 },
- })
-
- Name(APR1, Package(){
- /* Internal graphics - RS690 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, 0, 18 },
- Package(){0x0005FFFF, 1, 0, 19 },
- /* Package(){0x0005FFFF, 2, 0, 20 }, */
- /* Package(){0x0005FFFF, 3, 0, 17 }, */
- })
-
- Name(PS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, INTA, 0 },
- Package(){0x0000FFFF, 1, INTB, 0 },
- Package(){0x0000FFFF, 2, INTC, 0 },
- Package(){0x0000FFFF, 3, INTD, 0 },
- })
-
- Name(APS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, 0, 16 },
- Package(){0x0000FFFF, 1, 0, 17 },
- Package(){0x0000FFFF, 2, 0, 18 },
- Package(){0x0000FFFF, 3, 0, 19 },
- })
-
- Name(PS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, INTB, 0 },
- Package(){0x0000FFFF, 1, INTC, 0 },
- Package(){0x0000FFFF, 2, INTD, 0 },
- Package(){0x0000FFFF, 3, INTA, 0 },
- })
-
- Name(APS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
-
- Name(APS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, 0, 19 },
- Package(){0x0000FFFF, 1, 0, 16 },
- Package(){0x0000FFFF, 2, 0, 17 },
- Package(){0x0000FFFF, 3, 0, 18 },
- })
-
- Name(PCIB, Package(){
- /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
- Package(){0x0005FFFF, 0, 0, 0x14 },
- Package(){0x0005FFFF, 1, 0, 0x15 },
- Package(){0x0005FFFF, 2, 0, 0x16 },
- Package(){0x0005FFFF, 3, 0, 0x17 },
- Package(){0x0006FFFF, 0, 0, 0x15 },
- Package(){0x0006FFFF, 1, 0, 0x16 },
- Package(){0x0006FFFF, 2, 0, 0x17 },
- Package(){0x0006FFFF, 3, 0, 0x14 },
- Package(){0x0007FFFF, 0, 0, 0x16 },
- Package(){0x0007FFFF, 1, 0, 0x17 },
- Package(){0x0007FFFF, 2, 0, 0x14 },
- Package(){0x0007FFFF, 3, 0, 0x15 },
- })
-}
diff --git a/src/mainboard/technexion/tim5690/acpi/sata.asl b/src/mainboard/technexion/tim5690/acpi/sata.asl
deleted file mode 100644
index 474e5ed6d2..0000000000
--- a/src/mainboard/technexion/tim5690/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(SATA) {
- Name(_ADR, 0x00120000)
- #include "sata.asl"
- }
- }
-}
-*/
-
-Name(STTM, Buffer(20) {
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
- \_GPE._L1F()
-}
-
-Device(PMRY)
-{
- Name(_ADR, 0)
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(PMST) {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P0IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- }/* end of PMST */
-
- Device(PSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P1IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of PSLA */
-} /* end of PMRY */
-
-
-Device(SEDY)
-{
- Name(_ADR, 1) /* IDE Scondary Channel */
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(SMST)
- {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P2IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SMST */
-
- Device(SSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P3IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SSLA */
-} /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
- Method(_L1F,0x0,NotSerialized) {
- if (\_SB.P0PR) {
- if (LGreater(\_SB.P0IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P0PR)
- }
-
- if (\_SB.P1PR) {
- if (LGreater(\_SB.P1IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P1PR)
- }
-
- if (\_SB.P2PR) {
- if (LGreater(\_SB.P2IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P2PR)
- }
-
- if (\_SB.P3PR) {
- if (LGreater(\_SB.P3IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P3PR)
- }
- }
-}
diff --git a/src/mainboard/technexion/tim5690/acpi/usb.asl b/src/mainboard/technexion/tim5690/acpi/usb.asl
deleted file mode 100644
index dbffa39ad2..0000000000
--- a/src/mainboard/technexion/tim5690/acpi/usb.asl
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "usb.asl"
- }
-*/
-Method(UCOC, 0) {
- Sleep(20)
- Store(0x13,CMTI)
- Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
- Scope (\_GPE) {
- Method (_L13) {
- UCOC()
- if(LEqual(GPB0,PLC0)) {
- Not(PLC0,PLC0)
- Store(PLC0, \_SB.PT0D)
- }
- }
- }
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
- Scope (\_GPE) {
- Method (_L14) {
- UCOC()
- if (LEqual(GPB1,PLC1)) {
- Not(PLC1,PLC1)
- Store(PLC1, \_SB.PT1D)
- }
- }
- }
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
- Scope (\_GPE) {
- Method (_L15) {
- UCOC()
- if (LEqual(GPB2,PLC2)) {
- Not(PLC2,PLC2)
- Store(PLC2, \_SB.PT2D)
- }
- }
- }
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
- Scope (\_GPE) {
- Method (_L16) {
- UCOC()
- if (LEqual(GPB3,PLC3)) {
- Not(PLC3,PLC3)
- Store(PLC3, \_SB.PT3D)
- }
- }
- }
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
- Scope (\_GPE) {
- Method (_L19) {
- UCOC()
- if (LEqual(GPB4,PLC4)) {
- Not(PLC4,PLC4)
- Store(PLC4, \_SB.PT4D)
- }
- }
- }
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-/* If (LLessEqual(UOM5,9)) {
-* Scope (\_GPE) {
-* Method (_L1A) {
-* UCOC()
-* if (LEqual(GPB5,PLC5)) {
-* Not(PLC5,PLC5)
-* Store(PLC5, \_SB.PT5D)
-* }
-* }
-* }
-* }
-*/
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
- Scope (\_GPE) {
- /* Method (_L1C) { */
- Method (_L06) {
- UCOC()
- if (LEqual(GPB6,PLC6)) {
- Not(PLC6,PLC6)
- Store(PLC6, \_SB.PT6D)
- }
- }
- }
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
- Scope (\_GPE) {
- /* Method (_L1D) { */
- Method (_L07) {
- UCOC()
- if (LEqual(GPB7,PLC7)) {
- Not(PLC7,PLC7)
- Store(PLC7, \_SB.PT7D)
- }
- }
- }
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
- Scope (\_GPE) {
- Method (_L17) {
- if (LEqual(G8IS,PLC8)) {
- Not(PLC8,PLC8)
- Store(PLC8, \_SB.PT8D)
- }
- }
- }
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
- Scope (\_GPE) {
- Method (_L0E) {
- if (LEqual(G9IS,0)) {
- Store(1,\_SB.PT9D)
- }
- }
- }
-}
diff --git a/src/mainboard/technexion/tim5690/acpi_tables.c b/src/mainboard/technexion/tim5690/acpi_tables.c
deleted file mode 100644
index 75834b6c7f..0000000000
--- a/src/mainboard/technexion/tim5690/acpi_tables.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include <arch/cpu.h>
-#include <cpu/amd/powernow.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- get_bus_conf();
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB600 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
- IO_APIC_ADDR, 0);
-
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high */
-
- /* create all subtables for processors */
- /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
- /* 1: LINT1 connect to NMI */
-
- return current;
-}
diff --git a/src/mainboard/technexion/tim5690/board_info.txt b/src/mainboard/technexion/tim5690/board_info.txt
deleted file mode 100644
index c63907ad01..0000000000
--- a/src/mainboard/technexion/tim5690/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: half
-Board URL: http://www.technexion.com/index.php/embedded-mainboards/amd/tim-5690
diff --git a/src/mainboard/technexion/tim5690/cmos.layout b/src/mainboard/technexion/tim5690/cmos.layout
deleted file mode 100644
index 104d51f4c2..0000000000
--- a/src/mainboard/technexion/tim5690/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-##
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/technexion/tim5690/devicetree.cb b/src/mainboard/technexion/tim5690/devicetree.cb
deleted file mode 100644
index bf462e213a..0000000000
--- a/src/mainboard/technexion/tim5690/devicetree.cb
+++ /dev/null
@@ -1,112 +0,0 @@
-#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_S1G1
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1022 0x3050 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on # southbridge
- chip southbridge/amd/rs690
- device pci 0.0 on end # HT 0x7910
- device pci 1.0 on # Internal Graphics P2P bridge 0x7912
- device pci 5.0 on end # Internal Graphics 0x791F
- end
- device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
- device pci 3.0 off end # PCIE P2P bridge 0x791b
- device pci 4.0 on end # PCIE P2P bridge 0x7914
- device pci 5.0 on end # PCIE P2P bridge 0x7915
- device pci 6.0 on end # PCIE P2P bridge 0x7916
- device pci 7.0 on end # PCIE P2P bridge 0x7917
- device pci 8.0 off end # NB/SB Link P2P bridge
- register "gpp_configuration" = "4"
- register "port_enable" = "0xfc"
- register "gfx_dev2_dev3" = "1"
- register "gfx_dual_slot" = "0"
- register "gfx_lane_reversal" = "0"
- register "gfx_tmds" = "1"
- register "gfx_compliance" = "0"
- register "gfx_reconfiguration" = "0"
- register "gfx_link_width" = "0"
- end
- chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
- device pci 12.0 on end # SATA 0x4380
- device pci 13.0 on end # USB 0x4387
- device pci 13.1 on end # USB 0x4388
- device pci 13.2 on end # USB 0x4389
- device pci 13.3 on end # USB 0x438a
- device pci 13.4 on end # USB 0x438b
- device pci 13.5 on end # USB 2 0x4386
- device pci 14.0 on # SM 0x4385
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- end # SM
- device pci 14.1 on end # IDE 0x438c
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC 0x438d
- chip superio/ite/it8712f
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 off end # EC
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.6 on # Mouse
- irq 0x70 = 12
- end
- device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
- end
- device pnp 2e.8 off # MIDI
- io 0x60 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.9 off # GAME
- io 0x60 = 0x220
- end
- device pnp 2e.a off end # CIR
- end #superio/ite/it8712f
- end #LPC
- device pci 14.4 on end # PCI 0x4384
- device pci 14.5 on end # ACI 0x4382
- device pci 14.6 on end # MCI 0x438e
- register "hda_viddid" = "0x10ec0882"
- end #southbridge/amd/sb600
- end # device pci 18.0
-
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end #northbridge/amd/amdk8
- end #domain
-end #northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl
deleted file mode 100644
index 44da647f8e..0000000000
--- a/src/mainboard/technexion/tim5690/dsdt.asl
+++ /dev/null
@@ -1,1674 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <southbridge/amd/sb600/sb600.h>
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "TECHNE", /* OEMID */
- "COREBOOT", /* TABLE ID */
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
-
- /* Data to be patched by the BIOS during POST */
- /* FIXME the patching is not done yet! */
- /* Memory related values */
- Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
-
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
-
- /* USB overcurrent mapping pins. */
- Name(UOM0, 0)
- Name(UOM1, 2)
- Name(UOM2, 0)
- Name(UOM3, 7)
- Name(UOM4, 2)
- Name(UOM5, 2)
- Name(UOM6, 6)
- Name(UOM7, 2)
- Name(UOM8, 6)
- Name(UOM9, 6)
-
- /* Some global data */
- Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PMOD, One) /* Assume APIC */
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- /* PCI Error control register */
- OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
- Field(PERC, ByteAcc, NoLock, Preserve) {
- SENS, 0x00000001,
- PENS, 0x00000001,
- SENE, 0x00000001,
- PENE, 0x00000001,
- }
-
- /* Client Management index/data registers */
- OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
- Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
- /* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
- }
-
- /* GPM Port register */
- OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
- Field(GPT, ByteAcc, NoLock, Preserve) {
- GPB0,1,
- GPB1,1,
- GPB2,1,
- GPB3,1,
- GPB4,1,
- GPB5,1,
- GPB6,1,
- GPB7,1,
- }
-
- /* Flash ROM program enable register */
- OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
- Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
- FLRE, 0x00000001,
- }
-
- /* PM2 index/data registers */
- OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
- Field(PM2R, ByteAcc, NoLock, Preserve) {
- PM2I, 0x00000008,
- PM2D, 0x00000008,
- }
-
- /* Power Management I/O registers */
- OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
- Field(PIOR, ByteAcc, NoLock, Preserve) {
- PIOI, 0x00000008,
- PIOD, 0x00000008,
- }
- IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
- Offset(0x00), /* MiscControl */
- , 1,
- T1EE, 1,
- T2EE, 1,
- Offset(0x01), /* MiscStatus */
- , 1,
- T1E, 1,
- T2E, 1,
- Offset(0x04), /* SmiWakeUpEventEnable3 */
- , 7,
- SSEN, 1,
- Offset(0x07), /* SmiWakeUpEventStatus3 */
- , 7,
- CSSM, 1,
- Offset(0x10), /* AcpiEnable */
- , 6,
- PWDE, 1,
- Offset(0x1C), /* ProgramIoEnable */
- , 3,
- MKME, 1,
- IO3E, 1,
- IO2E, 1,
- IO1E, 1,
- IO0E, 1,
- Offset(0x1D), /* IOMonitorStatus */
- , 3,
- MKMS, 1,
- IO3S, 1,
- IO2S, 1,
- IO1S, 1,
- IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
- APEB, 16,
- Offset(0x36), /* GEvtLevelConfig */
- , 6,
- ELC6, 1,
- ELC7, 1,
- Offset(0x37), /* GPMLevelConfig0 */
- , 3,
- PLC0, 1,
- PLC1, 1,
- PLC2, 1,
- PLC3, 1,
- PLC8, 1,
- Offset(0x38), /* GPMLevelConfig1 */
- , 1,
- PLC4, 1,
- PLC5, 1,
- , 1,
- PLC6, 1,
- PLC7, 1,
- Offset(0x3B), /* PMEStatus1 */
- GP0S, 1,
- GM4S, 1,
- GM5S, 1,
- APS, 1,
- GM6S, 1,
- GM7S, 1,
- GP2S, 1,
- STSS, 1,
- Offset(0x55), /* SoftPciRst */
- SPRE, 1,
- , 1,
- , 1,
- PNAT, 1,
- PWMK, 1,
- PWNS, 1,
-
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
-
- Offset(0x65), /* UsbPMControl */
- , 4,
- URRE, 1,
- Offset(0x68), /* MiscEnable68 */
- , 3,
- TMTE, 1,
- , 1,
- Offset(0x92), /* GEVENTIN */
- , 7,
- E7IS, 1,
- Offset(0x96), /* GPM98IN */
- G8IS, 1,
- G9IS, 1,
- Offset(0x9A), /* EnhanceControl */
- ,7,
- HPDE, 1,
- Offset(0xA8), /* PIO7654Enable */
- IO4E, 1,
- IO5E, 1,
- IO6E, 1,
- IO7E, 1,
- Offset(0xA9), /* PIO7654Status */
- IO4S, 1,
- IO5S, 1,
- IO6S, 1,
- IO7S, 1,
- }
-
- /* PM1 Event Block
- * First word is PM1_Status, Second word is PM1_Enable
- */
- OperationRegion(P1EB, SystemIO, APEB, 0x04)
- Field(P1EB, ByteAcc, NoLock, Preserve) {
- TMST, 1,
- , 3,
- BMST, 1,
- GBST, 1,
- Offset(0x01),
- PBST, 1,
- , 1,
- RTST, 1,
- , 3,
- PWST, 1,
- SPWS, 1,
- Offset(0x02),
- TMEN, 1,
- , 4,
- GBEN, 1,
- Offset(0x03),
- PBEN, 1,
- , 1,
- RTEN, 1,
- , 3,
- PWDA, 1,
- }
-
- Scope(\_SB) {
-
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
- /* Byte offsets are computed using the following technique:
- * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
- * The 8 comes from 8 functions per device, and 4096 bytes per function config space
- */
- Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
- STB5, 32,
- Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
- PT0D, 1,
- PT1D, 1,
- PT2D, 1,
- PT3D, 1,
- PT4D, 1,
- PT5D, 1,
- PT6D, 1,
- PT7D, 1,
- PT8D, 1,
- PT9D, 1,
- Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
- SBIE, 1,
- SBME, 1,
- Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
- SBRI, 8,
- Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
- SBB1, 32,
- Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
- ,14,
- P92E, 1, /* Port92 decode enable */
- }
-
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
- Field(SB5, AnyAcc, NoLock, Preserve)
- {
- /* Port 0 */
- Offset(0x120), /* Port 0 Task file status */
- P0ER, 1,
- , 2,
- P0DQ, 1,
- , 3,
- P0BY, 1,
- Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
- , 4,
- P0IS, 4,
- Offset(0x12C), /* Port 0 Serial ATA control */
- P0DI, 4,
- Offset(0x130), /* Port 0 Serial ATA error */
- , 16,
- P0PR, 1,
-
- /* Port 1 */
- offset(0x1A0), /* Port 1 Task file status */
- P1ER, 1,
- , 2,
- P1DQ, 1,
- , 3,
- P1BY, 1,
- Offset(0x1A8), /* Port 1 Serial ATA status */
- P1DD, 4,
- , 4,
- P1IS, 4,
- Offset(0x1AC), /* Port 1 Serial ATA control */
- P1DI, 4,
- Offset(0x1B0), /* Port 1 Serial ATA error */
- , 16,
- P1PR, 1,
-
- /* Port 2 */
- Offset(0x220), /* Port 2 Task file status */
- P2ER, 1,
- , 2,
- P2DQ, 1,
- , 3,
- P2BY, 1,
- Offset(0x228), /* Port 2 Serial ATA status */
- P2DD, 4,
- , 4,
- P2IS, 4,
- Offset(0x22C), /* Port 2 Serial ATA control */
- P2DI, 4,
- Offset(0x230), /* Port 2 Serial ATA error */
- , 16,
- P2PR, 1,
-
- /* Port 3 */
- Offset(0x2A0), /* Port 3 Task file status */
- P3ER, 1,
- , 2,
- P3DQ, 1,
- , 3,
- P3BY, 1,
- Offset(0x2A8), /* Port 3 Serial ATA status */
- P3DD, 4,
- , 4,
- P3IS, 4,
- Offset(0x2AC), /* Port 3 Serial ATA control */
- P3DI, 4,
- Offset(0x2B0), /* Port 3 Serial ATA error */
- , 16,
- P3PR, 1,
- }
- }
-
- #include "acpi/routing.asl"
-
- Scope(\_SB) {
-
- Method(OSFL, 0){
-
- if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
-
- if(CondRefOf(\_OSI))
- {
- Store(1, OSVR) /* Assume some form of XP */
- if (\_OSI("Windows 2006")) /* Vista */
- {
- Store(2, OSVR)
- }
- } else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSVR) /* Linux */
- } Else {
- Store(4, OSVR) /* Gotta be WinCE */
- }
- }
- Return(OSVR)
- }
-
- Method(_PIC, 0x01, NotSerialized)
- {
- If (Arg0)
- {
- \_SB.CIRQ()
- }
- Store(Arg0, PMOD)
- }
-
- Method(CIRQ, 0x00, NotSerialized)
- {
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTA._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTE._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_PRS\n") */
- Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
- } /* End Scope(_SB) */
-
- #include <southbridge/amd/common/acpi/sleepstates.asl>
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- \_SB.PCI0.SIOS (Arg0)
- } /* End Method(\_PTS) */
-
- /*
- * The following method results in a "not a valid reserved NameSeg"
- * warning so I have commented it out for the duration. It isn't
- * used, so it could be removed.
- *
- *
- * \_GTS OEM Going To Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- *
- * Method(\_GTS, 1) {
- * DBGO("\\_GTS\n")
- * DBGO("From S0 to S")
- * DBGO(Arg0)
- * DBGO("\n")
- * }
- */
-
- /*
- * \_BFS OEM Back From Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- */
- Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
- }
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- Store(1,HPDE)
-
- /* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, Local1)
- Store(Local1, PWST)
-
- /* if(DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
- * } else {
- * Store(Arg0, Index(WKST,1))
- * }
- */
- \_SB.PCI0.SIOW ()
- Return(WKST)
- } /* End Method(\_WAK) */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* General event 0 */
- /* Method(_L00) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 1 */
- /* Method(_L01) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 2 */
- /* Method(_L02) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 3 */
- //Method(_L03) {
- // /* DBGO("\\_GPE\\_L00\n") */
- // Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- //}
-
- /* General event 4 */
- /* Method(_L04) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 5 */
- /* Method(_L05) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 6 - Used for GPM6, moved to USB.asl */
- /* Method(_L06) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 7 - Used for GPM7, moved to USB.asl */
- /* Method(_L07) {
- * DBGO("\\_GPE\\_L07\n")
- * }
- */
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
- }
-
- /* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
-
- /* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
-
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
-
- /* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
-
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event - Moved to USB.asl */
- /* Method(_L1A) {
- * DBGO("\\_GPE\\_L1A\n")
- * }
- */
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
-
- /* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
-
- /* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
-
- /* SATA SCI event - Moved to sata.asl */
- /* Method(_L1F) {
- * DBGO("\\_GPE\\_L1F\n")
- * }
- */
-
- } /* End Scope GPE */
-
- #include "acpi/usb.asl"
-
- /* System Bus */
- Scope(\_SB) { /* Start \_SB scope */
- #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0) {
- External (TOM1)
- External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* Dev3 is also an external GFX bridge, not used in Herring */
-
- Device(PBR4) {
- Name(_ADR, 0x00040000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR4 */
-
- Device(PBR5) {
- Name(_ADR, 0x00050000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR5 */
-
- Device(PBR6) {
- Name(_ADR, 0x00060000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR6 */
-
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR7 */
-
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
-
- /* Describe the Southbridge devices */
- Device(STCR) {
- Name(_ADR, 0x00120000)
- #include "acpi/sata.asl"
- } /* end STCR */
-
- Device(UOH1) {
- Name(_ADR, 0x00130000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH1 */
-
- Device(UOH2) {
- Name(_ADR, 0x00130001)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH2 */
-
- Device(UOH3) {
- Name(_ADR, 0x00130002)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH3 */
-
- Device(UOH4) {
- Name(_ADR, 0x00130003)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH4 */
-
- Device(UOH5) {
- Name(_ADR, 0x00130004)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UEH1) {
- Name(_ADR, 0x00130005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(SBUS) {
- Name(_ADR, 0x00140000)
- } /* end SBUS */
-
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "acpi/ide.asl"
- } /* end IDEC */
-
- Device(AZHD) {
- Name(_ADR, 0x00140002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6C),
- MMDT, 16,
- }
-
- Method(_INI) {
- If(LEqual(OSVR,3)){ /* If we are running Linux */
- Store(zero, NSEN)
- Store(one, NSDO)
- Store(one, NSDI)
- }
- }
- } /* end AZHD */
-
- Device(LIBR) {
- Name(_ADR, 0x00140003)
- /* Method(_INI) {
- * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
- } */ /* End Method(_SB.SBRDG._INI) */
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){8}
- IO(Decode16,0x0070, 0x0070, 0, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){0}
- IO(Decode16, 0x0040, 0x0040, 0, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 0, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){2}
- IO(Decode16,0x0020, 0x0020, 0, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,BusMaster,Transfer8){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
- IRQNoFlags(){13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPTM) { /* HPET */
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* HPET is visible */
- }
- Method(_CRS, 0) {
- Return(CRS)
- }
- } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
- } /* end LIBR */
-
- Device(HPBR) {
- Name(_ADR, 0x00140004)
- } /* end HostPciBr */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- } /* end Ac97modem */
-
- /* ITE IT8712F Support */
- OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
- Field (IOID, ByteAcc, NoLock, Preserve)
- {
- SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
- }
-
- IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
- {
- Offset (0x07),
- LDN, 8, /* Logical Device Number */
- Offset (0x20),
- CID1, 8, /* Chip ID Byte 1, 0x87 */
- CID2, 8, /* Chip ID Byte 2, 0x12 */
- Offset (0x30),
- ACTR, 8, /* Function activate */
- Offset (0xF0),
- APC0, 8, /* APC/PME Event Enable Register */
- APC1, 8, /* APC/PME Status Register */
- APC2, 8, /* APC/PME Control Register 1 */
- APC3, 8, /* Environment Controller Special Configuration Register */
- APC4, 8 /* APC/PME Control Register 2 */
- }
-
- /* Enter the IT8712F MB PnP Mode */
- Method (EPNP)
- {
- Store(0x87, SIOI)
- Store(0x01, SIOI)
- Store(0x55, SIOI)
- Store(0x55, SIOI) /* IT8712F magic number */
- }
- /* Exit the IT8712F MB PnP Mode */
- Method (XPNP)
- {
- Store (0x02, SIOI)
- Store (0x02, SIOD)
- }
-
- /*
- * Keyboard PME is routed to SB600 Gevent3. We can wake
- * up the system by pressing the key.
- */
- Method (SIOS, 1)
- {
- /* We only enable KBD PME for S5. */
- If (LLess (Arg0, 0x05))
- {
- EPNP()
- /* DBGO("IT8712F\n") */
-
- Store (0x4, LDN)
- Store (One, ACTR) /* Enable EC */
- /*
- Store (0x4, LDN)
- Store (0x04, APC4)
- */ /* falling edge. which mode? Not sure. */
-
- Store (0x4, LDN)
- Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
- Store (0x4, LDN)
- Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
- XPNP()
- }
- }
- Method (SIOW, 0)
- {
- EPNP()
- Store (0x4, LDN)
- Store (Zero, APC0) /* disable keyboard PME */
- Store (0x4, LDN)
- Store (0xFF, APC1) /* clear keyboard PME status */
- XPNP()
- }
-
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
-
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
- }
-
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * ShiftLeft(TOM2, 20, Local0)
- * Subtract(Local0, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-
- Return(CRES) /* note to change the Name buffer */
- } /* end of Method(_SB.PCI0._CRS) */
-
- /*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
- Method(_INI, 0) {
- /* DBGO("\\_SB\\_INI\n") */
- /* DBGO(" DSDT.ASL code from ") */
- /* DBGO(__DATE__) */
- /* DBGO(" ") */
- /* DBGO(__TIME__) */
- /* DBGO("\n Sleep states supported: ") */
- /* DBGO("\n") */
- /* DBGO(" \\_OS=") */
- /* DBGO(\_OS) */
- /* DBGO("\n \\_REV=") */
- /* DBGO(\_REV) */
- /* DBGO("\n") */
-
- /* Determine the OS we're running on */
- OSFL()
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
- * }
- */
- } /* End Method(_SB._INI) */
- } /* End Device(PCI0) */
-
- Device(PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- //Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
- } /* End \_SB scope */
-
- Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
- } /* End Scope SI */
-
- #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
-
- /* THERMAL */
- Scope(\_TZ) {
- Name (KELV, 2732)
- Name (THOT, 800)
- Name (TCRT, 850)
-
- ThermalZone(TZ00) {
- Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
- /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
- Return(Add(0, 2730))
- }
- Method(_AL0,0) { /* Returns package of cooling device to turn on */
- /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
- Return(Package() {\_TZ.TZ00.FAN0})
- }
- Device (FAN0) {
- Name(_HID, EISAID("PNP0C0B"))
- Name(_PR0, Package() {PFN0})
- }
-
- PowerResource(PFN0,0,0) {
- Method(_STA) {
- Store(0xF,Local0)
- Return(Local0)
- }
- Method(_ON) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
- }
- Method(_OFF) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
- }
- }
-
- Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
- Return (Add (THOT, KELV))
- }
- Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
- Return (Add (TCRT, KELV))
- }
- Method(_TMP,0) { /* return current temp of this zone */
- Store (SMBR (0x07, 0x4C,, 0x00), Local0)
- If (LGreater (Local0, 0x10)) {
- Store (Local0, Local1)
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400, KELV))
- }
-
- Store (SMBR (0x07, 0x4C, 0x01), Local0)
- /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
- /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
- If (LGreater (Local0, 0x10)) {
- If (LGreater (Local0, Local1)) {
- Store (Local0, Local1)
- }
-
- Multiply (Local1, 10, Local1)
- Return (Add (Local1, KELV))
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400 , KELV))
- }
- } /* end of _TMP */
- } /* end of TZ00 */
- }
-}
-/* End of ASL file */
diff --git a/src/mainboard/technexion/tim5690/fadt.c b/src/mainboard/technexion/tim5690/fadt.c
deleted file mode 100644
index b397f52aea..0000000000
--- a/src/mainboard/technexion/tim5690/fadt.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include "southbridge/amd/sb600/sb600.h"
-
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb ACPI */
-/* pm_base should be got from bar2 of rs690. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
-
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
- /* Prepare the header */
- memset((void *)fadt, 0, sizeof(acpi_fadt_t));
- memcpy(header->signature, "FACP", 4);
- header->length = 244;
- header->revision = 3;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->asl_compiler_revision = 0;
-
- fadt->firmware_ctrl = (u32) facs;
- fadt->dsdt = (u32) dsdt;
- /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
- fadt->preferred_pm_profile = 0x03;
- fadt->sci_int = 9;
- /* disable system management mode by setting to 0: */
- fadt->smi_cmd = 0;
- fadt->acpi_enable = 0xf0;
- fadt->acpi_disable = 0xf1;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0xe2;
-
- pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
-
- /* CpuControl is in \_PR.CP00, 6 bytes */
- pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
-
- pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
-
- pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
-
- pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 20-2B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
- pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
-
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
- fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
- fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
- fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
-
- fadt->cst_cnt = 0xe3;
- fadt->p_lvl2_lat = 101;
- fadt->p_lvl3_lat = 1001;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 1;
- fadt->duty_width = 3;
- fadt->day_alrm = 0; /* 0x7d these have to be */
- fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
- fadt->century = 0; /* 0x7f to make rtc alrm work */
- fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
- fadt->flags = 0x0001c1a5;/* 0x25; */
-
- fadt->res2 = 0;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 6;
- fadt->x_firmware_ctl_l = (u32) facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32) dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 4;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 2;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 32;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/technexion/tim5690/get_bus_conf.c b/src/mainboard/technexion/tim5690/get_bus_conf.c
deleted file mode 100644
index b1b7270802..0000000000
--- a/src/mainboard/technexion/tim5690/get_bus_conf.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_rs690[8];
-u8 bus_sb600[2];
-u32 apicid_sb600;
-
-/*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
-u32 pci1234x[] = {
- 0x0000ff0,
-};
-
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
- 0x20202020,
-};
-
-u32 sbdn_rs690;
-u32 sbdn_sb600;
-
-
-
-static u32 get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- u32 apicid_base;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* do it only once */
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
- sbdn_rs690 = sysconf.sbdn;
- sbdn_sb600 = 0;
-
- for (i = 0; i < 2; i++) {
- bus_sb600[i] = 0;
- }
- for (i = 0; i < 8; i++) {
- bus_rs690[i] = 0;
- }
-
- bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_sb600[0] = bus_rs690[0];
-
- /* sb600 */
- dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
- if (dev) {
- bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- /* rs690 */
- for (i = 1; i < 8; i++) {
- dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
- if (dev) {
- bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
- /* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_sb600 = apicid_base + 0;
-}
diff --git a/src/mainboard/technexion/tim5690/irq_tables.c b/src/mainboard/technexion/tim5690/irq_tables.c
deleted file mode 100644
index 4c2a48dff7..0000000000
--- a/src/mainboard/technexion/tim5690/irq_tables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern u8 bus_rs690[8];
-extern u8 bus_sb600[2];
-extern unsigned long sbdn_sb600;
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_sb600[0];
- pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c
deleted file mode 100644
index 12050f07fa..0000000000
--- a/src/mainboard/technexion/tim5690/mainboard.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb600/sb600.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include "tn_post_code.h"
-#include "vgabios.h"
-
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS 0x0C /* Alert Response Address */
-#define SMBUS_IO_BASE 0x1000
-
-
-/* Video BIOS Function Extensions Specification
- */
-//Callback Sub-Function 00h - Get LCD Panel ID
-#define LCD_PANEL_ID_NO 0x00 /* No LCD */
-#define LCD_PANEL_ID_01 0x01 /* 1024x768, 24 bits, 1 channel */
-#define LCD_PANEL_ID_02 0x02 /* 1280x1024, 24 bits, 2 channels */
-#define LCD_PANEL_ID_03 0x03 /* 1440x900, 24 bits, 2 channels */
-#define LCD_PANEL_ID_04 0x04 /* 1680x1050, 24 bits, 2 channels */
-#define LCD_PANEL_ID_05 0x05 /* 1920x1200, 24 bits, 2 channels */
-#define LCD_PANEL_ID_06 0x06 /* 1920x1080, 24 bits, 2 channels */
-//Callback Sub-Function 05h - Select Boot-up TV Standard
-#define TV_MODE_00 0x00 /* NTSC */
-#define TV_MODE_01 0x01 /* PAL */
-#define TV_MODE_02 0x02 /* PALM */
-#define TV_MODE_03 0x03 /* PAL60 */
-#define TV_MODE_04 0x04 /* NTSCJ */
-#define TV_MODE_05 0x05 /* PALCN */
-#define TV_MODE_06 0x06 /* PALN */
-#define TV_MODE_09 0x09 /* SCART-RGB */
-#define TV_MODE_NO 0xff /* No TV Support */
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE 0x2e
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA SIO_BASE+1
-
-/* Global configuration registers. */
-#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
-#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
-#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
-#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
-#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
-#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
-
-#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */
-#define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */
-
-int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
-#define ADT7461_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
- do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-
-
-/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
- LDN the register belongs to, before you can access the register. */
-static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
-{
- outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
-}
-
-static void it8712f_enter_conf(void)
-{
- /* Enter the configuration state (MB PnP mode). */
-
- /* Perform MB PnP setup to put the SIO chip at 0x2e. */
- /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
- /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
- outb(0x87, IT8712F_CONFIGURATION_PORT);
- outb(0x01, IT8712F_CONFIGURATION_PORT);
- outb(0x55, IT8712F_CONFIGURATION_PORT);
- outb(0x55, IT8712F_CONFIGURATION_PORT);
-}
-
-static void it8712f_exit_conf(void)
-{
- /* Exit the configuration state (MB PnP mode). */
- it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
-}
-
-/* set thermal config
- */
-static void set_thermal_config(void)
-{
- u8 byte;
- u16 word;
- struct device *sm_dev;
-
- /* set ADT 7461 */
- ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
- ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
- ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
- ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
-
- ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
- ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
-
- byte = ADT7461_read_byte(0x02); /* read status register to clear it */
- ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
- printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
-
- /* sb600 settings for thermal config */
- /* set SB600 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to input */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
-}
-
-/* Mainboard specific GPIO setup. */
-static void mb_gpio_init(u16 *iobase)
-{
- /* Init Super I/O GPIOs. */
- it8712f_enter_conf();
- outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX);
- outb(IT8712F_GPIO, SIO_DATA);
- outb(0x62, SIO_INDEX);
- outb((*iobase >> 8), SIO_DATA);
- outb(0x63, SIO_INDEX);
- outb((*iobase & 0xff), SIO_DATA);
- it8712f_exit_conf();
-}
-
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
-/* The LCD's panel id seletion. */
-static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
-{
- switch (num_id) {
- case 0x1:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_01;
- break;
- case 0x2:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_02;
- break;
- case 0x3:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_03;
- break;
- case 0x4:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_04;
- break;
- case 0x5:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_05;
- break;
- case 0x6:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_06;
- break;
- default:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_NO;
- break;
- }
-}
-#endif
-
-/*************************************************
-* enable the dedicated function in tim5690 board.
-* This function called early than rs690_enable.
-*************************************************/
-static void mainboard_enable(struct device *dev)
-{
- u16 gpio_base = IT8712F_SIMPLE_IO_BASE;
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
- rs690_vbios_regs vbios_regs;
- u8 port2;
-#endif
-
- printk(BIOS_INFO, "Mainboard tim5690 Enable. dev=0x%p\n", dev);
-
- mb_gpio_init(&gpio_base);
-
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
- /* The LCD's panel id seletion by switch. */
- port2 = inb(gpio_base+1);
- lcd_panel_id(&vbios_regs, ((~port2) & 0xf));
-
- /* No support TV */
- vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO;
- vgabios_init(&vbios_regs);
-#endif
-
- set_thermal_config();
-}
-
-void mainboard_post(u8 value)
-{
- switch (value) {
- case POST_ENTER_ELF_BOOT:
- technexion_post_code(LED_MESSAGE_FINISH);
- break;
- }
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c
deleted file mode 100644
index 9515931627..0000000000
--- a/src/mainboard/technexion/tim5690/mptable.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern u8 bus_rs690[8];
-extern u8 bus_sb600[2];
-
-extern u32 apicid_sb600;
-
-extern u32 sbdn_rs690;
-extern u32 sbdn_sb600;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- u32 dword;
- u8 byte;
-
- dev =
- dev_find_slot(bus_sb600[0],
- PCI_DEVFN(sbdn_sb600 + 0x14, 0));
- if (dev) {
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600,
- 0x11,(void *) dword);
-
- /* Initialize interrupt mapping */
- /* aza */
- byte = pci_read_config8(dev, 0x63);
- byte &= 0xf8;
- byte |= 0; /* 0: INTA, ...., 7: INTH */
- pci_write_config8(dev, 0x63, byte);
-
- /* SATA */
- dword = pci_read_config32(dev, 0xac);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
- /* dword |= 1 << 22; PIC and APIC co exists */
- pci_write_config32(dev, 0xac, dword);
-
- /*
- * 00:12.0: PROG SATA : INT F
- * 00:13.0: INTA USB_0
- * 00:13.1: INTB USB_1
- * 00:13.2: INTC USB_2
- * 00:13.3: INTD USB_3
- * 00:13.4: INTC USB_4
- * 00:13.5: INTD USB2
- * 00:14.1: INTA IDE
- * 00:14.2: Prog HDA : INT E
- * 00:14.5: INTB ACI
- * 00:14.6: INTB MCI
- */
- }
- }
-
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/technexion/tim5690/resourcemap.c b/src/mainboard/technexion/tim5690/resourcemap.c
deleted file mode 100644
index a513616703..0000000000
--- a/src/mainboard/technexion/tim5690/resourcemap.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_tim5690_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
deleted file mode 100644
index e3f40d1166..0000000000
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <spd.h>
-#include <cpu/x86/lapic.h>
-
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/early_setup.c"
-#include "southbridge/amd/sb600/early_setup.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(u32 device, u32 address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "tn_post_code.c"
-#include "speaker.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
- int needs_reset = 0;
- u32 bsp_apicid = 0;
- msr_t msr;
- struct cpuid_result cpuid1;
- struct sys_info *sysinfo = &sysinfo_car;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- /* sb600_lpc_port80(); */
- sb600_pci_port80();
- }
-
- technexion_post_code_init();
- technexion_post_code(LED_MESSAGE_START);
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- enable_rs690_dev8();
- sb600_lpc_init();
-
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- ite_kill_watchdog(GPIO_DEV);
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
- printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
-
- setup_tim5690_resource_map();
-
- setup_coherent_ht_domain();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched */
- wait_all_core0_started();
- start_other_cores();
-#endif
- wait_all_aps_started(bsp_apicid);
-
- ht_setup_chains_x(sysinfo);
-
- /* run _early_setup before soft-reset. */
- rs690_early_setup();
- sb600_early_setup();
-
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- cpuid1 = cpuid(0x80000007);
- if ((cpuid1.edx & 0x6) == 0x6) {
- /* Read FIDVID_STATUS */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
-
- /* show final fid and vid */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
- } else {
- printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
- }
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- rs690_htinit();
- printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
-
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- speaker_init(255);
- speaker_on_nodelay();
-
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now; */
- printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
- sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- technexion_post_code(LED_MESSAGE_RAM);
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
- speaker_off_nodelay();
-
- rs690_before_pci_init();
- sb600_before_pci_init();
-}
diff --git a/src/mainboard/technexion/tim5690/speaker.c b/src/mainboard/technexion/tim5690/speaker.c
deleted file mode 100644
index 7c0ea6492b..0000000000
--- a/src/mainboard/technexion/tim5690/speaker.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Libra Li <libra.li@technexion.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#ifdef __PRE_RAM__
-
-#include <arch/cpu.h>
-#include "southbridge/amd/sb600/sb600.h"
-
-#else
-
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "southbridge/amd/sb600/sb600.h"
-#include <delay.h>
-
-#endif /* __PRE_RAM__ */
-
-#include "speaker.h"
-
-void speaker_init(uint8_t time) {
- /* SB600 RRG.
- * Options_0 - RW - 8 bits - [PM_Reg: 60h].
- * SpkrEn, bit[5]=1b, Setting this bit will configure GPIO2 to be speaker output.
- */
-#ifdef __PRE_RAM__
- pmio_write(0x60, (pmio_read(0x60) | (1<<5)));
-#else
- pm_iowrite(0x60, (pm_ioread(0x60) | (1<<5)));
-#endif /* __PRE_RAM__ */
-
- /* SB600 RRG.
- * Tmr1CntrlWord - RW - 8 bits - [IO_Reg: 43h].
- * ModeSelect, bit[3:1]=011b, Square wave output.
- * CmmandSelect, bit[5:4]=11b, Read/write least, and then most significant byte.
- * CounterSelect, bit[7:6]=10b, Select counter 2.
- */
- outb(0xb6, 0x43);
-
-
- /* SB600 RRG.
- * TimerCh2- RW - 8 bits - [IO_Reg: 42h].
- */
- outb(time, 0x42);
-}
-
-void speaker_on_nodelay(void) {
- /* SB600 RRG.
- * Nmi_Status - RW - 8 bits - [IO_Reg: 61h].
- * SpkrEnable, bit[0]=1b, Enable counter 2
- * SpkrTmrEnable, bit[1]=1b, Speaker timer on
- */
- outb(inb(0x61) | 0x03, 0x61);
-}
-
-void speaker_on_delay(void) {
- speaker_on_nodelay();
- mdelay(100);
-}
-
-void speaker_off_nodelay(void) {
- /* SB600 RRG.
- * Nmi_Status - RW - 8 bits - [IO_Reg: 61h].
- * SpkrEnable, bit[0]=0b, Disable counter 2
- * SpkrTmrEnable, bit[1]=0b, Speaker timer off
- */
- outb(inb(0x61) & ~0x03, 0x61);
-}
-
-void speaker_off_delay(void) {
- speaker_off_nodelay();
- mdelay(100);
-}
diff --git a/src/mainboard/technexion/tim5690/speaker.h b/src/mainboard/technexion/tim5690/speaker.h
deleted file mode 100644
index bb544b0bce..0000000000
--- a/src/mainboard/technexion/tim5690/speaker.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Libra Li <libra.li@technexion.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-void speaker_init(uint8_t time);
-void speaker_on_nodelay(void);
-void speaker_off_nodelay(void);
-void speaker_on_delay(void);
-void speaker_off_delay(void);
diff --git a/src/mainboard/technexion/tim5690/tn_post_code.c b/src/mainboard/technexion/tim5690/tn_post_code.c
deleted file mode 100644
index 607c44664a..0000000000
--- a/src/mainboard/technexion/tim5690/tn_post_code.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Libra Li <libra.li@technexion.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#ifdef __PRE_RAM__
-
-#include <arch/cpu.h>
-#include "southbridge/amd/sb600/sb600.h"
-
-#else
-
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-#endif
-
-#include "tn_post_code.h"
-
-
-#ifdef __SIMPLE_DEVICE__
-
-// TechNexion's Post Code Initially.
-void technexion_post_code_init(void)
-{
- uint8_t reg8_data;
- pci_devfn_t dev = 0;
-
- // SMBus Module and ACPI Block (Device 20, Function 0)
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0);
-
- // LED[bit0]:GPIO0
- // This is reference SB600 RRG 4.1.1 GPIO
- reg8_data = pmio_read(0x60);
- reg8_data |= (1 << 7); // 1: GPIO if not used by SATA
- pmio_write(0x60, reg8_data);
-
- reg8_data = pci_read_config8(dev, 0x80);
- reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 4));
- pci_write_config8(dev, 0x80, reg8_data);
-
- // LED[bit1]:GPIO1
- // This is reference SB600 RRG 4.1.1 GPIO
- reg8_data = pci_read_config8(dev, 0x80);
- reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5));
- pci_write_config8(dev, 0x80, reg8_data);
-
- // LED[bit2]:GPIO4
- // This is reference SB600 RRG 4.1.1 GPIO
- reg8_data = pmio_read(0x5e);
- reg8_data &= ~(1 << 7); // 0: GPIO if not used by SATA
- pmio_write(0x5e, reg8_data);
-
- reg8_data = pci_read_config8(dev, 0xa8);
- reg8_data |= (1 << 0);
- pci_write_config8(dev, 0xa8, reg8_data);
-
- reg8_data = pci_read_config8(dev, 0xa9);
- reg8_data &= ~(1 << 0);
- pci_write_config8(dev, 0xa9, reg8_data);
-
- // LED[bit3]:GPIO6
- // This is reference SB600 RRG 4.1.1 GPIO
- reg8_data = pmio_read(0x60);
- reg8_data |= (1 << 7); // 1: GPIO if not used by SATA
- pmio_write(0x60, reg8_data);
-
- reg8_data = pci_read_config8(dev, 0xa8);
- reg8_data |= (1 << 2);
- pci_write_config8(dev, 0xa8, reg8_data);
-
- reg8_data = pci_read_config8(dev, 0xa9);
- reg8_data &= ~(1 << 2);
- pci_write_config8(dev, 0xa9, reg8_data);
- // LED[bit4]:GPIO7
- // This is reference SB600 RRG 4.1.1 GPIO
- reg8_data = pci_read_config8(dev, 0xa8);
- reg8_data |= (1 << 3);
- pci_write_config8(dev, 0xa8, reg8_data);
-
- reg8_data = pci_read_config8(dev, 0xa9);
- reg8_data &= ~(1 << 3);
- pci_write_config8(dev, 0xa9, reg8_data);
-
- // LED[bit5]:GPIO8
- // This is reference SB600 RRG 4.1.1 GPIO
- reg8_data = pci_read_config8(dev, 0xa8);
- reg8_data |= (1 << 4);
- pci_write_config8(dev, 0xa8, reg8_data);
-
- reg8_data = pci_read_config8(dev, 0xa9);
- reg8_data &= ~(1 << 4);
- pci_write_config8(dev, 0xa9, reg8_data);
-
- // LED[bit6]:GPIO10
- // This is reference SB600 RRG 4.1.1 GPIO
- reg8_data = pci_read_config8(dev, 0xab);
- reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 1));
- pci_write_config8(dev, 0xab, reg8_data);
-
- // LED[bit7]:GPIO66
- // This is reference SB600 RRG 4.1.1 GPIO
- reg8_data = pmio_read(0x68);
- reg8_data &= ~(1 << 5); // 0: GPIO
- pmio_write(0x68, reg8_data);
-
- reg8_data = pci_read_config8(dev, 0x7e);
- reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5));
- pci_write_config8(dev, 0x7e, reg8_data);
-
-}
-
-#endif
-
-/* TechNexion's Post Code.
- */
-void technexion_post_code(uint8_t udata8)
-{
- uint8_t u8_data;
-
- // SMBus Module and ACPI Block (Device 20, Function 0)
-#ifdef __SIMPLE_DEVICE__
- pci_devfn_t dev = 0;
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0);
-#else
- struct device *dev = NULL;
- dev = dev_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM, 0);
-#endif
-
- udata8 = ~(udata8);
-
- // LED[bit0]:GPIO0
- u8_data = pci_read_config8(dev, 0x80);
- if (udata8 & 0x1) {
- u8_data |= (1 << 0);
- }
- else {
- u8_data &= ~(1 << 0);
- }
- pci_write_config8(dev, 0x80, u8_data);
-
- // LED[bit1]:GPIO1
- u8_data = pci_read_config8(dev, 0x80);
- if (udata8 & 0x2) {
- u8_data |= (1 << 1);
- }
- else {
- u8_data &= ~(1 << 1);
- }
- pci_write_config8(dev, 0x80, u8_data);
-
- // LED[bit2]:GPIO4
- u8_data = pci_read_config8(dev, 0xa8);
- if (udata8 & 0x4) {
- u8_data |= (1 << 0);
- }
- else {
- u8_data &= ~(1 << 0);
- }
- pci_write_config8(dev, 0xa8, u8_data);
-
- // LED[bit3]:GPIO6
- u8_data = pci_read_config8(dev, 0xa8);
- if (udata8 & 0x8) {
- u8_data |= (1 << 2);
- }
- else {
- u8_data &= ~(1 << 2);
- }
- pci_write_config8(dev, 0xa8, u8_data);
-
- // LED[bit4]:GPIO7
- u8_data = pci_read_config8(dev, 0xa8);
- if (udata8 & 0x10) {
- u8_data |= (1 << 3);
- }
- else {
- u8_data &= ~(1 << 3);
- }
- pci_write_config8(dev, 0xa8, u8_data);
-
- // LED[bit5]:GPIO8
- u8_data = pci_read_config8(dev, 0xa8);
- if (udata8 & 0x20) {
- u8_data |= (1 << 4);
- }
- else {
- u8_data &= ~(1 << 4);
- }
- pci_write_config8(dev, 0xa8, u8_data);
-
- // LED[bit6]:GPIO10
- u8_data = pci_read_config8(dev, 0xab);
- if (udata8 & 0x40) {
- u8_data |= (1 << 0);
- }
- else {
- u8_data &= ~(1 << 0);
- }
- pci_write_config8(dev, 0xab, u8_data);
-
- // LED[bit7]:GPIO66
- u8_data = pci_read_config8(dev, 0x7e);
- if (udata8 & 0x80) {
- u8_data |= (1 << 1);
- }
- else {
- u8_data &= ~(1 << 1);
- }
- pci_write_config8(dev, 0x7e, u8_data);
-
-}
diff --git a/src/mainboard/technexion/tim5690/tn_post_code.h b/src/mainboard/technexion/tim5690/tn_post_code.h
deleted file mode 100644
index e969ea83cc..0000000000
--- a/src/mainboard/technexion/tim5690/tn_post_code.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Libra Li <libra.li@technexion.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define LED_MESSAGE_START 0xFF
-#define LED_MESSAGE_FINISH 0x99
-#define LED_MESSAGE_RAM 0x01
-
-
-#ifdef __PRE_RAM__
-
-// TechNexion's Post Code Initially.
-void technexion_post_code_init(void);
-
-#endif
-
-void technexion_post_code(uint8_t udata8);
diff --git a/src/mainboard/technexion/tim5690/vgabios.c b/src/mainboard/technexion/tim5690/vgabios.c
deleted file mode 100644
index fe4b41cde9..0000000000
--- a/src/mainboard/technexion/tim5690/vgabios.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2009 Libra Li <libra.li@technexion.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <console/console.h>
-#include <arch/interrupt.h>
-#include "vgabios.h"
-#include <x86emu/regs.h>
-
-
-int tim5690_int15_handler(void);
-
-static rs690_vbios_regs vbios_regs_local;
-
-/* Initialization interrupt function */
-static void vbios_fun_init(rs690_vbios_regs *vbios_regs)
-{
- vbios_regs_local.int15_regs.fun00_panel_id = vbios_regs->int15_regs.fun00_panel_id;
- vbios_regs_local.int15_regs.fun05_tv_standard = vbios_regs->int15_regs.fun05_tv_standard;
-}
-
-/* BIOS int15 function */
-int tim5690_int15_handler(void)
-{
- int res = 0;
-
- printk(BIOS_DEBUG, "tim5690_int15_handler\n");
-
- switch (X86_EAX & 0xffff) {
- case AMD_RS690_INT15:
- switch (X86_EBX & 0xff) {
- case 0x00:
- X86_EAX &= ~(0xff);
- X86_EBX = (X86_EBX & ~(0xff)) | vbios_regs_local.int15_regs.fun00_panel_id;
- res = 1;
- break;
- case 0x05:
- X86_EAX &= ~(0xff);
- X86_EBX = (X86_EBX & ~(0xff)) | vbios_regs_local.int15_regs.fun05_tv_standard;
- res = 1;
- break;
- }
- break;
- default:
- printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
- X86_EAX & 0xffff);
- break;
- }
-
- return res;
-}
-
-/* Initialization VBIOS function */
-void vgabios_init(rs690_vbios_regs *vbios_regs)
-{
- printk(BIOS_DEBUG, "vgabios_init\n");
-
- mainboard_interrupt_handlers(0x15, &tim5690_int15_handler);
- vbios_fun_init(vbios_regs);
-}
diff --git a/src/mainboard/technexion/tim5690/vgabios.h b/src/mainboard/technexion/tim5690/vgabios.h
deleted file mode 100644
index f6ad63e7a5..0000000000
--- a/src/mainboard/technexion/tim5690/vgabios.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2009 Libra Li <libra.li@technexion.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* AMD Chipset */
-#define AMD_RS690_INT15 0x4E08
-
-typedef struct __rs690_int15_regs__
-{
- u8 fun00_panel_id; // Callback Sub-Function 00h - Get LCD Panel ID
- u8 fun05_tv_standard; // Callback Sub-Function 05h - Select Boot-up TV Standard
-}rs690_int15_regs;
-
-typedef struct __rs690_vbios_regs__
-{
- rs690_int15_regs int15_regs;
-}rs690_vbios_regs;
-
-/* Initialization VBIOS function */
-extern void vgabios_init(rs690_vbios_regs *vbios_regs);
diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig
deleted file mode 100644
index ad80e853c3..0000000000
--- a/src/mainboard/technexion/tim8690/Kconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-if BOARD_TECHNEXION_TIM8690
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_S1G1
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_RS690
- select SOUTHBRIDGE_AMD_SB600
- select SUPERIO_ITE_IT8712F
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_512
- select QRANK_DIMM_SUPPORT
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default technexion/tim8690
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "TIM-8690"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_TECHNEXION_TIM8690
diff --git a/src/mainboard/technexion/tim8690/Kconfig.name b/src/mainboard/technexion/tim8690/Kconfig.name
deleted file mode 100644
index 6080e4e564..0000000000
--- a/src/mainboard/technexion/tim8690/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_TECHNEXION_TIM8690
- bool "TIM-8690"
diff --git a/src/mainboard/technexion/tim8690/acpi/ide.asl b/src/mainboard/technexion/tim8690/acpi/ide.asl
deleted file mode 100644
index d5badfcb6b..0000000000
--- a/src/mainboard/technexion/tim8690/acpi/ide.asl
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "ide.asl"
- }
- }
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
- 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
- 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
- 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
- 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
- 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
- Field(ICRG, AnyAcc, NoLock, Preserve)
-{
- PPTS, 8, /* Primary PIO Slave Timing */
- PPTM, 8, /* Primary PIO Master Timing */
- OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
- PMTM, 8, /* Primary MWDMA Master Timing */
- OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
- OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
- PPSM, 4, /* Primary PIO slave Mode */
- OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
- OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
- PDSM, 4, /* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
- Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
- Increment(Local0)
- Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
- Increment(Local1)
- Return(Multiply(30, Add(Local0, Local1)))
-}
-
-Device(PRID)
-{
- Name (_ADR, Zero)
- Method(_GTM, 0)
- {
- NAME(OTBF, Buffer(20) { /* out buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
- CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
- /* Just return if the channel is disabled */
- If(And(PPCR, 0x01)) { /* primary PIO control */
- Return(OTBF)
- }
-
- /* Always tell them independent timing available and IOChannelReady used on both drives */
- Or(BFFG, 0x1A, BFFG)
-
- Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
- Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
-
- If(And(PDCR, 0x01)) { /* It's under UDMA mode */
- Or(BFFG, 0x01, BFFG)
- Store(DerefOf(Index(UDTT, PDMM)), DSD0)
- }
- Else {
- Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
- }
-
- If(And(PDCR, 0x02)) { /* It's under UDMA mode */
- Or(BFFG, 0x04, BFFG)
- Store(DerefOf(Index(UDTT, PDSM)), DSD1)
- }
- Else {
- Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
- }
-
- Return(OTBF) /* out buffer */
- } /* End Method(_GTM) */
-
- Method(_STM, 3, NotSerialized)
- {
- NAME(INBF, Buffer(20) { /* in buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
- CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
- Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
- Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
- Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
- Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
-
- Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
- Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
-
- If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDMM,)
- Or(PDCR, 0x01, PDCR)
- }
- Else {
- If(LNotEqual(DSD0, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTM)
- }
- }
-
- If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDSM,)
- Or(PDCR, 0x02, PDCR)
- }
- Else {
- If(LNotEqual(DSD1, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTS)
- }
- }
- /* Return(INBF) */
- } /*End Method(_STM) */
- Device(MST)
- {
- Name(_ADR, 0)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xA0, CMDA)
- Store(0xA0, CMDB)
- Store(0xA0, CMDC)
-
- Or(PPMM, 0x08, POMD)
-
- If(And(PDCR, 0x01)) {
- Or(PDMM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTM),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(MST) */
-
- Device(SLAV)
- {
- Name(_ADR, 1)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xB0, CMDA)
- Store(0xB0, CMDB)
- Store(0xB0, CMDC)
-
- Or(PPSM, 0x08, POMD)
-
- If(And(PDCR, 0x02)) {
- Or(PDSM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTS),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(SLAV) */
-}
diff --git a/src/mainboard/technexion/tim8690/acpi/routing.asl b/src/mainboard/technexion/tim8690/acpi/routing.asl
deleted file mode 100644
index bcb14e7e37..0000000000
--- a/src/mainboard/technexion/tim8690/acpi/routing.asl
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "routing.asl"
- }
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
- Name(PR0, Package(){
- /* NB devices */
- /* Bus 0, Dev 0 - RS690 Host Controller */
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, INTC, 0 },
- Package(){0x0002FFFF, 1, INTD, 0 },
- Package(){0x0002FFFF, 2, INTA, 0 },
- Package(){0x0002FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, INTA, 0 },
- Package(){0x0004FFFF, 1, INTB, 0 },
- Package(){0x0004FFFF, 2, INTC, 0 },
- Package(){0x0004FFFF, 3, INTD, 0 },
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- /* Package(){0x0005FFFF, 0, INTB, 0 }, */
- /* Package(){0x0005FFFF, 1, INTC, 0 }, */
- /* Package(){0x0005FFFF, 2, INTD, 0 }, */
- /* Package(){0x0005FFFF, 3, INTA, 0 }, */
- /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
- Package(){0x0006FFFF, 0, INTC, 0 },
- Package(){0x0006FFFF, 1, INTD, 0 },
- Package(){0x0006FFFF, 2, INTA, 0 },
- Package(){0x0006FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
- Package(){0x0007FFFF, 0, INTD, 0 },
- Package(){0x0007FFFF, 1, INTA, 0 },
- Package(){0x0007FFFF, 2, INTB, 0 },
- Package(){0x0007FFFF, 3, INTC, 0 },
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0012FFFF, 1, INTA, 0 },
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){0x0013FFFF, 0, INTA, 0 },
- Package(){0x0013FFFF, 1, INTB, 0 },
- Package(){0x0013FFFF, 2, INTC, 0 },
- Package(){0x0013FFFF, 3, INTD, 0 },
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
- Package(){0x0014FFFF, 0, INTA, 0 },
- Package(){0x0014FFFF, 1, INTB, 0 },
- Package(){0x0014FFFF, 2, INTC, 0 },
- Package(){0x0014FFFF, 3, INTD, 0 },
- })
-
- Name(APR0, Package(){
- /* NB devices in APIC mode */
- /* Bus 0, Dev 0 - RS690 Host Controller */
-
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Package(){0x0001FFFF, 0, 0, 18 }, */
- /* Package(){0x0001FFFF, 1, 0, 19 }, */
-
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, 0, 18 },
- /* Package(){0x0002FFFF, 1, 0, 19 }, */
- /* Package(){0x0002FFFF, 2, 0, 16 }, */
- /* Package(){0x0002FFFF, 3, 0, 17 }, */
-
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){0x0003FFFF, 0, 0, 19 },
-
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, 0, 16 },
- /* Package(){0x0004FFFF, 1, 0, 17 }, */
- /* Package(){0x0004FFFF, 2, 0, 18 }, */
- /* Package(){0x0004FFFF, 3, 0, 19 }, */
-
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- Package(){0x0005FFFF, 0, 0, 17 },
- /* Package(){0x0005FFFF, 1, 0, 18 }, */
- /* Package(){0x0005FFFF, 2, 0, 19 }, */
- /* Package(){0x0005FFFF, 3, 0, 16 }, */
-
- /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
- Package(){0x0006FFFF, 0, 0, 18 },
- /* Package(){0x0006FFFF, 1, 0, 19 }, */
- /* Package(){0x0006FFFF, 2, 0, 16 }, */
- /* Package(){0x0006FFFF, 3, 0, 17 }, */
-
- /* Bus 0, Dev 7 - PCIe Bridge for network card */
- Package(){0x0007FFFF, 0, 0, 19 },
- /* Package(){0x0007FFFF, 1, 0, 16 }, */
- /* Package(){0x0007FFFF, 2, 0, 17 }, */
- /* Package(){0x0007FFFF, 3, 0, 18 }, */
-
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices in APIC mode */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0012FFFF, 0, 0, 22 },
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){0x0013FFFF, 0, 0, 16 },
- Package(){0x0013FFFF, 1, 0, 17 },
- Package(){0x0013FFFF, 2, 0, 18 },
- Package(){0x0013FFFF, 3, 0, 19 },
- /* Package(){0x00130004, 2, 0, 18 }, */
- /* Package(){0x00130005, 3, 0, 19 }, */
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
- Package(){0x0014FFFF, 0, 0, 16 },
- Package(){0x0014FFFF, 1, 0, 17 },
- Package(){0x0014FFFF, 2, 0, 18 },
- Package(){0x0014FFFF, 3, 0, 19 },
- /* Package(){0x00140004, 2, 0, 18 }, */
- /* Package(){0x00140004, 3, 0, 19 }, */
- /* Package(){0x00140005, 1, 0, 17 }, */
- /* Package(){0x00140006, 1, 0, 17 }, */
- })
-
- Name(PR1, Package(){
- /* Internal graphics - RS690 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, INTA, 0 },
- Package(){0x0005FFFF, 1, INTB, 0 },
- Package(){0x0005FFFF, 2, INTC, 0 },
- Package(){0x0005FFFF, 3, INTD, 0 },
- })
-
- Name(APR1, Package(){
- /* Internal graphics - RS690 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, 0, 18 },
- Package(){0x0005FFFF, 1, 0, 19 },
- /* Package(){0x0005FFFF, 2, 0, 20 }, */
- /* Package(){0x0005FFFF, 3, 0, 17 }, */
- })
-
- Name(PS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, INTA, 0 },
- Package(){0x0000FFFF, 1, INTB, 0 },
- Package(){0x0000FFFF, 2, INTC, 0 },
- Package(){0x0000FFFF, 3, INTD, 0 },
- })
-
- Name(APS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, 0, 16 },
- Package(){0x0000FFFF, 1, 0, 17 },
- Package(){0x0000FFFF, 2, 0, 18 },
- Package(){0x0000FFFF, 3, 0, 19 },
- })
-
- Name(PS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, INTB, 0 },
- Package(){0x0000FFFF, 1, INTC, 0 },
- Package(){0x0000FFFF, 2, INTD, 0 },
- Package(){0x0000FFFF, 3, INTA, 0 },
- })
-
- Name(APS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
-
- Name(APS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, 0, 19 },
- Package(){0x0000FFFF, 1, 0, 16 },
- Package(){0x0000FFFF, 2, 0, 17 },
- Package(){0x0000FFFF, 3, 0, 18 },
- })
-
- Name(PCIB, Package(){
- /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
- Package(){0x0005FFFF, 0, 0, 0x14 },
- Package(){0x0005FFFF, 1, 0, 0x15 },
- Package(){0x0005FFFF, 2, 0, 0x16 },
- Package(){0x0005FFFF, 3, 0, 0x17 },
- Package(){0x0006FFFF, 0, 0, 0x15 },
- Package(){0x0006FFFF, 1, 0, 0x16 },
- Package(){0x0006FFFF, 2, 0, 0x17 },
- Package(){0x0006FFFF, 3, 0, 0x14 },
- Package(){0x0007FFFF, 0, 0, 0x16 },
- Package(){0x0007FFFF, 1, 0, 0x17 },
- Package(){0x0007FFFF, 2, 0, 0x14 },
- Package(){0x0007FFFF, 3, 0, 0x15 },
- })
-}
diff --git a/src/mainboard/technexion/tim8690/acpi/sata.asl b/src/mainboard/technexion/tim8690/acpi/sata.asl
deleted file mode 100644
index 474e5ed6d2..0000000000
--- a/src/mainboard/technexion/tim8690/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(SATA) {
- Name(_ADR, 0x00120000)
- #include "sata.asl"
- }
- }
-}
-*/
-
-Name(STTM, Buffer(20) {
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
- \_GPE._L1F()
-}
-
-Device(PMRY)
-{
- Name(_ADR, 0)
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(PMST) {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P0IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- }/* end of PMST */
-
- Device(PSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P1IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of PSLA */
-} /* end of PMRY */
-
-
-Device(SEDY)
-{
- Name(_ADR, 1) /* IDE Scondary Channel */
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(SMST)
- {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P2IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SMST */
-
- Device(SSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P3IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SSLA */
-} /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
- Method(_L1F,0x0,NotSerialized) {
- if (\_SB.P0PR) {
- if (LGreater(\_SB.P0IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P0PR)
- }
-
- if (\_SB.P1PR) {
- if (LGreater(\_SB.P1IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P1PR)
- }
-
- if (\_SB.P2PR) {
- if (LGreater(\_SB.P2IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P2PR)
- }
-
- if (\_SB.P3PR) {
- if (LGreater(\_SB.P3IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P3PR)
- }
- }
-}
diff --git a/src/mainboard/technexion/tim8690/acpi/usb.asl b/src/mainboard/technexion/tim8690/acpi/usb.asl
deleted file mode 100644
index 638690697c..0000000000
--- a/src/mainboard/technexion/tim8690/acpi/usb.asl
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "usb.asl"
- }
-*/
-Method(UCOC, 0) {
- Sleep(20)
- Store(0x13,CMTI)
- Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
- Scope (\_GPE) {
- Method (_L13) {
- UCOC()
- if(LEqual(GPB0,PLC0)) {
- Not(PLC0,PLC0)
- Store(PLC0, \_SB.PT0D)
- }
- }
- }
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
- Scope (\_GPE) {
- Method (_L14) {
- UCOC()
- if (LEqual(GPB1,PLC1)) {
- Not(PLC1,PLC1)
- Store(PLC1, \_SB.PT1D)
- }
- }
- }
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
- Scope (\_GPE) {
- Method (_L15) {
- UCOC()
- if (LEqual(GPB2,PLC2)) {
- Not(PLC2,PLC2)
- Store(PLC2, \_SB.PT2D)
- }
- }
- }
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
- Scope (\_GPE) {
- Method (_L16) {
- UCOC()
- if (LEqual(GPB3,PLC3)) {
- Not(PLC3,PLC3)
- Store(PLC3, \_SB.PT3D)
- }
- }
- }
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
- Scope (\_GPE) {
- Method (_L19) {
- UCOC()
- if (LEqual(GPB4,PLC4)) {
- Not(PLC4,PLC4)
- Store(PLC4, \_SB.PT4D)
- }
- }
- }
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
- Scope (\_GPE) {
- Method (_L1A) {
- UCOC()
- if (LEqual(GPB5,PLC5)) {
- Not(PLC5,PLC5)
- Store(PLC5, \_SB.PT5D)
- }
- }
- }
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
- Scope (\_GPE) {
- /* Method (_L1C) { */
- Method (_L06) {
- UCOC()
- if (LEqual(GPB6,PLC6)) {
- Not(PLC6,PLC6)
- Store(PLC6, \_SB.PT6D)
- }
- }
- }
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
- Scope (\_GPE) {
- /* Method (_L1D) { */
- Method (_L07) {
- UCOC()
- if (LEqual(GPB7,PLC7)) {
- Not(PLC7,PLC7)
- Store(PLC7, \_SB.PT7D)
- }
- }
- }
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
- Scope (\_GPE) {
- Method (_L17) {
- if (LEqual(G8IS,PLC8)) {
- Not(PLC8,PLC8)
- Store(PLC8, \_SB.PT8D)
- }
- }
- }
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
- Scope (\_GPE) {
- Method (_L0E) {
- if (LEqual(G9IS,0)) {
- Store(1,\_SB.PT9D)
- }
- }
- }
-}
diff --git a/src/mainboard/technexion/tim8690/acpi_tables.c b/src/mainboard/technexion/tim8690/acpi_tables.c
deleted file mode 100644
index 75834b6c7f..0000000000
--- a/src/mainboard/technexion/tim8690/acpi_tables.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include <arch/cpu.h>
-#include <cpu/amd/powernow.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- get_bus_conf();
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB600 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
- IO_APIC_ADDR, 0);
-
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high */
-
- /* create all subtables for processors */
- /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
- /* 1: LINT1 connect to NMI */
-
- return current;
-}
diff --git a/src/mainboard/technexion/tim8690/board_info.txt b/src/mainboard/technexion/tim8690/board_info.txt
deleted file mode 100644
index dbda07e41b..0000000000
--- a/src/mainboard/technexion/tim8690/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: half
-Board URL: http://www.technexion.com/index.php/tim-8690
diff --git a/src/mainboard/technexion/tim8690/cmos.layout b/src/mainboard/technexion/tim8690/cmos.layout
deleted file mode 100644
index 104d51f4c2..0000000000
--- a/src/mainboard/technexion/tim8690/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-##
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/technexion/tim8690/devicetree.cb b/src/mainboard/technexion/tim8690/devicetree.cb
deleted file mode 100644
index 8d1df8be10..0000000000
--- a/src/mainboard/technexion/tim8690/devicetree.cb
+++ /dev/null
@@ -1,115 +0,0 @@
-#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_S1G1
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1022 0x3050 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on # southbridge
- chip southbridge/amd/rs690
- device pci 0.0 on end # HT 0x7910
- device pci 1.0 on # Internal Graphics P2P bridge 0x7912
- device pci 5.0 on end # Internal Graphics 0x791F
- end
- device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
- device pci 3.0 off end # PCIE P2P bridge 0x791b
- device pci 4.0 on end # PCIE P2P bridge 0x7914
- device pci 5.0 on end # PCIE P2P bridge 0x7915
- device pci 6.0 on end # PCIE P2P bridge 0x7916
- device pci 7.0 on end # PCIE P2P bridge 0x7917
- device pci 8.0 off end # NB/SB Link P2P bridge
- register "gpp_configuration" = "4"
- register "port_enable" = "0xfc"
- register "gfx_dev2_dev3" = "1"
- register "gfx_dual_slot" = "0"
- register "gfx_lane_reversal" = "0"
- register "gfx_tmds" = "0"
- register "gfx_compliance" = "0"
- register "gfx_reconfiguration" = "1"
- register "gfx_link_width" = "0"
- end
- chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
- device pci 12.0 on end # SATA 0x4380
- device pci 13.0 on end # USB 0x4387
- device pci 13.1 on end # USB 0x4388
- device pci 13.2 on end # USB 0x4389
- device pci 13.3 on end # USB 0x438a
- device pci 13.4 on end # USB 0x438b
- device pci 13.5 on end # USB 2 0x4386
- device pci 14.0 on # SM 0x4385
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- end # SM
- device pci 14.1 on end # IDE 0x438c
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC 0x438d
- chip superio/ite/it8712f
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 off end # EC
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.6 on # Mouse
- irq 0x70 = 12
- end
- device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
- end
- device pnp 2e.8 off # MIDI
- io 0x60 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.9 off # GAME
- io 0x60 = 0x220
- end
- device pnp 2e.a off end # CIR
- end #superio/ite/it8712f
- end #LPC
- device pci 14.4 on end # PCI 0x4384
- device pci 14.5 on end # ACI 0x4382
- device pci 14.6 on end # MCI 0x438e
- register "hda_viddid" = "0x10ec0882"
- end #southbridge/amd/sb600
- end # device pci 18.0
-
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end #northbridge/amd/amdk8
- end #domain
-end #northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl
deleted file mode 100644
index ae82a2a300..0000000000
--- a/src/mainboard/technexion/tim8690/dsdt.asl
+++ /dev/null
@@ -1,1674 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <southbridge/amd/sb600/sb600.h>
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "TECHNE", /* OEMID */
- "COREBOOT", /* TABLE ID */
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
-
- /* Data to be patched by the BIOS during POST */
- /* FIXME the patching is not done yet! */
- /* Memory related values */
- Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
-
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
-
- /* USB overcurrent mapping pins. */
- Name(UOM0, 0)
- Name(UOM1, 2)
- Name(UOM2, 0)
- Name(UOM3, 7)
- Name(UOM4, 2)
- Name(UOM5, 2)
- Name(UOM6, 6)
- Name(UOM7, 2)
- Name(UOM8, 6)
- Name(UOM9, 6)
-
- /* Some global data */
- Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PMOD, One) /* Assume APIC */
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- /* PCI Error control register */
- OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
- Field(PERC, ByteAcc, NoLock, Preserve) {
- SENS, 0x00000001,
- PENS, 0x00000001,
- SENE, 0x00000001,
- PENE, 0x00000001,
- }
-
- /* Client Management index/data registers */
- OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
- Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
- /* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
- }
-
- /* GPM Port register */
- OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
- Field(GPT, ByteAcc, NoLock, Preserve) {
- GPB0,1,
- GPB1,1,
- GPB2,1,
- GPB3,1,
- GPB4,1,
- GPB5,1,
- GPB6,1,
- GPB7,1,
- }
-
- /* Flash ROM program enable register */
- OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
- Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
- FLRE, 0x00000001,
- }
-
- /* PM2 index/data registers */
- OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
- Field(PM2R, ByteAcc, NoLock, Preserve) {
- PM2I, 0x00000008,
- PM2D, 0x00000008,
- }
-
- /* Power Management I/O registers */
- OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
- Field(PIOR, ByteAcc, NoLock, Preserve) {
- PIOI, 0x00000008,
- PIOD, 0x00000008,
- }
- IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
- Offset(0x00), /* MiscControl */
- , 1,
- T1EE, 1,
- T2EE, 1,
- Offset(0x01), /* MiscStatus */
- , 1,
- T1E, 1,
- T2E, 1,
- Offset(0x04), /* SmiWakeUpEventEnable3 */
- , 7,
- SSEN, 1,
- Offset(0x07), /* SmiWakeUpEventStatus3 */
- , 7,
- CSSM, 1,
- Offset(0x10), /* AcpiEnable */
- , 6,
- PWDE, 1,
- Offset(0x1C), /* ProgramIoEnable */
- , 3,
- MKME, 1,
- IO3E, 1,
- IO2E, 1,
- IO1E, 1,
- IO0E, 1,
- Offset(0x1D), /* IOMonitorStatus */
- , 3,
- MKMS, 1,
- IO3S, 1,
- IO2S, 1,
- IO1S, 1,
- IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
- APEB, 16,
- Offset(0x36), /* GEvtLevelConfig */
- , 6,
- ELC6, 1,
- ELC7, 1,
- Offset(0x37), /* GPMLevelConfig0 */
- , 3,
- PLC0, 1,
- PLC1, 1,
- PLC2, 1,
- PLC3, 1,
- PLC8, 1,
- Offset(0x38), /* GPMLevelConfig1 */
- , 1,
- PLC4, 1,
- PLC5, 1,
- , 1,
- PLC6, 1,
- PLC7, 1,
- Offset(0x3B), /* PMEStatus1 */
- GP0S, 1,
- GM4S, 1,
- GM5S, 1,
- APS, 1,
- GM6S, 1,
- GM7S, 1,
- GP2S, 1,
- STSS, 1,
- Offset(0x55), /* SoftPciRst */
- SPRE, 1,
- , 1,
- , 1,
- PNAT, 1,
- PWMK, 1,
- PWNS, 1,
-
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
-
- Offset(0x65), /* UsbPMControl */
- , 4,
- URRE, 1,
- Offset(0x68), /* MiscEnable68 */
- , 3,
- TMTE, 1,
- , 1,
- Offset(0x92), /* GEVENTIN */
- , 7,
- E7IS, 1,
- Offset(0x96), /* GPM98IN */
- G8IS, 1,
- G9IS, 1,
- Offset(0x9A), /* EnhanceControl */
- ,7,
- HPDE, 1,
- Offset(0xA8), /* PIO7654Enable */
- IO4E, 1,
- IO5E, 1,
- IO6E, 1,
- IO7E, 1,
- Offset(0xA9), /* PIO7654Status */
- IO4S, 1,
- IO5S, 1,
- IO6S, 1,
- IO7S, 1,
- }
-
- /* PM1 Event Block
- * First word is PM1_Status, Second word is PM1_Enable
- */
- OperationRegion(P1EB, SystemIO, APEB, 0x04)
- Field(P1EB, ByteAcc, NoLock, Preserve) {
- TMST, 1,
- , 3,
- BMST, 1,
- GBST, 1,
- Offset(0x01),
- PBST, 1,
- , 1,
- RTST, 1,
- , 3,
- PWST, 1,
- SPWS, 1,
- Offset(0x02),
- TMEN, 1,
- , 4,
- GBEN, 1,
- Offset(0x03),
- PBEN, 1,
- , 1,
- RTEN, 1,
- , 3,
- PWDA, 1,
- }
-
- Scope(\_SB) {
-
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
- /* Byte offsets are computed using the following technique:
- * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
- * The 8 comes from 8 functions per device, and 4096 bytes per function config space
- */
- Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
- STB5, 32,
- Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
- PT0D, 1,
- PT1D, 1,
- PT2D, 1,
- PT3D, 1,
- PT4D, 1,
- PT5D, 1,
- PT6D, 1,
- PT7D, 1,
- PT8D, 1,
- PT9D, 1,
- Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
- SBIE, 1,
- SBME, 1,
- Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
- SBRI, 8,
- Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
- SBB1, 32,
- Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
- ,14,
- P92E, 1, /* Port92 decode enable */
- }
-
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
- Field(SB5, AnyAcc, NoLock, Preserve)
- {
- /* Port 0 */
- Offset(0x120), /* Port 0 Task file status */
- P0ER, 1,
- , 2,
- P0DQ, 1,
- , 3,
- P0BY, 1,
- Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
- , 4,
- P0IS, 4,
- Offset(0x12C), /* Port 0 Serial ATA control */
- P0DI, 4,
- Offset(0x130), /* Port 0 Serial ATA error */
- , 16,
- P0PR, 1,
-
- /* Port 1 */
- offset(0x1A0), /* Port 1 Task file status */
- P1ER, 1,
- , 2,
- P1DQ, 1,
- , 3,
- P1BY, 1,
- Offset(0x1A8), /* Port 1 Serial ATA status */
- P1DD, 4,
- , 4,
- P1IS, 4,
- Offset(0x1AC), /* Port 1 Serial ATA control */
- P1DI, 4,
- Offset(0x1B0), /* Port 1 Serial ATA error */
- , 16,
- P1PR, 1,
-
- /* Port 2 */
- Offset(0x220), /* Port 2 Task file status */
- P2ER, 1,
- , 2,
- P2DQ, 1,
- , 3,
- P2BY, 1,
- Offset(0x228), /* Port 2 Serial ATA status */
- P2DD, 4,
- , 4,
- P2IS, 4,
- Offset(0x22C), /* Port 2 Serial ATA control */
- P2DI, 4,
- Offset(0x230), /* Port 2 Serial ATA error */
- , 16,
- P2PR, 1,
-
- /* Port 3 */
- Offset(0x2A0), /* Port 3 Task file status */
- P3ER, 1,
- , 2,
- P3DQ, 1,
- , 3,
- P3BY, 1,
- Offset(0x2A8), /* Port 3 Serial ATA status */
- P3DD, 4,
- , 4,
- P3IS, 4,
- Offset(0x2AC), /* Port 3 Serial ATA control */
- P3DI, 4,
- Offset(0x2B0), /* Port 3 Serial ATA error */
- , 16,
- P3PR, 1,
- }
- }
-
- #include "acpi/routing.asl"
-
- Scope(\_SB) {
-
- Method(OSFL, 0){
-
- if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
-
- if(CondRefOf(\_OSI))
- {
- Store(1, OSVR) /* Assume some form of XP */
- if (\_OSI("Windows 2006")) /* Vista */
- {
- Store(2, OSVR)
- }
- } else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSVR) /* Linux */
- } Else {
- Store(4, OSVR) /* Gotta be WinCE */
- }
- }
- Return(OSVR)
- }
-
- Method(_PIC, 0x01, NotSerialized)
- {
- If (Arg0)
- {
- \_SB.CIRQ()
- }
- Store(Arg0, PMOD)
- }
-
- Method(CIRQ, 0x00, NotSerialized)
- {
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTA._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTE._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_PRS\n") */
- Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
- } /* End Scope(_SB) */
-
- #include <southbridge/amd/common/acpi/sleepstates.asl>
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- \_SB.PCI0.SIOS (Arg0)
- } /* End Method(\_PTS) */
-
- /*
- * The following method results in a "not a valid reserved NameSeg"
- * warning so I have commented it out for the duration. It isn't
- * used, so it could be removed.
- *
- *
- * \_GTS OEM Going To Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- *
- * Method(\_GTS, 1) {
- * DBGO("\\_GTS\n")
- * DBGO("From S0 to S")
- * DBGO(Arg0)
- * DBGO("\n")
- * }
- */
-
- /*
- * \_BFS OEM Back From Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- */
- Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
- }
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- Store(1,HPDE)
-
- /* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, Local1)
- Store(Local1, PWST)
-
- /* if(DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
- * } else {
- * Store(Arg0, Index(WKST,1))
- * }
- */
- \_SB.PCI0.SIOW ()
- Return(WKST)
- } /* End Method(\_WAK) */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* General event 0 */
- /* Method(_L00) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 1 */
- /* Method(_L01) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 2 */
- /* Method(_L02) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 3 */
- Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* General event 4 */
- /* Method(_L04) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 5 */
- /* Method(_L05) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 6 - Used for GPM6, moved to USB.asl */
- /* Method(_L06) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 7 - Used for GPM7, moved to USB.asl */
- /* Method(_L07) {
- * DBGO("\\_GPE\\_L07\n")
- * }
- */
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
- }
-
- /* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
-
- /* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
-
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
-
- /* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
-
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event - Moved to USB.asl */
- /* Method(_L1A) {
- * DBGO("\\_GPE\\_L1A\n")
- * }
- */
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
-
- /* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
-
- /* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
-
- /* SATA SCI event - Moved to sata.asl */
- /* Method(_L1F) {
- * DBGO("\\_GPE\\_L1F\n")
- * }
- */
-
- } /* End Scope GPE */
-
- #include "acpi/usb.asl"
-
- /* System Bus */
- Scope(\_SB) { /* Start \_SB scope */
- #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0) {
- External (TOM1)
- External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* Dev3 is also an external GFX bridge, not used in Herring */
-
- Device(PBR4) {
- Name(_ADR, 0x00040000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR4 */
-
- Device(PBR5) {
- Name(_ADR, 0x00050000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR5 */
-
- Device(PBR6) {
- Name(_ADR, 0x00060000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR6 */
-
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR7 */
-
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
-
- /* Describe the Southbridge devices */
- Device(STCR) {
- Name(_ADR, 0x00120000)
- #include "acpi/sata.asl"
- } /* end STCR */
-
- Device(UOH1) {
- Name(_ADR, 0x00130000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH1 */
-
- Device(UOH2) {
- Name(_ADR, 0x00130001)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH2 */
-
- Device(UOH3) {
- Name(_ADR, 0x00130002)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH3 */
-
- Device(UOH4) {
- Name(_ADR, 0x00130003)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH4 */
-
- Device(UOH5) {
- Name(_ADR, 0x00130004)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UEH1) {
- Name(_ADR, 0x00130005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(SBUS) {
- Name(_ADR, 0x00140000)
- } /* end SBUS */
-
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "acpi/ide.asl"
- } /* end IDEC */
-
- Device(AZHD) {
- Name(_ADR, 0x00140002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6C),
- MMDT, 16,
- }
-
- Method(_INI) {
- If(LEqual(OSVR,3)){ /* If we are running Linux */
- Store(zero, NSEN)
- Store(one, NSDO)
- Store(one, NSDI)
- }
- }
- } /* end AZHD */
-
- Device(LIBR) {
- Name(_ADR, 0x00140003)
- /* Method(_INI) {
- * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
- } */ /* End Method(_SB.SBRDG._INI) */
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){8}
- IO(Decode16,0x0070, 0x0070, 0, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){0}
- IO(Decode16, 0x0040, 0x0040, 0, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 0, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){2}
- IO(Decode16,0x0020, 0x0020, 0, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,BusMaster,Transfer8){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
- IRQNoFlags(){13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPTM) { /* HPET */
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* HPET is visible */
- }
- Method(_CRS, 0) {
- Return(CRS)
- }
- } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
- } /* end LIBR */
-
- Device(HPBR) {
- Name(_ADR, 0x00140004)
- } /* end HostPciBr */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- } /* end Ac97modem */
-
- /* ITE IT8712F Support */
- OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
- Field (IOID, ByteAcc, NoLock, Preserve)
- {
- SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
- }
-
- IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
- {
- Offset (0x07),
- LDN, 8, /* Logical Device Number */
- Offset (0x20),
- CID1, 8, /* Chip ID Byte 1, 0x87 */
- CID2, 8, /* Chip ID Byte 2, 0x12 */
- Offset (0x30),
- ACTR, 8, /* Function activate */
- Offset (0xF0),
- APC0, 8, /* APC/PME Event Enable Register */
- APC1, 8, /* APC/PME Status Register */
- APC2, 8, /* APC/PME Control Register 1 */
- APC3, 8, /* Environment Controller Special Configuration Register */
- APC4, 8 /* APC/PME Control Register 2 */
- }
-
- /* Enter the IT8712F MB PnP Mode */
- Method (EPNP)
- {
- Store(0x87, SIOI)
- Store(0x01, SIOI)
- Store(0x55, SIOI)
- Store(0x55, SIOI) /* IT8712F magic number */
- }
- /* Exit the IT8712F MB PnP Mode */
- Method (XPNP)
- {
- Store (0x02, SIOI)
- Store (0x02, SIOD)
- }
-
- /*
- * Keyboard PME is routed to SB600 Gevent3. We can wake
- * up the system by pressing the key.
- */
- Method (SIOS, 1)
- {
- /* We only enable KBD PME for S5. */
- If (LLess (Arg0, 0x05))
- {
- EPNP()
- /* DBGO("IT8712F\n") */
-
- Store (0x4, LDN)
- Store (One, ACTR) /* Enable EC */
- /*
- Store (0x4, LDN)
- Store (0x04, APC4)
- */ /* falling edge. which mode? Not sure. */
-
- Store (0x4, LDN)
- Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
- Store (0x4, LDN)
- Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
- XPNP()
- }
- }
- Method (SIOW, 0)
- {
- EPNP()
- Store (0x4, LDN)
- Store (Zero, APC0) /* disable keyboard PME */
- Store (0x4, LDN)
- Store (0xFF, APC1) /* clear keyboard PME status */
- XPNP()
- }
-
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
-
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
- }
-
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * ShiftLeft(TOM2, 20, Local0)
- * Subtract(Local0, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-
- Return(CRES) /* note to change the Name buffer */
- } /* end of Method(_SB.PCI0._CRS) */
-
- /*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
- Method(_INI, 0) {
- /* DBGO("\\_SB\\_INI\n") */
- /* DBGO(" DSDT.ASL code from ") */
- /* DBGO(__DATE__) */
- /* DBGO(" ") */
- /* DBGO(__TIME__) */
- /* DBGO("\n Sleep states supported: ") */
- /* DBGO("\n") */
- /* DBGO(" \\_OS=") */
- /* DBGO(\_OS) */
- /* DBGO("\n \\_REV=") */
- /* DBGO(\_REV) */
- /* DBGO("\n") */
-
- /* Determine the OS we're running on */
- OSFL()
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
- * }
- */
- } /* End Method(_SB._INI) */
- } /* End Device(PCI0) */
-
- Device(PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
- } /* End \_SB scope */
-
- Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
- } /* End Scope SI */
-
- #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
-
- /* THERMAL */
- Scope(\_TZ) {
- Name (KELV, 2732)
- Name (THOT, 800)
- Name (TCRT, 850)
-
- ThermalZone(TZ00) {
- Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
- /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
- Return(Add(0, 2730))
- }
- Method(_AL0,0) { /* Returns package of cooling device to turn on */
- /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
- Return(Package() {\_TZ.TZ00.FAN0})
- }
- Device (FAN0) {
- Name(_HID, EISAID("PNP0C0B"))
- Name(_PR0, Package() {PFN0})
- }
-
- PowerResource(PFN0,0,0) {
- Method(_STA) {
- Store(0xF,Local0)
- Return(Local0)
- }
- Method(_ON) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
- }
- Method(_OFF) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
- }
- }
-
- Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
- Return (Add (THOT, KELV))
- }
- Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
- Return (Add (TCRT, KELV))
- }
- Method(_TMP,0) { /* return current temp of this zone */
- Store (SMBR (0x07, 0x4C,, 0x00), Local0)
- If (LGreater (Local0, 0x10)) {
- Store (Local0, Local1)
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400, KELV))
- }
-
- Store (SMBR (0x07, 0x4C, 0x01), Local0)
- /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
- /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
- If (LGreater (Local0, 0x10)) {
- If (LGreater (Local0, Local1)) {
- Store (Local0, Local1)
- }
-
- Multiply (Local1, 10, Local1)
- Return (Add (Local1, KELV))
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400 , KELV))
- }
- } /* end of _TMP */
- } /* end of TZ00 */
- }
-}
-/* End of ASL file */
diff --git a/src/mainboard/technexion/tim8690/fadt.c b/src/mainboard/technexion/tim8690/fadt.c
deleted file mode 100644
index f9768b20bd..0000000000
--- a/src/mainboard/technexion/tim8690/fadt.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include "southbridge/amd/sb600/sb600.h"
-
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb ACPI */
-/* pm_base should be got from bar2 of rs690. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
-
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
- /* Prepare the header */
- memset((void *)fadt, 0, sizeof(acpi_fadt_t));
- memcpy(header->signature, "FACP", 4);
- header->length = 244;
- header->revision = 3;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->asl_compiler_revision = 0;
-
- fadt->firmware_ctrl = (u32) facs;
- fadt->dsdt = (u32) dsdt;
- /* 3=Workstation,4=Enterprise Server, 7=Performance Server */
- fadt->preferred_pm_profile = 0x03;
- fadt->sci_int = 9;
- /* disable system management mode by setting to 0: */
- fadt->smi_cmd = 0;
- fadt->acpi_enable = 0xf0;
- fadt->acpi_disable = 0xf1;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0xe2;
-
- pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
-
- /* CpuControl is in \_PR.CP00, 6 bytes */
- pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
-
- pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
-
- pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
-
- pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 20-2B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
- pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
-
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
- fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
- fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
- fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
-
- fadt->cst_cnt = 0xe3;
- fadt->p_lvl2_lat = 101;
- fadt->p_lvl3_lat = 1001;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 1;
- fadt->duty_width = 3;
- fadt->day_alrm = 0; /* 0x7d these have to be */
- fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
- fadt->century = 0; /* 0x7f to make rtc alrm work */
- fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
- fadt->flags = 0x0001c1a5;/* 0x25; */
-
- fadt->res2 = 0;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 6;
- fadt->x_firmware_ctl_l = (u32) facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32) dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 4;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 2;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 32;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/technexion/tim8690/get_bus_conf.c b/src/mainboard/technexion/tim8690/get_bus_conf.c
deleted file mode 100644
index b1b7270802..0000000000
--- a/src/mainboard/technexion/tim8690/get_bus_conf.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_rs690[8];
-u8 bus_sb600[2];
-u32 apicid_sb600;
-
-/*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
-u32 pci1234x[] = {
- 0x0000ff0,
-};
-
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
- 0x20202020,
-};
-
-u32 sbdn_rs690;
-u32 sbdn_sb600;
-
-
-
-static u32 get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- u32 apicid_base;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* do it only once */
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
- sbdn_rs690 = sysconf.sbdn;
- sbdn_sb600 = 0;
-
- for (i = 0; i < 2; i++) {
- bus_sb600[i] = 0;
- }
- for (i = 0; i < 8; i++) {
- bus_rs690[i] = 0;
- }
-
- bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_sb600[0] = bus_rs690[0];
-
- /* sb600 */
- dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
- if (dev) {
- bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- /* rs690 */
- for (i = 1; i < 8; i++) {
- dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
- if (dev) {
- bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
- /* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_sb600 = apicid_base + 0;
-}
diff --git a/src/mainboard/technexion/tim8690/irq_tables.c b/src/mainboard/technexion/tim8690/irq_tables.c
deleted file mode 100644
index 4c2a48dff7..0000000000
--- a/src/mainboard/technexion/tim8690/irq_tables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern u8 bus_rs690[8];
-extern u8 bus_sb600[2];
-extern unsigned long sbdn_sb600;
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_sb600[0];
- pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c
deleted file mode 100644
index 2f2b453994..0000000000
--- a/src/mainboard/technexion/tim8690/mainboard.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb600/sb600.h>
-
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS 0x0C /* Alert Response Address */
-#define SMBUS_IO_BASE 0x1000
-
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-#define ADT7461_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
- do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-
-
-
-
-/***************************************************
-* This board, the TIM-8690 has two Marvel 88e5056 PCI-E
-* 10/100/1000 chips on board.
-* Both of their pin PERSTn pins are connected to GPIO 5 of the
-* SB600 southbridge.
-****************************************************/
-static void enable_onboard_nic(void)
-{
-
- u8 byte;
- struct device *sm_dev;
-
- printk(BIOS_INFO, "enable_onboard_nic.\n");
-
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0x9a);
- byte |= ( 1 << 7);
- pci_write_config8(sm_dev, 0x9a, byte);
-
- byte = pm_ioread(0x59);
- byte &= ~( 1<< 5);
- pm_iowrite(0x59,byte);
-
- byte = pci_read_config8(sm_dev, 0xA8);
-
- byte |= (1 << 1); //set bit 1 to high
- pci_write_config8(sm_dev, 0xA8, byte);
-}
-
-/* set thermal config
- */
-static void set_thermal_config(void)
-{
- u8 byte;
- u16 word;
- struct device *sm_dev;
-
- /* set ADT 7461 */
- ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
- ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
- ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
- ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
-
- ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
- ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
-
- byte = ADT7461_read_byte(0x02); /* read status register to clear it */
- ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
- printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
-
- /* sb600 settings for thermal config */
- /* set SB600 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to input */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
-}
-
-/*************************************************
-* enable the dedicated function in tim8690 board.
-* This function called early than rs690_enable.
-*************************************************/
-static void mainboard_enable(struct device *dev)
-{
- printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev);
-
- enable_onboard_nic();
- set_thermal_config();
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c
deleted file mode 100644
index 9515931627..0000000000
--- a/src/mainboard/technexion/tim8690/mptable.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern u8 bus_rs690[8];
-extern u8 bus_sb600[2];
-
-extern u32 apicid_sb600;
-
-extern u32 sbdn_rs690;
-extern u32 sbdn_sb600;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- u32 dword;
- u8 byte;
-
- dev =
- dev_find_slot(bus_sb600[0],
- PCI_DEVFN(sbdn_sb600 + 0x14, 0));
- if (dev) {
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600,
- 0x11,(void *) dword);
-
- /* Initialize interrupt mapping */
- /* aza */
- byte = pci_read_config8(dev, 0x63);
- byte &= 0xf8;
- byte |= 0; /* 0: INTA, ...., 7: INTH */
- pci_write_config8(dev, 0x63, byte);
-
- /* SATA */
- dword = pci_read_config32(dev, 0xac);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
- /* dword |= 1 << 22; PIC and APIC co exists */
- pci_write_config32(dev, 0xac, dword);
-
- /*
- * 00:12.0: PROG SATA : INT F
- * 00:13.0: INTA USB_0
- * 00:13.1: INTB USB_1
- * 00:13.2: INTC USB_2
- * 00:13.3: INTD USB_3
- * 00:13.4: INTC USB_4
- * 00:13.5: INTD USB2
- * 00:14.1: INTA IDE
- * 00:14.2: Prog HDA : INT E
- * 00:14.5: INTB ACI
- * 00:14.6: INTB MCI
- */
- }
- }
-
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/technexion/tim8690/resourcemap.c b/src/mainboard/technexion/tim8690/resourcemap.c
deleted file mode 100644
index 20a8d91bee..0000000000
--- a/src/mainboard/technexion/tim8690/resourcemap.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_tim8690_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
deleted file mode 100644
index 67d0b06470..0000000000
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <spd.h>
-#include <cpu/x86/lapic.h>
-
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/early_setup.c"
-#include "southbridge/amd/sb600/early_setup.c"
-#include <northbridge/amd/amdk8/f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(u32 device, u32 address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
- int needs_reset = 0;
- u32 bsp_apicid = 0;
- msr_t msr;
- struct cpuid_result cpuid1;
- struct sys_info *sysinfo = &sysinfo_car;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- /* sb600_lpc_port80(); */
- sb600_pci_port80();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- enable_rs690_dev8();
- sb600_lpc_init();
-
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- ite_kill_watchdog(GPIO_DEV);
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
- printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
-
- setup_tim8690_resource_map();
-
- setup_coherent_ht_domain();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched */
- wait_all_core0_started();
- start_other_cores();
-#endif
- wait_all_aps_started(bsp_apicid);
-
- ht_setup_chains_x(sysinfo);
-
- /* run _early_setup before soft-reset. */
- rs690_early_setup();
- sb600_early_setup();
-
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- cpuid1 = cpuid(0x80000007);
- if ((cpuid1.edx & 0x6) == 0x6 ) {
- /* Read FIDVID_STATUS */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
-
- /* show final fid and vid */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
- } else {
- printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
- }
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- rs690_htinit();
- printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
-
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now; */
- printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
- sysinfo->nodes, sysinfo->ctrl, spd_addr);
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
- rs690_before_pci_init();
- sb600_before_pci_init();
-}
diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig
deleted file mode 100644
index 66c885d424..0000000000
--- a/src/mainboard/tyan/s2912/Kconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-if BOARD_TYAN_S2912
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_F
- select DIMM_DDR2
- select DIMM_REGISTERED
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_MCP55
- select HT_CHAIN_DISTRIBUTE
- select MCP55_USE_NIC
- select SUPERIO_WINBOND_W83627HF
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_512
- select QRANK_DIMM_SUPPORT
- select K8_ALLOCATE_IO_RANGE
-
-config MAINBOARD_DIR
- string
- default tyan/s2912
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MEM_TRAIN_SEQ
- int
- default 1
-
-config MAINBOARD_PART_NUMBER
- string
- default "S2912"
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-config MCP55_PCI_E_X_0
- int
- default 1
-
-endif # BOARD_TYAN_S2912
diff --git a/src/mainboard/tyan/s2912/Kconfig.name b/src/mainboard/tyan/s2912/Kconfig.name
deleted file mode 100644
index f8f8828808..0000000000
--- a/src/mainboard/tyan/s2912/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_TYAN_S2912
- bool "S2912 (Thunder n3600R)"
diff --git a/src/mainboard/tyan/s2912/board_info.txt b/src/mainboard/tyan/s2912/board_info.txt
deleted file mode 100644
index 0e2b6df6fa..0000000000
--- a/src/mainboard/tyan/s2912/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Board name: Thunder n3600R (S2912)
-Category: server
-Board URL: http://www.tyan.com/product_board_detail.aspx?pid=157
-Release year: 2007
diff --git a/src/mainboard/tyan/s2912/cmos.layout b/src/mainboard/tyan/s2912/cmos.layout
deleted file mode 100644
index 9e6a9e56f2..0000000000
--- a/src/mainboard/tyan/s2912/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 200Mhz
-8 1 166Mhz
-8 2 133Mhz
-8 3 100Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/tyan/s2912/devicetree.cb b/src/mainboard/tyan/s2912/devicetree.cb
deleted file mode 100644
index 42f764a35f..0000000000
--- a/src/mainboard/tyan/s2912/devicetree.cb
+++ /dev/null
@@ -1,138 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_F # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x10f1 0x2912 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.0 on
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627hf # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # SFI
- io 0x62 = 0x100
- end
- device pnp 2e.7 off # GPIO, game port, MIDI
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # WDTO PLED
- device pnp 2e.9 off end # GPIO SUSLED
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic # DIMM 1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic # DIMM 1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic # DIMM 1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic # DIMM 1-1-1
- device i2c 57 on end
- end
- end
- device pci 1.1 on # SM 1
- # PCI device SMBus address will
- # depend on addon PCI device, do
- # we need to scan_smbus_bus?
- # chip drivers/generic/generic # PCIXA slot 1
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 2
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # PCI slot 1
- # device i2c 53 on end
- # end
- # chip drivers/generic/generic # Master MCP55 PCI-E
- # device i2c 54 on end
- # end
- # chip drivers/generic/generic # Slave MCP55 PCI-E
- # device i2c 55 on end
- # end
- chip drivers/generic/generic # MAC EEPROM
- device i2c 51 on end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
- device pci 6.0 on end # PCI
- device pci 6.1 off end # AZA
- device pci 8.0 on end # NIC
- device pci 9.0 on end # NIC
- device pci a.0 on end # PCI E 5
- device pci b.0 off end # PCI E 4
- device pci c.0 off end # PCI E 3
- device pci d.0 on end # PCI E 2
- device pci e.0 off end # PCI E 1
- device pci f.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/tyan/s2912/get_bus_conf.c b/src/mainboard/tyan/s2912/get_bus_conf.c
deleted file mode 100644
index d13f737aa1..0000000000
--- a/src/mainboard/tyan/s2912/get_bus_conf.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-unsigned pci1234x[] =
-{
- // Here you only need to set value in pci1234 for HT-IO that could be
- // installed or not.
- // You may need to preset pci1234 for HTIO board, please refer to
- // src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
- 0x0000ff0,
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-unsigned hcdnx[] =
-{
- // HT Chain device num, actually it is unit id base of every ht device
- // in chain, assume every chain only have 4 ht device at most
- 0x20202020,
- 0x20202020,
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- unsigned apicid_base;
- struct mb_sysconf_t *m;
-
- device_t dev;
- int i;
-
- if(get_bus_conf_done == 1) return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.mb = &mb_sysconf;
-
- m = sysconf.mb;
- memset(m, 0, sizeof(struct mb_sysconf_t));
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for(i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
-
- m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* MCP55 */
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
- if (dev) {
- m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
- }
-
- for(i = 2; i < 8; i++) {
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
- if (dev) {
- m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- m->apicid_mcp55 = apicid_base+0;
-}
diff --git a/src/mainboard/tyan/s2912/irq_tables.c b/src/mainboard/tyan/s2912/irq_tables.c
deleted file mode 100644
index 1c997d8db2..0000000000
--- a/src/mainboard/tyan/s2912/irq_tables.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
- struct mb_sysconf_t *m;
- unsigned sbdn;
-
- uint8_t sum = 0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = m->bus_mcp55[0];
- pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x0370;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
- unsigned devn = sysconf.hcdn[i] & 0xff;
-
- write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8,
- 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
- }
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/tyan/s2912/mb_sysconf.h b/src/mainboard/tyan/s2912/mb_sysconf.h
deleted file mode 100644
index ddd6cfe38f..0000000000
--- a/src/mainboard/tyan/s2912/mb_sysconf.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_mcp55[8]; //1
- unsigned apicid_mcp55;
-};
-
-#endif
diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c
deleted file mode 100644
index 9b46ad68a2..0000000000
--- a/src/mainboard/tyan/s2912/mptable.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- struct mb_sysconf_t *m;
- unsigned sbdn;
- int i, j, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- device_t dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
- }
-
- dword = 0x43c6c643;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x81001a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0xd00002d2;
- pci_write_config32(dev, 0x84, dword);
-
- }
-
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
-
- /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
-
- for(j = 7; j >= 2; j--) {
- if(!m->bus_mcp55[j]) continue;
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
- }
- }
-
- for(j = 0; j < 1; j++)
- for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
- }
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/tyan/s2912/resourcemap.c b/src/mainboard/tyan/s2912/resourcemap.c
deleted file mode 100644
index 9ac7ae4536..0000000000
--- a/src/mainboard/tyan/s2912/resourcemap.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
-// PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
-// PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
-// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
deleted file mode 100644
index 1650d3d38c..0000000000
--- a/src/mainboard/tyan/s2912/romstage.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <southbridge/nvidia/mcp55/mcp55.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define MCP55_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
-
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- /*serial 0 */
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset = 0;
- unsigned bsp_apicid = 0;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- setup_mb_resource_map();
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
- setup_coherent_ht_domain(); // routing table and start other core0
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- // It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
- {
- msr_t msr;
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-#endif
-
- init_timer(); // Need to use TMICT to synchronize FID/VID
-
- needs_reset |= optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= mcp55_early_setup_x();
-
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
- /* all ap stopped? */
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig
deleted file mode 100644
index 5a3b81d604..0000000000
--- a/src/mainboard/winent/mb6047/Kconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-if BOARD_WINENT_MB6047
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_940
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_CK804
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_WINBOND_W83627THG
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_512
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select QRANK_DIMM_SUPPORT
- select CK804_USE_NIC
- select CK804_USE_ACI
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default winent/mb6047
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "MB6047"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-config CK804_PCI_E_X
- int
- default 0
-
-config VGA_BIOS_ID
- string
- default "126f,0720"
-
-config VGA_BIOS_FILE
- string
- default "DM22383.ROM"
-
-endif # BOARD_WINENT_MB6047
diff --git a/src/mainboard/winent/mb6047/Kconfig.name b/src/mainboard/winent/mb6047/Kconfig.name
deleted file mode 100644
index 9997dd6a27..0000000000
--- a/src/mainboard/winent/mb6047/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_WINENT_MB6047
- bool "MB6047"
diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c
deleted file mode 100644
index 6302c1da89..0000000000
--- a/src/mainboard/winent/mb6047/acpi_tables.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * ACPI support
- * written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
- *
- *
- * Copyright 2005 AMD
- * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include <assert.h>
-
-/* APIC */
-unsigned long acpi_fill_madt(unsigned long current)
-{
- struct device *dev;
- struct resource *res;
-
- get_bus_conf();
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write NVIDIA CK804 IOAPIC. */
- dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
- ASSERT(dev != NULL);
-
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- ASSERT(res != NULL);
-
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4,
- res->base, 0);
- /* Initialize interrupt mapping if mptable.c didn't. */
-#if (!CONFIG_GENERATE_MP_TABLE)
- pci_write_config32(dev, 0x7c, 0x0120d218);
- pci_write_config32(dev, 0x80, 0x12008a00);
- pci_write_config32(dev, 0x84, 0x0000007d);
-#endif
-
- /* IRQ9 */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* create all subtables for processors */
- /* acpi_create_madt_lapic_nmis returns current, not size. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/winent/mb6047/board_info.txt b/src/mainboard/winent/mb6047/board_info.txt
deleted file mode 100644
index 7680e6f854..0000000000
--- a/src/mainboard/winent/mb6047/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: half
diff --git a/src/mainboard/winent/mb6047/cmos.layout b/src/mainboard/winent/mb6047/cmos.layout
deleted file mode 100644
index 9cd93c72da..0000000000
--- a/src/mainboard/winent/mb6047/cmos.layout
+++ /dev/null
@@ -1,53 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 8 h 0 century
-408 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/winent/mb6047/devicetree.cb b/src/mainboard/winent/mb6047/devicetree.cb
deleted file mode 100644
index 98a9247e5d..0000000000
--- a/src/mainboard/winent/mb6047/devicetree.cb
+++ /dev/null
@@ -1,120 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_940 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x10de 0xcb84 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/ck804 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627thg # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # PS/2 keyboard & mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off end # Consumer IR
- device pnp 2e.7 off end # Game port, MIDI, GPIO1
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 0
- end
- end
- end
- device pci 1.1 on # SM 0
- # chip drivers/generic/generic # DIMM 0-0-0
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # DIMM 0-0-1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # DIMM 0-1-0
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # DIMM 0-1-1
- # device i2c 53 on end
- # end
- # chip drivers/generic/generic # DIMM 1-0-0
- # device i2c 54 on end
- # end
- # chip drivers/generic/generic # DIMM 1-0-1
- # device i2c 55 on end
- # end
- # chip drivers/generic/generic # DIMM 1-1-0
- # device i2c 56 on end
- # end
- # chip drivers/generic/generic # DIMM 1-1-1
- # device i2c 57 on end
- # end
- end
- # device pci 1.1 on # SM 1
- # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
- # device i2c 2d on end
- # end
- # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
- # device i2c 2e on end
- # end
- # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
- # device i2c 2a on end
- # end
- # chip drivers/generic/generic # Winbond HWM 0x92
- # device i2c 49 on end
- # end
- # chip drivers/generic/generic # Winbond HWM 0x94
- # device i2c 4a on end
- # end
- # end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # ACI
- device pci 4.1 off end # MCI
- device pci 6.0 on end # IDE
- device pci 7.0 on end # SATA 1
- device pci 8.0 on end # SATA 0
- device pci 9.0 on # PCI
- # device pci 6.0 on end
- end
- device pci a.0 on end # NIC
- device pci b.0 on end # PCI E 3
- device pci c.0 on end # PCI E 2
- device pci d.0 on end # PCI E 1
- device pci e.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "ide1_enable" = "0"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- end
- end
- device pci 18.0 on end # Link 1
- device pci 18.0 on end # Link 2 == LDT 2
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/winent/mb6047/dsdt.asl b/src/mainboard/winent/mb6047/dsdt.asl
deleted file mode 100644
index 43b4535957..0000000000
--- a/src/mainboard/winent/mb6047/dsdt.asl
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * Any others would involve declaring the wake up methods.
- */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
-
- Name (PICM, 0x00)
- Method (_PIC, 1, Serialized) {
- Store (Arg0, PICM)
- }
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device (CK804) */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- #include "southbridge/nvidia/ck804/acpi/ck804.asl"
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LLAS, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LLAS, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LUOH, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LUEH, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LAUD, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LMOD, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LPA0, 0x00 },
- Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 },
- Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 },
- })
-
- Device (PCIL)
- {
- Name (_ADR, 0x00090000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- /* onboard SM720 VGA */
- Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
- })
- }
-
- Device (PEX0)
- {
- Name (_ADR, 0x000e0000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
- })
- }
-
- Device (PEX1)
- {
- Name (_ADR, 0x000d0000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
- })
- }
-
- Device (PEX2)
- {
- Name (_ADR, 0x000c0000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- })
- }
-
- Device (PEX3)
- {
- Name (_ADR, 0x000b0000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
- })
- }
-
- Device (ISA) {
- Name (_HID, EisaId ("PNP0A05"))
- Name (_ADR, 0x00010000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
- }
- }
- }
-}
diff --git a/src/mainboard/winent/mb6047/get_bus_conf.c b/src/mainboard/winent/mb6047/get_bus_conf.c
deleted file mode 100644
index de79fa05a7..0000000000
--- a/src/mainboard/winent/mb6047/get_bus_conf.c
+++ /dev/null
@@ -1,98 +0,0 @@
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_ck804_0; //1
-unsigned char bus_ck804_1; //2
-unsigned char bus_ck804_2; //3
-unsigned char bus_ck804_3; //4
-unsigned char bus_ck804_4; //5
-unsigned char bus_ck804_5; //6
-unsigned apicid_ck804;
-
-unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000000,
-};
-
-unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
- unsigned sbdn;
-
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- sbdn = sysconf.sbdn;
-
- bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* CK804 */
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09, 0));
- if (dev) {
- bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_4++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x09);
-
- bus_ck804_1 = 2;
- bus_ck804_4 = 3;
- }
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d, 0));
- if (dev) {
- bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_5++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x0d);
-
- bus_ck804_5 = bus_ck804_4 + 1;
- }
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0e, 0));
- if (dev)
- bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- else
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x0e);
-
-/*I/O APICs: APIC ID Version State Address*/
- apicid_base = get_apicid_base(1);
- apicid_ck804 = apicid_base + 0;
-}
diff --git a/src/mainboard/winent/mb6047/irq_tables.c b/src/mainboard/winent/mb6047/irq_tables.c
deleted file mode 100644
index 885f9e927e..0000000000
--- a/src/mainboard/winent/mb6047/irq_tables.c
+++ /dev/null
@@ -1,151 +0,0 @@
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern unsigned char bus_ck804_0; //1
-extern unsigned char bus_ck804_1; //2
-extern unsigned char bus_ck804_2; //3
-extern unsigned char bus_ck804_3; //4
-extern unsigned char bus_ck804_4; //5
-extern unsigned char bus_ck804_5; //6
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
- unsigned sbdn;
-
- uint8_t sum = 0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_ck804_0;
- pirq->rtr_devfn = ((sbdn + 9) << 3) | 0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x005c;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 9) << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
-#if 0
-//smbus
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 1) << 3) | 0, 0x2,
- 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-//usb
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 2) << 3) | 0, 0x1,
- 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-//audio
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 4) << 3) | 0, 0x1,
- 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-//sata
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 7) << 3) | 0, 0x1,
- 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-//sata
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 8) << 3) | 0, 0x1,
- 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-//nic
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 0xa) << 3) | 0, 0x1,
- 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-//Slot1 PCIE x16
- write_pirq_info(pirq_info, bus_ck804_5, (0 << 3) | 0, 0x3, 0xdef8, 0x4,
- 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
- pirq_info++;
- slot_num++;
-
-//firewire
- write_pirq_info(pirq_info, bus_ck804_1, (0x5 << 3) | 0, 0x3, 0xdef8, 0,
- 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-//Slot2 pci
- write_pirq_info(pirq_info, bus_ck804_1, (0x4 << 3) | 0, 0x1, 0xdef8,
- 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
- pirq_info++;
- slot_num++;
-#endif
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum)
- pirq->checksum = sum;
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/winent/mb6047/mainboard.c b/src/mainboard/winent/mb6047/mainboard.c
deleted file mode 100644
index 7d9516b4f5..0000000000
--- a/src/mainboard/winent/mb6047/mainboard.c
+++ /dev/null
@@ -1,55 +0,0 @@
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pnp_def.h>
-#include <stdlib.h>
-#include <superio/winbond/w83627thg/w83627thg.h>
-
-static void hwm_write(u16 base, u8 bank, u8 reg, u8 value)
-{
- outb(0x4e, base + 0x05);
- outb(bank, base + 0x06);
- outb(reg, base + 0x05);
- outb(value, base + 0x06);
-}
-
-static void mb6047_hwm_init(void)
-{
- struct device *dev;
- struct resource *res;
- size_t i;
-
- static const struct { u8 bnk; u8 idx; u8 dat; } hwmtab[] = {
- { 0x00, 0x5d, 0x05 }, /* CPUTIN diode */
- { 0x04, 0x55, 0x32 }, /* CPUTIN offset */
- { 0x00, 0x4e, 0x00 }, /* reset bank */
- };
-
- dev = dev_find_slot_pnp(0x2e, W83627THG_HWM);
- if (dev == NULL)
- return;
-
- res = find_resource(dev, PNP_IDX_IO0);
- if (res == NULL)
- return;
-
- printk(BIOS_INFO, "setting up hardware monitor at 0x%04x\n", (unsigned int)res->base);
-
- /* Init hardware monitor. */
- for (i = 0; i < ARRAY_SIZE(hwmtab); i++)
- hwm_write(res->base, hwmtab[i].bnk, hwmtab[i].idx, hwmtab[i].dat);
-}
-
-static void mb6047_mainboard_init(struct device *dev)
-{
- mb6047_hwm_init();
-}
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->init = mb6047_mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c
deleted file mode 100644
index 407c59c7e6..0000000000
--- a/src/mainboard/winent/mb6047/mptable.c
+++ /dev/null
@@ -1,109 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_ck804_0; //1
-extern unsigned char bus_ck804_1; //2
-extern unsigned char bus_ck804_2; //3
-extern unsigned char bus_ck804_3; //4
-extern unsigned char bus_ck804_4; //5
-extern unsigned char bus_ck804_5; //6
-extern unsigned apicid_ck804;
-
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned sbdn;
- int i, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
-
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x1, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res)
- smp_write_ioapic(mc, apicid_ck804, 0x11,
- res2mmio(res, 0, 0));
-
- /* Initialize interrupt mapping*/
-
- dword = 0x0120d218;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x12008a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0x0000007d;
- pci_write_config32(dev, 0x84, dword);
- }
-
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
-
-// Onboard ck804 smbus
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_ck804_0, ((sbdn + 1) << 2) | 1, apicid_ck804, 0xa);
-
-// Onboard ck804 USB 1.1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_ck804_0, ((sbdn + 2) << 2) | 0, apicid_ck804, 0x15);
-
-// Onboard ck804 USB 2
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_ck804_0, ((sbdn + 2) << 2 ) | 1, apicid_ck804, 0x14);
-
-// Onboard ck804 SATA 0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_ck804_0, ((sbdn + 7) << 2 ) | 0, apicid_ck804, 0x17);
-
-// Onboard ck804 SATA 1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_ck804_0, ((sbdn + 8) << 2) | 0, apicid_ck804, 0x16);
-
-//Slot PCIE x16
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_ck804_5, (0x00 << 2) | i, apicid_ck804, 0x10 + (2 + i + 4 - sbdn%4)%4);
-
-//Slot PCIE x4
- for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_ck804_4, (0x00 << 2) | i, apicid_ck804, 0x10 + (1 + i + 4 - sbdn%4)%4);
-
-//Onboard SM720 VGA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_ck804_1, (6 << 2) | 0, apicid_ck804, 0x13);
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c
deleted file mode 100644
index 29def69d72..0000000000
--- a/src/mainboard/winent/mb6047/romstage.c
+++ /dev/null
@@ -1,147 +0,0 @@
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include <southbridge/nvidia/ck804/early_smbus.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627thg/w83627thg.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
-
-static void memreset_setup(void) { }
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <southbridge/nvidia/ck804/early_setup_ss.h>
-#include "southbridge/nvidia/ck804/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#if IS_ENABLED(CONFIG_SET_FIDVID)
-#include "cpu/amd/model_fxx/fidvid.c"
-#endif
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- /* subject decoding*/
- byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-
- /* LPC Positive Decode 0 */
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
- /* Serial 0, Serial 1 */
- dword |= (1 << 0) | (1 << 1);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr [] = {
- DIMM0, 0, 0, 0,
- DIMM1, 0, 0, 0,
- };
-
- int needs_reset;
- unsigned bsp_apicid = 0, nodes;
- struct mem_controller ctrl[8];
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx);
-
-// post_code(0x32);
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 0));
-#endif
-
- needs_reset = setup_coherent_ht_domain();
-
- wait_all_core0_started();
- // It is said that we should start core1 after all core0 launched
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- if ((cpuid_edx(0x80000007) & 0x6) == 0x6) {
- msr_t msr;
- /* Read FIDVID_STATUS */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
- enable_fid_change();
- init_fidvid_bsp(bsp_apicid);
-
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
- }
-#endif
-
- needs_reset |= ht_setup_chains_x();
- needs_reset |= ck804_early_setup_x();
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- nodes = get_nodes();
- //It's the time to set ctrl now;
- fill_mem_ctrl(nodes, ctrl, spd_addr);
-
- enable_smbus();
-#if 0
- dump_spd_registers(&cpu[0]);
- dump_smbus_registers();
-#endif
-
- memreset_setup();
- sdram_initialize(nodes, ctrl);
-
-#if 0
- print_pci_devices();
- dump_pci_devices();
-#endif
-}
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 7b9621ac10..ab6be96ddb 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -829,9 +829,6 @@ static void setup_uma_memory(void)
#if IS_ENABLED(CONFIG_GFXUMA)
uint32_t topmem = (uint32_t) bsp_topmem();
-#if !IS_ENABLED(CONFIG_BOARD_ASROCK_939A785GMH) && \
- !IS_ENABLED(CONFIG_BOARD_AMD_MAHOGANY)
-
switch (topmem) {
case 0x10000000: /* 256M system memory */
uma_memory_size = 0x2000000; /* 32M recommended UMA */
@@ -849,22 +846,6 @@ static void setup_uma_memory(void)
uma_memory_size = 0x8000000; /* 128M recommended UMA */
break;
}
-#else
- /* refer to UMA Size Consideration in 780 BDG. */
- switch (topmem) {
- case 0x10000000: /* 256M system memory */
- uma_memory_size = 0x4000000; /* 64M recommended UMA */
- break;
-
- case 0x20000000: /* 512M system memory */
- uma_memory_size = 0x8000000; /* 128M recommended UMA */
- break;
-
- default: /* 1GB and above system memory */
- uma_memory_size = 0x10000000; /* 256M recommended UMA */
- break;
- }
-#endif
uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 39c5ad842c..ba17df28f9 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -2348,7 +2348,7 @@ static void set_ecc(const struct mem_controller *ctrl,
dcl &= ~DCL_DimmEccEn;
}
#else // CMOS_VSTART_ECC_memory not defined
-#if !IS_ENABLED(CONFIG_ECC_MEMORY)
+#if 1 // was !IS_ENABLED CONFIG_ECC_MEMORY
dcl &= ~DCL_DimmEccEn;
#endif
#endif