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-rw-r--r--src/soc/intel/apollolake/acpi/lpc.asl23
-rw-r--r--src/soc/intel/apollolake/acpi/southbridge.asl2
-rw-r--r--src/soc/intel/apollolake/include/soc/iomap.h2
-rw-r--r--src/soc/intel/cannonlake/acpi/southbridge.asl2
-rw-r--r--src/soc/intel/common/block/acpi/acpi/lpc.asl (renamed from src/soc/intel/cannonlake/acpi/lpc.asl)38
-rw-r--r--src/soc/intel/denverton_ns/acpi/lpc.asl97
-rw-r--r--src/soc/intel/denverton_ns/include/soc/iomap.h2
-rw-r--r--src/soc/intel/icelake/acpi/espi.asl117
-rw-r--r--src/soc/intel/icelake/acpi/southbridge.asl2
-rw-r--r--src/soc/intel/skylake/acpi/lpc.asl102
10 files changed, 50 insertions, 337 deletions
diff --git a/src/soc/intel/apollolake/acpi/lpc.asl b/src/soc/intel/apollolake/acpi/lpc.asl
deleted file mode 100644
index 749daf78b1..0000000000
--- a/src/soc/intel/apollolake/acpi/lpc.asl
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Intel LPC Bus Device - 0:1f.0 */
-
-Device (LPCB)
-{
- Name (_ADR, 0x001f0000)
-}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 7c9c873ddb..9acb9aeb03 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -33,7 +33,7 @@
#include "xhci.asl"
/* LPC */
-#include "lpc.asl"
+#include <soc/intel/common/block/acpi/acpi/lpc.asl>
/* eMMC */
#include "scs.asl"
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 4b82365284..3057fbe33e 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -25,6 +25,8 @@
#define MCH_BASE_ADDRESS 0xfed10000
#define MCH_BASE_SIZE (32 * KiB)
+#define HPET_BASE_ADDRESS 0xfed00000
+
#define ACPI_BASE_ADDRESS 0x400
#define ACPI_BASE_SIZE 0x100
#define R_ACPI_PM1_TMR 0x8
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index 8ba3d89b0f..b52de65e36 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -32,7 +32,7 @@
#endif
/* LPC 0:1f.0 */
-#include "lpc.asl"
+#include <soc/intel/common/block/acpi/acpi/lpc.asl>
/* PCH HDA */
#include "pch_hda.asl"
diff --git a/src/soc/intel/cannonlake/acpi/lpc.asl b/src/soc/intel/common/block/acpi/acpi/lpc.asl
index f1c1bf3bc3..e7f6660645 100644
--- a/src/soc/intel/cannonlake/acpi/lpc.asl
+++ b/src/soc/intel/common/block/acpi/acpi/lpc.asl
@@ -15,11 +15,29 @@
* GNU General Public License for more details.
*/
+/* Intel LPC/eSPI Bus Device - 0:1f.0 */
+#include <soc/iomap.h>
+
Device (LPCB)
{
Name (_ADR, 0x001f0000)
Name (_DDN, "LPC Bus Device")
+ /* DMA Controller */
+ Device (DMAC)
+ {
+ Name (_HID, EISAID("PNP0200"))
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x00, 0x00, 0x01, 0x20)
+ IO (Decode16, 0x81, 0x81, 0x01, 0x11)
+ IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
+ IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
+ DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
+ })
+ }
+
+ /* Firmware Hub */
Device (FWH)
{
Name (_HID, EISAID ("INT0800"))
@@ -30,9 +48,11 @@ Device (LPCB)
})
}
+ /* High Precision Event Timer */
Device (HPET)
{
Name (_HID, EISAID ("PNP0103"))
+ Name (_CID, 0x010CD041)
Name (_DDN, "High Precision Event Timer")
Name (_CRS, ResourceTemplate ()
{
@@ -40,10 +60,22 @@ Device (LPCB)
})
Method (_STA, 0)
{
- Return (0xf)
+ Return (0xF)
}
}
+ /* FPU */
+ Device(MATH)
+ {
+ Name (_HID, EISAID("PNP0C04"))
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
+ IRQNoFlags() { 13 }
+ })
+ }
+
+ /* AT Interrupt Controller */
Device (PIC)
{
Name (_HID, EISAID ("PNP0000"))
@@ -71,6 +103,7 @@ Device (LPCB)
})
}
+ /* LPC device: Resource consumption */
Device (LDRC)
{
Name (_HID, EISAID ("PNP0C02"))
@@ -92,6 +125,7 @@ Device (LPCB)
})
}
+ /* Real Time Clock Device */
Device (RTC)
{
Name (_HID, EISAID ("PNP0B00"))
@@ -102,6 +136,7 @@ Device (LPCB)
})
}
+ /* Timer */
Device (TIMR)
{
Name (_HID, EISAID ("PNP0100"))
@@ -113,5 +148,4 @@ Device (LPCB)
IRQNoFlags () {0}
})
}
-
}
diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl
index cc36451de2..4b6e78698c 100644
--- a/src/soc/intel/denverton_ns/acpi/lpc.asl
+++ b/src/soc/intel/denverton_ns/acpi/lpc.asl
@@ -16,10 +16,11 @@
*/
// Intel LPC Bus Device - 0:1f.0
+#include <soc/intel/common/block/acpi/acpi/lpc.asl>
-Device (LPCB)
+Scope (\_SB.PCI0.LPCB)
{
- Name(_ADR, 0x001f0000)
+ #include "irqlinks.asl"
OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
Field (LPC0, AnyAcc, NoLock, Preserve)
@@ -29,8 +30,6 @@ Device (LPCB)
IOD1, 8,
}
- #include "irqlinks.asl"
-
Device(APIC) // IO APIC
{
Name(_HID,EISAID("PNP0003"))
@@ -40,96 +39,6 @@ Device (LPCB)
})
}
- Device (HPET)
- {
- Name (_HID, EISAID("PNP0103"))
- Name (_CID, 0x010CD041)
-
- Method (_STA, 0) // Device Status
- {
- Return (0xF) // Enable and show device
- }
-
- Name(_CRS, ResourceTemplate()
- {
- Memory32Fixed(ReadOnly, DEFAULT_HPET_ADDR, 0x400)
- })
- }
-
- Device(PIC) // 8259 Interrupt Controller
- {
- Name(_HID,EISAID("PNP0000"))
- Name(_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x20, 0x20, 0x01, 0x02)
- IO (Decode16, 0x24, 0x24, 0x01, 0x02)
- IO (Decode16, 0x28, 0x28, 0x01, 0x02)
- IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
- IO (Decode16, 0x30, 0x30, 0x01, 0x02)
- IO (Decode16, 0x34, 0x34, 0x01, 0x02)
- IO (Decode16, 0x38, 0x38, 0x01, 0x02)
- IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
- IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
- IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
- IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
- IO (Decode16, 0xac, 0xac, 0x01, 0x02)
- IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
- IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
- IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
- IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
- IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
- IRQNoFlags () { 2 }
- })
- }
-
- Device(LDRC) // LPC device: Resource consumption
- {
- Name (_HID, EISAID("PNP0C02"))
- Name (_UID, 2)
- Name (_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
- IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
- IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
- IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x70, 0x70, 0x1, 0x01) // NMI Enable.
- IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
- IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
- //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap
-
- // BIOS ROM shadow memory range
- Memory32Fixed(ReadOnly, 0x000E0000, 0x20000)
-
- // BIOS flash 16MB
- Memory32Fixed(ReadOnly,0xFF000000,0x1000000)
- })
- }
-
- Device (RTC) // Real Time Clock
- {
- Name (_HID, EISAID("PNP0B00"))
- Name (_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x70, 0x70, 1, 8)
-// Disable as Windows doesn't like it, and systems don't seem to use it.
-// IRQNoFlags() { 8 }
- })
- }
-
- Device (TIMR) // Intel 8254 timer
- {
- Name(_HID, EISAID("PNP0100"))
- Name(_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x40, 0x40, 0x01, 0x04)
- IO (Decode16, 0x50, 0x50, 0x10, 0x04)
- IRQNoFlags() {0}
- })
- }
-
Device(IUR3) // Internal UART 1
{
Name(_HID, EISAID("PNP0501"))
diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h
index 8bcef91c2e..c512d55fd0 100644
--- a/src/soc/intel/denverton_ns/include/soc/iomap.h
+++ b/src/soc/intel/denverton_ns/include/soc/iomap.h
@@ -31,6 +31,8 @@
#define ACPI_BASE_ADDRESS DEFAULT_PMBASE
#define DEFAULT_TCO_BASE 0x400
+#define HPET_BASE_ADDRESS 0xfed00000
+
/* Southbridge internal device MEM BARs (Set to match FSP settings) */
#define DEFAULT_PCR_BASE 0xfd000000
#define DEFAULT_PWRM_BASE 0xfe000000
diff --git a/src/soc/intel/icelake/acpi/espi.asl b/src/soc/intel/icelake/acpi/espi.asl
deleted file mode 100644
index 4456812ba6..0000000000
--- a/src/soc/intel/icelake/acpi/espi.asl
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-/* Device identifier is not changed to ESPI to maintain coherency with ec.asl */
-Device (LPCB)
-{
- Name (_ADR, 0x001f0000)
- Name (_DDN, "ESPI Bus Device")
-
- Device (FWH)
- {
- Name (_HID, EISAID ("INT0800"))
- Name (_DDN, "Firmware Hub")
- Name (_CRS, ResourceTemplate ()
- {
- Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)
- })
- }
-
- Device (HPET)
- {
- Name (_HID, EISAID ("PNP0103"))
- Name (_DDN, "High Precision Event Timer")
- Name (_CRS, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
- })
- Method (_STA, 0)
- {
- Return (0xf)
- }
- }
-
- Device (PIC)
- {
- Name (_HID, EISAID ("PNP0000"))
- Name (_DDN, "8259 Interrupt Controller")
- Name (_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x20, 0x20, 0x01, 0x02)
- IO (Decode16, 0x24, 0x24, 0x01, 0x02)
- IO (Decode16, 0x28, 0x28, 0x01, 0x02)
- IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
- IO (Decode16, 0x30, 0x30, 0x01, 0x02)
- IO (Decode16, 0x34, 0x34, 0x01, 0x02)
- IO (Decode16, 0x38, 0x38, 0x01, 0x02)
- IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
- IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
- IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
- IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
- IO (Decode16, 0xac, 0xac, 0x01, 0x02)
- IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
- IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
- IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
- IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
- IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
- IRQNoFlags () { 2 }
- })
- }
-
- Device (LDRC)
- {
- Name (_HID, EISAID ("PNP0C02"))
- Name (_UID, 2)
- Name (_DDN, "Legacy Device Resources")
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
- IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
- IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
- IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
- IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
- IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
- 0x1, 0xff)
- })
- }
-
- Device (RTC)
- {
- Name (_HID, EISAID ("PNP0B00"))
- Name (_DDN, "Real Time Clock")
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x70, 0x70, 1, 8)
- })
- }
-
- Device (TIMR)
- {
- Name (_HID, EISAID ("PNP0100"))
- Name (_DDN, "8254 Timer")
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x40, 0x40, 0x01, 0x04)
- IO (Decode16, 0x50, 0x50, 0x10, 0x04)
- IRQNoFlags () {0}
- })
- }
-
-}
diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl
index ffd2fcca71..389963e79c 100644
--- a/src/soc/intel/icelake/acpi/southbridge.asl
+++ b/src/soc/intel/icelake/acpi/southbridge.asl
@@ -33,7 +33,7 @@
#include "gpio.asl"
/* ESPI 0:1f.0 */
-#include "espi.asl"
+#include <soc/intel/common/block/acpi/acpi/lpc.asl>
/* PCH HDA */
#include "pch_hda.asl"
diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl
index c9167ad4ec..7dd0298cb7 100644
--- a/src/soc/intel/skylake/acpi/lpc.asl
+++ b/src/soc/intel/skylake/acpi/lpc.asl
@@ -15,105 +15,11 @@
* GNU General Public License for more details.
*/
-Device (LPCB)
-{
- Name (_ADR, 0x001f0000)
- Name (_DDN, "LPC Bus Device")
-
- Device (FWH)
- {
- Name (_HID, EISAID ("INT0800"))
- Name (_DDN, "Firmware Hub")
- Name (_CRS, ResourceTemplate ()
- {
- Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)
- })
- }
-
- Device (HPET)
- {
- Name (_HID, EISAID ("PNP0103"))
- Name (_DDN, "High Precision Event Timer")
- Name (_CRS, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
- })
- Method (_STA, 0)
- {
- Return (0xf)
- }
- }
-
- Device (PIC)
- {
- Name (_HID, EISAID ("PNP0000"))
- Name (_DDN, "8259 Interrupt Controller")
- Name (_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x20, 0x20, 0x01, 0x02)
- IO (Decode16, 0x24, 0x24, 0x01, 0x02)
- IO (Decode16, 0x28, 0x28, 0x01, 0x02)
- IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
- IO (Decode16, 0x30, 0x30, 0x01, 0x02)
- IO (Decode16, 0x34, 0x34, 0x01, 0x02)
- IO (Decode16, 0x38, 0x38, 0x01, 0x02)
- IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
- IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
- IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
- IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
- IO (Decode16, 0xac, 0xac, 0x01, 0x02)
- IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
- IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
- IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
- IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
- IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
- IRQNoFlags () { 2 }
- })
- }
-
- Device (LDRC)
- {
- Name (_HID, EISAID ("PNP0C02"))
- Name (_UID, 2)
- Name (_DDN, "Legacy Device Resources")
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
- IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
- IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
- IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
- IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
- IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
- 0x1, 0xff)
- })
- }
-
- Device (RTC)
- {
- Name (_HID, EISAID ("PNP0B00"))
- Name (_DDN, "Real Time Clock")
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x70, 0x70, 1, 8)
- })
- }
-
- Device (TIMR)
- {
- Name (_HID, EISAID ("PNP0100"))
- Name (_DDN, "8254 Timer")
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x40, 0x40, 0x01, 0x04)
- IO (Decode16, 0x50, 0x50, 0x10, 0x04)
- IRQNoFlags () {0}
- })
- }
+// Intel LPC Bus Device - 0:1f.0
+#include <soc/intel/common/block/acpi/acpi/lpc.asl>
+Scope (\_SB.PCI0.LPCB)
+{
#include <acpi/ec.asl>
#include <acpi/superio.asl>
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 00:26:36 +0000