diff options
Diffstat (limited to 'src')
4 files changed, 27 insertions, 6 deletions
diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 429aa09d8f..bdf951b016 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -23,13 +23,16 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + struct cnl_mb_cfg memcfg; + const struct spd_info spd = { .spd_by_index = true, .spd_spec.spd_index = variant_memory_sku(), }; + variant_memory_params(&memcfg); cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memory_params(), &spd); + &memcfg, &spd); } void mainboard_get_dram_part_num(const char **part_num, size_t *len) diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 091f6b8b30..93e0af1753 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -281,7 +281,7 @@ static const struct pad_config gpio_table[] = { /* F1 : WWAN_RESET_1V8_ODL */ PAD_CFG_GPO(GPP_F1, 1, DEEP), /* F2 : MEM_CH_SEL */ - PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + PAD_CFG_GPI(GPP_F2, DN_20K, PLTRST), /* F3 : GPP_F3 ==> NC */ PAD_NC(GPP_F3, NONE), /* F4 : CNV_BRI_DT */ @@ -429,7 +429,7 @@ static const struct pad_config early_gpio_table[] = { /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* F2 : MEM_CH_SEL */ - PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + PAD_CFG_GPI(GPP_F2, DN_20K, PLTRST), /* F11 : PCH_MEM_STRAP2 */ PAD_CFG_GPI(GPP_F11, NONE, PLTRST), /* F20 : PCH_MEM_STRAP0 */ diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 038ec6e2c6..aa7c67d693 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -16,6 +16,7 @@ #ifndef BASEBOARD_VARIANTS_H #define BASEBOARD_VARIANTS_H +#include <soc/cnl_memcfg_init.h> #include <soc/gpio.h> #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -29,7 +30,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num); int variant_memory_sku(void); /* Return board specific memory configuration */ -const struct cnl_mb_cfg *variant_memory_params(void); +void variant_memory_params(struct cnl_mb_cfg *bcfg); /* Return ChromeOS gpio table and fill in number of entries. */ const struct cros_gpio *variant_cros_gpios(size_t *num); diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c index 80f3ba4260..6ca98e4c7f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/memory.c +++ b/src/mainboard/google/hatch/variants/baseboard/memory.c @@ -17,6 +17,7 @@ #include <baseboard/gpio.h> #include <gpio.h> #include <soc/cnl_memcfg_init.h> +#include <string.h> static const struct cnl_mb_cfg baseboard_memcfg = { /* @@ -42,9 +43,25 @@ static const struct cnl_mb_cfg baseboard_memcfg = { .ect = 1, }; -const struct cnl_mb_cfg *__weak variant_memory_params(void) +void __weak variant_memory_params(struct cnl_mb_cfg *bcfg) { - return &baseboard_memcfg; + memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); + /* + * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single + * channel skus and 0 for dual channel skus. + */ + if (gpio_get(GPP_F2) == 1) { + /* + * Single channel config: for Hatch, Channel 0 is + * always populated. + */ + bcfg->channel_empty[0] = 0; + bcfg->channel_empty[1] = 1; + } else { + /* Dual channel config: both channels populated. */ + bcfg->channel_empty[0] = 0; + bcfg->channel_empty[1] = 0; + } } int __weak variant_memory_sku(void) |