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-rw-r--r--src/soc/amd/picasso/BiosCallOuts.c166
-rw-r--r--src/soc/amd/picasso/enable_usbdebug.c42
-rw-r--r--src/soc/amd/picasso/makefile.inc13
-rw-r--r--src/soc/amd/picasso/nb_util.c40
-rw-r--r--src/soc/amd/picasso/smbus_spd.c76
5 files changed, 0 insertions, 337 deletions
diff --git a/src/soc/amd/picasso/BiosCallOuts.c b/src/soc/amd/picasso/BiosCallOuts.c
deleted file mode 100644
index c55e73499a..0000000000
--- a/src/soc/amd/picasso/BiosCallOuts.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011, 2017 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- * Copyright (C) 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <amdblocks/BiosCallOuts.h>
-#include <console/console.h>
-#include <soc/southbridge.h>
-#include <soc/pci_devs.h>
-#include <stdlib.h>
-#include <amdblocks/agesawrapper.h>
-#include <amdblocks/dimm_spd.h>
-#include <amdblocks/car.h>
-
-#include "chip.h"
-
-void __weak platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) {}
-
-AGESA_STATUS agesa_fch_initreset(uint32_t Func, uintptr_t FchData,
- void *ConfigPtr)
-{
- AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
-
- if (StdHeader->Func == AMD_INIT_RESET) {
- FCH_RESET_DATA_BLOCK *FchParams_reset;
- FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
- printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
-
- /* Get platform specific configuration changes */
- platform_FchParams_reset(FchParams_reset);
-
- printk(BIOS_DEBUG, "Done\n");
- }
-
- return AGESA_SUCCESS;
-}
-
-AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData,
- void *ConfigPtr)
-{
- AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
- const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
-
- if (StdHeader->Func == AMD_INIT_ENV) {
- FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
- printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
-
- /* XHCI configuration */
- if (CONFIG(STONEYRIDGE_XHCI_ENABLE))
- FchParams_env->Usb.Xhci0Enable = TRUE;
- else
- FchParams_env->Usb.Xhci0Enable = FALSE;
- FchParams_env->Usb.Xhci1Enable = FALSE;
-
- /* SATA configuration */
- FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
- if (dev && dev->enabled) {
- switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) {
- case SataRaid:
- case SataAhci:
- case SataAhci7804:
- case SataLegacyIde:
- FchParams_env->Sata.SataIdeMode = FALSE;
- break;
- case SataIde2Ahci:
- case SataIde2Ahci7804:
- default: /* SataNativeIde */
- FchParams_env->Sata.SataIdeMode = TRUE;
- break;
- }
- } else
- FchParams_env->Sata.SataIdeMode = FALSE;
-
- /* Platform updates */
- platform_FchParams_env(FchParams_env);
-
- printk(BIOS_DEBUG, "Done\n");
- }
-
- return AGESA_SUCCESS;
-}
-
-AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr)
-{
- uint8_t spd_address;
- int err;
- DEVTREE_CONST struct device *dev;
- DEVTREE_CONST struct soc_amd_stoneyridge_config *conf;
- AGESA_READ_SPD_PARAMS *info = ConfigPtr;
-
- if (!ENV_ROMSTAGE)
- return AGESA_UNSUPPORTED;
-
- dev = pcidev_path_on_root(DCT_DEVFN);
- if (dev == NULL)
- return AGESA_ERROR;
-
- conf = dev->chip_info;
- if (conf == NULL)
- return AGESA_ERROR;
-
- if (info->SocketId >= ARRAY_SIZE(conf->spd_addr_lookup))
- return AGESA_ERROR;
- if (info->MemChannelId >= ARRAY_SIZE(conf->spd_addr_lookup[0]))
- return AGESA_ERROR;
- if (info->DimmId >= ARRAY_SIZE(conf->spd_addr_lookup[0][0]))
- return AGESA_ERROR;
-
- spd_address = conf->spd_addr_lookup
- [info->SocketId][info->MemChannelId][info->DimmId];
- if (spd_address == 0)
- return AGESA_ERROR;
-
- err = mainboard_read_spd(spd_address, (void *)info->Buffer,
- CONFIG_DIMM_SPD_SIZE);
-
- /* Read the SPD if the mainboard didn't fill the buffer */
- if (err || (*info->Buffer == 0))
- err = sb_read_spd(spd_address, (void *)info->Buffer,
- CONFIG_DIMM_SPD_SIZE);
-
- if (err)
- return AGESA_ERROR;
-
- return AGESA_SUCCESS;
-}
-
-AGESA_STATUS agesa_HaltThisAp(uint32_t Func, uintptr_t Data, void *ConfigPtr)
-{
- AGESA_HALT_THIS_AP_PARAMS *info = ConfigPtr;
- uint32_t flags = 0;
-
- if (info->PrimaryCore == TRUE)
- return AGESA_UNSUPPORTED; /* force normal path */
- if (info->ExecWbinvd == TRUE)
- flags |= 1;
- if (info->CacheEn == TRUE)
- flags |= 2;
-
- ap_teardown_car(flags); /* does not return */
-
- /* Should never reach here */
- return AGESA_UNSUPPORTED;
-}
-
-/* Allow mainboards to fill the SPD buffer */
-__weak int mainboard_read_spd(uint8_t spdAddress, char *buf,
- size_t len)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
- return -1; /* SPD not read */
-}
diff --git a/src/soc/amd/picasso/enable_usbdebug.c b/src/soc/amd/picasso/enable_usbdebug.c
deleted file mode 100644
index 19b9550847..0000000000
--- a/src/soc/amd/picasso/enable_usbdebug.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// Use simple device model for this file even in ramstage
-#define __SIMPLE_DEVICE__
-
-#include <stdint.h>
-#include <device/pci_ops.h>
-#include <device/pci_ehci.h>
-#include <device/pci_def.h>
-#include <soc/pci_devs.h>
-#include <soc/southbridge.h>
-
-pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
-{
- pm_io_write8(PM_USB_ENABLE, PM_USB_ALL_CONTROLLERS);
- return SOC_EHCI1_DEV;
-}
-
-void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
-{
- u32 reg32, value;
-
- value = (port & 0x3) << DEBUG_PORT_SELECT_SHIFT;
- value |= DEBUG_PORT_ENABLE;
- reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4);
- reg32 &= ~DEBUG_PORT_MASK;
- reg32 |= value;
- pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32);
-}
diff --git a/src/soc/amd/picasso/makefile.inc b/src/soc/amd/picasso/makefile.inc
index babd878524..05529d9a97 100644
--- a/src/soc/amd/picasso/makefile.inc
+++ b/src/soc/amd/picasso/makefile.inc
@@ -38,35 +38,28 @@ subdirs-y += ../../../cpu/x86/pae
subdirs-y += ../../../cpu/x86/smm
bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
-bootblock-y += BiosCallOuts.c
bootblock-y += bootblock/bootblock.c
bootblock-y += gpio.c
bootblock-y += i2c.c
-bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c
bootblock-y += monotonic_timer.c
bootblock-y += pmutil.c
bootblock-y += reset.c
bootblock-y += tsc_freq.c
bootblock-y += southbridge.c
-bootblock-y += nb_util.c
bootblock-$(CONFIG_SPI_FLASH) += spi.c
bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
-romstage-y += BiosCallOuts.c
romstage-y += i2c.c
romstage-y += romstage.c
-romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += gpio.c
romstage-y += monotonic_timer.c
romstage-y += pmutil.c
romstage-y += reset.c
romstage-y += smbus.c
-romstage-y += smbus_spd.c
romstage-y += ramtop.c
romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
romstage-y += tsc_freq.c
romstage-y += southbridge.c
-romstage-y += nb_util.c
romstage-$(CONFIG_SPI_FLASH) += spi.c
romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
@@ -77,22 +70,18 @@ verstage-y += pmutil.c
verstage-y += reset.c
verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
verstage-y += tsc_freq.c
-verstage-y += nb_util.c
verstage-$(CONFIG_SPI_FLASH) += spi.c
postcar-y += monotonic_timer.c
postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
postcar-y += ramtop.c
-postcar-y += nb_util.c
postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c
postcar-y += tsc_freq.c
-ramstage-y += BiosCallOuts.c
ramstage-y += i2c.c
ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += mca.c
-ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-y += gpio.c
ramstage-y += monotonic_timer.c
@@ -111,7 +100,6 @@ ramstage-y += usb.c
ramstage-y += tsc_freq.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-y += finalize.c
-ramstage-y += nb_util.c
smm-y += monotonic_timer.c
smm-y += smihandler.c
@@ -119,7 +107,6 @@ smm-y += smi_util.c
smm-y += tsc_freq.c
smm-$(CONFIG_DEBUG_SMI) += uart.c
smm-$(CONFIG_SPI_FLASH) += spi.c
-smm-y += nb_util.c
smm-y += gpio.c
CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge
diff --git a/src/soc/amd/picasso/nb_util.c b/src/soc/amd/picasso/nb_util.c
deleted file mode 100644
index d5de067814..0000000000
--- a/src/soc/amd/picasso/nb_util.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Advanced Micro Devices
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/northbridge.h>
-#include <soc/pci_devs.h>
-#include <device/pci_ops.h>
-
-uint32_t nb_ioapic_read(unsigned int index)
-{
- pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
- return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA);
-}
-
-void nb_ioapic_write(unsigned int index, uint32_t value)
-{
- pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
- pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value);
-}
-
-void *get_ap_entry_ptr(void)
-{
- return (void *)nb_ioapic_read(AP_SCRATCH_REG);
-}
-
-void set_ap_entry_ptr(void *entry)
-{
- nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry);
-}
diff --git a/src/soc/amd/picasso/smbus_spd.c b/src/soc/amd/picasso/smbus_spd.c
deleted file mode 100644
index e57ecde578..0000000000
--- a/src/soc/amd/picasso/smbus_spd.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <amdblocks/agesawrapper.h>
-#include <console/console.h>
-#include <device/pci_def.h>
-#include <device/device.h>
-#include <soc/southbridge.h>
-#include <soc/smbus.h>
-#include <amdblocks/dimm_spd.h>
-
-/*
- * readspd - Read one or more SPD bytes from a DIMM.
- * Start with offset zero and read sequentially.
- * Optimization relies on autoincrement to avoid
- * sending offset for every byte.
- * Reads 128 bytes in 7-8 ms at 400 KHz.
- */
-static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count)
-{
- uint8_t dev_addr;
- size_t index;
- int error;
- char *pbuf = buffer;
-
- printk(BIOS_SPEW, "-------------READING SPD-----------\n");
- printk(BIOS_SPEW, "SmbusSlave: 0x%08X, count: %zd\n",
- SmbusSlaveAddress, count);
-
- /*
- * Convert received device address to the format accepted by
- * do_smbus_read_byte and do_smbus_recv_byte.
- */
- dev_addr = (SmbusSlaveAddress >> 1);
-
- /* Read the first SPD byte */
- error = do_smbus_read_byte(ACPIMMIO_SMBUS_BASE, dev_addr, 0);
- if (error < 0) {
- printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
- return error;
- }
- *pbuf = (char) error;
- pbuf++;
-
- /* Read the remaining SPD bytes using do_smbus_recv_byte for speed */
- for (index = 1 ; index < count ; index++) {
- error = do_smbus_recv_byte(ACPIMMIO_SMBUS_BASE, dev_addr);
- if (error < 0) {
- printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
- return error;
- }
- *pbuf = (char) error;
- pbuf++;
- }
- printk(BIOS_SPEW, "\n");
- printk(BIOS_SPEW, "-------------FINISHED READING SPD-----------\n");
-
- return 0;
-}
-
-int sb_read_spd(uint8_t spdAddress, char *buf, size_t len)
-{
- return readspd(spdAddress, buf, len);
-}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 07:20:03 +0000