diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/rambi/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/acpi/ec.asl | 57 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/acpi/mainboard.asl | 20 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/dsdt.asl | 7 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/irqroute.c | 22 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/irqroute.h | 47 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/acpi/cpu.asl | 77 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/acpi/irq_helper.h | 48 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/acpi/irqlinks.asl | 493 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/acpi/irqroute.asl | 37 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/acpi/lpc.asl | 164 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/acpi/platform.asl (renamed from src/mainboard/google/rambi/acpi/platform.asl) | 0 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/acpi/southcluster.asl | 23 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/baytrail/irq.h | 89 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/baytrail/pci_devs.h | 30 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/southcluster.c | 20 |
16 files changed, 1075 insertions, 60 deletions
diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index 77b2f2cb73..1b15ad7adf 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -23,5 +23,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += gpio.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c +ramstage-y += irqroute.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/google/rambi/acpi/ec.asl b/src/mainboard/google/rambi/acpi/ec.asl index 9ae5951aca..9a4cd4a1a8 100644 --- a/src/mainboard/google/rambi/acpi/ec.asl +++ b/src/mainboard/google/rambi/acpi/ec.asl @@ -1,37 +1,24 @@ -Device (EC0) -{ - Name (_HID, EISAID ("PNP0C09")) - Name (_UID, 1) - Name (_GPE, 10) // GPIO 10 is SMC_RUNTIME_SCI_N +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ - OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) - Field (ERAM, ByteAcc, Lock, Preserve) - { - Offset (0x03), - ACPR, 1, // AC Power (1=present) - , 2, - CFAN, 1, // CPU Fan (1=on) - , 2, - LIDS, 1, // Lid State (1=open) - , 1, - SPTR, 8, // SMBUS Protocol Register - SSTS, 8, // SMBUS Status Register - SADR, 8, // SMBUS Address Register - SCMD, 8, // SMBUS Command Register - SBFR, 256, // SMBUS Block Buffer - SCNT, 8, // SMBUS Block Count +/* mainboard configuration */ +#include <mainboard/google/rambi/ec.h> - Offset (0x3a), - ECMD, 8, // EC Command Register - - Offset (0x82), - PECL, 8, // PECI fractional (1/64 Celsius) - PECH, 8, // PECI integer (Celsius) - } - - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x62, 0x62, 0, 1) - IO (Decode16, 0x66, 0x66, 0, 1) - }) -} +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index 3e0eb339ee..948d7dfe87 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. + * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,10 +19,20 @@ * MA 02110-1301 USA */ -Device (PWRB) +Scope (\_SB) { - Name(_HID, EisaId("PNP0C0C")) + Device (LID0) + { + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + } - // Wake from deep sleep via GPIO27 - Name(_PRW, Package(){27, 4}) + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } } diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 55e44b586e..1fbb8eb537 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <soc/intel/baytrail/baytrail/iomap.h> - #define ENABLE_TPM DefinitionBlock( @@ -32,14 +30,15 @@ DefinitionBlock( ) { // Some generic macros - #include "acpi/platform.asl" + #include <soc/intel/baytrail/acpi/platform.asl> + #include "acpi/mainboard.asl" // global NVS and variables #include <soc/intel/baytrail/acpi/globalnvs.asl> //#include "acpi/thermal.asl" - //#include <soc/intel/baytrail/acpi/cpu.asl> + #include <soc/intel/baytrail/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/rambi/irqroute.c b/src/mainboard/google/rambi/irqroute.c new file mode 100644 index 0000000000..552be8f605 --- /dev/null +++ b/src/mainboard/google/rambi/irqroute.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h new file mode 100644 index 0000000000..20f421b5b8 --- /dev/null +++ b/src/mainboard/google/rambi/irqroute.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/intel/baytrail/baytrail/irq.h> +#include <soc/intel/baytrail/baytrail/pci_devs.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) diff --git a/src/soc/intel/baytrail/acpi/cpu.asl b/src/soc/intel/baytrail/acpi/cpu.asl new file mode 100644 index 0000000000..16f62ba309 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/cpu.asl @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* These devices are created at runtime */ +External (\_PR.CPU0, DeviceObj) +External (\_PR.CPU1, DeviceObj) +External (\_PR.CPU2, DeviceObj) +External (\_PR.CPU3, DeviceObj) + +/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ +Method (PNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CPU0, 0x81) // _CST + Notify (\_PR.CPU1, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CPU2, 0x81) // _CST + Notify (\_PR.CPU3, 0x81) // _CST + } +} + +/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ +Method (PPCN) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CPU0, 0x80) // _PPC + Notify (\_PR.CPU1, 0x80) // _PPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CPU2, 0x80) // _PPC + Notify (\_PR.CPU3, 0x80) // _PPC + } +} + +/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ +Method (TNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CPU0, 0x82) // _TPC + Notify (\_PR.CPU1, 0x82) // _TPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CPU2, 0x82) // _TPC + Notify (\_PR.CPU3, 0x82) // _TPC + } +} + +/* Return a package containing enabled processor entries */ +Method (PPKG) +{ + If (LGreaterEqual (\PCNT, 4)) { + Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + } ElseIf (LGreaterEqual (\PCNT, 2)) { + Return (Package() {\_PR.CPU0, \_PR.CPU1}) + } Else { + Return (Package() {\_PR.CPU0}) + } +} diff --git a/src/soc/intel/baytrail/acpi/irq_helper.h b/src/soc/intel/baytrail/acpi/irq_helper.h new file mode 100644 index 0000000000..b19895b583 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/irq_helper.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#undef PCI_DEV_PIRQ_ROUTES +#undef ACPI_DEV_APIC_IRQ +#undef PCI_DEV_PIRQ_ROUTE +#undef PIRQ_PIC_ROUTES +#undef PIRQ_PIC + +#if defined(PIC_MODE) + +#define ACPI_DEV_APIC_IRQ(dev_, pin_, pin_name_) \ + Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } + +#else /* defined(PIC_MODE) */ + +#define ACPI_DEV_APIC_IRQ(dev_, pin_, pin_name_) \ + Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } + +#endif + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + ACPI_DEV_APIC_IRQ(dev_, 0, a_), \ + ACPI_DEV_APIC_IRQ(dev_, 1, b_), \ + ACPI_DEV_APIC_IRQ(dev_, 2, c_), \ + ACPI_DEV_APIC_IRQ(dev_, 3, d_) + +/* Empty PIRQ_PIC definition. */ +#define PIRQ_PIC(pirq_, pic_irq_) + +/* Include the mainboard irq route definition. */ +#include "irqroute.h" diff --git a/src/soc/intel/baytrail/acpi/irqlinks.asl b/src/soc/intel/baytrail/acpi/irqlinks.asl new file mode 100644 index 0000000000..5fcee45f29 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/irqlinks.asl @@ -0,0 +1,493 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (LNKA) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 1) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTA) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLA, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTA + ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + + Return (RTLA) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTA) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTA, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKB) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 2) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTB) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLB, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLB, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTB + ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + + Return (RTLB) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTB) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTB, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKC) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 3) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTC) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLC, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLC, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTC + ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + + Return (RTLC) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTC) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTC, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKD) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 4) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTD) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLD, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLD, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTD + ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + + Return (RTLD) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTD) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTD, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKE) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 5) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTE) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLE, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLE, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTE + ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + + Return (RTLE) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTE) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTE, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKF) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 6) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTF) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLF, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLF, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTF + ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + + Return (RTLF) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTF) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTF, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKG) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 7) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTG) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLG, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLG, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTG + ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + + Return (RTLG) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTG) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTG, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKH) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 8) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTH) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLH, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLH, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTH + ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + + Return (RTLH) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTH) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTH, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + diff --git a/src/soc/intel/baytrail/acpi/irqroute.asl b/src/soc/intel/baytrail/acpi/irqroute.asl new file mode 100644 index 0000000000..23987d7d2a --- /dev/null +++ b/src/soc/intel/baytrail/acpi/irqroute.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + #undef PIC_MODE + #include <soc/intel/baytrail/acpi/irq_helper.h> + PCI_DEV_PIRQ_ROUTES + }) + } Else { + Return (Package() { + #define PIC_MODE + #include <soc/intel/baytrail/acpi/irq_helper.h> + PCI_DEV_PIRQ_ROUTES + }) + } +} diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl new file mode 100644 index 0000000000..24fa9c7b5d --- /dev/null +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -0,0 +1,164 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Intel LPC Bus Device - 0:1f.0 + +Device (LPCB) +{ + Name(_ADR, 0x001f0000) + + #include "irqlinks.asl" + + #include "acpi/ec.asl" + + Device (DMAC) // DMA Controller + { + Name(_HID, EISAID("PNP0200")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x00, 0x00, 0x01, 0x20) + IO (Decode16, 0x81, 0x81, 0x01, 0x11) + IO (Decode16, 0x93, 0x93, 0x01, 0x0d) + IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } + }) + } + + Device (FWH) // Firmware Hub + { + Name (_HID, EISAID("INT0800")) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + }) + } + + Device (HPET) + { + Name (_HID, EISAID("PNP0103")) + Name (_CID, 0x010CD041) + + Method (_STA, 0) // Device Status + { + Return (0xf) // Enable and show device + } + + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + }) + } + + Device(PIC) // 8259 Interrupt Controller + { + Name(_HID,EISAID("PNP0000")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x20, 0x20, 0x01, 0x02) + IO (Decode16, 0x24, 0x24, 0x01, 0x02) + IO (Decode16, 0x28, 0x28, 0x01, 0x02) + IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) + IO (Decode16, 0x30, 0x30, 0x01, 0x02) + IO (Decode16, 0x34, 0x34, 0x01, 0x02) + IO (Decode16, 0x38, 0x38, 0x01, 0x02) + IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) + IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) + IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) + IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) + IO (Decode16, 0xac, 0xac, 0x01, 0x02) + IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) + IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) + IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) + IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) + IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) + IRQNoFlags () { 2 } + }) + } + + Device(LDRC) // LPC device: Resource consumption + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 2) + + Name (RBUF, ResourceTemplate() + { + IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status + IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post + IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + }) + + Method (_CRS, 0, NotSerialized) + { + Return (RBUF) + } + } + + Device (RTC) // Real Time Clock + { + Name (_HID, EISAID("PNP0B00")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x70, 0x70, 1, 8) +// Disable as Windows doesn't like it, and systems don't seem to use it. +// IRQNoFlags() { 8 } + }) + } + + Device (TIMR) // Intel 8254 timer + { + Name(_HID, EISAID("PNP0100")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x40, 0x40, 0x01, 0x04) + IO (Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags() {0} + }) + } + +#ifdef ENABLE_TPM + Device (TPM) // Trusted Platform Module + { + Name(_HID, EISAID("IFX0102")) + Name(_CID, 0x310cd041) + Name(_UID, 1) + + Method(_STA, 0) + { + If (TPMP) { + Return (0xf) + } + Return (0x0) + } + + Name(_CRS, ResourceTemplate() { + IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) + IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) + Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) + IRQ (Edge, Activehigh, Exclusive) { 6 } + }) + } +#endif +} diff --git a/src/mainboard/google/rambi/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl index e0693928fa..e0693928fa 100644 --- a/src/mainboard/google/rambi/acpi/platform.asl +++ b/src/soc/intel/baytrail/acpi/platform.asl diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 87b5b6e386..7aabcf3fa0 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -19,6 +19,8 @@ * MA 02110-1301 USA */ +#include <soc/intel/baytrail/baytrail/iomap.h> + Scope(\) { // IO-Trap at 0x800. This is the ACPI->SMI communication interface. @@ -29,6 +31,21 @@ Scope(\) Offset(0x8), TRP0, 8 // IO-Trap at 0x808 } + + // Intel Legacy Block + OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) + Field (ILBS, AnyAcc, NoLock, Preserve) + { + Offset (0x8), + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + } } Name(_HID,EISAID("PNP0A08")) // PCIe @@ -210,3 +227,9 @@ Method (_OSC, 4) Return (Arg3) } } + +// LPC Bridge 0:1f.0 +#include "lpc.asl" + +// IRQ routing for each PCI device +#include "irqroute.asl" diff --git a/src/soc/intel/baytrail/baytrail/irq.h b/src/soc/intel/baytrail/baytrail/irq.h new file mode 100644 index 0000000000..d037b89059 --- /dev/null +++ b/src/soc/intel/baytrail/baytrail/irq.h @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_IRQ_H_ +#define _BAYTRAIL_IRQ_H_ + +#define PIRQA_APIC_IRQ 16 +#define PIRQB_APIC_IRQ 17 +#define PIRQC_APIC_IRQ 18 +#define PIRQD_APIC_IRQ 19 +#define PIRQE_APIC_IRQ 20 +#define PIRQF_APIC_IRQ 21 +#define PIRQG_APIC_IRQ 22 +#define PIRQH_APIC_IRQ 23 + +#define PIRQ_PIC_IRQDISABLE 0x0 +#define PIRQ_PIC_IRQ3 0x3 +#define PIRQ_PIC_IRQ4 0x4 +#define PIRQ_PIC_IRQ5 0x5 +#define PIRQ_PIC_IRQ6 0x6 +#define PIRQ_PIC_IRQ7 0x7 +#define PIRQ_PIC_IRQ9 0x9 +#define PIRQ_PIC_IRQ10 0xa +#define PIRQ_PIC_IRQ11 0xb +#define PIRQ_PIC_IRQ12 0xc +#define PIRQ_PIC_IRQ14 0xe +#define PIRQ_PIC_IRQ15 0xf + +/* Overloaded term, but these values determine the per device route. */ +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* In each mainbaord directory there should exist a header file irqroute.h that + * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which + * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ + +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) +#include <stdint.h> + +#define NUM_IR_DEVS 32 +#define NUM_PIRQS 8 + +struct baytrail_irq_route { + /* Per device configuration. */ + uint16_t pcidev[NUM_IR_DEVS]; + /* Route path for each internal PIRQx in PIC mode. */ + uint8_t pic[NUM_PIRQS]; +}; + +extern const struct baytrail_irq_route global_baytrail_irq_route; + +#define DEFINE_IRQ_ROUTES \ + const struct baytrail_irq_route global_baytrail_irq_route = { \ + .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ + .pic = { PIRQ_PIC_ROUTES, }, \ + } + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ + ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) + +#define PIRQ_PIC(pirq_, pic_irq_) \ + [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ + +#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ + +#endif /* _BAYTRAIL_IRQ_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/pci_devs.h b/src/soc/intel/baytrail/baytrail/pci_devs.h index 96e9547f5b..b3fdce234a 100644 --- a/src/soc/intel/baytrail/baytrail/pci_devs.h +++ b/src/soc/intel/baytrail/baytrail/pci_devs.h @@ -23,27 +23,27 @@ /* All these devices live on bus 0 with the associated device and function */ /* SoC transaction router */ -#define SOC_DEV 0 +#define SOC_DEV 0x0 #define SOC_FUNC 0 # define SOC_DEVID 0x0f00 /* Graphics and Display */ -#define GFX_DEV 2 +#define GFX_DEV 0x2 #define GFX_FUNC 0 # define GFX_DEVID 0x0f31 /* SDIO Port */ -#define SDIO_DEV 17 +#define SDIO_DEV 0x11 #define SDIO_FUNC 0 # define SDIO_DEVID 0x0f15 /* SD Port */ -#define SD_DEV 18 +#define SD_DEV 0x12 #define SD_FUNC 0 # define SD_DEVID 0x0f16 /* SATA */ -#define SATA_DEV 19 +#define SATA_DEV 0x13 #define SATA_FUNC 0 #define IDE1_DEVID 0x0f20 #define IDE2_DEVID 0x0f21 @@ -51,22 +51,22 @@ #define AHCI2_DEVID 0x0f23 /* xHCI */ -#define XHCI_DEV 20 +#define XHCI_DEV 0x14 #define XHCI_FUNC 0 # define XHCI_DEVID 0x0f35 /* LPE Audio */ -#define LPE_DEV 21 +#define LPE_DEV 0x15 #define LPE_FUNC 0 # define LPE_DEVID 0x0f28 /* MMC Port */ -#define MMC_DEV 23 +#define MMC_DEV 0x17 #define MMC_FUNC 0 # define MMC_DEVID 0x0f50 /* Serial IO 1 */ -#define SIO1_DEV 24 +#define SIO1_DEV 0x18 # define SIO_DMA1_DEV SIO1_DEV # define SIO_DMA1_FUNC 0 # define SIO_DMA1_DEVID 0x0f40 @@ -93,17 +93,17 @@ # define I2C7_DEVID 0x0f47 /* Trusted Execution Engine */ -#define TXE_DEV 26 +#define TXE_DEV 0x1a #define TXE_FUNC 0 # define TXE_DEVID 0x0f18 /* HD Audio */ -#define HDA_DEV 27 +#define HDA_DEV 0x1b #define HDA_FUNC 0 # define HDA_DEVID 0x0f04 /* PCIe Ports */ -#define PCIE_DEV 28 +#define PCIE_DEV 0x1c # define PCIE_PORT1_DEV PCIE_DEV # define PCIE_PORT1_FUNC 0 # define PCIE_PORT1_DEVID 0x0f48 @@ -118,12 +118,12 @@ # define PCIE_PORT4_DEVID 0x0f4e /* EHCI */ -#define EHCI_DEV 29 +#define EHCI_DEV 0x1d #define EHCI_FUNC 0 # define EHCI_DEVID 0x0f34 /* Serial IO 2 */ -#define SIO2_DEV 30 +#define SIO2_DEV 0x1e # define SIO_DMA2_DEV SIO2_DEV # define SIO_DMA2_FUNC 0 # define SIO_DMA2_DEVID 0x0f06 @@ -144,7 +144,7 @@ # define SPI_DEVID 0xf0e /* Platform Controller Unit */ -#define PCU_DEV 31 +#define PCU_DEV 0x1f # define LPC_DEV PCU_DEV # define LPC_FUNC 0 # define LPC_DEVID 0x0f1c diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index f8b4f18472..10c0b896fb 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -27,6 +27,7 @@ #include <romstage_handoff.h> #include <baytrail/iomap.h> +#include <baytrail/irq.h> #include <baytrail/lpc.h> #include <baytrail/nvs.h> #include <baytrail/pci_devs.h> @@ -116,6 +117,23 @@ static void sc_read_resources(device_t dev) sc_add_io_resources(dev); } +static void sc_init(device_t dev) +{ + int i; + const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; + const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; + const struct baytrail_irq_route *ir = &global_baytrail_irq_route; + + /* Set up the PIRQ PIC routing based on static config. */ + for (i = 0; i < NUM_PIRQS; i++) { + write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]); + } + /* Set up the per device PIRQ routing base on static config. */ + for (i = 0; i < NUM_IR_DEVS; i++) { + write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]); + } +} + /* * Common code for the south cluster devices. */ @@ -412,7 +430,7 @@ static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = NULL, - .init = NULL, + .init = sc_init, .enable = southcluster_enable_dev, .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, |